PROTECTIVE LAYER TO REDUCE STI LOSS AND THE METHODS FOR FORMING THIS

Abstract

A method comprises forming a region of shallow trench isolation adjacent to a protruding fin. The protruding fin has a first semiconductor nanostructure and a second semiconductor nanostructure. The method further comprises: forming a hard mask on the region of shallow trench isolation, forming a dummy gate stack over the protruding fin, removing a sacrificial layer in the protruding fin to leave a space between the first and second semiconductor nanostructures, forming a removable interposer in the space, removing the dummy gate stack, removing the removable interposer using an etching chemical, wherein, when the removable interposer is removed, the hard mask is exposed to the etching chemical, and forming a gate stack, wherein a portion of the gate stack is placed into the space.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority over the following provisional US patent application: Application No.: 63 / 651,043, filed on May 23, 2024, entitled “SEMICONDUCTOR STRUCTURE”, which is incorporated herein by reference. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers onto a semiconductor substrate, and by lithography to structure the various material layers and form circuit components and elements.

[0003] The semiconductor industry is constantly improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum element size, thus enabling more components to be integrated into a given area. However, reducing the smallest element sizes brings additional problems to light that must be addressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood from the detailed description below, when read together with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figures 1 to 18A and 18B show views of intermediate stages in the formation of transistors according to some embodiments. Fig. Figure 19 shows a process flow for forming transistors according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forming a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is done for the sake of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0006] Furthermore, terms relating to spatial relativity, such as "underlying," "below," "lower," "above," "upper," and the like, may be used herein to facilitate description of the relationship of one element or structural element to another element or structural element (or other elements or structural elements), as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the device used or operated in addition to the orientation illustrated in the figures. The device may be oriented in a different way (rotated by 90 degrees or otherwise), and the terms relating to spatial relativity used herein may be interpreted accordingly.

[0007] A gate-all-around transistor (GAA transistor) and the method for forming it are provided. According to some embodiments of the present disclosure, the formation of the GAA transistor uses disposable oxide interposing (DOI) processes, which include the formation of sacrificial layers containing oxides. Since the sacrificial layers do not exhibit sufficient etch selectivity with respect to shallow trench insulation (STI) regions, the STI regions may be unintentionally spared, leading to an undesired increase in the effective capacitance Ceff between conductive elements and an undesired increase in the outer edge capacitance. A protective layer (also referred to as a hard mask) is therefore formed on the STI regions to prevent the STI regions from being spared during the removal of the sacrificial layers.

[0008] The embodiments discussed here are intended to provide examples to enable the manufacture or use of the subject matter of this disclosure, and a person skilled in the art will readily understand modifications that may be made while maintaining the scope of the various embodiments under consideration. The same reference numerals are used in the different views and embodiments to refer to the same elements. Although embodiments of methods may be discussed in such a way as to be carried out in a particular order, other embodiments of methods may be carried out in any logical order.

[0009] Fig. 1 to Fig. 18A and Fig. Figure 18B shows cross-sectional views of intermediate stages in the formation of a GAA transistor according to some embodiments of the present disclosure. The corresponding processes are also shown schematically in the figure in Fig. The process flow shown in 19 is reproduced in 200.

[0010] With reference to Fig. Figure 1 shows a perspective view of a wafer 10. The wafer 10 has a multilayer structure comprising a multilayer stack 22 on a substrate 20. According to some embodiments, the substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon-germanium substrate (SiGe substrate), or the like, although other substrates and / or structures, such as semiconductor-on-insulator (SOI), strained SOI, silicon-germanium-on-insulator, or the like, could be used. The substrate 20 may be doped as a p-type semiconductor, although in other embodiments it may be doped as an n-type semiconductor.

[0011] According to some embodiments, the multilayer stack 22 is formed by a series of deposition processes for depositing alternating materials. The corresponding process is designated as process 202 in the Fig. The process flow 200 is shown in Figure 19. According to some embodiments, the multilayer stack 22 has first layers 22A formed from a first semiconductor material and second layers 22B formed from a second semiconductor material different from the first semiconductor material.

[0012] According to some embodiments, the first semiconductor material of a first layer 22A is formed from or contains SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or the like. According to some embodiments, the deposition of the first layers 22A (for example, SiGe) takes place by epitaxial growth, and the corresponding deposition method may be vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced-pressure CVD (RPCVD), or the like. According to some embodiments, the first layer 22A is formed to a first thickness in the range of approximately 30 Å to approximately 300 Å. However, any suitable thickness may be used without departing from the scope of the embodiments.

[0013] After the first layer 22A has been deposited onto the substrate 20, a second layer 22B is deposited onto the first layer 22A. According to some embodiments, the second layer 22B is formed from or contains a second semiconductor material, such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations thereof, or the like, wherein the second semiconductor material is different from the first semiconductor material of the first layer 22A. According to some embodiments, in which the first layer 22A is silicon germanium, for example, the second layer 22B can be formed from silicon, or vice versa. It is understood that any suitable combination of materials can be used for the first layer 22A and the second layer 22B.

[0014] In some embodiments, the second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to that used to form the first layer 22A. In some embodiments, the second layer 22B is formed to a thickness similar to that of the first layer 22A. Alternatively, the second layer 22B can be formed to a thickness different from that of the first layer 22A. For example, in some embodiments, the second layer 22A has a thickness in the range of approximately 4 nm to 7 nm, while the second layer 22B has a thickness in the range of approximately 8 nm to 12 nm.

[0015] After the second layer 22B has been formed over the first layer 22A, the deposition process is repeated to form the remaining layers in the multilayer stack 22 until a desired top layer of the multilayer stack 22 has been formed. According to some embodiments, the first layers 22A have the same or similar thicknesses, and the second layers 22B have the same or similar thicknesses. The first layers 22A may also have the same thickness as the second layers 22B or different thicknesses. According to some embodiments, the first layers 22A are removed in a subsequent process and are alternatively referred to throughout this description as sacrificial layers 22A. According to alternative embodiments, the second layers 22B are sacrificial layers and are removed in the subsequent processes.

[0016] According to some embodiments, some pad oxide layer(s) and hard mask(s) (not shown) can be formed over the multilayer stack 22. These layers are patterned and are used for the subsequent structuring of the multilayer stack 22.

[0017] With reference to Fig. 2. The multilayered stack 22 and a section of the underlying substrate 20 are structured in an etching process(s) so that grooves 23 are formed. The corresponding process is described as process 204 in the Fig. The process flow 200 is shown in Figure 19. The trenches 23 extend into the substrate 20. The remaining sections of the multilayer stacks are referred to below as multilayer stacks 22'. Some sections of the substrate 20 are left beneath the multilayer stacks 22' and are referred to below as substrate strips 20'. The multilayer stacks 22' have semiconductor layers 22A and 22B. The semiconductor layers 22A are alternatively referred to as sacrificial layers, and the semiconductor layers 22B are alternatively referred to below as nanostructures. The sections of the multilayer stacks 22' and the underlying substrate strips 20' are collectively referred to as semiconductor bridges 24.

[0018] In the embodiments described above, the GAA transistor structures can be structured by any suitable method. For example, the structures can be structured using one or more photolithographic processes, including dual-structuring or multiple-structuring processes. In general, dual-structuring or multiple-structuring processes combine photolithographic and self-aligning processes, enabling the creation of structures with, for example, smaller pitches than would otherwise be achievable using a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithographic process. Spacers are formed along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers can then be used to structure the GAA structure.

[0019] Fig. Figure 3A shows the formation of isolation areas 26, which are also referred to throughout the description as shallow trench isolation areas (STI areas). The corresponding process is described as process 206 in the Fig. The process flow shown in Figure 19 is illustrated in Figure 200. The STI areas 26 can contain a dielectric liner (see Figure 26). Fig. 3B) exhibit, which may be a thermal oxide formed by the thermal oxidation of an area layer of the substrate 20. The dielectric liner may also be a deposited silicon oxide layer formed, for example, using ALD, high-density plasma chemical vapor deposition (HDPCVD), CVD, or the like. The STI regions 26 may also have a dielectric material overlying the dielectric liner, the dielectric material being formed using flowable chemical vapor deposition (FCVD), rotational coating, HDPCVD, or the like. A planarization process, such asA chemical-mechanical polishing process (CMP process) or a mechanical grinding process can then be carried out to flatten the top surface of the dielectric material, and the remaining sections of the dielectric material represent the STI areas 26.

[0020] The STI regions 26 are then recessed so that the upper sections of the semiconductor webs 24 protrude higher than the upper surfaces 26T of the remaining sections of the STI regions 26, forming protruding fins 28. The protruding fins 28 feature the multilayer stacks 22' and the upper sections of the substrate strips 20'. The recession of the STI regions 26 can be carried out by a dry etching process, using, for example, NF3 and NH3 as the etching gases. A plasma can be generated during the etching process. Argon can also be incorporated. According to alternative embodiments of the present disclosure, the recession of the STI regions 26 is carried out using a wet etching process. The etching chemical can, for example, contain HF.

[0021] Fig. 3B shows a cross-section A1 - A1 in Fig. 3A. As in Fig. As shown in Figure 3B, the STI regions 26 can have a dielectric liner 26A and a dielectric region 26B on the dielectric liner 26A. The dielectric liner 26A and the dielectric region 26B can be formed from different dielectric materials or from the same dielectric material. For example, the dielectric liner 26A can be formed from silicon nitride or silicon oxide, while the dielectric region 26B can be formed from silicon oxide or silicon nitride. The dielectric liner 26A and the dielectric region 26B can also be formed from the same dielectric material, such as silicon oxide, but exhibit different properties. For example, the dielectric region 26B can have a lower density and a higher etch rate than the dielectric liner 26A.According to some alternative embodiments, the entirety of the STI regions 26 is formed from a homogeneous material, such as silicon oxide. In subsequent figures, the dielectric liner 26A and the dielectric region 26B are not shown separately.

[0022] According to some embodiments, the distance S1 between adjacent protruding fins 28 can be in the range between approximately 20 nm and approximately 200 nm. The height H1 of the protruding fins 28 can be in the range between approximately 50 nm and approximately 70 nm.

[0023] With reference to Fig. 4 A dielectric layer 120 is formed. The corresponding process is described as process 208 in the Fig. The process flow 200 is shown in Figure 19. According to some embodiments, the dielectric layer 120 contains silicon oxide. The formation can include a deposition process, which may be a conformal deposition process, such as ALD, CVD, or the like. The thickness T3 of the dielectric layer 120 must not be too small. Otherwise, it cannot effectively protect the protruding fins 28 in subsequent etching processes. The thickness T3 of the dielectric layer 120 must also not be too large. Otherwise, sagging of the edges may occur, as described in Figure 19. Fig. 16A will be discussed. According to some embodiments, the thickness T3 of the dielectric layer 120 is in the range between approximately 1 nm and approximately 8 nm, and can be in the range between approximately 1 nm and approximately 4 nm.

[0024] Fig. Figure 5 shows the deposition of the hard mask layer 122 (also referred to as protective layer 122). The corresponding process is described as process 210 in the Fig. The process flow 200 is shown in Figure 19. According to some embodiments, the hard mask layer 122 is formed as a non-conforming layer having sidewall sections with a thickness of T4, upper sections with a thickness of T5, and lower sections with a thickness of T6. The thicknesses T5 and T6 are greater than the thickness T4. For example, the ratios T5 / T4 and T6 / T4 can be in the range between approximately 3 and approximately 20.

[0025] The hard mask layer 122 is formed from a dielectric material that differs from the dielectric material of the underlying STI regions 26 (and exhibits high etch selectivity with respect to it). The material of the hard mask layer 122 can also differ from the material of the subsequently formed removable oxide interposers 29 (disposable oxide interposers) ( Fig. 13A and Fig. 13B) may differ (and exhibit high etch selectivity with respect to this). The etch selectivity can be higher than approximately 10 and may, for example, be in the range between approximately 10 and 100.

[0026] According to some embodiments, the hard mask layer 122 can be formed from or contain a silicon and nitrogen dielectric material and / or a silicon and carbon dielectric material, such as SiN, SiCN, SiON, SiCON, SiC, SiOC, or the like. The hard mask layer 122 can also contain a high-k dielectric material, such as Al₂O₃ (ALD), HfO₂, HfSiO₂, ZrO₂, La₂O₃, Y₂O₃, or the like, or combinations thereof. The hard mask layer 122 can also contain an inorganic or organic low-k material, such as fluorine-doped silicate glass (FSG), porous carbon-doped oxide (such as porous SiOC), xerogel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB), polyimide, or the like.

[0027] According to some embodiments, the formation of the non-conforming hard mask layer 122 can comprise several cycles. Each of the cycles can include the deposition of a silicon layer, followed by a nitriding process to convert the silicon layer into a silicon nitride layer. The deposition process can also include ALD, CVD, PVD, RPCVD, PECVD, HDPCVD, FCVD, HARP, LPCVD, ALCVD, APCVD, SACVD, MOCVD, or the like, or combinations thereof. According to some embodiments, the deposition of the silicon layer is carried out using plasma deposition with applied bias power.Accordingly, the horizontal sections of the silicon layer on the upper side of the protruding fins 28 and on the undersides of the spaces (between the protruding fins 28) have more unsaturated bonds due to the plasma, while the vertical sections of the silicon layer on the side walls of the protruding fins 28 have fewer unsaturated bonds.

[0028] During the nitriding process, the horizontal sections of the silicon layer exhibit a higher conversion rate (conversion to silicon nitride) due to their higher concentration of unsaturated bonds, while the sidewall sections exhibit a lower conversion rate. The unconverted sections of the silicon layer on the sidewalls can be removed from the respective process chamber during the conversion process. Consequently, the resulting silicon nitride layer is non-conformal. Through multiple cycles, the thickness of the silicon nitride layer is increased in each cycle until the desired thickness is reached.

[0029] According to alternative embodiments, the hard mask layer 122 is formed as a conformal layer. According to these embodiments, silicon nitride can be deposited by plasma deposition with applied bias power (for example, using ALD, CVD, or the like). The upper and lower sections of the hard mask layer 122, which may contain silicon nitride, can be denser and harder than the sidewall sections. Consequently, in the subsequent etching processes, as described in Fig. 7 and Fig. As shown in Figure 8, the sidewall sections exhibit a higher etch rate and are completely removed, while the lower sections still retain some remaining sections. Accordingly, the lower sections can have a sufficient thickness to be used in a subsequent film formation process, as shown in Figure 8. Fig. 16A is shown to act as a protective layer.

[0030] Fig. Figure 6 shows the formation of a sacrificial layer 124, which is used as an etching mask. The corresponding process is described as process 212 in the Fig. The process flow 200 is shown in Figure 19. According to some embodiments, the sacrificial layer 124 comprises a material that can be used as a bottom antireflection coating (BARC) and may include a crosslinked photoresist, SiOC, or the like. The formation of the sacrificial layer 124 may include a deposition (or dispensing) process, followed by a planarization process and then a back-etching process. The upper portions of the hard mask layer 122 are exposed in this way.

[0031] Fig. Figure 7 shows an etching process for removing part of the upper section of the hard mask layer 122. The etching chemical is selected to have a low etch rate on the dielectric layer 120. The etching can be carried out by a dry etching process, a wet etching process, or the like. According to some embodiments, the etching gas can contain a fluorine-containing gas, such as CF4, NF3, SF6, CHF3, ClF3, or the like, or combinations thereof. Other gases, such as O2, N2, H2, Ar, NO, and the like, can also be added. According to alternative embodiments, a wet etching process can be used, for example, using H3PO4. After the etching process, the upper section of the hard mask layer 122 can be completely removed to expose the dielectric layer 120, or a thin remaining section may be present.

[0032] The sacrificial layer 124 is then removed, followed by an etching process to remove the upper sections (if any remaining) and sidewall sections of the hard mask layer 122. The corresponding process is described as process 214 in the Fig. The process flow shown in 19 is illustrated in 200. The resulting structure is in Fig. Figure 8 shows the remaining sections of the hard mask layer 122, also referred to as hard masks 122. The etching process can be isotropic and can be carried out using either a dry or wet etching process, for example, using the chemical mentioned above to remove the upper sections of the hard mask layer 122. The dielectric layer 120 is used as an etch stop layer.

[0033] In some embodiments where the sidewall sections (vertical sections) of the hard mask layer 122 are thinner than the lower sections, the etching process of the sacrificial layer 124 is controlled such that the upper and sidewall sections are completely removed, while the lower sections retain at least some remaining sections. In embodiments where the sidewall sections have the same thickness as the lower sections but a lower density, the sidewall sections are etched faster than the lower sections. When the sidewall sections are completely removed, the lower sections retain at least some remaining sections.

[0034] According to some embodiments, as in Fig. As shown in Figure 8, the hard masks 122 can have curved upper surfaces due to etching, with central sections of the curved upper surface located midway between adjacent semiconductor strates 20' at lower heights than the sections closer to the semiconductor strates 20'. Although the upper surfaces of the hard masks 122 are not shown to be curved in subsequent figures, the upper surfaces of the hard masks 122 can, for example, be curved in the Fig. 18A and Fig. The final structure shown in Figure 18B may also be curved.

[0035] According to some embodiments, the remaining hard masks 122 are neither too thick nor too thin when etching is stopped. Hard masks 122 that are too thin pose a challenge for process control, and non-uniformity in the wafer can cause the hard masks 122 to be etched completely or too thinly in some sections of the wafer, and thus unable to protect the underlying STI regions in the subsequent foil formation processes. Hard masks 122 that are too thick can result in an excessively high capacitance between the subsequently formed gate electrode and the semiconductor ridge 20' (also referred to as a semiconductor protrusion) due to the high dielectric constant of the hard masks 122. According to some embodiments, the thickness of the remaining hard masks 122 is in the range of approximately 0.5 nm to approximately 10 nm.

[0036] The dielectric layer 120 is then etched, exposing the protruding fins 28. The resulting structure is in Fig. Figure 9 shows that some sections of the dielectric layer 120 on the side walls of the hard masks 122 and under the hard masks 122 are left in place so that they act as dielectric liners, and these are also referred to as dielectric liners 120. Throughout this description, the hard masks 122 and the respective dielectric liners 120 are collectively referred to as hard masks 122 / 120 or composite hard masks 122 / 120.

[0037] With reference to Fig. Figure 10, which shows a perspective view, depicts dummy gate stacks 30 and gate spacers 38 formed on the upper surfaces and side walls of the (protruding) fins 28. The dummy gate stacks 30 can have dummy gate dielectrics 32 and dummy gate electrodes 34 over the dummy gate dielectrics 32. The dummy gate dielectrics 32 can be formed by oxidizing the surface sections of the protruding fins 28 to form oxide layers or by depositing a dielectric layer, such as a silicon oxide layer. The dummy gate electrodes 34 can be formed, for example, using polysilicon or amorphous silicon, and other materials, such as amorphous carbon, can also be used.

[0038] Each of the dummy gate stacks 30 can also have one (or more) hard mask(s) 36 over the dummy gate electrode 34. The hard masks 36 can be formed from silicon nitride, silicon oxide, silicon carbonitride, silicon oxica carbonitride, or multiple layers thereof. The dummy gate stacks 30 can overlap one or more of the protruding fins 28 and STI regions 26 between the protruding fins 28. The dummy gate stacks 30 also have longitudinal directions that are perpendicular to the longitudinal directions of the protruding fins 28. The formation of the dummy gate stacks 30 comprises: forming a dummy gate dielectric layer, depositing a dummy gate electrode layer over the dummy gate dielectric layer, depositing one or more hard masks, and subsequently structuring the formed layers by a structuring process.

[0039] Next, gatespacers 38 are formed on the side walls of the dummy gate stacks 30. According to some embodiments of the present disclosure, the gatespacers 38 are formed from a dielectric material, such as silicon nitride (SiN), silicon carbide (SiC), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or the like, and can have a single-layer structure or a multi-layer structure having several dielectric layers. The formation process of the gatespacers 38 can include depositing one or more dielectric layers and subsequently performing an anisotropic etching process on the dielectric layer(s). The remaining portions of the dielectric layer(s) constitute the gatespacers 38.

[0040] Fig. Figure 11 shows the source / drain recession process. The corresponding process is designated as process 218 in the [document / section]. Fig. The process flow 200 is shown in Figure 19. The protruding fins 28, which are not directly under dummy gate stacks 30 and the gate spacers 38, are etched in an anisotropic etching process. Source / drain recesses 42 are formed in this way, as shown in Figure 19. Fig. 11 shown. Fig. Figure 11 shows the cross-section B - B, as in Fig. 10 shown.

[0041] Fig. 12A, Fig. 12B, Fig. 13A, and Fig. Figure 13B shows the replacement of sacrificial layers 22A by removable interposers 29. With reference to Fig. 12A and Fig. 12B, each with cross-section BB or A2-A2 in Fig. Figure 10 shows that the sacrificial layers 22A are removed first, creating openings 27 between nanostructures 22B. The corresponding process is described as process 220 in the Fig. The process flow shown in 19 is illustrated in 200.

[0042] With reference to Fig. 13A and Fig. In 13B, the removable interposers 29 are formed between the nanostructures 22B. The corresponding process is described as process 222 in the Fig. The process flow 200 is shown in Figure 19. According to some embodiments, the removable interposers 29 contain an oxide, such as silicon oxide, and can therefore also be referred to as removable oxide interposers (DOIs) 29. According to other embodiments, other types of oxides can be used.

[0043] Forming the removable interposers 29 can involve depositing a dielectric layer using a conformal deposition process, such that the dielectric layer has some sections filling the openings 27 and some other sections outside the openings 27. A trimming process, which can be an isotropic etching process, is then performed to etch and remove the sections of the dielectric layer outside the openings 27. The remaining sections of the dielectric layer thus constitute the removable interposers 29.

[0044] The removable interposers 29 are then recessed laterally to accommodate the inner spacers 44 ( Fig. 13A). The lateral recession of the removable interposers 29 can be achieved using a wet etching process or a dry etching process. The wet etching process can be carried out using an immersion process, a spraying process, a rotary coating process, or the like. The nanostructures 22B are not etched.

[0045] The 44 inner spacers are then formed. The corresponding process is described as process 224 in the [document / document / etc.]. Fig. The process flow 200 is shown in Figure 19. According to some embodiments, forming the inner spacers 44 involves depositing a conformal dielectric layer extending into the lateral recesses. Next, an etching process (also referred to as a spacer trimming process) is performed to trim the portions of the dielectric layer outside the lateral recesses, leaving the portions of the dielectric layer within the lateral recesses. The remaining portions of the dielectric layer are referred to as the inner spacers 44.

[0046] With reference to Fig. 14A and Fig. 14B, which have the same cross-section as the respective cross-sections A1-A1 and BB in Fig. As shown in Figure 10, epitaxial source / drain regions 48 are formed in the recesses 42 by means of selective epitaxy. The corresponding process is represented as process 226 in the figure shown in Fig. The process flow shown in Figure 19 is illustrated in Figure 200. Depending on whether the resulting transistor is a p-type or an n-type transistor, a p-type or an n-type impurity can be introduced in situ as epitaxy progresses. For example, if the resulting transistor is a p-type transistor, silicon germanium boron (SiGeB), silicon boron (SiB), or the like can be grown. Conversely, if the resulting transistor is an n-type transistor, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or the like can be grown.

[0047] Fig. 15A and Fig. Figure 15B shows the cross-sectional intentions of the structure after the formation of a contact etch stop layer (CESL) 50 and a dielectric intermediate layer (ILD) 52. Fig. 15A and Fig. Figures 15B show the cross-sections A2-A2 and BB respectively. Fig. 10. The CESL 50 can be formed from silicon oxide, silicon nitride, silicon carbonitride, or the like, and can be formed using CVD, ALD, or the like. The ILD 52 can contain a dielectric material formed, for example, using FCVD, spin coating, CVD, or any other suitable deposition process. The ILD 52 can be formed from an oxygen-containing dielectric material, which may contain silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like.

[0048] The CESL 50 and the ILD 52 are planarized using a planarization process, such as a CMP process or a mechanical grinding process. According to some embodiments, the planarization process can remove the hard masks 36 to expose the dummy gate electrodes 34, as shown in Fig. 15A and Fig. Figure 15B is shown. According to alternative embodiments, the planarization process can expose the hard masks 36 and is stopped at them. According to some embodiments, after the planarization process, the upper surfaces of the dummy gate electrodes 34 (or the hard masks 36), the gate spacer 38, and the ILD 52 are flat within process variations.

[0049] Next, the dummy gate electrodes 34 and the dummy gate dielectrics 32 (and the hard masks 36, if remaining) are removed in one or more etching processes, so that recesses 58 are formed, as shown in Fig. 16A and Fig. shown in 16B. The corresponding process is designated as process 228 in the Fig. The process flow 200 is shown in Figure 19. According to some embodiments, the dummy gate electrodes 34 and the dummy gate dielectrics 32 are removed by an anisotropic dry etching process(s). For example, the etching process can be carried out using a reactive gas (gases) that selectively etches (etches) the dummy gate electrodes 34 and the dummy gate dielectrics 32 at faster rates than the ILD 52. Each recess 58 exposes and / or lies above sections of the multilayer stacks 22' that feature the future channel regions in subsequently completed transistors.

[0050] The removable interposers 29 are then removed to extend the recesses 58 between the nanostructures 22B. The corresponding process is described as process 230 in the Fig. The process flow 200 is shown in Figure 19. The removable interposers 29 can be removed by performing an isotropic etching process, such as a wet etching process, using etchants that are selective with respect to the materials of the removable interposers 29, while the nanostructures 22B and the substrate 20 remain relatively unetched compared to the removable interposers 29. According to some embodiments in which the removable interposers 29 contain, for example, silicon dioxide, a mixture of NF3 and NH3, a mixture of HF and NH3, and HF can be used to remove the removable interposers 29.

[0051] During etching of the removable interposers 29, the STI regions 26 are protected from the etching chemical by the hard masks 122 due to the high etch selectivity, which is the ratio of the etch rate of the removable interposers 29 to the etch rate of the hard masks 122. It is understood that when removing the removable interposers 29, the remaining sections of the dielectric layer 120 can be spared. For example, the sections of the dielectric layer 120 can be shown in dashed circles 59 in Fig. 16A is removed, and the upper surfaces of the sidewall sections of the dielectric layer 120 are recessed such that they are lower than the upper surfaces of the hard masks 122. However, due to the selected small thickness of the dielectric layer 120, the recession of the dielectric layer 120 is controlled, and the lower sections of the dielectric layer 120 can remain. The upper surfaces of the hard masks 122 can also have a curvature, with the central section of the upper surfaces being lower than the respective opposite sections.

[0052] Some example dimensions are given with reference to Fig. Discussed in 16A. The nanostructures 22B can have a height A, which may be in the range of approximately 50 nm to approximately 70 nm. The height A is calculated from a top surface of the nanostructure to a top surface of the fin / projection 20' and is also referred to as a thickness. The nanostructures 22B can have heights in the range of approximately 6 nm to approximately 10 nm. The spaces between the nanostructures 22B can be in the range of approximately 8 nm to approximately 10 nm. The width B of the nanostructure 22B can be in the range of approximately 20 nm to approximately 30 nm, with the space S1 in the range of approximately 20 nm to approximately 200 nm. The thickness C of the hard masks 122 can be in the range of approximately 0.5 nm to approximately 20 nm, or in the range of approximately 10 nm to approximately 20 nm.The thickness D of the dielectric layer 120 can be in the range between approximately 1 nm and approximately 8 nm, and can be in the range between approximately 1 nm and approximately 4 nm, or in the range between approximately 4 nm and approximately 8 nm.

[0053] The distance E from the top of the semiconductor ridge 20' to the bottom of the hard masks 122 can be in the range of approximately 5 nm to approximately 20 nm. The distance F from the top of the semiconductor ridge 20' to the top of the hard masks 122 (at the edge of the hard mask 122) can be in the range of approximately 2 nm to approximately 5 nm. The distance G from the top of the semiconductor ridge 20' to the top of the hard masks 122 (in the center of the hard mask 122) can be in the range of approximately 2 nm to approximately 8 nm.

[0054] With reference to Fig. 17A and Fig. In step 17B, gate dielectrics 62 and gate electrodes 68 are formed, thereby forming replacement gate stacks 70. The corresponding process is described as process 232 in the Fig. The process flow 200 is shown in Figure 19. According to some embodiments, each gate dielectric 62 has an interface layer and a high-k dielectric layer on the interface layer. The interface layer can be formed from or contain silicon oxide, which can be deposited by a conformal deposition process, such as ALD or CVD, or by an oxidation process. According to some embodiments, the interface layer can be formed on both the nanostructures 22B and the semiconductor webs 20'. According to some embodiments, the high-k dielectric layers comprise one or more high-k dielectric layers. For example, the high-k dielectric layer(s) can contain a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof.

[0055] Gate electrodes 68 are also formed. During formation, conductive layers are first formed on the high-k dielectric layer, and the remaining sections of the recesses 58 are filled. The gate electrodes 68 can consist of a metal-containing material, such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multiple layers thereof. For example, the gate electrodes 68 can have any number of layers, any number of exit work layers, and possibly a filler material. The gate dielectrics 62 and the gate electrodes 68 also fill the spaces between adjacent nanostructures 22B and the spaces between the lower portions of the nanostructures 22B and the underlying substrate strips 20'.

[0056] After the recesses 58 are filled, a planarization process, such as a CMP process or a mechanical grinding process, is performed to remove the excess sections of the gate dielectrics 62 and the gate electrodes 68, which are located above the top surface of the ILD 52. The gate electrodes 68 and the gate dielectrics 62 are collectively referred to as the gate stack 70 of the resulting transistors.

[0057] In the Fig. 18A and Fig. In the processes shown in Figure 18B, the gate stacks 70 are recessed, forming recesses directly above the gate stacks 70 and between opposing sections of the gate spacers 38. A gate mask 74, comprising one or more layers of a dielectric material such as silicon nitride, silicon oxynitride, or the like, is placed into each of the recesses, followed by a planarization process to remove excess sections of the dielectric material extending over the ILD 52.

[0058] Furthermore, how through Fig. 18A and Fig. As shown in Figure 18B, an ILD 76 is deposited over the ILD 52 and over the gate masks 74. An etch stop layer (not shown) may (or may not) be deposited prior to the formation of the ILD 76. According to some embodiments, the ILD 76 is formed using FCVC, CVC, PECVD, or the like. The ILD 76 is formed from a dielectric material, which may be selected from silicon dioxide, PSG, BSG, BPSG, USG, or the like.

[0059] The ILD 76, the ILD 52, the CESL 50, and the gate masks 74 are then etched to form recesses (occupied by contact plugs 80A and 80B) that expose the surfaces of the source / drain regions 48 and / or the gate stacks 70. Although Fig. Figure 18B shows that the contact plugs 80A and 80B are located in one cross-section; in various embodiments, the contact plugs 80A and 80B can be formed in different cross-sections, thereby reducing the risk of mutual short circuits.

[0060] After the recesses have been formed, silicide areas 78 are formed over the source / drain areas 48. The contact plugs 80B are then formed over the silicide areas 78. Additionally, the contacts 80A (which can also be referred to as gate contact plugs) are formed in the recesses and are located over the gate electrodes 68, making contact with them. The corresponding structure is also shown in Fig. 18A is shown. Transistor 82 is formed in this way.

[0061] The embodiments of the present disclosure exhibit several advantageous features. By forming a hard mask on a top surface of the STI regions, the hard mask protects the STI regions from being missed when the removable interposers are removed. The undesirable increase in parasitic capacitance between gate electrodes and semiconductor bridges is thus reduced.

[0062] According to some embodiments of the present disclosure, a method comprises: forming a region of shallow trench insulation adjacent to a protruding fin; forming a hard mask on the region of shallow trench insulation; forming a dummy gate stack over the protruding fin; removing a sacrificial layer in the protruding fin to leave a space between a first semiconductor nanostructure and a second semiconductor nanostructure, wherein the first semiconductor nanostructure and the second semiconductor nanostructure are contained in the protruding fin; forming a removable interposer in the space; removing the dummy gate stack; removing the removable interposer using an etching chemical, wherein, when the removable interposer is removed, the hard mask is exposed to the etching chemical, and a lower portion of the hard mask remains after the removable interposer has been removed;and forming a gate stack, with a section of the gate stack being placed into the room.;

[0063] In one embodiment, the hard mask is deposited such that it comprises: an upper section that overlaps the protruding fin and has a first thickness; and a sidewall section on a sidewall of the protruding fin, which has a second thickness that is less than the first thickness. In one embodiment, the method further comprises: removing the upper section and the sidewall section before the dummy gate stack is formed, leaving a lower section of the hard mask. In one embodiment, forming the hard mask includes forming a silicon nitride layer. In one embodiment, forming the silicon nitride layer comprises multiple cycles, and each of the multiple cycles comprises depositing a silicon layer; and performing a nitriding process on the silicon layer.

[0064] In one embodiment, the deposition of the silicon layer is carried out with applied bias power, and the silicon nitride layer generated by the nitriding process has a sidewall thickness and a bottom wall thickness that is greater than the sidewall thickness. In another embodiment, the method further comprises, before the hard mask is formed, the deposition of a dielectric layer on the protruding fin.

[0065] In one embodiment, the dielectric layer has the same dielectric material as the flat trench insulation region. In another embodiment, when the removable interposer is etched, the flat trench insulation region is separated from the etching chemical by the lower portion of the hard mask. In another embodiment, the gate stack contacts the lower portion of the hard mask.

[0066] According to some embodiments of the present disclosure, a structure comprises: a semiconductor bridge; a first semiconductor nanostructure overlapping and spaced apart from the semiconductor bridge; a region of shallow trench insulation contacting an edge of the semiconductor bridge; a gate stack having a first section between the first semiconductor nanostructure and the semiconductor bridge; and a hard mask between the region of shallow trench insulation and the gate stack. In one embodiment, the hard mask comprises a different dielectric material than the region of shallow trench insulation.

[0067] In one embodiment, the hard mask comprises silicon nitride, and the flat trench insulation region comprises silicon oxide. In another embodiment, the structure further comprises a dielectric liner between and in contact with the hard mask and the semiconductor bridge. In yet another embodiment, the structure further comprises a second semiconductor nanostructure that overlaps and is spaced apart from the first semiconductor nanostructure, the gate stack further comprising a third section between the first and second semiconductor nanostructures. In another embodiment, a top end of the hard mask is lower than a top end of the semiconductor bridge.

[0068] According to some embodiments of the present disclosure, a structure comprises: a semiconductor substrate; a region of shallow trench insulation in the semiconductor substrate, wherein a section of the semiconductor substrate is adjacent to and contacts the region of shallow trench insulation to act as a semiconductor bridge; a dielectric liner over and in contact with the region of shallow trench insulation; a dielectric hard mask over the dielectric liner, wherein a sidewall section of the dielectric liner has opposing sidewalls that contact the dielectric hard mask and the semiconductor bridge; and a gate stack over and in contact with the dielectric hard mask.

[0069] In one embodiment, the dielectric hard mask is formed from a different material than the flat trench insulation region. In another embodiment, the dielectric hard mask has a curved upper surface, wherein a central section of the curved upper surface is lower than sections of the curved upper surface on opposite sides of the central section. In yet another embodiment, the structure further comprises multiple semiconductor nanostructures, wherein upper sections of the multiple semiconductor nanostructures overlap lower sections of the multiple semiconductor nanostructures, and wherein the gate stack includes sections between adjacent sections of the multiple semiconductor nanostructures.

[0070] The foregoing outlines features of several embodiments so that a person skilled in the art can better understand the aspects of the present disclosure. A person skilled in the art should recognize that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to accomplish the same tasks and / or achieve the same advantages as the embodiments presented herein. A person skilled in the art should also understand that such equivalent embodiments do not deviate from the inventive concept and scope of the present disclosure, and that they can make various changes, substitutions, and modifications here without deviating from the inventive concept and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 651,043

[0001]

Claims

[1] Procedure, encompassing: Forming an area of ​​shallow trench isolation next to a protruding fin, wherein the protruding fin has a first semiconductor nanostructure and a second semiconductor nanostructure, Forming a hard mask in the field of shallow trench isolation, Training a dummy gate stack over the protruding fin, Removing a sacrificial layer in the protruding fin to leave a space between the first semiconductor nanostructure and the second semiconductor nanostructure, Forming a removable interposer in the space, Removing the dummy gate stack, Removal of the removable interposer using an etching chemical, wherein, when the removable interposer is removed, the hard mask is exposed to the etching chemical, and Forming a gate stack, with a section of the gate stack being placed into the room. [2] Method according to claim 1, wherein the hard mask is deposited such that it has: an upper section that overlaps the protruding fin and has an initial thickness, and a side wall section on a side wall of the protruding fin, which has a second thickness that is smaller than the first thickness. [3] Method according to claim 2, further comprising: Before the dummy gate stack is formed, the upper section and the side wall section are removed, leaving a lower section of the hard mask. [4] Method according to claim 1, wherein a lower section of the hard mask remains after the removable interposer has been removed. [5] Method according to claim 4, wherein forming the hard mask comprises several cycles, and each of the several cycles comprises: Deposition of a silicon layer, and Performing a nitriding process on the silicon layer. [6] Method according to claim 5, wherein the deposition of the silicon layer is carried out with applied preload power, and the hard mask has a sidewall thickness and a bottom wall thickness which is greater than the sidewall thickness. [7] The method of claim 1, further comprising, before the hard mask is formed, the deposition of a dielectric layer on the protruding fin. [8] Method according to claim 7, wherein the dielectric layer has the same dielectric material as the area of ​​shallow trench insulation. [9] Method according to claim 1, wherein, when the removable interposer is etched, the area of ​​shallow trench isolation is separated from the etching chemical by a lower section of the hard mask. [10] Method according to claim 9, wherein the gate stack contacts the lower section of the hard mask. [11] Procedure, encompassing: Forming an area of ​​shallow trench insulation in a semiconductor substrate, wherein a portion of the semiconductor substrate forms a semiconductor protrusion adjacent to the semiconductor substrate, Forming a first semiconductor nanostructure that overlaps and is spaced away from the semiconductor protrusion, Forming a hard mask over the area of ​​shallow trench isolation, and Forming a gate stack, exhibiting: a first section between the first semiconductor nanostructure and the semiconductor protrusion, and a second section, with the hard mask located between the area of ​​shallow trench isolation and the second section of the gate stack. [12] Method according to claim 11, wherein the hard mask has a different dielectric material than the area of ​​shallow trench insulation. [13] Method according to claim 12, wherein the formation of the hard mask comprises a deposition process and an etching process following the deposition process. [14] Method according to any one of claims 11 to 13, further comprising forming a dielectric liner between the hard mask and the semiconductor protrusion and in contact with them. [15] Method according to any one of claims 11 to 14, further comprising forming a second semiconductor nanostructure which overlaps and is spaced apart from the first semiconductor nanostructure, wherein the gate stack further comprises a third section between the first semiconductor nanostructure and the second semiconductor nanostructure. [16] Method according to any one of claims 11 to 15, wherein an upper end of the hard mask is lower than an upper surface of the semiconductor protrusion. [17] Procedures, including: Forming a shallow trench insulation region in a semiconductor substrate, wherein a section of the semiconductor substrate is adjacent to and contacts the shallow trench insulation region to act as a semiconductor bridge. Forming a dielectric liner over and in contact with the area of ​​shallow trench insulation, Forming a dielectric hard mask over the dielectric liner, wherein a sidewall section of the dielectric liner has opposing sidewalls that contact the dielectric hard mask and the semiconductor bridge, and Forming a gate stack above and in contact with the dielectric hard mask. [18] Method according to claim 17, wherein the dielectric hard mask is formed from a different material than the area of ​​shallow trench insulation. [19] Method according to claim 17 or 18, wherein at a time when the gate stack is formed the dielectric hard mask has a curved upper surface, wherein a central section of the curved upper surface is lower than sections of the curved upper surface on opposite sides of the central section. [20] Method according to any one of claims 17 to 19, wherein the formation of the dielectric hard mask comprises a deposition process and an etching process following the deposition process.

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