Semiconductor gate structure and method for forming it

Abstract

One method comprises depositing a gate dielectric layer on a first channel region; depositing a p-function matching layer on the gate dielectric layer; exposing the p-function matching layer to a silicon-based precursor for a time period; and depositing an n-function matching layer on the p-function matching layer. Exposing the p-function matching layer to the silicon-based precursor can form a silicon-containing layer on the p-function matching layer.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority over the preliminary US patent application No. 63 / 638,492, filed on April 25, 2024, which is incorporated by reference into the present application. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of a material over a semiconductor substrate, and structuring the various material layers using lithography to create circuit components and elements on them.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature sizes are reduced, additional problems arise that should be addressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It is understood that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 illustrates an example of a nanostructured field-effect transistor (nanostructured FET) in a three-dimensional view according to some embodiments. The Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8A, Fig. 8B, Fig. 8C, Fig. 9A, Fig. 9B, Fig. 9C, Fig. 10, Fig. 11A, Fig. 11B, Fig. 11C, Fig. 12A, Fig. 12B, Fig. 12C, Fig. 13A, Fig. 13B, Fig. 13C, Fig. 14A, Fig. 14B, Fig. 14C, Fig. 15A, Fig. 15B, Fig. 15C, Fig. 16A, Fig. 16B, Fig. 16C, Fig. 17A, Fig. 17B, Fig. 17C, Fig. 18A, Fig. 18B and Fig. Figure 18C shows views of intermediate stages in the fabrication of nanostructured FETs according to some embodiments. The Fig. 19A, Fig. 19B and Fig. Figures 19C are schematic illustrations of intermediate stages in a silicon soaking process according to some embodiments. The Fig. 20A, Fig. 20B, Fig. 20C, Fig. 21A, Fig. 21B, Fig. 21C, Fig. 22A, Fig. 22B, Fig. 22C, Fig. 23A, Fig. 23B and Fig. 23C are views of intermediate stages in the fabrication of nanostructured FETs according to some embodiments. The Fig. 24A, Fig. 24B and Fig. Figures 24C are schematic illustrations of intermediate stages in the formation of an n-output work matching layer according to some embodiments. Fig. Figure 25 illustrates a graph of the cultivation of an n-exit work matching layer according to some embodiments. The Fig. 26A, Fig. 26B, Fig. 26C, Fig. 27A, Fig. 27B, Fig. 27C, Fig. 28A, Fig. 28B and Fig. 28C are views of intermediate stages in the fabrication of nanostructured FETs according to some embodiments. The Fig. 29, Fig. 30, Fig. 31, Fig. 32 and Fig. Figure 33 shows views of intermediate stages in the fabrication of nanostructured FETs according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also embodiments in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves for simplicity and clarity and does not in itself indicate any relationship between the various designs and / or configurations discussed.

[0006] Furthermore, spatially related terms such as "underlying," "below," "lower," "above," "upper," and the like may be used herein for a more convenient description of the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. These spatially related terms are intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or with other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0007] In various embodiments, a silicon soaking process is performed on a p-type output function matching layer. The silicon soaking process modifies the surface properties of the p-type output function matching layer, resulting in the formation of less n-type output function matching material on the p-type layer. Reducing the amount of n-type output function matching material formed on the p-type layer in this way can decrease the amount of n-type output function matching material that diffuses into the underlying p-type output function matching layer. This can mitigate undesirable performance problems in p-type devices caused by the diffusion of n-type output function matching material, such as aluminum atoms, into the p-type output function matching layer.

[0008] Embodiments are described below in a specific context, namely a die comprising nanostructured field-effect transistors (e.g., “nanostructured FETs” or “nano-FETs”). However, various embodiments can be applied to dies comprising other types of transistors (e.g., fin field-effect transistors (FinFETs), planar transistors, or the like) instead of, or in combination with, the nanostructured FETs.

[0009] Fig. Figure 1 illustrates an example of nanostructured FETs (e.g., nanowire FETs, nanolayer FETs), gate-all-around FETs (GAA FETs), or the like, in a three-dimensional view according to some embodiments. Some features of the nanostructured FETs may be omitted for clarity. Fig. The nanostructured FETs feature nanostructures 66 (e.g., nanolayers, nanowires, or the like) over the fins 62 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructures 66 are semiconductor features that act as channel regions for the nanostructured FETs. Insulation regions 70, such as shallow trench isolation regions (STI regions), are arranged between adjacent fins 62, which may project above and between adjacent isolation regions 70. The nanostructures 66 are arranged above and between adjacent isolation regions 70. Although the isolation regions 70 are described / illustrated as separate from the substrate 50, the term "substrate" as used herein may refer to the semiconductor substrate alone or to a combination of the semiconductor substrate and the isolation regions.Additionally, although a lower section of the fins 62 is illustrated as a single element, continuous materials with the substrate 50, the lower section of the fins 62, and / or the substrate 50 can comprise a single material or a plurality of materials. In this context, the fins 62 refer to the section extending between the adjacent isolation regions 70.

[0010] Gate dielectrics 110 are located above the upper surfaces of the fins 62 and along the upper surfaces, sidewalls, and lower surfaces of the nanostructures 66. Gate electrodes 120 are located above the gate dielectrics 110. The gate electrodes 120 can have one or more exit working layers (not shown separately in Fig. (1 illustrated) over the gate dielectrics 110 and a filler material over the exit layer(s). Source / drain regions 100 are arranged on the fins 62 on opposite sides of the gate dielectrics 110 and the gate electrodes 120. The source / drain region(s) 100 can refer individually or collectively to a source or a drain, depending on the context. An interlayer dielectric (ILD) 104 is formed over the source / drain regions 100. Contacts (described below) with the source / drain regions 100 are formed by the ILD 104. The source / drain regions 100 can be shared between different nanostructures 66. For example, adjacent source / drain regions 100 can be electrically connected, such as by fusing or joining the source / drain regions 100 by epitaxial growth or by coupling the source / drain regions 100 with the same contact.

[0011] Fig. Figure 1 further illustrates reference cross-sections used in later figures. Cross-section AA' is located along a longitudinal axis of a fin 62 of a nanostructured FET and in a direction of, for example, current flow between the source / drain regions 100 of the nanostructured FET. Cross-section BB' is perpendicular to cross-section AA' and extends through the source / drain regions 100 of the nanostructured FETs. Cross-section CC' is parallel to cross-section BB' and is located along a longitudinal axis of a gate electrode 120. For clarity, the following figures refer to these reference cross-sections.

[0012] Some embodiments discussed herein are related to nanostructured FETs fabricated using a gate-last process. In other embodiments, a gate-first process may be used. Likewise, some embodiments consider aspects used in planar devices, such as planar FETs, or in fin field-effect transistors (FinFETs), instead of or in combination with the nanostructured FETs. For example, FinFETs may have semiconductor fins on a substrate, wherein the semiconductor fins are semiconductor features that act as channel regions for the FinFETs. Similarly, planar FETs may have a substrate, wherein planar sections of the substrate are semiconductor features that act as channel regions for the planar FETs.

[0013] The Fig. Figures 2-28C show views of intermediate steps in the fabrication of nanostructured FETs according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6 and Fig. 7 are three-dimensional views that provide a similar three-dimensional view to Fig. Show 1. The Fig. 8A, Fig. 9A, Fig. 10, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A, Fig. 20A, Fig. 21A, Fig. 22A, Fig. 23A, Fig. 26A, Fig. 27A and Fig. 28A illustrates cross-sectional views along a cross-section similar to the reference cross-section AA' in Fig. 1. The Fig. 8B, Fig. 9B, Fig. 11B, Fig. 12B, Fig. 13B, Fig. 14B, Fig. 15B, Fig. 16B, Fig. 17B, Fig. 18B, Fig. 20B, Fig. 21B, Fig. 22B, Fig. 23B, Fig. 26B, Fig. 27B and Fig. Figure 28B illustrates cross-sectional views along a cross-section similar to the reference cross-section BB' in Fig. 1. The Fig. 8C, Fig. 9C, Fig. 11C, Fig. 12C, Fig. 13C, Fig. 14C, Fig. 15C, Fig. 16C, Fig. 17C, Fig. 18C, Fig. 20C, Fig. 21C, Fig. 22C, Fig. 23C, Fig. 26C, Fig. 27C and Fig. 28C illustrate cross-sectional views along a cross-section similar to the reference cross-section CC' in Fig. 1.

[0014] In Fig. 2. A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a silicon-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates may also be used, such as a multilayer substrate or a gradient substrate.In some embodiments, the semiconductor material of the substrate 50 may comprise silicon; germanium; a composite semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof.

[0015] The substrate 50 has an n-region 50N and a p-region 50P. The n-region 50N can be used to form n-devices, such as NMOS transistors, e.g., n-nanostructure FETs, and the p-region 50P can be used to form p-devices, such as PMOS transistors, e.g., p-nanostructure FETs. The n-region 50N may (or may not) be physically separated from the p-region 50P (not illustrated separately), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be placed between the n-region 50N and the p-region 50P. Although one n-region 50N and one p-region 50P are illustrated, any number of n-regions 50N and p-regions 50P can be provided.

[0016] Furthermore, in Fig. 2. A multilayer stack 52 is formed on the substrate 50. The multilayer stack 52 has alternating first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layers 54 are formed from a first semiconductor material, and the second semiconductor layers 56 are formed from a second semiconductor material. The semiconductor materials can each be selected from the candidate semiconductor materials of the substrate 50.

[0017] In the illustrated embodiment, and as will be described in more detail below, the first semiconductor layers 54 are removed and the second semiconductor layers 56 are structured to form channel regions for the nanostructured FETs in both the n-region 50N and the p-region 50P. In such embodiments, the channel regions in both the n-region 50N and the p-region 50P can have the same material composition (e.g., silicon or another semiconductor material) and be formed simultaneously. The first semiconductor layers 54 are dummy layers that are removed in a subsequent processing step to expose the top and bottom faces of the second semiconductor layers 56. The first semiconductor material of the first semiconductor layers 54 is a material that exhibits high etch selectivity with respect to the etching of the second semiconductor layers 56, such as silicon germanium.The second semiconductor material of the second semiconductor layers 56 is a material suitable for both n- and p-type devices, such as silicon.

[0018] In another embodiment (not shown separately), the first semiconductor layers 54 are structured to form channel regions for nanostructured FETs in one region (e.g., the p-region 50P), and the second semiconductor layers 56 are structured to form channel regions for nanostructured FETs in another region (e.g., the n-region 50N). The first semiconductor material of the first semiconductor layers 54 can be a material suitable for p-type devices, such as silicon germanium (e.g., Si3). x Ge 1-x, where x can be in the range of 0 to 1), pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The second semiconductor material of the second semiconductor layers 56 can be a material suitable for n devices, such as silicon, silicon carbide, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The first semiconductor material and the second semiconductor material can exhibit high etch selectivity with respect to each other, such that the first semiconductor layers 54 can be removed without significantly removing the second semiconductor layers 56 in the n-region 50N, and the second semiconductor layers 56 can be removed without significantly removing the first semiconductor layers 54 in the p-region 50P.

[0019] The multilayer stack 52 is illustrated as having three of the first semiconductor layers 54 and three of the second semiconductor layers 56. It should be noted that the multilayer stack 52 can have any number of first semiconductor layers 54 and second semiconductor layers 56. Each of the layers of the multilayer stack 52 can be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or the like. In some embodiments, some layers of the multilayer stack 52 are thinner than other layers of the multilayer stack 52.

[0020] In Fig. 3. Fins 62 are formed in the substrate 50, and nanostructures 64 and nanostructures 66 (collectively referred to as "nanostructures 64 / 66") are formed in the multilayer stack 52. In some embodiments, the nanostructures 64 / 66 and the fins 62 in the multilayer stack 52 and the substrate 50 can each be formed by etching trenches in the multilayer stack 52 and the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching can be anisotropic. The formation of the nanostructures 64 / 66 by etching the multilayer stack 52 can further define first nanostructures 64 from the first semiconductor layers 54 and second nanostructures 66 from the second semiconductor layers 56.

[0021] The fins 62 and the nanostructures 64 / 66 can be structured by any suitable method. For example, the fins 62 and the nanostructures 64 / 66 can be structured using one or more photolithography processes, including dual-structuring or multiple-structuring processes. In general, dual-structuring or multiple-structuring processes combine photolithography and self-alignment processes, making it possible to create structures that, for example, have spacings smaller than those that can otherwise be obtained using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-alignment process.The sacrificial layer is then removed and the remaining spacers can then be used to structure the fins 62 and the nanostructures 64 / 66.

[0022] The fins 62 are illustrated to have essentially the same widths in both the n-region 50N and the p-region 50P. In some embodiments, the widths of the fins 62 in the n-region 50N may be greater or lesser than the width of the fins 62 in the p-region 50P. Furthermore, although each of the fins 62 and the nanostructures 64 / 66 is illustrated to have a constant width throughout, in other embodiments the fins 62 and / or the nanostructures 64 / 66 may have tapered sidewalls such that the width of each of the fins 62 and / or the nanostructures 64 / 66 increases continuously in one direction towards the substrate 50. In such embodiments, each of the nanostructures 64 / 66 may have a different width and be trapezoidal.

[0023] In Fig. In embodiment 4, an insulating material 68 is formed over the substrate 50 and between adjacent fins 62 and adjacent nanostructures 64 / 66. The insulating material 68 can be an oxide, such as silicon dioxide, a nitride, the like, or a combination thereof, and can be formed by high-density plasma deposition modeling (HDP-CVD), flowable deposition modeling (FCVD), the like, or a combination thereof. Other insulating materials formed by any acceptable process may be used. In some embodiments, the insulating material 68 comprises silicon dioxide formed by an FCVD process. An annealing process may be performed after the insulating material 68 is formed. Although the insulating material 68 is illustrated as a single layer, some embodiments may use multiple layers.For example, in some embodiments, a lining (not shown separately) can first be formed along a surface of the substrate 50, the fins 62, and the nanostructures 64 / 66. A filler material, such as one of the previously described insulating materials, can then be formed over the lining.

[0024] The insulating material 68 can be deposited over the fins 62 and the nanostructures 64 / 66, such that excess insulating material 68 covers the nanostructures 64 / 66. A removal process is then applied to the insulating material 68 to remove the excess insulating material covering the nanostructures 64 / 66. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, can be used. The planarization process exposes the nanostructures 64 / 66 so that the upper surfaces of the nanostructures 64 / 66 and the insulating material 68 lie on the same plane after the planarization process is complete.

[0025] In Fig. In section 5, the insulating material 68 is recessed to form STI regions 70. The STI regions 70 are adjacent to the fins 62. The insulating material 68 is recessed such that the upper portions of the fins 62 and / or the nanostructures 64 / 66 project between adjacent STI regions 70. The upper portions of the fins 62 and / or the nanostructures 64 / 66 are located above the STI regions 70. Furthermore, the upper surfaces of the STI regions 70 can have a flat surface, a convex surface, a concave surface (such as molds), or a combination thereof, as illustrated. The upper surfaces of the STI regions 70 can be formed as flat, convex, and / or concave by suitable etching. The STI regions 70 can be spared using an acceptable etching process, such as one that is selective with respect to the insulating material 68 (e.g.The insulating material 68 etches at a faster rate than the materials of the fins 62 and the nanostructures 64 / 66). For example, oxide removal can be carried out using, for example, dilute hydrofluoric acid (dHF acid).

[0026] The process described above is only one example of how the fins 62 and the nanostructures 64 / 66 can be formed. In some embodiments, the fins 62 and / or the nanostructures 64 / 66 can be formed using a mask and an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be grown epitaxially in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 62 and / or the nanostructures 64 / 66. The epitaxial structures can comprise the previously described alternating semiconductor materials, such as the first semiconductor materials and the second semiconductor materials.In some embodiments in which epitaxial structures are grown epitaxially, the epitaxially grown materials can be doped on-site during the growing process, which may eliminate the need for prior and / or subsequent implantations, although on-site doping and implantation doping can be used together.

[0027] Furthermore, suitable wells (not illustrated separately) can be formed in the fins 62, the nanostructures 64 / 66, and / or the STI regions 70. In embodiments with different well types, different implantation steps for the n-region 50N and the p-region 50P can be achieved using a photoresist or other mask (not illustrated separately). For example, a photoresist can be formed over the fins 62, the nanostructures 64 / 66, and the STI regions 70 in the n-region 50N and the p-region 50P. The photoresist is structured to expose the p-region 50P. The photoresist can be formed using a spin-coating technique and can be structured using acceptable photolithography techniques.After the photoresist is structured, an n-impurity implantation is performed in the p-region 50P, and the photoresist can act as a mask to essentially prevent n-impurities from being implanted into the n-region 50N. The n-impurities can be phosphorus, arsenic, antimony, or the like, present in the region at a concentration in the range of approximately 10. 13 atoms / cm² 3 up to about 10 14 atoms / cm² 3 The photoresist is implanted. After implantation, it is removed, for example by an acceptable ashing process.

[0028] Prior to or following the implantation of the p-region 50P, a photoresist or other mask (not shown separately) is formed over the fins 62, the nanostructures 64 / 66, and the STI regions 70 in the p-region 50P and the n-region 50N. The photoresist is patterned to expose the n-region 50N. The photoresist can be formed using a spin-casting technique and can be patterned using acceptable photolithography techniques. After the photoresist is patterned, p-impurity implantation can be performed in the n-region 50N, and the photoresist can act as a mask to essentially prevent p-impurities from being implanted into the p-region 50P. The p-impurities can be boron, boron fluoride, indium, or the like, present in the region at a concentration in the range of approximately 10 13 atoms / cm² 3 up to about 10 14 atoms / cm² 3It can be implanted. After implantation, the photoresist can be removed, for example by an acceptable ashing process.

[0029] Following the implantation of the n-region 50N and the p-region 50P, annealing can be performed to repair the implantation damage and activate the implanted p- and / or n-impurities. In some embodiments, the grown epitaxial fin materials can be doped in place during growth, which may eliminate the need for implantation, although in-place and implantation doping can be used together.

[0030] In Fig. A dummy dielectric layer 72 is formed on the fins 62 and / or the nanostructures 64 / 66. The dummy dielectric layer 72 can be formed from silicon oxide, silicon nitride, a combination thereof, or the like, which can be thermally grown or deposited according to acceptable techniques. A dummy gate layer 74 is formed over the dummy dielectric layer 72, and a mask layer 76 is formed over the dummy gate layer 74. The dummy gate layer 74 can be deposited over the dummy dielectric layer 72 and then planarized, for example by a CMP process or the like. The dummy gate layer 74 can be formed from a conductive or non-conductive material and can be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides and metals.The dummy gate layer 74 material can be deposited by CVD, physical vapor deposition (PVD), sputtering, or other techniques for depositing the selected material. The dummy gate layer 74 can be formed from other materials exhibiting high etch selectivity with respect to insulating materials, such as the STI regions 70 and / or the dummy dielectric layer 72. The mask layer 76 can be deposited over the dummy gate layer 74. The mask layer 76 can be formed from a dielectric material such as silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 74 and a single mask layer 76 are formed over the n-region 50N and the p-region 50P, respectively.In the illustrated embodiment, the dummy dielectric layer 72 covers the STI regions 70, such that the dummy dielectric layer 72 extends between the dummy gate layer 74 and the STI regions 70. In another embodiment, the dummy dielectric layer 72 covers only the fins 62 and / or the nanostructures 64 / 66.

[0031] In Fig. In 7, the mask layer 76 is patterned using acceptable photolithography and etching techniques to form masks 86. The pattern of the masks 86 can then be transferred to the dummy gate layer 74 and the dummy dielectric layer 72 to form dummy gates 84 and dummy dielectrics 82, respectively. The dummy gates 84 cover respective channel regions of the nanostructures 64 / 66. The pattern of the masks 86 can be used to physically separate each dummy gate 84 from adjacent dummy gates 84. The dummy gates 84 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the respective fins 62. The masks 86 can optionally be removed after patterning, for example, by any acceptable etching technique.

[0032] In the Fig. 8A-8C is a spacer layer 90 conformally formed over the nanostructures 64 / 66 and the STI regions 70 on exposed sidewalls of the masks 86 (if present), the dummy gates 84, the dummy dielectrics 82, the nanostructures 64 / 66, and the fins 62. The spacer layer 90 can be formed from one or more dielectric materials. Fig. Figures 8A-8C show a spacer layer 90 formed from a single layer of dielectric material; however, in other embodiments, the spacer layer 90 may be formed from two or more layers of dielectric materials. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which may be formed by a deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. Other insulating materials formed by any acceptable process may be used. The spacer layer 90 is subsequently etched to form spacers.

[0033] In the Fig. In steps 9A-9C, the spacer layer 90 is patterned to form gate spacers 92 and fin spacers 94. Any acceptable etching process, such as dry etching, wet etching, the like, or a combination thereof, can be used to pattern the spacer layer 90. The etching can be anisotropic. When etched, the spacer layer 90 has sections left on the sidewalls of the dummy gates 84 (forming the gate spacers 92) and sections left on the sidewalls of the fins 62 and / or the nanostructures 64 / 66 (forming the fin spacers 94). After etching, the fin spacers 94 and / or the gate spacers 92 can have straight or curved sidewalls. Additionally, the STI regions 70 can also be etched if the spacer layer 90 is structured.The etching process can omit sections of the STI regions 70 between the fins 62.

[0034] Furthermore, implantations for lightly doped source / drain regions (LDD regions) (not illustrated separately) can be performed. In embodiments with different device types, similar to the implantations for the previously described basins, a mask, such as a photoresist, can be formed over the n-region 50N while the p-region 50P is exposed, and impurities of a suitable type (e.g., a p-type) can be implanted into the fins 62 and the nanostructures 64 / 66 exposed in the p-region 50P. The mask can then be removed. Subsequently, a mask, such as a photoresist, can be formed over the p-region 50P while the n-region 50N is exposed, and impurities of a suitable type (e.g., n-type) can be implanted into the fins 62 and the nanostructures 64 / 66 exposed in the n-region 50N. The mask can then be removed.The n-impurities can be any of the previously discussed n-impurities, and the p-impurities can be any of the previously discussed p-impurities. The lightly doped source / drain regions can have an impurity concentration in the range of approximately 10. 15 atoms / cm² 3 up to about 10 19 atoms / cm² 3 exhibiting [unclear]. Tempering can be used to repair implantation damage and activate the implanted impurities.

[0035] It should be noted that the preceding disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, a different sequence of steps can be used, additional spacers can be formed and removed, and / or the like. Furthermore, the n-devices and the p-devices can be formed using different structures and steps.

[0036] Further with reference to the Fig. In some embodiments, source / drain recesses 96 are structured in the fins 62, the nanostructures 64 / 66, and the substrate 50 as described in 9A-9C. Epitaxial source / drain regions are subsequently formed in the source / drain recesses 96. The source / drain recesses 96 can extend through the nanostructures 64 / 66 and into the substrate 50. In some embodiments, the fins 62 can be etched such that the lower surfaces of the source / drain recesses 96 are located below the upper surfaces of the STI regions 70. The source / drain recesses 96 can be formed by etching the fins 62, the nanostructures 64 / 66, and the substrate 50 using anisotropic etching processes such as RIE, NBE, or the like.In some embodiments, the gate spacers 92 and the dummy gates 84 mask sections of the fins 62, the nanostructures 64 / 66, and the substrate 50 during the etching processes used to form the source / drain recesses 96. A single etching process or multiple etching processes can be used to etch each layer of the nanostructures 64 / 66 and / or the fins 62. Time-controlled etching processes can be used to stop the etching of the source / drain recesses 96 after they reach a desired depth.

[0037] In Fig. 10. The source / drain recesses 96 are laterally extended to form sidewall recesses 97 in the first nanostructures 64 according to some embodiments. In particular, sections of the sidewalls of the first nanostructures 64 exposed by the source / drain recesses 96 can be recessed to form sidewall recesses 97. Accordingly, a sidewall recess 97 can have a height approximately the same as a height (e.g., a thickness) of its corresponding first nanostructure 64. Although sidewalls of the first nanostructures 64 within the sidewall recesses 97 are illustrated as flat, the sidewalls can be concave or convex. The sidewalls can be recessed by any acceptable etching process, such as one that is selective with respect to the material of the first nanostructures 64 (e.g.,The material of the first nanostructures 64 is selectively etched at a faster rate than the material of the second nanostructures 66. The etching can be isotropic. For example, if the second nanostructures 66 are formed from silicon and the first nanostructures 64 are formed from silicon germanium, the etching process can be wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. In another embodiment, the etching process can be dry etching using a fluorine-based gas, such as hydrogen fluoride gas (HF gas). In some cases, the etching process can slightly recess (e.g., remove sections of) the second nanostructures 66, which are exposed by the sidewall recesses 97 when the sidewall recesses 97 are formed (not illustrated). In such cases, a sidewall recess 97 can have a height greater than the height (e.g.,the thickness) of their corresponding first nanostructure 64. In some embodiments, the same etching process can be carried out continuously to form both the source / drain recesses 96 and to recess the sidewalls of the first nanostructures 64 to form the sidewall recesses 97. In some cases, the sidewall recesses 97 can be considered part of the source / drain recesses 96.

[0038] In the Fig. In some embodiments, internal spacers 98 are located in the sidewall recesses 97, as shown in sections 11A-11C. In other words, the internal spacers 98 are formed on the sidewalls of the remaining sections of the first nanostructures 64. As will be described in more detail below, source / drain regions are subsequently formed in the source / drain recesses 96, and the first nanostructures 64 are subsequently replaced by corresponding gate structures. The internal spacers 98 act as insulating features between the subsequently formed source / drain regions and the subsequently formed gate structures. Furthermore, the internal spacers 98 can be used to prevent damage to the subsequently formed source / drain regions by subsequent etching processes, such as those used to remove the first nanostructures 64.

[0039] In some embodiments, the inner spacers 98 are formed by conformal formation of an insulating material in the source / drain recesses 96 and in the sidewall recesses 97, followed by etching of the insulating material. The insulating material can be silicon nitride or silicon oxynitride, although any suitable material, such as materials with a low dielectric constant (a low k-value) with a k-value of less than about 3.5, can be used. The insulating material can be formed by a deposition process, such as ALD, CVD, or the like. The etching of the insulating material can be anisotropic. For example, the etching process can be a dry etching, such as RIE, NBE, or the like. After etching the insulating material, the remaining portions of the insulating material within the sidewall recesses 97 form the inner spacers 98.

[0040] Although the outer sidewalls of the inner spacers 98 are illustrated as flush (e.g., approximately coplanar) with the sidewalls of the second nanostructures 66, the outer sidewalls of the inner spacers 98 may extend beyond or be recessed from the sidewalls of the second nanostructures 66. In other words, the inner spacers 98 may partially fill, completely fill, or overfill the sidewall recesses 97. Furthermore, although the sidewalls of the inner spacers 98 are illustrated as flat, the sidewalls of the inner spacers 98 may be concave or convex. In some embodiments, an inner spacer 98 may have a thickness that is approximately equal to or greater than the thickness of an adjacent first nanostructure 64.

[0041] In the Fig. 12A-12C are epitaxial source / drain regions 100 formed in the source / drain recesses 96 of the n-region 50N and in the source / drain recesses 96 of the p-region 50P according to some embodiments. The epitaxial source / drain regions 100 in the n-region 50N can be referred to as "n-source / drain regions" and the epitaxial source / drain regions 100 in the p-region 50P can be referred to as "p-source / drain regions". The n-source / drain regions 100 can be formed before, after, or simultaneously with the formation of the p-source / drain regions 100. In other embodiments, a semiconductor layer (not illustrated) can be formed in the source / drain recesses 96 prior to the formation of the epitaxial source / drain regions 100 in the source / drain recesses 96. The semiconductor layer can, for example, comprise undoped silicon or the like.In other embodiments, an insulating layer (not illustrated) can be deposited in the source / drain recesses before the epitaxial source / drain regions 100 are formed in the source / drain recesses 96.

[0042] In some embodiments, the epitaxial source / drain regions 100 exert a load in the respective channel regions of the second nanostructures 66 within the p-region 50P, thereby improving performance. The epitaxial source / drain regions 100 are formed in the source / drain recesses 96 such that each dummy gate 84 of the p-region 50P is positioned between respective adjacent pairs of the epitaxial source / drain regions 100. In some embodiments, the gate spacers 92 are used to separate the epitaxial source / drain regions 100 from the dummy gates 84, and the inner spacers 98 are used to separate the epitaxial source / drain regions 100 by a suitable lateral distance from the nanostructures 64, so that the epitaxial source / drain regions 100 do not short-circuit with subsequently formed gates of the resulting p-nanostructure FETs.

[0043] The epitaxial source / drain regions 100 may also have surfaces that are raised from the respective surfaces of the nanostructures 64 / 66 and may exhibit facets. For example, as a result of the epitaxial processes used to form the epitaxial source / drain regions 100, the upper surfaces of the epitaxial source / drain regions 100 may have facets that extend laterally beyond the sidewalls of the nanostructures 64 / 66. In some embodiments, these facets cause adjacent epitaxial source / drain regions 100 of the same nanostructure FET to be joined together. In other embodiments, adjacent epitaxial source / drain regions 100 remain separate after the epitaxial process is complete, as described by Fig. Figure 12B illustrates this. In the illustrated embodiments, the fin spacers 94 are formed on the upper surfaces of the STI regions 70, thereby blocking epitaxial growth. In some other embodiments, the fin spacers 94 can cover sections of the sidewalls of the nanostructures 64 / 66 and / or the fins 62, further blocking epitaxial growth. In another embodiment, the spacer etching used to form the gate spacers 92 is controlled such that the fin spacers 94 are not formed, allowing the epitaxial source / drain regions 100 to extend to the surface of the STI region 70. In some embodiments, the epitaxial source / drain regions 100 extend above the upper surface of the nanostructures 66.Consequently, the upper surface of an epitaxial source / drain region 100 can be located further away from the substrate 50 than the upper surface of the adjacent nanostructures 66.

[0044] The p-source / drain regions 100 can be formed by an epitaxial process, such as vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. The p-source / drain regions 100 can comprise any acceptable material suitable for p-nanostructure FETs. For example, if the second nanostructures 66 are formed from silicon, the p-source / drain regions 100 can comprise materials that exert compressive stress on the second nanostructures 66, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or the like. The p-source / drain regions 100 can be formed from a single layer of semiconductor material or from two or more sublayers of semiconductor materials.The epitaxial source / drain regions 100, the nanostructures 64 / 66 and / or the fins 62 within the p-region 50P can be implanted with dopants, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The p-source / drain regions 100 can accommodate an impurity concentration of between approximately 10. 19 atoms / cm² 3 up to about 10 21 atoms / cm² 3 exhibiting other concentrations. In some embodiments, the p-source / drain regions can be doped on-site during cultivation.

[0045] The n-source / drain regions 100 can be formed by an epitaxial process such as VPE, MBE, or the like. The n-source / drain regions 100 can comprise any acceptable material suitable for n-nanostructure FETs. For example, if the second nanostructures 66 are formed from silicon, the n-source / drain regions 100 can comprise materials that exert tensile stress on the second nanostructures 66, such as silicon, silicon carbide, phosphor-doped silicon carbide, silicon phosphide (SiP), or the like. The n-source / drain regions 100 can be formed from a single layer of semiconductor material or from two or more sublayers of semiconductor materials.The epitaxial source / drain regions 100, the nanostructures 64 / 66 and / or the fins 62 within the n-region 50N can be implanted with dopants, similar to the previously discussed process for forming lightly doped source / drain regions followed by annealing. The n-source / drain regions 100 can accommodate an impurity concentration of between approximately 10. 19 atoms / cm² 3 up to about 10 21 atoms / cm² 3 exhibiting other concentrations. In some embodiments, the n-source / drain regions can be doped on-site during cultivation.

[0046] In the Fig. 13A-13C is a first ILD 104 deposited over the epitaxial source / drain regions 100, the fin spacers 94, the gate spacers 92, the masks 86 (if present), and / or the dummy gates 84. The first ILD 104 can be formed from an electrical material deposited by any suitable process, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Suitable dielectric materials may include silicon dioxide, phosphosilicate glass (PSG), boron silicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used.

[0047] In some embodiments, a contact etch stop layer (CESL) 102 is formed between the first ILD 104 and the epitaxial source / drain regions 100, the fin spacers 94, the gate spacers 92, the masks 86 (if present), and / or the dummy gates 84. The CESL 102 can be formed from a dielectric material exhibiting high etch selectivity with respect to the etching of the first ILD 104, such as silicon nitride, silicon oxide, silicon oxynitride, a combination thereof, or the like, which can be formed using any suitable deposition process, such as CVD, ALD, or the like.

[0048] In the Fig. In 14A-14C, a removal process is performed to bring the top surfaces of the first ILD 104 to the same plane as the top surfaces of the gate spacers 92 and the masks 86 (if present) or the dummy gates 84. In some embodiments, the removal process includes a planarization process, such as chemical-mechanical polishing (CMP), grinding, etching, a combination thereof, or the like. The planarization process may also remove the masks 86 on the dummy gates 84 and sections of the gate spacers 92 along the sidewalls of the masks 86. After the planarization process, the top surfaces of the first ILD 104, the gate spacers 92, and the masks 86 (if present) and / or the dummy gates 84 are substantially on the same plane or substantially coplanar (within process variations).Accordingly, the upper surfaces of the masks 86 (if present) and / or the dummy gates 84 can be exposed by the first ILD 104.

[0049] In the Fig. In steps 15A-15C, the masks 86 (if present) and the dummy gates 84 are removed in one or more etching steps, creating recesses between the gate spacers 92. In some embodiments, the dummy gates 84 and the dummy dielectrics 82 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process that uses reactive gas(es) that selectively etch the dummy gate material 84 at a faster rate than the materials of the first ILD 104 and the gate spacers 92. Each recess exposes and / or lies over sections of nanostructures 64 / 66, which act as the channel regions in subsequently closed nanostructure FETs.Sections of the nanostructures 64 / 66, which act as the channel regions, are arranged between adjacent pairs of the epitaxial source / drain regions 100 in the n-region 50N or between adjacent pairs of the epitaxial source / drain regions 100 in the p-region 50P. During removal, the dummy dielectrics 82 can be used as etch stop layers when the dummy gates 84 are etched. The dummy dielectrics 82 can then be removed after the dummy gates 84 have been removed.

[0050] The remaining portions of the first nanostructures 64 are then removed to form openings 108 in regions between the second nanostructures 66. The remaining portions of the first nanostructures 64 can be removed by any acceptable etching process that selectively etches the material of the first nanostructures 64 at a faster rate than the material of the second nanostructures 66. The etching can be isotropic. For example, if the first nanostructures 64 are formed from silicon germanium and the second nanostructures 66 are formed from silicon, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH₄OH), or the like. In some embodiments, a trimming process (not illustrated separately) is performed to reduce the thicknesses of the exposed portions of the second nanostructures 66 and to enlarge the openings 108.In the following, the second nanostructures 66 can be referred to as nanostructures 66 and the nanostructures 66 above each fin 62 can be referred to as a “stack” of nanostructures 66.

[0051] The Fig. Figures 16A to 26C illustrate intermediate steps in the formation of replacement gates comprising gate dielectrics 110 and gate electrodes 120, according to some embodiments. Each pair of a gate dielectric 110 and a gate electrode 120 can be collectively referred to as a “gate structure” or a “gate stack.” Each gate structure is wrapped around a channel region of a nanostructure 66 such that the gate structure extends along sidewalls, a bottom surface, and a top surface of the nanostructure 66. Some of the gate structures also extend along the sidewalls and / or a top surface of a fin 62.

[0052] In the Fig. In embodiments 16A-16C, gate dielectrics 110 are formed as part of the replacement gates according to some embodiments. The gate dielectrics 110 have one or more gate dielectric layers arranged on the sidewalls and / or upper surfaces of the fins 62; on the upper surfaces, sidewalls, and lower surfaces of the channel regions of the nanostructures 66; on the sidewalls of the inner spacers 98 adjacent to the source / drain regions 100; and on the sidewalls of the gate spacers 92. In other words, the gate dielectrics 110 can be conformally deposited within the openings 108. The gate dielectrics 110 can also be formed on the upper surfaces of the gate spacers 92, the first ILD 104, and / or the CESL 102. The gate dielectrics 110 can be formed from an oxide, such as silicon oxide or a metal oxide, a silicate, such as a metal silicate, combinations thereof, multiple layers thereof or the like.Additionally or alternatively, the gate dielectrics 110 can be formed from a dielectric material with a high k-value (e.g., dielectric materials with a k-value greater than approximately 7.0), such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The dielectric material(s) of the gate dielectrics 110 can be formed by molecular beam deposition (MBD), ALD, PECVD, or the like. Although single-layer gate dielectrics 110 are illustrated, the gate dielectrics 110 can have any number of interface layers and any number of main layers. For example, the gate dielectrics 110 can have an interface layer and an overlying dielectric layer with a high k-value.The formation of the gate dielectrics 110 in the n-region 50N and the p-region 50P can occur simultaneously, so that the gate dielectrics 110 in each region are formed from the same materials. In some embodiments, the gate dielectrics 110 in each region can be formed by different processes, so that the gate dielectrics 110 can be made of different materials and / or have a different number of layers. Various masking steps can be used to mask and expose suitable regions when using different processes.

[0053] The Fig. Figures 17A to 27C illustrate intermediate steps in the formation of gate electrodes 120 as part of the replacement gates according to some embodiments. The gate electrodes 120 comprise one or more work function matching layers (“WF layers”) and a filler material formed over the WF layers, which are described in more detail below. The gate electrodes 120 can have any number of WF layers, any number of barrier layers, any number of adhesive layers, or other layers.

[0054] In the Fig. In some embodiments, a first WF layer 112 is deposited over the gate dielectrics 110, as described in 17A-17C. The first WF layer 112 can be conformally deposited within the openings 108. For example, the first WF layer 112 is deposited over the top surfaces, side walls, and bottom surfaces of the channel regions of the nanostructures 66. In some embodiments, the first WF layer 112 is deposited in both the n-region 50N and the p-region 50P using the same deposition process.

[0055] The first WF layer 112 comprises any acceptable material for adjusting the work function of a device in the p-region 50P to a desired level, depending on the application of the device to be formed. Accordingly, the first WF layer 112 can, in some cases, be considered a "p-work function matching layer" or "p-WF layer." For example, the first WF layer 112 can subsequently be used as a work function matching layer for nanostructured FETs in the p-region 50P. The first WF layer 112 can be deposited using any acceptable deposition process. For example, if the first WF layer 112 is a p-work function matching layer, it may be formed from a p-work function metal (PWFM), such as titanium nitride (TiN), tantalum nitride (TaN), combinations thereof or the like, which may be deposited by ALD, CVD, PVD or the like.Although the first WF layer 112 is shown as a single layer, it can be multilayered. For example, the first WF layer 112 can have a layer of titanium nitride and a layer of tantalum nitride. Other materials or combinations of materials are possible.

[0056] In the Fig. In some embodiments, 18A-18C, a silicon soaking process 114 is performed on the first WF layer 112. After performing the silicon soaking process 114, the first WF layer 112 is referred to herein as the first WF layer 112' after soaking or simply as the first WF layer 112'. The silicon soaking process 114 forms a silicon-containing layer on the first WF layer 112, which reduces the subsequent formation of a second WF layer, which is described in more detail below. The silicon soaking process 114 comprises placing the substrate 50 in a chamber and exposing the faces of the first WF layer 112 to a silicon-based precursor for a period of time.For example, in some embodiments, the silicon soaking process 114 comprises placing the substrate 50 into a chamber, introducing one or more silicon-based precursors into the chamber, and then closing the inlets and outlets of the chamber for a predetermined time. The silicon-based precursor adsorbs or reacts with the surfaces of the first WF layer 112, and the silicon-based precursor is ejected from the chamber after the predetermined time has elapsed. The chamber can be a process chamber of an ALD deposition system, a plasma-enhanced ALD deposition system (PEALD deposition system), a plasma-enhanced cyclic CVD system (PECCVD system), a pulsed CVD system, an implantation system, or any other suitable process chamber or chamber.Therefore, in some cases the silicon soaking process 114 can be considered an ALD process, a PEALD process, a PECVD process, a pulsed CVD process or the like.

[0057] The silicon soaking process 114 can be carried out at a temperature in the range of approximately 0 °C to approximately 900 °C and at a pressure in the range of approximately 0.5 Torr to approximately 20 Torr, for example, by maintaining the chamber at such a temperature and / or pressure. The silicon soaking process 114 can be carried out for a duration in the range of approximately 1 second to approximately 600 seconds, for example, by holding the silicon-based precursor in the chamber for such a duration. Exemplary silicon-based precursors can include molecules such as silanes, organosilanes, or the like (but are not limited to these). Silanes can be silane (SiH4), disilane (Si2H6), trisilane (Si3H8), tetrasilane (Si4H4), or silane (Si4H4). 10Organosilanes can comprise compounds with the empirical formula RySixH(2x+2-y), where R is independent of methyl, ethyl, propyl, butyl, or the like. For example, organosilanes can include methylsilane ((CH3)SiH3), dimethylsilane ((CH3)2SiH2), ethylsilane ((CH3CH2)SiH3), methyldisilane ((CH3)Si2H5), dimethyldisilane ((CH3)2Si2H4), hexamethyldisilane ((CH3)6Si2), tris(dimethylamino)silane (TDMAS), the like, or any combination thereof. Other parameters or precursors are possible. Controlling the parameters or precursors used for the silicon soaking process 114 can change the thickness (e.g., the number of monolayers), the composition (e.g., % silicon), or other characteristics of the silicon-containing layer formed by the silicon soaking process 114.

[0058] The Fig. 19A, Fig. 19B and Fig. Figure 19C illustrates intermediate steps in the formation of a first WF layer 112' after soaking using a silicon soaking process 114 according to some embodiments. Fig. Figure 19A schematically illustrates a cross-section of a section of the first WF layer 112 covering the gate dielectrics 110 before the silicon soaking process 114. Fig. Figure 19B schematically illustrates the first WF layer 112 and the gate dielectrics 110 during the silicon soaking process 114. Fig. Figure 19C schematically illustrates the gate dielectrics 110 and the first WF layer 112' after soaking, including a silicon-containing layer 116 after completion of the silicon soaking process 114. Fig. 19A-19C are intended to be illustrative examples, and other materials or configurations are possible.

[0059] Fig. Figure 19A illustrates the first WF layer 112 after deposition on the gate dielectrics 110, similar to the one in the Fig. Step 17A-17C is shown. For example, the first WF layer can comprise titanium nitride 112 or the like. As shown schematically in Fig. As shown in Figure 19A, the surface of the first WF layer 112 may be covered in hydroxide surface ligands (e.g., -OH compounds) or the like.

[0060] In Fig. In 19B, the first WF layer 112 is subjected to the silicon soaking process 114. The silicon-based precursors, schematically shown in Fig. 19B, represented by silane molecules, collide with or adsorb onto the surface of the first WF layer 112 and react with the hydroxide surface ligands. The reaction between the silicon-based precursors and the hydroxide surface ligands allows the silicon of the silicon-based precursors to bind to the oxygen on the surface of the first WF layer 112. This enables the formation of a silicon-containing layer 116 (see Fig. 19C) are formed on the surface of the first WF layer 112 when more silicon-based precursors react with the hydroxide surface ligands.

[0061] In Fig. In step 19C, the silicon soaking process 114 was carried out, forming a silicon-containing layer 116 that covers the first WF layer 112. The first WF layer 112 and the overlying silicon-containing layer 116 together form the first WF layer 112' after soaking. The silicon-containing layer 116 can comprise a single silicon-containing layer (e.g., a silicon-containing monolayer) or multiple silicon-containing layers (e.g., a silicon-containing multilayer). For example, in some embodiments, the silicon-containing layer 116 can comprise a monolayer of silicon oxide (e.g., SiO2) or multiple layers of silicon oxide (e.g., multiple layers of SiO2), although other layer compositions are possible. This allows hydroxide-OH compounds on the surfaces of the first WF layer 112 to be replaced by Si-O compounds (e.g. silicon-oxygen compounds) and / or Si-OH compounds (e.g.silicon hydroxide compounds) can be replaced using the silicon soaking process 114. In some cases, the silicon-containing layer 116 can have a thickness in the range of about 5 Å to about 50 Å.

[0062] In the Fig. In 20A-20C, a mask 117 is formed over the p-region 50P according to some embodiments. The mask 117 can, for example, comprise a photoresist, a multilayer photoresist structure, an antireflective coating (e.g., a BARC layer), or the like. The mask 117 can be formed using a suitable technique (e.g., spin coating or the like) and structured using suitable photolithography techniques to expose the n-region 50N. This protects the first WF layer 112' in the p-region 50P and exposes the first WF layer 112' in the n-region 50N.

[0063] In the Fig. In embodiments 21A-21C, an etching process is performed to remove the first WF layer 112' in the n-region 50N according to some embodiments. The etching process removes the silicon-containing layer 116 and the first WF layer 112 to expose the underlying gate dielectrics 110 of the n-region 50N. The mask 117 protects the first WF layer 112' in the p-region 50P from the etching process. The etching process may include a wet etching process and / or a dry etching process. In some cases, the etching process may selectively etch the first WF layer 112' with minimal etching or without etching the gate dielectrics 110.

[0064] In the Fig. At 22A-22C, mask 117 is removed from the p-region 50P. Mask 117 can be removed using a suitable technique, such as an etching process, an ashing process, or the like. After removal of mask 117, the gate dielectrics 110 in the n-region 50N are exposed, and the first WF layer 112' in the p-region 50P is exposed.

[0065] In the Fig. In embodiments 23A-23C, a second WF layer 118 is deposited over the gate dielectrics 110 in the n-region 50N and over the first WF layer 112' in the p-region 50P. The second WF layer 118 can be deposited conformally within the openings 108. For example, the second WF layer 118 is deposited over the top surfaces, sidewalls, and bottom surfaces of the channel regions of the nanostructures 66. The second WF layer 118 is deposited in both the n-region 50N and the p-region 50P using the same deposition process. As explained in more detail below, the silicon-containing layer 116 in the first WF layer 112' delays the formation of the second WF layer 118 in the p-region 50P during the deposition process. Accordingly, the second WF layer 118 formed in the p-region 50P can be thinner than the second WF layer 118 formed in the n-region 50N.In some cases, the second WF layer 118 formed on the first WF layer 112' in the p-region 50P is referred to herein as the second WF layer 118' to distinguish it from the second WF layer 118 formed on the gate dielectrics 110 in the n-region 50N. In other cases, the second WF layer 118 may refer, depending on the context, to either the second WF layer 118 formed in the n-region 50N or the second WF layer 118' formed in the p-region 50P. Forming a thinner second WF layer 118 in the p-region 50P can reduce the amount of material from the second WF layer 118 that undesirably diffuses into the first WF layer 112, which is described in more detail below.

[0066] The second WF layer 118 comprises any acceptable material(s) for adjusting the work function of a device in the n-region 50N to a desired level, depending on the application of the device to be formed. Accordingly, the second WF layer 118 can, in some cases, be considered an "n-work function matching layer" or "n-WF layer." For example, the second WF layer 118 can subsequently be used as a work function matching layer for nanostructured FETs in the n-region 50N. The second WF layer 118 can be formed using any acceptable deposition process.For example, if the second WF layer 118 is an n-type work function matching layer, it can be formed from an n-type work function metal (NWFM), such as titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), combinations thereof, or the like, which can be deposited by ALD, CVD, PVD, or the like. Although the second WF layer 118 is shown as a single layer, it can also be multilayer.

[0067] In embodiments where the second WF layer 118 is an n-work function matching layer, it may comprise a metallic element suitable for matching the threshold stresses of n-devices, such as aluminum. In some cases, aluminum in an n-work function matching layer may diffuse into underlying layers during subsequent process steps, particularly during elevated-temperature process steps. For structures in which an n-work function matching layer is deposited over a p-work function matching layer, the aluminum in the n-work function matching layer may diffuse into the p-work function matching layer, shifting the effective work function of the p-work function matching layer.Aluminum or other n-type work elements diffusing into the p-type work function matching layer can decrease the accuracy or uniformity of the work function matching in the p-region 50P and shift the effective work function of the p-type work function matching layer in ways that negatively affect device performance. For example, the presence of aluminum in the p-type work function matching layer can undesirably decrease the flat-band voltage in a p-MOS capacitor or undesirably increase the threshold voltage of a p-type transistor (e.g., a p-MOSFET, a p-type nanostructured FET, or the like).

[0068] Forming a thinner n-work function matching layer over a p-work function matching layer can reduce the amount of aluminum available to diffuse into the p-work function matching layer, and thus reduce the amount of aluminum that diffuses into it. By reducing the amount of aluminum diffusing into the p-work function matching layer, the degree to which the p-work function matching layer's work function is shifted by the presence of aluminum can be reduced, thereby improving device performance and uniformity.

[0069] Subjecting the first WF layer 112 of the p-region 50P to a silicon soaking process 114, as described herein, can modify the surface of the first WF layer 112 in a way that prevents the subsequent growth of the second WF layer 118 on the first WF layer 112. This allows a thinner second WF layer 118' to form on the first WF layer 112 in the p-region 50P, while the second WF layer 118 forms in the n-region 50N. Thus, the use of the silicon soaking process 114, as described herein, can reduce aluminum diffusion into the first WF layer 112, thereby improving the work function matching accuracy, improving device performance, and improving device uniformity.

[0070] With reference to the Fig. Figures 24A-24C show intermediate steps in the formation of a second WF layer 118' on a first WF layer 112' according to some embodiments. Fig. 24A and Fig. Figure 24B schematically illustrates cross-sections of a section of the first WF layer 112' during the deposition of the second WF layer 118'. Fig. Figure 24C schematically illustrates the formation of a section of a second WF layer 118'. Fig. Figures 24A-24C illustrate sections of the first WF layer 112' in the p-region 50P, which are similar to those in the Fig. The views shown in 19A-C may be. Fig. 24A-24C are intended to be illustrative examples, and other materials or configurations are possible.

[0071] The Fig. Figures 24A-24C illustrate an embodiment in which the second WF layer comprises titanium aluminum (TiAl) deposited using an aluminum-based precursor and a titanium-based precursor, although other materials or precursors are possible. For example, Figure 24A illustrates Fig. 19A the use of trimethylaluminium (TMA) (Al2(CH3)6) as an aluminum-based precursor and illustrates Fig. 19B the use of titanium tetrachloride (TiCl4) as a titanium-based precursor, although other precursors are possible.

[0072] In Fig. 24A is the first WF layer 112' exposed opposite the aluminium-based precursor, which adsorbs onto the Si-O / Si-OH compounds of the silicon-containing layer 116 and reacts with them to form SiOAl x to form compounds that include Al-O-Si compounds (e.g., aluminum-oxygen-silicon compounds, in Fig. 24B). For example, without the presence of the silicon-containing layer 116, the TMA molecules react with the -OH compounds (see Fig. 19A) on the first WF layer 112 to form Al-methyl compounds on the surface. The Si-O / Si-OH compounds in the silicon-containing layer 116 cause the TMA molecules to form Al-O-Si compounds above the first WF layer 112 instead of Al-methyl compounds. Fig. 24B shows a single monolayer of SiOAl x However, in other embodiments, multiple layers of SiOAl can be used. x be formed.

[0073] In Fig. In 24B, after the formation of Al-O-Si compounds, the first WF layer 112' is exposed relative to the titanium-based precursor. However, the titanium-based precursor does not react with the Al-O-Si compounds as readily as it does with other types of surfaces, such as Al-methyl compounds. Consequently, the formation of the initial titanium-aluminum layer is slowed down due to the reduced rate of reactions between the titanium-based precursor and the Al-O-Si compounds. This allows a thinner second WF layer 118' to form on top of the first WF layer 112'. Fig. Figure 24C illustrates a second WF layer 118' comprising a monolayer of titanium aluminum, however, in other cases, multiple cycles of the aluminum-based precursor and the titanium-based precursor can be used to form multiple layers of titanium aluminum.

[0074] In some cases, a second WF layer 118' formed over a first WF layer 112' with a silicon-containing layer 116, as described herein, can have a thickness that is between about 0% and about 30% smaller than the thickness of a second WF layer 118 formed over a first WF layer 112 without a silicon-containing layer 116. In some cases, the second WF layer 118' in the p-region 50P can have a thickness in the range of about 10 Å to about 50 Å, although other thicknesses are possible.

[0075] As an example, it illustrates Fig. Figure 25 shows a graph of experimental data illustrating the thickness of titanium aluminum formed using multiple cycles. The closed circles represent titanium aluminum formed on a layer of titanium nitride that has not undergone a silicon soaking process 114, and the open circles represent titanium aluminum formed on a layer of titanium nitride that has undergone a silicon soaking process 114. As in Fig. As shown in Figure 25, even over several growth cycles, the titanium aluminum formed via titanium nitride with a silicon soaking process 114 exhibits a smaller thickness than the titanium aluminum formed via titanium nitride without a silicon soaking process 114. Accordingly, Figure 200 shows that the silicon soaking process 114, as described herein, can reduce the growth rate and the final thickness of the second WF layer 118. Figure 200 is representative, and other thicknesses or growth rates are possible.

[0076] The Fig. Figures 26A-26C illustrate the formation of the filler material 121 for forming gate electrodes 120 in the n-region 50N and the p-region 50P according to some embodiments. The filler material 121 is deposited over the second WF layer 118 in the n-region 50N to form gate electrodes 120 in the n-region 50N. The filler material 121 is deposited over the first WF layer 112' and the second WF layer 118' in the p-region 50P to form gate electrodes 120 in the p-region 50P. The filler material 121 fills the remaining portions of the openings 108. The filler material 121 can be any acceptable material with low resistance. For example, the filler material 121 can be made of a metal such as tungsten, aluminum, cobalt, ruthenium, combinations thereof, or the like, which can be deposited by ALD, CVD, PVD, or the like. Other materials or deposition techniques are possible.

[0077] A removal process can then be carried out to remove the excess sections of the gate dielectric layer(s) and the gate electrode layer(s), wherein the excess sections are located above the upper surfaces of the first ILD 104, the CESL 102, and the gate spacer 92. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a re-etching process, a combination thereof, or the like, can be used. The remaining sections of the gate dielectric layer(s) form the gate dielectrics 110, and the remaining sections of the gate electrode layer(s) form the gate electrodes 120. When a planarization process is used, the top surfaces of the gate spacers 92, the CESL 102, the first ILD 104, the gate dielectrics 110, and the gate electrodes 120 are on the same plane or are coplanar (within process variations).

[0078] In the Fig. In 27A-27C, a second ILD 124 is deposited over the gate spacers 92, the CESL 102, the first ILD 104, the gate dielectrics 110, and the gate electrodes 120. In some embodiments, the second ILD 124 is a flowable film formed by a flowable CVD process. In other embodiments, the second ILD 124 is formed from a dielectric material, such as PSG, BSG, BPSG, USG, or the like, which can be formed by any suitable deposition process, such as CVD, PECVD, or the like.

[0079] In some embodiments, an etch stop layer (ESL) 122 is formed between the second ILD 124 and the gate spacers 92, the CESL 102, the first ILD 104, the gate dielectrics 110, and the gate electrodes 120. The ESL 122 can be formed from a dielectric material exhibiting high etch selectivity with respect to the etching of the second ILD 124, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which can be formed by any suitable deposition process, such as CVD, ALD, or the like.

[0080] In the Fig. In components 28A-28C, gate contacts 126 and source / drain contacts 128 are formed to contact the gate electrodes 120 and the source / drain regions 100, respectively. The gate contacts 126 can be physically and electrically coupled to the gate electrodes 120. The source / drain contacts 128 can be physically and electrically coupled to the source / drain regions 100.

[0081] As an example of forming the gate contacts 126 and the source / drain contacts 128, openings for the gate contacts 126 are formed by the second ILD 124 and the ESL 122, and openings for the source / drain contacts 128 are formed by the second ILD 124, the ESL 122, the first ILD 104, and the CESL 102. The openings can be formed by using acceptable photolithography and etching techniques. A lining (not illustrated separately), such as a diffusion barrier layer, an adhesive layer, or the like, and a conductive material are formed in the openings. The lining can contain titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, can be performed to remove excess material from a surface of the second ILD 124.The remaining lining and conductive material form the gate contacts 126 and the source / drain contacts 128 in the openings. The gate contacts 126 and the source / drain contacts 128 can be formed in different processes or in the same process. Although they are shown formed in the same cross-sections, it should be noted that each of the gate contacts 126 and the source / drain contacts 128 can be formed in different cross-sections, which can prevent short-circuiting of the contacts.

[0082] Optionally, metal-semiconductor alloy regions 129 are formed at the interfaces between the source / drain regions 100 and the source / drain contacts 128. The metal-semiconductor alloy regions 129 can be silicide regions formed from a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), germanide regions formed from a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), silicon germanide regions formed from both a metal silicide and a metal germanide, or the like. The metal-semiconductor alloy regions 129 can be formed upstream of the source / drain contact material(s) 128 by depositing a metal in the openings for the source / drain contacts 128 and then performing a thermal tempering process. The metal can be any metal that is able to interact with the semiconductor materials (e.g. silicon, silicon carbide, silicon germanium, germanium, etc.).The source / drain regions 100 are to react to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare-earth metals, or their alloys. The metal can be formed by a deposition process, such as ALD, CVD, PVD, or the like. After the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the source / drain contact openings 128, such as from the surfaces of the metal-semiconductor alloy regions 129. The source / drain contact material(s) 128 can then be formed on the metal-semiconductor alloy regions 129.

[0083] The Fig. Figures 2 to 28C illustrate an embodiment in which the first WF layer 112 is removed from the n-region 50N after performing the silicon soaking process 114; however, in other embodiments, the first WF layer 112 can be removed from the n-region 50N before performing the silicon soaking process 114. Accordingly, the Fig. 29-33 Intermediate steps in the formation of nanostructured FETs, in which the first WF layer 112 is structured before performing the silicon soaking process 114. Fig. Figures 29-33 illustrate cross-sectional views along a cross-section similar to the reference cross-section AA' in Fig. 1. Some of the process steps that are described in the Fig. Figures 29-33 may be similar to the process steps described previously, and therefore some similar details may not be repeated.

[0084] Fig. Figure 29 shows a structure after the first WF layer 112 was deposited over the n-region 50N and the p-region 50P, similar to that in Fig. Structure shown in 17A. The one in Fig. The structure shown in Figure 29 can be formed using similar techniques or materials that are used to form the structure shown in the Fig. The structure shown in sections 17A-17C is described. The first WF layer 112 of Fig. 29 can be used similarly to the previous one for the Fig. 17A-C described and can be deposited using similar techniques.

[0085] In Fig. According to some embodiments, a mask 157 is formed over the p-region 50P and the first WF layer 112 in the n-region 50N is removed. The mask 157 can, for example, comprise a photoresist or the like and can be similar to the one previously used for the Fig. The mask 117 described in 20A-20C can be formed using a suitable technique (e.g., spin coating or the like) and structured using suitable photolithographic techniques to expose the n-region 50N. This protects the first WF layer 112 in the p-region 50P and exposes the first WF layer 112 in the n-region 50N.

[0086] Further with reference to Fig. 30 An etching process is performed to remove the first WF layer 112 in the n-region 50N according to some embodiments. The etching process removes the first WF layer 112 to expose the underlying gate dielectrics 110 of the n-region 50N. The mask 157 protects the first WF layer 112 in the p-region 50P from the etching process. The etching process may include a wet etching process and / or a dry etching process. In some cases, the etching process may selectively etch the first WF layer 112 with minimal etching or without etching the gate dielectrics 110. The etching process may be similar to the one previously described for the Fig. 21A-21C described.

[0087] In Fig. According to some embodiments, the mask 157 is removed and a silicon soaking process 114 is performed. The mask 157 can be removed using a suitable technique, such as an etching process, an ashing process, or the like. After removal of the mask 117, the gate dielectrics 110 in the n-region 50N are exposed, and the first WF layer 112 in the p-region 50P is exposed. The silicon soaking process 114 can be performed similarly to the one previously described for the Fig. as described in Sections 18A-18C. For example, the silicon soaking process 114 forms a silicon-containing layer (not illustrated separately) on the first WF layer 112 in the p-region 50P. In some cases, the silicon soaking process 114 may also form a silicon-containing layer (not illustrated separately) on the gate dielectrics 110 in the n-region 50N. In some embodiments, any silicon-containing layer formed in the n-region 50N is left behind during subsequent processing. After performing the silicon soaking process 114, the first WF layer 112 is referred to herein as the first WF layer 112' after soaking or simply as the first WF layer 112'.

[0088] In Fig. 32 is a second WF layer 118 formed over the n-region 50N and the p-region 50P according to some embodiments. The second WF layer 118 is formed over the gate dielectrics 110 in the n-region 50N and is formed over the first WF layer 112' in the p-region 50P. The second WF layer 118 can be similar to the second WF layer 118 previously described for the Fig. 23A-23C, and can be formed using similar techniques. For example, the second WF layer 118 can comprise aluminum. Similar to the previous discussion of the second WF layer 118, the silicon-containing layer of the first WF layer 112', formed by the silicon soaking process 114, inhibits the formation of the second WF layer 118 on top of the first WF layer 112'. Accordingly, the second WF layer 118 can be formed in the p-region 50P with a smaller thickness and is referred to as the second WF layer 118'.

[0089] In Fig. 33 A filler material 121 is deposited over the second WF layer 118 to form gate electrodes 120, similar to the discussion of the Fig. 26A-26C. For example, the gate electrodes 120 of the n-region 50N comprise the second WF layer 118 and the filler material 121, and the gate electrodes 120 of the p-region 50P comprise the first WF layer 112', the second WF layer 118', and the filler material 121. The filler material 121 can be similar to the filler material 121 used for the Fig. 26A-26C, and can be formed using similar techniques. This allows the formation of gate structures comprising the gate dielectrics 110 and the gate electrodes 120. The structure can subsequently be produced using suitable process steps, such as the one previously described for the Fig. 27A-28C described, processed.

[0090] These embodiments can offer advantages. Performing a silicon soaking process on a p-work function matching layer modifies the surface of the p-work function matching layer, thereby reducing the growth of an n-work function on the surface. For example, the silicon soaking process can form a silicon-containing layer on the p-work function matching layer, which reduces the growth rate and thickness of the n-work function matching layer. The techniques described herein enable the formation of a thinner n-work function matching layer on top of a p-work function matching layer. Forming a thinner n-work function matching layer in this way can reduce the amount of material that undesirably diffuses from the n-work function matching layer into the p-work function matching layer.For example, the techniques described herein can reduce the diffusion of aluminum from the n-outflow function matching layer to the p-outflow function matching layer. Reducing the amount of aluminum diffusing into the p-outflow function matching layer can lessen undesirable effects caused by the presence of aluminum in the p-outflow function matching layer, such as increased threshold voltage or reduced flat-band voltage. Therefore, the use of a silicon soaking process, as described herein, can improve device performance and uniformity.

[0091] In one embodiment of the present disclosure, a method comprises depositing a gate dielectric layer in a first channel region; depositing a p-efficiency matching layer on the gate dielectric layer; exposing the p-efficiency matching layer to a silicon-based precursor for a time period; and depositing an n-efficiency matching layer on the p-efficiency matching layer. In one embodiment, the silicon-based precursor comprises at least one of silane, disilane, trisilane, tetrasilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, or tris(dimethylamino)silane. In one embodiment, the p-efficiency matching layer comprises titanium nitride. In one embodiment, the n-efficiency matching layer comprises aluminum.In one embodiment, the exposure of the p-discharge function matching layer to the silicon-based precursor forms a silicon oxide layer on the p-discharge function matching layer. In one embodiment, the method comprises the deposition of the gate dielectric layer in a second channel region; and the exposure of the gate dielectric layer in the second channel region to the silicon-based precursor for a specified duration. In one embodiment, the exposure of the p-discharge function matching layer to the silicon-based precursor involves a process temperature in the range of 0 °C to 900 °C. In one embodiment, the duration is in the range of 1 second to 600 seconds.

[0092] In one embodiment of the present disclosure, a method comprises forming a first gate dielectric layer in a first channel region and a second gate dielectric layer in a second channel region; forming a first output function matching layer over the first gate dielectric layer and over the second gate dielectric layer; performing a surface modification process on the first output function matching layer to form a silicon-containing layer on the first output function matching layer; removing the first output function matching layer from the first gate dielectric layer; and forming a second output function matching layer on the first gate dielectric layer and over the first output function matching layer located over the second gate dielectric layer.In one embodiment, the thickness of the second output function matching layer on the first gate dielectric layer is greater than the thickness of the second output function matching layer above the first output function matching layer. In another embodiment, the growth rate of the second output function matching layer on the first gate dielectric layer is greater than the growth rate of the second output function matching layer above the first output function matching layer. In another embodiment, the formation of the second output function matching layer includes an aluminum-based precursor and a titanium-based precursor. In another embodiment, the surface modification process includes exposing the first output function matching layer to silane molecules or organosilane molecules.In one embodiment, the surface modification process replaces hydroxyl compounds with silicon-oxygen compounds. In another embodiment, the silicon-containing layer is a silicon oxide monolayer. In another embodiment, the formation of the second output work matching layer over the first output work matching layer includes the formation of aluminum-oxygen-silicon compounds.

[0093] In one embodiment of the present disclosure, a device comprises a first gate structure over first nanostructures, wherein the first gate structure comprises a first gate dielectric layer; a first layer of an n-output work-matching material over the first gate dielectric layer; and a metal filler material over the first layer of the n-output work-matching material; and a second gate structure over second nanostructures, wherein the second gate structure comprises a second gate dielectric layer; a first layer of a p-output work-matching material over the second gate dielectric layer; a first silicon-containing layer over the first layer of the p-output work-matching material; a second layer of the n-output work-matching material over the first silicon-containing layer; and the metal filler material over the second layer of the n-output work-matching material.In one embodiment, the thickness of the first layer of the n-output work-matching material is greater than the thickness of the second layer of the n-output work-matching material. In one embodiment, the device has a silicon-containing layer between the first gate dielectric layer and the first layer of the n-output work-matching material. In one embodiment, the first silicon-containing layer has at least one monolayer of silicon oxide.

[0094] The foregoing presents features of various embodiments so that a person skilled in the art may better understand the aspects of the present disclosure. A person skilled in the art should recognize that he can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or to obtain the same advantages as the embodiments presented herein. A person skilled in the art should also realize that such equivalent designs do not deviate from the spirit and scope of the present disclosure and that he can make various changes, substitutions, and modifications herein without deviating from the spirit and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 638,492

[0001]

Claims

[1] Procedure encompassing: Deposition of a gate dielectric layer on a first channel region; Deposition of a p-function matching layer on the gate dielectric layer; Exposure of the p-work-matching layer to a silicon-based precursor over a time period; and Deposition of an n-output work matching layer on the p-output work matching layer. [2] The method of claim 1, wherein the silicon-based precursor comprises at least one of silane, disilane, trisilane, tetrasilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane or tris(dimethylamino)silane. [3] Method according to claim 1 or 2, wherein the p-exit work matching layer comprises titanium nitride. [4] Method according to any of the preceding claims, wherein the n-output work matching layer comprises aluminium. [5] Method according to any of the preceding claims, wherein the exposure of the p-work function matching layer to the silicon-based precursor forms a silicon oxide layer on the p-work function matching layer. [6] A method according to any of the preceding claims, further comprising: Deposition of the gate dielectric layer on a second channel region; and Exposure of the gate dielectric layer in the second channel region opposite the silicon-based precursor during the time period. [7] Method according to any of the preceding claims, wherein the exposure of the p-work function matching layer to the silicon-based precursor comprises a process temperature in the range of 0 °C to 900 °C. [8] Method according to any of the preceding claims, wherein the time duration is in the range of 1 second to 600 seconds. [9] Procedure encompassing: Forming a first gate dielectric layer in a first channel region and a second gate dielectric layer in a second channel region; Forming a first output function matching layer over the first gate dielectric layer and over the second gate dielectric layer; Performing a surface modification process on the first exit work matching layer to form a silicon-containing layer on the first exit work matching layer; Removal of the first output function matching layer from the first gate dielectric layer; and Forming a second output function matching layer on top of the first gate dielectric layer and above the first output function matching layer located above the second gate dielectric layer. [10] Method according to claim 9, wherein the thickness of the second output function matching layer on the first gate dielectric layer is greater than the thickness of the second output function matching layer above the first output function matching layer. [11] Method according to claim 9 or 10, wherein a growth rate of the formation of the second output function matching layer on the first gate dielectric layer is greater than a growth rate of the formation of the second output function matching layer above the first output function matching layer. [12] Method according to any one of claims 9 to 11, wherein the formation of the second exit work matching layer comprises an aluminium-based precursor and a titanium-based precursor. [13] Method according to any one of claims 9 to 12, wherein the surface modification process comprises exposing the first work function matching layer to silane molecules or organosilane molecules. [14] Method according to any one of claims 9 to 13, wherein the surface modification process replaces hydroxyl compounds with silicon-oxygen compounds. [15] Method according to any one of claims 9 to 14, wherein the silicon-containing layer is a silicon oxide monolayer. [16] Method according to any one of claims 9 to 15, wherein forming the second output work matching layer over the first output work matching layer comprises forming aluminium-oxygen-silicon compounds. [17] Device comprising: a first gate structure over a first plurality of nanostructures, wherein the first gate structure comprises the following: a first gate dielectric layer; a first layer of an n-function matching material over the first gate dielectric layer; and a metal filler material above the first layer of the n-exit work-matching material; and a second gate structure over a second plurality of nanostructures, wherein the second gate structure comprises the following: a second gate dielectric layer; a first layer of a p-type output function matching material over the second gate dielectric layer; a first silicon-containing layer above the first layer of the p-exit work matching material; a second layer of the n-exit work-matching material over the first silicon-containing layer; and the metal filler material above the second layer of the n-exit work matching material. [18] Device according to claim 17, wherein the thickness of the first layer of the n-outlet work matching material is greater than the thickness of the second layer of the n-outlet work matching material. [19] Device according to claim 17 or 18, further comprising a silicon-containing layer between the first gate dielectric layer and the first layer of the n-output work matching material. [20] Device according to one of claims 17 to 19, wherein the first silicon-containing layer comprises at least one monolayer of silicon oxide.

Images