Resistive switching structure to improve an RRAM

Abstract

The task of reducing the forming voltage for an RRAM cell is solved with a resistive switching structure comprising at least two distinct layers. The thicknesses and compositions of the layers are selected such that a difference in oxygen affinity between the layers creates intrinsic oxygen vacancies in one of the layers. The task of increasing endurance is achieved by adding a dopant metal to the layer with the lower oxygen affinity. This dopant metal has a higher oxygen affinity than a primary metal in the layer with the lower oxygen affinity. The layer with the lower oxygen affinity can have a laminate structure in which the dopant metal is arranged in different layers.

Description

Reference to related registration

[0001] The present application claims priority over the preliminary US patent application filed on September 4, 2024, under file number 63 / 690.333, which is incorporated by reference into the present application. background

[0002] Numerous modern electronic devices contain electronic memory (EMO) designed to store data. EMO can be volatile or non-volatile. Volatile memory retains data while powered on, whereas non-volatile memory retains data even when power is turned off. Resistive random-access memory (RRAM) is a promising candidate for next-generation non-volatile memory due to its simple structure and compatibility with CMOS (complementary metal-oxide semiconductor) processes. An RRAM cell features a resistive circuit with variable resistance. This resistive circuit is generally placed between two electrodes arranged in a metallic interconnect structure. Brief description of the drawings

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows a sectional view of an integrated chip with an RRAM cell according to an embodiment of the present disclosure. Fig. Figure 2 shows a sectional view of an RRAM cell with a resistive switching structure according to an embodiment of the present disclosure. The Fig. Figures 3 to 8 show sectional views of integrated chips according to various embodiments, which have RRAM cells with resistive switching structures according to various embodiments of the present disclosure. Fig. Figure 9 shows a sectional view of an integrated chip with a flash memory cell according to an embodiment of the present disclosure. Fig. Figure 10A shows a sectional view of an integrated chip with a three-dimensional matrix (3D matrix) of RRAM cells with resistive switching structures according to some embodiments of the present disclosure. Fig. Figure 10B shows a truncated perspective view of one of the RRAM cells in the integrated chip of Fig. 10A. Fig. 10C shows a top view of the integrated chip of Fig. 10A according to some embodiments. The Fig. Figures 11 to 16 show sectional views of an integrated chip with an RRAM cell undergoing a manufacturing process according to some embodiments of a method of the present disclosure. The Fig. Figures 17 to 23 show sectional views of an integrated chip with an RRAM cell undergoing a manufacturing process according to some embodiments of another method of the present disclosure. The Fig. Figures 24 to 27 show sectional views of an integrated chip with a flash memory cell undergoing a manufacturing process according to some embodiments of a method of the present disclosure. The Fig. Figures 28 to 32 show sectional views of an integrated chip with a 3D matrix of RRAM cells, which undergoes a manufacturing process according to some embodiments of a method of the present disclosure. Fig. 33 provides a flowchart showing some embodiments of a method for manufacturing an RRAM cell with a resistive switching structure according to the present disclosure. The Fig. References 34 to 36 provide flowcharts for methods for manufacturing integrated chips according to various embodiments of the present disclosure. Detailed description

[0004] The present disclosure provides many different embodiments or examples for implementing various features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present disclosure.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0005] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of one element or structural element to one or more other elements or structural elements depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90° or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0006] Integrated chips can contain RRAM cells, which have a resistive switching structure located between an upper and a lower electrode. Current pulses can be used to reversibly switch the resistive switching structure between a high-resistance state (HRS) and a low-resistance state (LRS). Data can be encoded based on the difference between the HRS and LRS states and detected in a read operation. The read operation can be performed at lower voltages than those used to program the HRS and LRS, allowing the state of the RRAM cell to be detected without changing it.

[0007] Before an RRAM cell is used to store data, a conductive starter filament is typically formed across the resistive circuitry. Forming this conductive starter filament facilitates subsequent write operations (which create the conductive filament). The conductive starter filament is created by pulsed a forming voltage across the top and bottom electrodes.

[0008] In some types of RRAM cells, the resistive switching structure contains metal oxides, and the conductive filament is formed from oxygen vacancies within the metal oxide structure. In these types of RRAM cells, the forming voltage can break metal oxide bonds and release oxygen ions. The released oxygen ions migrate to the upper electrode, where some of the oxygen ions can be absorbed. The migrating oxygen ions leave behind oxygen vacancies. New oxygen vacancies form more readily near existing ones, so the oxygen vacancies tend to align to form a conductive filament that extends along a continuous path through the resistive switching structure.

[0009] Once the conductive starter filament has been produced, the RRAM cell can be switched between the HRS and LRS using voltages lower than the forming voltage. In a reset operation, the oxygen ions are driven to return approximately to their original positions, rendering the conductive filament inactive. During a setting operation, the oxygen ions are driven again to and into the upper electrode, thus restoring the conductive filament.

[0010] When transistors are manufactured smaller, their safe operating capabilities are reduced. Therefore, the drive to increase the density of integrated circuit devices has led to the long-standing need to lower forming voltages for RRAM cells. One method for lowering forming voltages is to reduce the thickness of the resistive circuit structure, but because the resistive circuit structure then becomes very thin (e.g., below 10 Å), leakage currents tend to become too high. Furthermore, as the resistive circuit structure becomes thinner, the tendency for oxygen ions to spontaneously diffuse back into the resistive circuit structure from the upper electrode increases. This tendency can compromise the reliability of the RRAM cell.

[0011] According to certain aspects of the present disclosure, an RRAM cell has a resistive switching structure that reduces the forming voltage (e.g., to about 2.3 V or less) without requiring a thinning of the resistive switching structure. The resistive switching structure has two metal oxide layers that differ in the oxygen affinities of their metals. The layer with the lower oxygen affinity is located near a first electrode, and the layer with the higher oxygen affinity is located near a second electrode. The second electrode is an electrode in which oxygen ions dissolve during the fabrication of the conductive filament.In the examples of the present disclosure, the second electrode is often referred to as the upper electrode, but this is merely a convention for the sake of simplicity, and the lower electrode may be an electrode designed to have oxygen ion solubility. The difference in oxygen affinities causes some oxygen ions to spontaneously migrate from the layer with the lower oxygen affinity to the layer with the higher oxygen affinity, thereby creating intrinsic oxygen vacancies in the layer with the lower oxygen affinity. If the difference in oxygen affinities is large enough and the thicknesses of the layers with the lower and higher oxygen affinities are selected accordingly, the forming stress is reduced.

[0012] One measure of a metal's oxygen affinity is the standard free energy of formation for oxygen vacancies for a maximum oxide (the oxide with the highest oxygen content) of the metal. A higher standard free energy of formation for oxygen vacancies indicates a greater oxygen affinity. Another, practically equivalent measure is the standard free energy of formation for the maximum oxide on a per-mol oxygen basis. A lower (more negative) standard free energy of formation for a metal oxide indicates a greater oxygen affinity. In some embodiments, the difference between the standard free energy of formation for a metal oxide of a first metal, which is the metal of the layer with the lower oxygen affinity, and the standard free energy of formation for a metal oxide of a second metal, which is the metal of the layer with the higher oxygen affinity, is at least about 100 kJ / mol oxygen (O₂).In some embodiments, the difference is at least approximately 200 kJ / mol oxygen (O2).

[0013] In some embodiments, the thickness ratio between the layer with the lower oxygen affinity and the layer with the higher oxygen affinity is approximately 0.5 to approximately 1.3. In some embodiments, the thickness ratio is approximately 0.8 to approximately 1.0. In some embodiments, the thickness of the resistive switching structure is approximately 20 Å to approximately 45 Å. In some embodiments, the layer with the lower oxygen affinity and the layer with the higher oxygen affinity each have a thickness of at least approximately 10 Å. If the layer with the higher oxygen affinity is too thin, or too thin relative to the layer with the lower oxygen affinity, it may not be able to create a sufficient number of oxygen vacancies in the layer with the lower oxygen affinity to significantly reduce the forming stress.If the layer with the higher oxygen affinity is too thick, it can increase the forming stress. If the layer with the lower oxygen affinity is too thin, it may not be able to maintain sufficient oxygen vacancies to significantly reduce the forming stress. If the layer with the lower oxygen affinity and the layer with the higher oxygen affinity are too thin in combination, leakage currents may be too high.

[0014] Another important aspect of RRAM is endurance. Endurance refers to the ability of a large number of RRAM cells to operate reliably throughout the lifetime of an integrated chip. In a typical endurance test, the performance of a large number of RRAM cells (e.g., 500,000) is compared before and after 10,000 program and reset operations combined with heat treatment. Read currents in the HRS and LRS exhibit Gaussian distributions between the RRAM cells. A memory device passes the endurance test if, even after the test, there is no overlap for a given read voltage between the range of read currents between the RRAM cells when they are in the HRS and the range of read currents between the RRAM cells when they are in the LRS.It has been found that a memory device consisting of RRAM cells, which have a lower oxygen affinity layer and a higher oxygen affinity layer, may fail the endurance test if the heat treatment conditions are harsh, e.g., 200 °C for an extended period. The inventors have determined that this failure is primarily due to the progressively increasing distribution of oxygen vacancies in the lower oxygen affinity layer, which is partly evident from the progressively wider conductive filament passing through the lower oxygen affinity layer. As the oxygen vacancies become more widely distributed, it can become difficult to fill all of them with oxygen ions during a reset operation.

[0015] In some aspects of the present disclosure, the endurance problem is solved by adding a suitable amount of a third metal, which has a higher oxygen affinity than the first metal, to the layer with the lower oxygen affinity. The third metal can be referred to as a dopant, since its concentration in the layer with the lower oxygen affinity is relatively low compared to the first metal. The third metal prevents the distribution of oxygen vacancies in the layer with the lower oxygen affinity without significantly increasing the forming stress. In some embodiments, the atomic fraction of the third metal in the layer with the lower oxygen affinity is about 0.1% to about 10%. In other embodiments, the atomic fraction of the third metal in the layer with the lower oxygen affinity is about 0.5% to about 4%.If the concentration of the third metal is too low, it may not be effective in reducing the distribution of oxygen vacancies. If the concentration of the third metal is too high, it may increase the forming stress excessively.

[0016] In some embodiments, the difference in oxygen affinity between the first metal (the main metal in the layer with the lower oxygen affinity) and the third metal (the dopant metal) is at least approximately 100 kJ / mol oxygen (O₂). In some embodiments, this difference is at least approximately 200 kJ / mol oxygen (O₂). In some embodiments, the dopant metal has a lower oxygen affinity than the metal of the layer with the higher oxygen affinity (the second metal). If the oxygen affinity of the dopant metal is too low, it may not be effective in reducing the distribution of oxygen vacancies. If the oxygen affinity of the dopant metal is too high, it may prevent the formation of intrinsic oxygen vacancies or, conversely, increase the forming stress excessively.

[0017] In some embodiments, the layer with the higher oxygen affinity is or contains zirconium oxide (ZrO). In some embodiments, the layer with the lower oxygen affinity is or contains hafnium tantalum oxide (HfTaO), aluminum tantalum oxide (AlTaO), lanthanum tantalum oxide (LaTaO), titanium tantalum oxide (TiTaO), titanium silicon oxide (TiSiO), hafnium silicon oxide (HfSiO), or hafnium zinc oxide (HfZnO). These specific combinations of main metal and dopant metal in the lower oxygen affinity layer, in conjunction with a higher oxygen affinity layer containing zirconium oxide (ZrO), are particularly well suited to providing an RRAM switching structure that exhibits low forming stress, associated with the formation of intrinsic oxygen vacancies, and high endurance, associated with the prevention of distributed oxygen vacancy formation.

[0018] In some embodiments, the layer with the higher oxygen affinity is or contains hafnium oxide (HfO). In some of these embodiments, the layer with the lower oxygen affinity is or contains zirconium tantalum oxide (ZrTaO), lanthanum tantalum oxide (LaTaO), titanium tantalum oxide (TiTaO), zirconium silicon oxide (ZrSiO), or zirconium zinc oxide (ZrZnO). These particular combinations of a metal and a dopant metal with a low oxygen affinity, in conjunction with a layer with a higher oxygen affinity containing hafnium oxide (HfO), are especially well suited to providing an RRAM switching structure that exhibits low forming stress, associated with the formation of intrinsic oxygen vacancies, and high endurance, associated with the prevention of distributed oxygen vacancy formation.

[0019] In some embodiments, the layer with the higher oxygen affinity is or contains lanthanum oxide (LaO). In some of these embodiments, the layer with the lower oxygen affinity is or contains hafnium tantalum oxide (HfTaO), aluminum tantalum oxide (AlTaO), hafnium silicon oxide (HfSiO), hafnium zinc oxide (HfZnO), or zirconium zinc oxide (ZrZnO). These particular combinations of a metal and a dopant metal with a low oxygen affinity, in conjunction with a layer with a higher oxygen affinity containing lanthanum oxide (LaO), are especially well suited to providing an RRAM circuit structure that exhibits low forming stress, associated with the formation of intrinsic oxygen vacancies, and high endurance, associated with the prevention of distributed oxygen vacancy formation.

[0020] In accordance with the present disclosure, when determining which is the main metal and which is the doping metal in the preceding embodiments, the following standard free enthalpies of formation for an oxide, expressed in kJ / mol oxygen (O2), can be used: Ruthenium (Ru, -274), Zinc (Zn, -640), Tantalum (Ta, -750), Silicon (Si, -860), Titanium (Ti, -889), Hafnium (Hf, -1000), Aluminum (Al, -1055), Zirconium (Zr, -1100), Lanthanum (La, -1140), Neodymium (Nd, -1150), Gadolinium (Gd, -1160), Yttrium (Y, -1270).

[0021] In some embodiments, the lower-oxygen-affinity switching layer is produced by atomic layer deposition (ALD). In some embodiments, a dopant metal oxide is deposited in cycles separate from those for a main metal oxide. It has been found that the lower-oxygen-affinity switching layer performs better when the dopant metal is deposited in separate cycles, as opposed to when a dopant metal precursor is combined with a main metal precursor, resulting in the simultaneous deposition of both metal oxides. In some embodiments, the ratio of main metal oxide to dopant metal oxide deposition cycles is 3:1 to 15:1. In some embodiments, this ratio is 5:1 to 10:1. In some embodiments, this ratio is at least 6:1. If the ratio is too low, the forming stress may increase.If the ratio is too high, there may not be enough doping metal to improve endurance.

[0022] It is understood that the ratio of main metal atoms to dopant atoms in the interface layer with the lower oxygen affinity may not correspond to the ratio of deposition cycles: fewer dopant atoms than main metal atoms may be deposited per cycle. The extent of doping deposition per cycle can be influenced by the crystal structure and can be controlled up to an upper limit by varying the deposition conditions. In some embodiments, the conditions are chosen to avoid surface saturation during the doping deposition cycles.

[0023] Although the doping metal oxide may not form a complete monolayer during a doping deposition cycle, the main metal oxide is typically deposited in complete monolayers. Therefore, between adjacent dopant-containing layers in the lower-oxygen affinity interface layer, there is a plurality of main metal oxide monolayers approximately equal to the number of main metal oxide deposition cycles per doping metal oxide deposition cycle. Thus, in some embodiments, there are approximately 3 to 15 main metal oxide monolayers between adjacent dopant-containing layers in the lower-oxygen affinity interface layer. In other embodiments, there are approximately 5 to 10 main metal oxide monolayers between adjacent dopant-containing layers.In some embodiments, there are three or more dopant-containing layers in the switching layer with the lower oxygen affinity, so that the structure is repeated at least once. The thickness of a monolayer of the main metal oxide can be determined, for example, from the density of the main metal oxide, and then the number of monolayers between adjacent dopant-containing layers can be determined from the spacing between the dopant-containing layers. The effectiveness of the dopant in improving endurance has been experimentally demonstrated for the case where the dopant metal is distributed as described in this paragraph.

[0024] An RRAM cell according to the present disclosure can be set to the LRS and reset to the HRS by applying suitable voltages to the upper and lower electrodes for appropriate periods of time. The reset operation can be either unipolar or bipolar. In a bipolar reset, the current for the reset operation flows in a direction opposite to that of the setting operation. In some embodiments of a process for operating a memory cell according to the present disclosure, the reset is bipolar. It has been found that the RRAM cells according to the present disclosure are less susceptible to overshoot currents that can gradually damage the resistive switching structure, thereby reducing endurance, when a bipolar reset is used throughout.

[0025] Fig. Figure 1 shows a sectional view of an integrated chip 100 with an RRAM cell 104, which in some embodiments has a resistive switching structure 110. The resistive switching structure 110 comprises a switching layer 116 with a lower oxygen affinity near a lower electrode 108 and a switching layer 118 with a higher oxygen affinity near an upper electrode 141. The RRAM cell 104 is arranged on a substrate 102. A transistor 103, arranged on the substrate 102, can provide an access control device for the RRAM cell 104. In some embodiments, the transistor 103 is a metal-oxide-semiconductor field-effect transistor (MOSFET) or another suitable transistor.In various embodiments, the transistor 103 can be configured to provide suitable bias conditions for the RRAM cell 104 and / or to enable this provision, so that the RRAM cell 104 can be switched between an LRS and an HRS.

[0026] A dielectric structure 124, containing one or more dielectric materials, is arranged above the substrate 102. The RRAM cell 104 is arranged within the dielectric structure 124. One or more conductive structures arranged within the dielectric structure 124 can be configured to electrically connect the transistor 103 to the RRAM cell 104. For example, the transistor 103 can be electrically connected to the RRAM cell 104 via a lower via 105 and a lower conductive trace 106. An upper dielectric structure 120, arranged within the dielectric structure 124, provides a second contact for the RRAM cell 104.

[0027] The switching layer 116 with the lower oxygen affinity and the switching layer 118 with the higher oxygen affinity contain metal oxides. In some embodiments, the switching layer 118 with the higher oxygen affinity is or contains an oxide of a metal with a standard free enthalpy of formation for an oxide of -1000 kJ / mol oxygen (O₂) or less. In some embodiments, the switching layer 118 with the higher oxygen affinity is or contains zirconium oxide (ZrO), lanthanum oxide (LaO), hafnium oxide (HfO), gadolinium oxide (GdO), and / or yttrium oxide (YO), or the like. In some embodiments, the switching layer 118 with the higher oxygen affinity has a thickness 130 of about 10 Å to about 25 Å.

[0028] In some embodiments, the lower-oxygen affinity switching layer 116 contains an oxide of a metal with a standard free enthalpy of formation for an oxide of approximately -900 kJ / mol O2 or more. In other embodiments, the lower-oxygen affinity switching layer 116 contains an oxide of a metal with a standard free enthalpy of formation for an oxide of approximately -750 kJ / mol O2 (that for tantalum) to approximately -500 kJ / mol O2. If the oxygen affinity of the lower-oxygen affinity switching layer 116 is too high, intrinsic oxygen vacancies may not form, and the forming voltage cannot be reduced. If the oxygen affinity of the lower-oxygen affinity switching layer 116 is too low, the leakage current may become too high.In some embodiments, the switching layer 116 with the lower oxygen affinity contains zinc oxide (ZnO), tantalum oxide (TaO), silicon dioxide (SiO), germanium oxide (GeO), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), and / or ruthenium oxide (RuO), or the like. Indium tin oxide (ITO) has a standard free enthalpy of formation of about -550 kJ / mol O₂. Indium gallium zinc oxide (IGZO) has a standard free enthalpy of formation of about -620 kJ / mol O₂.

[0029] In some embodiments, the switching layer 116 with the lower oxygen affinity has a thickness 128 of about 10 Å to about 25 Å. A difference in oxygen affinity between the switching layer 116 with the lower oxygen affinity and the switching layer 118 with the higher oxygen affinity is sufficient to cause oxygen ions to migrate spontaneously from the switching layer 116 with the lower oxygen affinity to the switching layer 118 with the higher oxygen affinity, thereby creating intrinsic oxygen vacancies in the switching layer 116 with the lower oxygen affinity to an extent that reduces the forming voltage for the RRAM cell 104.

[0030] The number of intrinsic oxygen vacancies in the switching layer 116 with the lower oxygen affinity depends on the relative thicknesses of the switching layer 118 with the higher oxygen affinity. In some embodiments, the ratio of the thickness 130 of the switching layer 118 with the higher oxygen affinity to the thickness 128 of the switching layer 116 with the lower oxygen affinity is 0.85 or greater. In some embodiments, the ratio is 1:1 or greater. These ratios enable the switching layer 118 with the higher oxygen affinity to receive a sufficient number of oxygen ions from the switching layer 116 with the lower oxygen affinity and to generate a sufficient number of oxygen vacancies to achieve the desired reduction in forming stress.

[0031] In some embodiments, the switching layer 116 with the lower oxygen affinity also contains a dopant metal oxide. The metal with the higher concentration in the switching layer 116 with the lower oxygen affinity can then be referred to as the main metal. The concentration of the dopant metal can be so low that the overall oxygen affinity of the switching layer 116 with the lower oxygen affinity is not significantly altered by the dopant metal. The dopant metal has a higher oxygen affinity than the main metal. In some embodiments, the dopant metal has a standard free enthalpy of formation for an oxide of less than about -750 kJ / mol O₂ (smaller than that of tantalum). The dopant metal increases the endurance of the RRAM cell 104.

[0032] In some embodiments, the switching layer 116 with the lower oxygen affinity contains a substoichiometric amount of oxygen relative to the maximum oxides of its metal constituents. In some embodiments, the oxygen amount is approximately 80% to approximately 99.5% of the stoichiometric amount. In other embodiments, the oxygen amount is approximately 90% to approximately 99.5% of the stoichiometric amount. A substoichiometric oxygen amount reduces the forming voltage. If the oxygen amount is too high, the forming voltage may become too high. If the oxygen amount is too low, leakage currents may become too high.

[0033] In some embodiments, the switching layer 116 with the lower oxygen affinity has a doping concentration of 0.1 atomic percent to approximately 10 atomic percent. If the amount of dopant is too small, the benefit of improved endurance cannot be realized. If the amount of dopant is too large, the forming stress can increase excessively.

[0034] In some embodiments, the switching layer 118 with the higher oxygen affinity contains a substoichiometric amount of oxygen relative to the maximum oxides of its metal constituents. In some embodiments, the oxygen amount is approximately 80% to approximately 99.5% of the stoichiometric amount. In other embodiments, the oxygen amount is approximately 90% to approximately 99.5% of the stoichiometric amount. A substoichiometric amount of oxygen in the switching layer 118 with the higher oxygen affinity also contributes to achieving a lower forming voltage. If the oxygen amount in the switching layer 118 with the higher oxygen affinity is too high, the forming voltage may become too high. If the oxygen amount in the switching layer 118 with the higher oxygen affinity is too low, leakage currents may become too high.

[0035] The conductive initial filament contains oxygen vacancies located in region 115, extending from the top of the lower electrode 108 to the bottom of a capping structure 112. Typically, generating the conductive initial filament involves applying a forming voltage across the lower electrode 108 and the upper electrode 141 via transistor 103 and the upper conductive structure 120. The forming voltage can knock oxygen atoms out of a lattice in the resistive switching structure 110, creating localized oxygen vacancies that tend to align in region 115 to form the conductive initial filament. Subsequently, a series of reset voltages can be applied across the lower electrode 108 and the upper electrode 141 to change the specific electrical resistance of the resistive switching structure 110 between the HRS and the LRS.

[0036] The upper electrode 141 of the RRAM cell 104 has a capping structure 112 to facilitate the absorption of oxygen ions. Fig. Figure 2 shows a sectional view 200, which provides a more detailed representation of the layers in RAM cell 104. Fig. 1 provides for embodiments in which the capping structure 112 comprises a capping metal layer 204 and an optional diffusion barrier layer 202. The diffusion barrier layer 202 is arranged directly between the capping metal layer 204 and the switching layer 118 with the higher oxygen affinity. In addition to the capping structure 112, the upper electrode 141 can also have an upper metal layer 114 above the capping structure 112. The switching layer 116 with the lower oxygen affinity is arranged between the switching layer 118 with the higher oxygen affinity and the lower electrode 108 and can directly contact the lower electrode 108.

[0037] In some embodiments, the RRAM cell 104 relies on redox reactions during operation to produce and dissolve a conductive filament 208 in a region 115 of the resistive switching structure 110. The conductive filament 208 extends from the lower electrode 108 to the capping structure 112. The formation of the conductive filament 208 in region 115 creates the LRS, and the dissolution of the conductive filament 208 along at least a portion of a thickness 131 of the resistive switching structure 110 creates the HRS. Thus, the RRAM cell 104 can be switched between the LRS and the HRS by applying appropriate bias voltages to the RRAM cell 104 to produce and dissolve the conductive filament 208 in region 115.In some embodiments, the conductive filament 208 contains oxygen vacancies 206 which are arranged in the area 115 and extend between the lower electrode 108 and the capping structure 112.

[0038] In some embodiments, the capping structure 112 is configured to absorb oxygen ions from the resistive switching structure 110 during setting operations and to release oxygen ions to the resistive switching structure 110 during reset operations. This function as an oxygen ion reservoir enables the fabrication and dissolution of the conductive filament 208 in the region 115. In some embodiments, the capping metal layer 204 contains one or more layers of metals with high oxygen ion solubility, such as tantalum (Ta), titanium (Ti), hafnium (Hf), zirconium (Zr), nickel (Ni), iridium (Ir), or the like.

[0039] The diffusion barrier layer 202 is part of the capping structure 112, designed to restrict or slow the transport of oxygen ions between the capping structure 112 and the resistive switching structure 110, thereby attenuating spontaneous diffusion of oxygen ions that could compromise the stability of the RRAM cell 104. In some embodiments, the diffusion barrier layer 202 is or contains tantalum nitride (TaN), titanium nitride (TiN), or the like. In some embodiments, the diffusion barrier layer 202 is a metal nitride of the capping metal layer 204. For example, the diffusion barrier layer 202 may be or contain tantalum nitride, while the capping metal layer 204 is or contains tantalum.

[0040] In some embodiments, the thickness 203 of the diffusion barrier layer 202 is approximately 20 Å to approximately 30 Å. In some embodiments, the thickness 203 of the diffusion barrier layer 202 is greater than the thickness 130 of the switching layer 118 with the higher oxygen affinity and greater than the thickness 128 of the switching layer 116 with the lower oxygen affinity. In some embodiments, the ratio between the thickness 203 of the diffusion barrier layer 202 and the thickness 130 of the switching layer 118 with the higher oxygen affinity is approximately 2 to approximately 3. If the diffusion barrier layer 202 is too thin, excessive spontaneous diffusion of oxygen ions may occur. If the diffusion barrier layer 202 is too thick, it may excessively increase the forming stress.

[0041] The thickness 205 of the capping metal layer 204 is, for example, approximately 10 Å to 50 Å, or has another suitable value. In some embodiments, the ratio between the thickness 131 of the switching structure 110 and the thickness 205 of the capping structure 112 is approximately 0.6 to approximately 1. If the capping structure 112 is too thin, it cannot absorb sufficient oxygen ions during the setting operation. If the capping structure 112 is too thick, oxygen ions can become distributed within the capping structure 112 during reset operations and not return to the resistive switching structure 110.

[0042] The upper metal layer 114 is an optional layer in the upper electrode 141. The upper metal layer 114 has good conductivity but does not need to absorb oxygen significantly. The upper metal layer 114 can be, for example, tantalum nitride (TaN), titanium nitride (TiN), ruthenium (Ru), platinum (Pt), a combination thereof, or the like. The thickness 134 of the upper electrode 141 is, for example, about 80 Å to 195 Å or has another suitable value. In some embodiments, the total thickness 207 of the upper electrode 141 is about 125 Å to about 275 Å. In some embodiments, the ratio between the thickness 131 of the resistive switching structure 110 and the thickness 132 of the capping structure 112 is about 0.1 to about 0.3.

[0043] In some embodiments, the composition of the lower electrode 108 is selected such that the lower electrode 108 does not significantly absorb oxygen ions from or release them to the resistive switching structure 110. In some embodiments, the lower electrode 108 is or contains tantalum nitride (TaN), titanium nitride (TiN), ruthenium (Ru), platinum (Pt), or the like, or a combination thereof. The composition of the lower electrode 108 can be selected such that its work function is well matched with the work function of the switching layer 116, which has a lower oxygen affinity. The thickness 126 of the lower electrode 108 can, for example, be approximately 75 Å to 90 Å, or another suitable value. In some embodiments, the thickness 134 of the upper electrode 141 is greater than the thickness 126 of the lower electrode 108.

[0044] Fig. Figure 3 shows a sectional view of an integrated chip 300 according to some embodiments. The integrated chip 300 has an RRAM cell 104A. The RRAM cell 104A can be assigned to the RRAM cell 104 of Fig. 1. Similar, except that the RRAM cell 104A has a lower electrode 108A that is narrower than the resistive switching structure 110. By making the lower electrode 108A narrower than the resistive switching structure 110, the fabrication of a narrower filament 208 (see Fig. 2) be made possible.

[0045] The RRAM cell 104A is located above a lower conductive conductor 106, which is arranged in a first intermetal dielectric (IMD) layer 302. A lower dielectric layer 304 is arranged above the first IMD layer 302, and a second IMD layer 306 is arranged above the lower dielectric layer 304. The lower conductive conductor 106 is electrically connected to the RRAM cell 104A. The first and second IMD layers 302 and 306 can be, for example, silicon dioxide, a low-k dielectric material such as undoped silicate glass (USG) or carbon-doped silicon dioxide, another suitable dielectric material, or a combination thereof. The lower dielectric layer 304 can be, for example, silicon carbide, silicon oxide carbide, silicon nitride, silicon oxide nitride, another suitable dielectric material, or a combination thereof.

[0046] A sidewall spacer structure 308 extends around the RRAM cell 104A. An upper conductive structure 120 is arranged above and connected to the upper electrode 141. The lower conductive conductor 106 and the upper conductive structure 120 can be, for example, made of or contain aluminum, copper, tungsten, ruthenium, titanium nitride, another suitable conductive material, or a combination thereof.

[0047] In some embodiments, the sidewalls of the switching layer 116 with the lower oxygen affinity, the switching layer 118 with the higher oxygen affinity, the diffusion barrier layer 202, the capping metal layer 204, and the top electrode 141 are aligned. This alignment is achieved by etching the RRAM cell 104A from a stack containing all these layers. The sidewall spacer structure 308 extends along these aligned sidewalls. In some embodiments, the sidewall spacer structure 308 extends to the top of the RRAM cell 104A.

[0048] Fig. Figure 4 shows a sectional view of an integrated chip 400. The integrated chip 400 has an RRAM cell 104B according to some embodiments. The RRAM cell 104B has a lower electrode 108B, a resistive switching structure 110B, and an upper electrode 141B. The lower electrode 108B, the resistive switching structure 110B, and the upper electrode 141B are identical to the corresponding parts of the RRAM cell 104B, except for their shapes. Fig. 1 similarly. The lower electrode 108B is recessed, giving it a convex top surface 410. The lower electrode 108B can have a peripheral region extending over the top surface of the lower dielectric layer 304 and a central region extending through the lower dielectric layer 304. In the central region, the lower electrode 108B has the convex top surface 410.

[0049] The layers of the resistive switching structure 110B are arranged on the convex upper surface 410, giving them corresponding convexities. The layers of the upper electrode 141B are arranged on the resistive switching structure 110B, and they therefore have the same convexity, but the convexity can be relaxed by the height of the upper electrode 141B. The convexity of the resistive switching structure 110B can improve the uniformity of the conductive filaments 208 (see Fig. 2) promote 104B between multiple RRAM cells, thereby improving the reliability of the memory.

[0050] In some embodiments, the resistive switching structure 110B is narrower than the lower electrode 108B. In some embodiments, the upper electrode 141B is narrower than the resistive switching structure 110B. In the RRAM cell 104B, these structural elements can ensure the uniformity of the conductive filaments 208 (see Fig. 2) further promote 104B between multiple RRAM cells, thereby improving the reliability of the memory.

[0051] A third IMD layer 402 can be arranged above the second IMD layer 306. An upper conductive via 404 and an upper conductive line 406 can be arranged in the third IMD layer 402. The upper conductive via 404 and the upper conductive line 406 are electrically connected to the RRAM cell 104B by means of the upper conductive structure 120. The upper conductive structure 120 can be an upper electrode via.

[0052] Fig. Figure 5 shows a sectional view of an integrated chip 500. The integrated chip 500 has an RRAM cell 104C with a resistive switching structure 110C according to some embodiments. The integrated chip 500, the RRAM cell 104C, and the resistive switching structure 110C are related to the integrated chip 400, the RRAM cell 104B, and the resistive switching structure 110B, respectively, of Fig. 4 similarly, except that the resistive switching structure 110C contains an additional layer, namely a layer 502 with an even higher oxygen affinity, above the switching layer 118 with the higher oxygen affinity. The layer 502 with the even higher oxygen affinity contains an oxide of a metal with a higher oxygen affinity than the metal of the switching layer 118 with the higher oxygen affinity. In some embodiments, the layer 502 with the even higher oxygen affinity contains an oxide of a metal with a standard free enthalpy of formation for an oxide of about -1100 kJ / mol O2 or less. In some embodiments, the layer 502 with the even higher oxygen affinity contains an oxide of a metal with a standard free enthalpy of formation for an oxide of at least about -100 kJ / mol O2, which is lower than the standard free enthalpy of formation for an oxide of the metal of the switching layer 118 with the higher oxygen affinity.Layer 502, with its even higher oxygen affinity, can facilitate the formation of intrinsic oxygen vacancies and further reduce the forming stress.

[0053] In some embodiments, the thickness of layer 502 with the even higher oxygen affinity is equal to or less than the thickness of switching layer 116 with the lower oxygen affinity. In some embodiments, the thickness of layer 502 with the even higher oxygen affinity is equal to or less than the thickness of switching layer 118 with the higher oxygen affinity. The thickness of layer 502 with the even higher oxygen affinity may, for example, be about 10 Å to 15 Å, or another suitable value. If layer 502 with the even higher oxygen affinity is too thick, it may increase the forming stress. If layer 502 with the even higher oxygen affinity is too thin, it may not be effective in reducing the forming stress.

[0054] Fig. Figure 6 shows a sectional view of an integrated chip 600, which has a memory region 602 laterally adjacent to a logic region 604. The integrated chip 600 has a first RRAM cell 104AA and a second RRAM cell 104AB, which are elements in a matrix arranged in the memory region 602. In some embodiments, the first and second RRAM cells 104AA and 104AB are, like the RRAM cell 104B of Fig. 3. In the logic area 604, an upper conductive via 404 is arranged, which extends continuously from an upper conductive line 406 to a lower conductive line 106 in the logic area 604.

[0055] Fig. Figure 7 shows a sectional view of an integrated chip 700, which has a first RRAM cell 104CA and a second RRAM cell 104CB, which are laterally adjacent to each other. The first and second RRAM cells 104CA and 104CB can replicate the structural elements of the RRAM cell 104B from Fig. 4, the RRAM cell 104C from Fig. 5 or any other RRAM cell of the present disclosure.

[0056] The integrated chip 700 has a plurality of lower conductive traces 106 below the first and second RRAM cells 104CA and 104CB. A plurality of upper vias 404 are arranged above the first and second RRAM cells 104CA and 104CB. The plurality of lower conductive traces 106, the plurality of upper conductive vias 404, and the upper conductive trace 406 each have a conductive body 704 and a conductive coating 702. In some embodiments, the conductive coating 702 extends along a bottom surface and opposite side walls of the conductive body 704. The conductive body 704 can be, for example, copper (Cu), aluminum (Al), tungsten (W), ruthenium (Ru), a combination thereof, or the like. The conductive coating 702 can be, for example, titanium nitride (TiN), tantalum nitride (TaN) or the like.In some embodiments, the upper conductive trace 406 extends laterally in a continuous manner from a region above the first RRAM cell 104CA to a region above the RRAM cell 104CB. Layers in the first and second RRAM cells 104CA and 104CB each have a projecting segment that extends downward to a corresponding lower conductive trace 106. In some embodiments, the upper conductive vias 404 are laterally offset from the projecting segments of the first and second RRAM cells 104CA and 104CB.

[0057] Fig. Figure 8 shows a sectional view of an integrated chip 800, which includes an RRAM cell 104 arranged in an interconnect structure 812 located on a substrate 102. Another RRAM cell 104 from the present disclosure could be used instead of the RRAM cell 104 in the integrated chip 800. The integrated chip 800 includes a semiconductor device 806 arranged on the substrate 102. The semiconductor device 806 can be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), a high electron mobility transistor (HEMT), another front-end-of-line semiconductor device, or the like. The semiconductor device 806 includes a dielectric gate layer 808, a gate electrode 810 above the dielectric gate layer 808, and a source / drain pair 804a and 804b.An isolation structure 802 is arranged in the substrate 102, configured to electrically isolate the semiconductor device 806 from other devices (not shown) arranged in and / or on the substrate 102. A source / drain region can, depending on the context, designate a source or a drain individually or collectively. The semiconductor device 806 can be an access control device for the RRAM cell 104.

[0058] An interconnect structure 812 is arranged above the substrate 102 and the semiconductor device 806. The interconnect structure 812 can comprise a dielectric interconnect structure 816, a plurality of conductive contacts 814, a plurality of conductive lines 818 (e.g., metal lines), and a plurality of conductive vias 820 (e.g., metal vias). The plurality of conductive lines are arranged in metallization layers separated by via layers. The plurality of conductive contacts 814, the plurality of conductive lines 818, and the plurality of conductive vias 820 are electrically connected in a defined manner and are configured to establish electrical connections between various devices arranged throughout the integrated chip 800.The majority of conductive contacts 814, the majority of conductive lines 818, and / or the majority of conductive vias 820 may be, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), ruthenium (Ru), aluminum (Al), copper (Cu), or the like, another conductive material, or a combination thereof. The dielectric interconnect structure 816 may have one or more intermetal dielectric layers, each of which may contain a low-k dielectric material, an oxide (e.g., silicon dioxide), another dielectric material, or a combination thereof.

[0059] A first of the plurality of conductive lines 818 is designated 818wl and can be called a word line. In some embodiments, the word line 818wl can be electrically connected to the gate electrode 810 of the semiconductor device 806 via the interconnect structure 812. A second of the plurality of conductive lines 818 is designated 818sl and can be called a source line. In further embodiments, the source line 818sl can be electrically connected to a first source / drain region 804a of the semiconductor device 806 via the interconnect structure 812. A third of the plurality of conductive lines 818 is designated 818bl and can be called a bit line.In further embodiments, the bit line 818bl can be electrically connected to the upper electrode 141 of the RRAM cell 104, and the lower electrode 108 can be electrically connected via the interconnect structure 812 to a second source / drain area 804b of the semiconductor device 806.

[0060] In some embodiments, the RRAM cell 104 is electrically connected to the second source / drain region 804b of the semiconductor device 806 via the interconnect structure 812. Thus, in some embodiments, by applying a suitable word line voltage to the word line 818wl, the RRAM cell 104 can be electrically connected between the bit line 818bl and the source line 818sl. Therefore, by providing suitable bias conditions, the RRAM cell 104 can be read or switched between two different data states. A current through the RRAM cell 104 also flows through the semiconductor device 806. To reduce the size of the semiconductor device 806, the RRAM cell 104 is designed to operate at lower voltages.

[0061] Fig. Figure 9 shows a sectional view of an integrated chip 900, which has a flash memory cell 901 arranged on top of the substrate 102. The flash memory cell 901 has the structure of a transistor with an RRAM cell 104D instead of the gate electrode. The flash memory cell 901 has the source / drain regions 804a and 804b, the dielectric gate layer 808, and the RRAM cell 104D. A spacer 903 can enclose the portion of the flash memory cell 901 that includes the dielectric gate layer 808 and the RRAM cell 104D.

[0062] The RRAM cell 104D comprises a lower electrode 108, a resistive switching structure 110, and an upper electrode 141. The lower electrode 108, the resistive switching structure 110, and the upper electrode 141 can have compositions, thicknesses, and other properties according to any of the examples of the present disclosure. As in the other examples of the present disclosure, in the flash memory cell 901, the order of the layers in the RRAM cell 104D can be reversed, but when reversing the order of the layers, the switching layer 118 with the higher oxygen affinity should remain closer to the electrode containing the capping metal layer 204, which has a solubility for oxygen ions, than the switching layer 116 with the lower oxygen affinity.

[0063] In flash memory cell 901, the lower electrode 108 is a floating-gate electrode. However, by applying suitable voltages between the source / drain regions 804a and 804b and the upper electrode 141, the RRAM cell 104D can be switched to the LRS and back to the HRS. The upper electrode 141 serves as a gate electrode for the flash memory cell 901. Switching the RRAM cell 104D between the LRS and the HRS changes its capacitive resistance, thereby changing the threshold voltage of the flash memory cell 901. The state of the flash memory cell 901 can be determined by applying a voltage to the upper electrode 141 that lies between the higher threshold voltage, corresponding to the LRS, and the lower threshold voltage, corresponding to the HRS.In some embodiments, the Flash memory cell 901 has threshold voltages that are lower than or equal to approximately 2.0 V in the HRS and the LRS.

[0064] By providing the RRAM cell 104D with a resistive switching structure 110 according to the present disclosure, the endurance of the flash memory cell 901 is greatly increased, since the resistive switching structure 110, which provides a low forming voltage, allows the RRAM cell 104D to be configured, reset, and read without progressively damaging the dielectric gate layer 808. The dielectric gate layer 808 can be silicon dioxide (SiO2). However, in some embodiments, the dielectric gate layer 808 is a high-k dielectric. The high-k dielectric can be a metal oxide or a silicate of hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), lead (Pb), or the like.Examples include hafnium-based materials such as hafnium oxide (HfO₂), hafnium silicon oxide (HfSiO₂), hafnium silicon oxide nitride (HfSiON₂), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO₂), hafnium zirconium oxide (HfZrO₂), a hafnium oxide-aluminum oxide alloy (HfO₂-Al₂O₃ alloy), and the like. Further examples include, without limitation, zirconium oxide (ZrO₂), tantalum oxide (Ta₂O₅), aluminum oxide (Al₂O₃), yttrium oxide (Y₂O₃), lanthanum oxide (La₂O₃), strontium titanium oxide (SrTiO₃), and the like. The dielectric gate layer 808 can have a thickness of approximately 4 Å to approximately 100 Å. In some embodiments, the dielectric gate layer 808 has a thickness of about 5 Å to about 25 Å.

[0065] Fig. Figure 10A shows a sectional view of an integrated chip 1000 which has a three-dimensional matrix (3D matrix) of RRAM cells 104E arranged over a substrate 102. Fig. Figure 10B is a truncated perspective view 1010 showing one of the RRAM cells 104E in the 3D matrix. Lower electrodes 108E are provided by horizontal layers in a stack 1012. In the stack 1012, the lower electrodes 108E are interlocked with dielectric layers 1001. The stack 1012 is shown with three layers containing lower electrodes 108E, but the stack 1012 can also contain a smaller or larger number of lower electrode layers. Vias 1003 through the stack 1012 contain upper electrodes 141E. The upper electrodes 141E are covered with a resistive switching structure 110E, such that the resistive switching structure 110E has a cylindrical shape.The RRAM cells 104E are manufactured at intersections between the upper electrodes 141E and the lower electrodes 108E at locations where an upper electrode 141E and a lower electrode 108E are separated only by a thickness of the resistive switching structure 110E.

[0066] The lower electrodes 108E protrude from one side of the stack 1012 to form edges 1014 in a stair-stepped structure 1015. Vias 1009 rest on the edges 1014 to connect leads 1011 to the lower electrodes 108E. Vias 1005 connect leads 1007 to the upper electrodes 141E. By selecting one of the leads 1007 and one of the leads 1011, one of the RRAM cells 104E in the 3D matrix can be individually addressed.

[0067] Fig. Figure 10C shows a top view 1020 of the integrated chip 1000. Dielectric-filled trenches 1021, which are in Fig. As shown in 10C, the lower electrodes 108E (see Fig. 10A) cut through to divide the 3D matrix into sections 1018. Each section 1018 shows only one row of vias 1003, but each section 1018 can contain multiple rows of vias 1003. The vias 1003 in adjacent rows can be aligned or offset.

[0068] The integrated chip 1000 has been described as a chip whose lower electrodes are arranged in horizontal layers and whose upper electrode is located in the vias 1003 through the stack 1012. However, the electrode designed to have oxygen solubility can be located in the horizontal layers, and the electrode with low or no oxygen solubility can be located in the vias 1003. In both cases, the switching layer 118 with the higher oxygen affinity of the resistive switching structure 110 should be located closer to the electrode designed to have oxygen solubility. If the electrode with the higher oxygen solubility has multiple layers, the fabrication process may be simpler if this electrode is located in the vias 1003.

[0069] In a 3D RRAM matrix, charging resistors tend to absorb the voltages used for programming, reading, and erasing the RRAM cells. This can be problematic in a 3D RRAM matrix with conventional RRAM cells. A 3D RRAM matrix with resistive circuit structures according to the present disclosure solves the charging resistor problem by enabling the memory to operate at lower voltages, e.g., 2 V or less.

[0070] The Fig. Figures 11 to 16 show a series of sectional views (1100 to 1600) of an integrated chip with a resistive switching structure according to the present disclosure at various manufacturing stages according to a process of the present disclosure. Fig. Although sections 11 to 16 describe a series of steps, it is understood that the order of the steps can be changed in some cases and that this series of steps can also be used for structures other than those shown. In some embodiments, some of these steps can be omitted completely or partially. It is also understood that the steps described in the Fig. The structures shown in Figures 11 to 16 are not limited to a single manufacturing process, but can be used as structures separate from the process.

[0071] As shown in section view 1100 of Fig. As shown in Figure 11, a first IMD layer 302 can be fabricated over a substrate 102, and a lower conductive conductor 106 can be fabricated in the first IMD layer 302. The substrate 102 can be, for example, silicon, monocrystalline silicon, silicon germanium, a silicon-on-insulator (SOI) substrate, one or more epitaxial layers, another suitable substrate, or a combination thereof. The first IMD layer 302 can be fabricated over the substrate 102, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or by another suitable growth or deposition process. In some embodiments, the lower conductive conductor 106 is fabricated as follows: etching the first IMD layer 302 to create an opening in it; and deposition (e.g. by PVD, CVD, electroplating, electroless plating, etc.).) the lower conductive line 106 in the opening.

[0072] A lower dielectric layer 304 is produced above the lower conductive line 106, and a lower electrode 108 is produced in the lower dielectric layer 304. The lower dielectric layer 304 can be produced above the lower conductive line 106, for example, by CVD, PVD, ALD, or by another suitable growth or deposition process. In some embodiments, a process for producing the lower electrode 108 includes: producing a masking layer (not shown) over the lower dielectric layer 304; etching (e.g., wet etching, dry etching, etc.) the lower dielectric layer 304 to create an opening above the lower conductive line 106; depositing (e.g., by PVD, CVD, electroplating, electroless plating, etc.) a lower electrode material in the opening; and performing a planarization process, e.g.,a chemical-mechanical polishing (CMP) process to remove excess lower electrode material.

[0073] The first IMD layer 302 can be, for example, silicon dioxide, a low-k dielectric material such as undoped silicate glass (USG) or carbon-doped silicon dioxide, another suitable dielectric material, or a combination thereof. The lower conductive conductor 106 can be, for example, aluminum (Al), copper (Cu), tungsten (W), ruthenium (Ru), titanium nitride (TiN), or the like, or a combination thereof. The lower dielectric layer 304 can be, for example, silicon oxide (SiO), silicon carbide (SiC), silicon oxide carbide (SiOC), silicon nitride (SiN), silicon oxide nitride (SiON), or the like, another dielectric material, or a combination thereof.

[0074] As shown in section view 1200 of Fig. As shown in Figure 12, a stack 1202 of memory layers can be fabricated above the lower electrode 108, and a masking layer 1204 can be fabricated above the stack 1202 of memory layers. In some embodiments, the stack 1202 of memory layers comprises the following: the switching layer 116 with the lower oxygen affinity, the switching layer 118 with the higher oxygen affinity, the diffusion barrier layer 202, the capping metal layer 204, and an upper metal layer 114. The layers in the stack 1202 of memory layers can be fabricated by CVD, PVD, ALD, electroplating, electroless plating, or the like, or by one or more other suitable growth or deposition processes. The masking layer 1204 is fabricated with a structure such that the masking layer 1204 covers a region of the stack 1202 of memory layers (e.g.,above the lower electrode 108) and leaves surrounding areas of the stack 1202 uncovered by storage layers.

[0075] In some embodiments, the switching layer 116 with the lower oxygen affinity and the switching layer 118 with the higher oxygen affinity are produced by ALD. In some embodiments, the switching layer 116 with the lower oxygen affinity contains a main metal oxide and a doping metal oxide, and the doping metal oxide is deposited in different ALD cycles than those for the main metal oxide.

[0076] As shown in section view 1300 of Fig. As shown in Figure 13, an etching process can be performed to remove the stack of 1202 memory layers (see Figure 13). Fig. 12) to structure according to the masking layer 1204, thereby forming the resistive switching structure 110, the capping structure 112, and the RRAM cell 104A. The etching process may, for example, include one or more dry etching processes, wet etching processes, a combination thereof, or the like. The masking layer 1204 (see Fig. 12) can be removed during or after the structuring process.

[0077] As shown in section view 1400 of Fig. As shown in Figure 14, a sidewall spacer structure 308 is fabricated above and around the RRAM cell 104A, and a second IMD layer 306 is fabricated above the sidewall spacer structure 308 and the lower dielectric layer 304. The sidewall spacer structure 308 can be fabricated above the RRAM cell 104A, for example, by CVD, PVD, ALD, or another suitable growth or deposition process. The second IMD layer 306 can be fabricated above the lower dielectric layer 304, for example, by CVD, PVD, ALD, or another suitable growth or deposition process.

[0078] As shown in section view 1500 of Fig. As shown in Figure 15, an upper conductive structure 120 is produced above the upper electrode 141. In some embodiments, a process for producing the upper conductive structure 120 comprises: producing a masking layer (not shown) over the second IMD layer 306; structuring the second IMD layer 306 and the sidewall spacer structure 308 according to the masking layer, thereby creating an opening above the upper electrode 141; depositing (e.g., by CVD, PVD, electroplating, electroless plating, etc.) a conductive material (containing, for example, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, etc.) in the opening; and performing a planarization process (e.g., a CMP process) on the conductive material.

[0079] As shown in section view 1600 of Fig. As shown in Figure 16, a third IMD layer 402 is fabricated over the second IMD layer 306, and an upper conductive via 404 and an upper conductive line 406 are fabricated in the third IMD layer 402. The third IMD layer 402 is fabricated over the second IMD layer 306, for example, by CVD, PVD, ALD, or by another suitable growth or deposition process. In some embodiments, fabricating the upper conductive via 404 and the upper conductive line 406 includes: etching the third IMD layer 402 to create one or more openings in it; depositing (e.g., by CVD, PVD, sputtering, electroplating, etc.) a conductive material (e.g., aluminum, copper, titanium nitride, tantalum nitride, ruthenium, etc.) in the one or more openings; and performing a planarization process (e.g., a CMP process) on the conductive material.The third IMD layer 402 can, for example, contain silicon dioxide, a dielectric low-k material such as USG or carbon-doped silicon dioxide, another suitable dielectric material, or a combination thereof.

[0080] The Fig. Figures 17 to 23 show a series of sectional views (1700 to 2300) of an integrated chip having a resistive switching structure according to the present disclosure, at various manufacturing stages according to a further process of the present disclosure. Fig. Although sections 17 to 23 describe a series of steps, it is understood that the order of the steps can be changed in some cases and that this series of steps can also be used for structures other than those shown. In some embodiments, some of these steps can be omitted completely or partially. It is also understood that the steps described in the Fig. The structures shown in Figures 17 to 23 are not limited to a single manufacturing process, but can be used as structures separate from the process.

[0081] As shown in section view 1700 of Fig. As shown in Figure 17, a first IMD layer 302 is fabricated over a substrate 102, and a lower conductive line 106 is fabricated in the first IMD layer 302. The first IMD layer 302 and the lower conductive line 106 can be fabricated as shown in Figure 17. Fig. Figure 11 shows and / or describes the lower dielectric layer 304 above the lower conductive line 106. The lower dielectric layer 304 can be produced, for example, by CVD, PVD, ALD, or another suitable process.

[0082] As shown in the sectional view 1800 from Fig. As shown in Figure 18, a structuring process is carried out on the lower dielectric layer 304 to create an opening 1802 in it. In some embodiments, the structuring process includes producing a masking layer (not shown) over the lower dielectric layer 304 and treating unmasked areas of the lower dielectric layer 304 with one or more etching agents. The structuring process may, for example, include a wet etching process, a dry etching process, or the like.

[0083] As shown in the 1900 section view. Fig. As shown in Figure 19, a stack of 1902 storage layers is produced above the lower conductive line 106 and the lower dielectric layer 304, thereby creating the opening (1802 of Fig. 18) is filled. In some embodiments, the stack 1902 of storage layers comprises the following: the lower electrode 108B, the lower oxygen affinity switching layer 116, the higher oxygen affinity switching layer 118, the diffusion barrier layer 202, the capping metal layer 204, and the upper electrode 141. The storage layers 1902 can be fabricated by CVD, PVD, ALD, electroplating, electroless plating, or by one or more other suitable growth or deposition processes. The lower electrode 108 is fabricated to have a domed top surface 410 with a depression corresponding to the opening 1802. In some embodiments, the lower oxygen affinity switching layer 116 and the higher oxygen affinity switching layer 118 are fabricated by ALD, such that their shapes each correspond to the domed top surface 410.A masking layer 1904 can be produced above the stack 1902 of memory layers, defining the shape of a memory cell centered over the opening 1802.

[0084] As shown in the section view 2000 from Fig. As shown in Figure 20, a structuring process is performed on the stack of 1902 memory layers (see Figure 20). Fig. 19) is carried out, defining the resistive switching structure 110B, the upper electrode 141B, and the RRAM cell 104B. In some embodiments, the structuring process includes treating unmasked areas (e.g., in the peripheral region) of the layers in the stack 1902 of memory layers with one or more etchants. The structuring process may, for example, include one or more dry etching processes, one or more wet etching processes, or the like. The masking layer 1904 (see Fig. 19) can be removed during or after the structuring process.

[0085] As shown in section view 2100 from Fig. As shown in Figure 21, a sidewall spacer structure 308 can be fabricated above and around the RRAM cell 104B, and a second IMD layer 306 can be fabricated above the sidewall spacer structure 308 and the lower dielectric layer 304. The sidewall spacer structure 308 can be fabricated, for example, by CVD, PVD, ALD, or another suitable growth or deposition process. The second IMD layer 306 can be fabricated above the lower dielectric layer 304, for example, by CVD, PVD, ALD, or another suitable growth or deposition process.

[0086] As shown in section view 2200 from Fig. As shown in Figure 22, an upper conductive structure 120 can be fabricated above the upper electrode 141. In some embodiments, a process for fabricating the upper conductive structure 120 comprises: fabricating a masking layer (not shown) over the second IMD layer 306; structuring the second IMD layer 306 and the sidewall spacer structure 308 according to the masking layer, thereby creating an opening above the upper electrode 141; depositing (e.g., by CVD, PVD, electroplating, electroless plating, etc.) a conductive material (e.g., aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, etc.) in the opening; and performing a planarization process (e.g., a CMP process) on the conductive material.

[0087] As shown in section view 2300 of Fig. As shown in Figure 23, a third IMD layer 402 is fabricated over the second IMD layer 306, and an upper conductive via 404 and an upper conductive line 406 are fabricated in the third IMD layer 402. The third IMD layer 402 is fabricated over the second IMD layer 306, for example, by CVD, PVD, ALD, or by another suitable growth or deposition process. In some embodiments, fabricating the upper conductive via 404 and the upper conductive line 406 includes: etching the third IMD layer 402 to create one or more openings in it; depositing (e.g., by CVD, PVD, sputtering, electroplating, etc.) a conductive material (e.g., aluminum, copper, titanium nitride, tantalum nitride, ruthenium, etc.) in the one or more openings; and performing a planarization process (e.g., a CMP process) on the conductive material.

[0088] The Fig. Figures 24 to 27 show a series of sectional views (2400 to 2700) of an integrated chip according to the present disclosure at various manufacturing stages using a process according to some embodiments. Fig. Although sections 24 to 27 describe a series of steps, it is understood that the order of the steps can be changed in some cases and that this series of steps can also be used for structures other than those shown. In some embodiments, some of these steps can be omitted completely or partially. It is also understood that the steps described in the Fig. The structures shown in Figures 24 to 27 are not limited to a single manufacturing process, but can be used as structures separate from the process. The process is illustrated by the fabrication of the integrated chip 900. Fig. 9, which has the flash memory cell 901, is explained, but it can also be used to manufacture other integrated chips according to the present disclosure.

[0089] As shown in section view 2400 of Fig. As shown in Figure 24, the process can begin with the fabrication of the insulating structures 802 in the substrate 102. In this example, the substrate 102 is a semiconductor substrate. The process can include etching trenches in the substrate 102 and filling the trenches with a dielectric.

[0090] As shown in section view 2500 of Fig. As shown in Figure 25, a flash memory cell stack 2501 is fabricated on substrate 102. The flash memory cell stack 2501 comprises: the dielectric gate layer 808; the bottom electrode 108; the switching layer 116 with the lower oxygen affinity; the switching layer 118 with the higher oxygen affinity; the diffusion barrier layer 202, which is optional; the capping metal layer 204; and the top metal layer 114, which is also optional. The layers of the flash memory cell stack 2501 can be fabricated by CVD, PVD, ALD, electroplating, electroless plating, or the like, or by one or more other suitable growth or deposition processes. In some embodiments, the switching layer 116 with the lower oxygen affinity and the switching layer 118 with the higher oxygen affinity are fabricated by ALD.In some embodiments, the switching layer 116 with the lower oxygen affinity contains a main metal oxide and a doping metal oxide, wherein the doping metal oxide is deposited in ALD cycles that differ from those for the main metal oxide. A masking layer 2503 is fabricated over the flash memory cell stack 2501 and subsequently patterned.

[0091] As shown in section view 2600 of Fig. As shown in Figure 26, an etching process can be performed to modify the flash memory cell stack 2501 (see Figure 26). Fig. 25) to structure according to the masking layer 2503, thereby separating the flash memory cell 901, which contains the RRAM cell 104D, from the flash memory cell stack 2501. The etching process may, for example, include one or more dry etching processes, wet etching processes, a combination thereof, or the like. The masking layer 2503 (see Fig. 25) can be removed during or after the structuring process.

[0092] As shown in section view 2700 of Fig. As shown in Figure 27, the spacer 903 can be fabricated around the flash memory cell stacks 2501. The fabrication process for the spacer 903 can include depositing a spacer material and subsequent anisotropic etching. Then, an ion implantation process can be performed to create a first and a second source / drain region 804a and 804b (see Figure 27). Fig. 9) to produce by doping the substrate 102 in accordance with the spacer 903.

[0093] In some embodiments, the order of the RRAM cell layers in the flash memory cell stack 2501 (see Fig. 25) conversely, so that the upper electrode 141 (see Fig. 27) is located under the resistive switching structure 110 and the switching layer 116 with the lower oxygen affinity is deposited after the switching layer 118 with the higher oxygen affinity.

[0094] In some embodiments, the process of Fig. 24 to 27 are modified to provide a gate replacement process. In the gate replacement process, a dummy gate stack is first fabricated and structured. After the spacer 903 is fabricated, a dielectric layer is deposited, and after the dummy gate is removed, the surface is planarized. The flash memory cell stack 2501 is deposited to fill the opening created by the removal of the dummy gate. After planarization, a flash memory cell remains with a resistive switching structure featuring a convex central region, similar to the resistive switching structure 110C of Fig. 5 back.

[0095] The Fig. Figures 28 to 32 show a series of sectional views 2800 to 3200 of an integrated chip according to the present disclosure at various manufacturing stages using a process according to some embodiments. Fig. Although sections 28 to 32 describe a series of steps, it is understood that the order of the steps can be changed in some cases and that this series of steps can also be used for structures other than those shown. In some embodiments, some of these steps can be omitted completely or partially. It is also understood that the steps described in the Fig. The structures shown in Figures 28 to 32 are not limited to a single manufacturing process, but can be used as structures separate from the process. The process is illustrated by the fabrication of the integrated chip 1000. Fig. 10A explains, but it can also be used to manufacture other integrated chips according to the present disclosure.

[0096] As shown in section view 2800 of Fig. As shown in Figure 28, the process can begin with the fabrication of the stack 1012 over the substrate 102. The stack 1012 is fabricated using alternating processes for depositing the dielectric layers 1001 and processes for depositing the lower electrodes 108E. The dielectric layers 1001 can be deposited by CVD, PVD, ALD, or the like, or by any other suitable growth or deposition process. The lower electrodes 108E can be fabricated by CVD, PVD, ALD, electroplating, electroless plating, or the like, or by any other suitable growth or deposition process. In some embodiments, sacrificial layers are initially provided instead of the lower electrodes 108E. Subsequently, the sacrificial layers can be replaced by the lower electrodes 108E.

[0097] As shown in section view 2900 of Fig. As shown in Figure 29, the stair structure 1015 can then be created on one side of the stack 1012. Creating the stair structure 1015 can involve multiple masking and etching operations.

[0098] As shown in section view 3000 of Fig. As shown in Figure 30, a mask 3001 can be fabricated and used to etch holes 3005 extending through the lower electrodes 108E of the stack 1012. The etching process can, for example, include one or more dry etching processes, wet etching processes, or the like. Prior to fabricating the mask 3001, a dielectric 3003 can be deposited and planarized to facilitate the fabrication and structuring of the mask 3001. Optionally, after etching, a remaining portion of the mask 3001 can be removed.

[0099] As shown in section view 3100 of Fig. As shown in Figure 31, the switching layer 116 with the lower oxygen affinity and the switching layer 118 with the higher oxygen affinity are deposited by a conformal deposition process to line the holes 3005. In some embodiments, the conformal deposition process is an ALD or the like. In some embodiments, the switching layer 116 with the lower oxygen affinity contains a main metal oxide and a doping metal oxide, the doping metal oxide being deposited in ALD cycles that differ from those for the main metal oxide.

[0100] As shown in section view 3200 of Fig. As shown in Figure 32, the material for the upper electrodes 141E can be deposited to fill the holes 3005, and subsequently a planarization process can be performed to confine the upper electrodes 141E to the holes 3005. The upper electrodes 141E can contain multiple layers of different materials, as shown in other examples. The upper electrodes 141E can be deposited using one or more CVD, PVD, ALD, electroplating, or electroless plating processes, or other suitable growth or deposition processes. The planarization process can be CMP or the like. An IMD layer 1013 can be deposited, and subsequently the vias 1005 and 1009 and the leads 1007 and 1011 can be fabricated to provide a structure as shown in Figure 32. Fig. 10A is shown.

[0101] The Fig. Figures 33 to 36 show flowcharts for processes 3300 to 3600 for fabricating RRAM cells with resistive switching structures according to some embodiments and for fabricating integrated chips with the RRAM cells. Although processes 3300 to 3600 are presented and / or described as a series of steps or events, it is understood that these processes are not limited to the sequence or steps shown. Therefore, in some embodiments, the steps may be performed in a different sequence than shown, and / or they may be performed concurrently. Furthermore, in some embodiments, the steps or events shown may be subdivided into several steps or events that may occur at separate times or concurrently with other steps or substeps.In some embodiments, some of the illustrated steps or events may be omitted, and other, unillustrated steps or events may be used.

[0102] Fig. Figure 33 shows a flowchart for a method 3300 for fabricating an RRAM cell with a resistive switching structure according to some embodiments. The method 3300 begins with a step 3301 for fabricating a lower electrode. In some embodiments, the lower electrode is selected to have low oxygen solubility and whose work function is well matched to a work function of the switching layer with the lower oxygen affinity.

[0103] Step 3303 comprises fabricating the lower oxygen affinity interface layer and includes steps 3305, 3307, and 3309. Step 3305 comprises performing N ALD cycles in which monolayers of an oxide of the lower oxygen affinity metal are deposited. N is a number that is 4 or greater. In some embodiments, N is 6 or greater. Step 3307 comprises performing a single ALD cycle in which an oxide of a dopant metal is deposited. The dopant metal has a higher oxygen affinity than the lower oxygen affinity metal (primary metal). Step 3309 comprises determining whether the deposition of the lower oxygen affinity interface layer has been completed.

[0104] Step 3303 is depicted as a step that begins with a primary metal deposition and ends with a dopant metal deposition, but this depiction is only for the sake of simplicity in the flowchart. The deposition can begin or end with a primary metal oxide deposition or a dopant metal oxide deposition. If the deposition begins or ends with a primary metal oxide deposition, there can be fewer than N dopant metal depositions at the beginning or end. The completion check in step 3309 can be performed after each cycle instead of after each complete group of N + 1 cycles. Regardless, there are N primary metal oxide deposition cycles between each successive pair of dopant metal oxide deposition cycles.

[0105] Method 3300 continues with step 3311 for the deposition of the switching layer with the higher oxygen affinity. In some embodiments, this comprises a plurality of ALD cycles in which monolayers of the metal oxide with the higher oxygen affinity are deposited.

[0106] Step 3313 includes fabricating an upper electrode. Fabricating the upper electrode may include the following steps: a step 3315 for depositing a diffusion barrier layer; a step 3317 for depositing a capping layer; and a step 3319 for depositing an upper metal layer. These layers may be deposited by CVD, PVD, ALD, electroplating, electroless plating, or the like, or by other suitable growth or deposition processes. The capping layer is a metal with high oxygen solubility. Steps 3315 and 3319 are optional. In some embodiments, the order of the steps in process 3300 is reversed, so that the layers of the RRAM cell are fabricated in reverse order.

[0107] Fig. Figure 34 shows a flowchart for a method 3400 for fabricating an integrated chip with an RRAM cell according to some embodiments. The method 3400 begins with a step 3402 for fabricating a lower electrode over a substrate. Sectional views 1100 and 1800 of the Fig. 11 and Fig. 18 provide examples.

[0108] Step 3404 involves fabricating a memory stack above the substrate. The memory stack contains a switching layer with a lower oxygen affinity, a switching layer with a higher oxygen affinity, and an upper electrode layer. Sectional views 1200 and 1900 of the Fig. 12 and Fig. 19 provide examples. Steps 3402 and 3404 can be performed according to procedure 3300 of Fig. 33 will be executed.

[0109] Step 3406 involves structuring the memory stack to define one or more RRAM cells. Sectional views 1300 and 2000 of the Fig. 13 and Fig. 20 provide examples.

[0110] Step 3408 involves fabricating a sidewall spacer structure around the RRAM cell and, optionally, above the RRAM cell. Sectional views 1400 and 2100 of the Fig. 14 and Fig. 21 provide examples.

[0111] Step 3410 involves fabricating an intermetal dielectric layer over the RRAM cell. Step 3412 involves fabricating a conductive via through the intermetal dielectric to contact the RRAM cell. Sectional views 1500 and 2200 of the Fig. 15 and Fig. 22 provide examples.

[0112] Fig. Figure 35 shows a flowchart for a process 3500 for fabricating an integrated chip with a flash memory cell in which an RRAM cell structure is integrated. The process 3500 begins with a step 3502 for fabricating isolation structures in a semiconductor substrate. The sectional view 2400 of Fig. 24 provides an example.

[0113] Step 3504 involves fabricating a flash memory stack on top of the substrate. Sectional view 2500 of Fig. Figure 25 provides an example. The flash memory stack comprises a dielectric gate layer, a lower electrode layer, a lower oxygen affinity switching layer, a higher oxygen affinity switching layer, and an upper electrode layer. In some embodiments, the lower electrode layer, the lower oxygen affinity switching layer, the higher oxygen affinity switching layer, and an upper electrode layer are formed according to Method 3300 of Fig. 33 manufactured. In a gate replacement process, a dummy gate stack is first manufactured instead of the flash memory stack.

[0114] Step 3506 involves structuring the flash memory stack to define a flash memory cell. Sectional view 2600 of Fig. Section 26 provides an example. In a gate replacement process, this process is used to structure a dummy gate from the dummy gate stack.

[0115] Step 3508 involves creating a spacer around the flash memory cell. Sectional view 2700 of Fig. Figure 27 provides an example. In a gate replacement process, this spacer is manufactured around a dummy gate.

[0116] Step 3510 involves doping in alignment with the spacer to create source / drain areas for the flash memory cell. The integrated 900 chip from Fig. Figure 9 shows this type of doping. In a gate replacement process, the dummy gate is removed after this doping process, and the flash memory stack is deposited in the resulting opening.

[0117] Fig. Figure 36 shows a flowchart for process 3600 for fabricating an integrated chip with a 3D matrix of RRAM cells. Process 3600 begins with step 3601 for fabricating a stack of alternating layers of an electrode material and an insulating material. The sectional view 2800 of Fig. 28 provides an example.

[0118] Step 3603 involves creating a stair-step structure at one edge of the stack. In the stair-step structure, each electrode layer is manufactured so that it protrudes from the higher electrode layers in an offset arrangement. Section 2900 of Fig. 29 provides an example.

[0119] Step 3605 involves etching a matrix of holes through the stack. Section view 3000 of Fig. 30 provides an example.

[0120] Step 3607 comprises lining the sidewalls of the holes with a resistive switching structure. In some embodiments, the resistive switching structure has a layer with a lower oxygen affinity and a layer with a higher oxygen affinity. In some embodiments, the layer with the lower oxygen affinity is formed according to step 3303 in method 3300 of Fig. 33 manufactured. The sectional view 3100 of Fig. Figure 31 provides an example of the type of structure that is created by lining the sidewalls of the holes with the resistive switching structure.

[0121] Step 3609 comprises filling the holes with the materials of a second electrode. In some embodiments, the second electrode has a diffusion barrier layer. In some embodiments, filling the holes comprises depositing a diffusion barrier layer and a capping metal layer, wherein the capping metal is a metal with high oxygen solubility. Sectional view 3200 of Fig. 32 provides an example.

[0122] Step 3611 involves etching trenches through the electrode layers of the stack. These trenches are arranged to divide the electrode layers beneath memory cell sections. The trenches can then be filled with a dielectric. Top view 1020 of Fig. Figure 10C shows exemplary positions for these trenches.

[0123] Step 3613 involves fabricating an intermetal dielectric layer over the stack. Step 3615 involves fabricating vias through the intermetal dielectric layer. The vias include first vias to make contacts with the electrode layers of the stack and second vias for contacts with the second electrodes located in the holes. The sectional view of the integrated chip 1000 of Fig. Figure 10A shows an example of these vias.

[0124] Some aspects of the present disclosure relate to an integrated chip having a resistive switching structure between a first and a second electrode. The resistive switching structure has a first layer adjacent to the first electrode and a second layer adjacent to the second electrode. A majority of the first layer comprises oxides of a first metal. A minority of the first layer comprises oxides of a second metal. The second layer contains oxides of a third metal. The second and third metals have lower (more negative) standard free enthalpies of formation for oxides on a per-molar oxygen basis than the first metal.

[0125] In some embodiments, a difference in oxygen affinity between the first and second layers increases the concentration of intrinsic oxygen vacancies in the first layer to a level that lowers the forming voltage for a memory cell comprising the first and second electrodes and the resistive switching structure. In some embodiments, the proportion of the second metal in the first layer ranges from 0.1 atomic percent to 10 atomic percent. In some embodiments, the second metal has a per-mol oxygen-based (per-mol O₂-based) standard free enthalpy of formation of an oxide that is at least 200 kJ / mol lower than that of the first metal. In some embodiments, the third metal has a per-mol oxygen-based (per-mol O₂-based) standard free enthalpy of formation of an oxide that is at least 200 kJ / mol lower than that of the first metal.In some embodiments, the second metal has a per-mol oxygen-based (per-mol O₂-based) standard free enthalpy of formation of an oxide that is higher than that of the third metal. In some embodiments, the thickness of the first layer is 0.5 to 1.3 times the thickness of the second layer. In some embodiments, the second metal in the first layer reduces the width of a conductive filament in the first layer formed by the resistive switching structure through pulses of a voltage difference between the first and second electrodes. In some embodiments, the second electrode has a higher oxygen solubility than the first electrode.

[0126] In some embodiments, the second layer contains zirconium oxide, and the first layer contains hafnium tantalum oxide, aluminum tantalum oxide, lanthanum tantalum oxide, titanium tantalum oxide, titanium silicon oxide, hafnium silicon oxide, or hafnium zinc oxide. In some embodiments, the second layer contains hafnium oxide, and the first layer contains zirconium tantalum oxide, lanthanum tantalum oxide, titanium tantalum oxide, zirconium silicon oxide, or zirconium zinc oxide. In some embodiments, the second layer contains lanthanum oxide, and the first layer contains hafnium tantalum oxide, aluminum tantalum oxide, hafnium silicon oxide, hafnium zinc oxide, or zirconium zinc oxide.

[0127] In some embodiments, the resistive switching structure is non-planar. In some embodiments, the resistive switching structure is a data storage structure for a memory cell in a three-dimensional matrix of memory cells. In some embodiments, the integrated chip further comprises a dielectric gate layer between the first electrode and a semiconductor channel of a transistor, wherein the second electrode provides a gate electrode for the transistor, the first electrode is a floating gate in the transistor, and the resistive switching structure provides a variable threshold voltage for the transistor. In some embodiments, the first layer contains a substoichiometric amount of oxygen with respect to the maximum oxides of its metallic constituents.

[0128] Some aspects of the present disclosure relate to an integrated chip having a resistive switching structure between a first and a second electrode. The resistive switching structure has a first layer adjacent to the first electrode and a second layer adjacent to the second electrode. A majority of the first layer comprises oxides of a first metal. A minority of the first layer comprises oxides of a second metal. The second layer contains oxides of a third metal. The second and third metals have lower oxygen affinities than the first metal. In some embodiments, the second metal is contained in dopant-containing layers of the first layer, and multiple monolayers of oxides of the first metal are arranged between adjacent dopant-containing layers.

[0129] Some aspects of the present disclosure relate to a method for fabricating an integrated chip. The method comprises fabricating a first electrode over a substrate and depositing a first metal oxide layer, wherein the first metal oxide layer contains a first and a second metal, wherein an atomic ratio between the first and the second metal in the first metal oxide layer is 5:1 or greater, and the first metal has a lower standard free enthalpy of formation for oxygen vacancies for its maximum oxide than the second metal.The process further comprises: depositing a second metal oxide layer, wherein the second metal oxide layer contains a third metal and the first metal has a lower standard free enthalpy of formation for oxygen vacancies for its maximum oxide than the third metal; and fabricating a second electrode, wherein the first and second metal oxide layers are positioned between the first and second electrodes, and the first electrode, the first and second metal oxide layers, and the second electrode form an RRAM cell. In some embodiments, the first and second metal oxide layers are deposited by atomic layer deposition, and the first and second metals are deposited in different atomic layer deposition cycles.

[0130] Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present disclosure. It should be clear to those skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other methods and structures to achieve the same objectives and / or to obtain the same advantages as in the embodiments presented here. Those skilled in the art should also recognize that such equivalent interpretations do not deviate from the fundamental concept and scope of protection of the present disclosure and that they can make various changes, substitutions, and modifications without deviating from the fundamental concept and scope of protection of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 690.333

[0001]

Claims

[1] Integrated chip with: a metallic interconnect structure over a semiconductor substrate, wherein the metallic interconnect structure has first and second conductive lines; a first and a second electrode arranged in the metallic interconnect structure, wherein the first and the second electrode are electrically connected to the first and second conductive lines, respectively; and a resistive switching structure between the first and second electrode, wherein The resistive switching structure has a first layer near the first electrode and a second layer near the second electrode. a majority of the first layer comprises oxides of a first metal and a minority of the first layer comprises oxides of a second metal, the second layer contains oxides of a third metal, and The second and third metals have lower (more negative) standard free enthalpies of formation for oxides on a per-mol oxygen basis than the first metal. [2] Integrated chip according to claim 1, wherein a difference in oxygen affinity between the first and second layers increases the concentration of intrinsic oxygen vacancies in the first layer to a size that lowers a forming voltage for a memory cell comprising the first and second electrodes and the resistive radiation structure. [3] Integrated chip according to claim 1 or 2, wherein the content of the second metal in the first layer is 0.1 atomic % to 10 atomic %. [4] Integrated chip according to any of the preceding claims, wherein the second metal has a standard free enthalpy of formation for an oxide on a per-mol oxygen basis (per-mol O2 basis) which is at least 200 kJ / mol lower than that of the first metal. [5] Integrated chip according to any of the preceding claims, wherein the third metal has a standard free enthalpy of formation for an oxide on a per-mol oxygen basis (per-mol O2 basis) which is at least 200 kJ / mol lower than that of the first metal. [6] Integrated chip according to one of the preceding claims, wherein the second metal has a standard free enthalpy of formation for an oxide on a per-mol oxygen basis (per-mol O2 basis) that is higher than that of the third metal. [7] Integrated chip according to any of the preceding claims, wherein the thickness of the first layer is 0.5 to 1.3 times the thickness of the second layer. [8] Integrated chip according to one of the preceding claims, wherein the second metal in the first layer reduces the width of a conductive filament in the first layer formed through the resistive switching structure by pulsing a voltage difference between the first and the second electrode. [9] Integrated chip according to any of the preceding claims, wherein the second electrode has a greater oxygen solubility than the first electrode. [10] Integrated chip according to any of the preceding claims, wherein the second layer contains zirconium oxide, and the first layer contains hafnium tantalum oxide, aluminum tantalum oxide, lanthanum tantalum oxide, titanium tantalum oxide, titanium silicon oxide, hafnium silicon oxide or hafnium zinc oxide. [11] Integrated chip according to any of the preceding claims, wherein the second layer contains hafnium oxide, and the first layer contains zirconium tantalum oxide, lanthanum tantalum oxide, titanium tantalum oxide, zirconium silicon oxide or zirconium zinc oxide. [12] Integrated chip according to any of the preceding claims, wherein the second layer contains lanthanum oxide, and the first layer contains hafnium tantalum oxide, aluminum tantalum oxide, hafnium silicon oxide, hafnium zinc oxide or zirconium zinc oxide. [13] Integrated chip according to any of the preceding claims, wherein the resistive switching structure is non-planar. [14] Integrated chip according to one of the preceding claims, wherein the resistive switching structure is a data storage structure for a memory cell in a three-dimensional matrix of memory cells. [15] Integrated chip according to any of the preceding claims, wherein the integrated chip further comprises a dielectric gate layer between the first electrode and a semiconductor channel of a transistor, wherein the second electrode provides a gate electrode for the transistor, the first electrode is a floating gate in the transistor, and The resistive switching structure provides a variable threshold voltage for the transistor. [16] Integrated chip according to any of the preceding claims, wherein the first layer contains a substoichiometric amount of oxygen with respect to maximum oxides of its metal constituents. [17] Method for manufacturing an integrated chip, comprising: Creating a metallization layer that has a conductive path over a substrate; Manufacturing a stack containing a first electrode layer, a resistive switching structure and a second electrode layer above the metallization layer, wherein the first electrode layer is electrically connected to the conductive line, the resistive switching structure is arranged between the first and second electrode layers, The resistive switching structure has a first metal oxide layer near the first electrode layer and a second metal oxide layer near the second electrode layer. a majority of the first metal oxide layer comprises oxides of a first metal and a minority of the first metal oxide layer comprises oxides of a second metal, the second metal oxide layer contains oxides of a third metal, and the second and third metals have lower oxygen affinities than the first metal; and Structuring the stack to define a resistive random access memory cell. [18] Method according to claim 17, wherein the second metal is contained in dopant-containing layers of the first electrode layer, and Multiple monolayers of oxides of the first metal are arranged between adjacent dopant-containing layers. [19] Method for manufacturing an integrated chip, comprising: Establishing a first electrode over a substrate; Deposition of a first metal oxide layer, wherein the first metal oxide layer contains a first and a second metal, wherein an atomic ratio between the first and the second metal in the first metal oxide layer is 5:1 or greater, and the first metal has a lower standard free enthalpy of formation for oxygen vacancies for its maximum oxide than the second metal; Deposition of a second metal oxide layer, wherein the second metal oxide layer contains a third metal and the first metal has a lower standard free enthalpy of formation for oxygen vacancies for its maximum oxide than the third metal; and Manufacturing a second electrode, wherein the first and second metal oxide layers are arranged between the first and second electrodes, and the first electrode, the first and second metal oxide layers, and the second electrode form a resistive direct access memory cell. [20] Method according to claim 19, wherein the first and second metal oxide layers are deposited by atomic layer deposition, and The first and second metals are deposited in different atomic layer deposition cycles.

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