Neural network with variable resolution

Abstract

Apparatus, systems, and techniques for using one or more neural networks with adjusted resolution information. For example, in at least one embodiment, one or more encoders of a low-resolution neural network are trained to one or more higher resolutions. In at least one embodiment, as another example, a processor adjusts an information resolution to be used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application incorporates by reference for all purposes the entire disclosure of copending U.S. patent application No. 18 / 402,415, filed January 2, 2024, entitled "IMAGE GENERATION USING TEXT" (Attorney Docket No. 0112912-A13US0US0I) and copending U.S. patent application No. 18 / 543,898, filed December 18, 2023, entitled "IMAGE GENERATION USING NEURAL NETWORKS" (Attorney Docket No. 0112912-A12US0). TECHNICAL FIELD

[0002] At least one embodiment relates to adapting an information resolution for use by one or more neural networks. For example, at least one embodiment relates to processors and / or computer systems used to adapt an information resolution to be used by one or more neural networks based at least in part on one or more performance metrics of the one or more neural networks. BACKGROUND

[0003] Methods for using a neural network, for example, to generate an image, require significant investment in resources. Techniques for executing a neural network can be improved. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a training circuit communicating with a neural network, in accordance with at least one embodiment; Fig. 2 is a block diagram illustrating the flow of information within a training circuit communicating with a neural network, according to at least one embodiment; Fig. 3 is a block diagram showing a processor and modules according to at least one embodiment; Fig. 4 is a block diagram illustrating a neural network training module, according to at least one embodiment; Fig. 5 is a block diagram illustrating one or more neural networks that adjust resolution, in accordance with at least one embodiment; Fig. 6 is a block diagram illustrating one or more neural networks adapting to higher resolution using one or more neural network outputs, in accordance with at least one embodiment; Fig. 7 is a process flow diagram illustrating resolution adjustment according to at least one embodiment; Fig. 8 is a block diagram illustrating a driver and / or runtime including one or more libraries to provide one or more APIs, according to at least one embodiment; Fig. 9A shows logic according to at least one embodiment; Fig. 9B shows the logic according to at least one embodiment; Fig. 10 shows the training and deployment of a neural network according to at least one embodiment; Fig. 11 shows an example of a data center system according to at least one embodiment; Fig. 12A shows an example of an autonomous vehicle according to at least one embodiment; Fig. Figure 12B shows an example of camera positions and fields of view for the autonomous vehicle of Fig. 12A, according to at least one embodiment; Fig. 12C is a block diagram showing an example system architecture for the autonomous vehicle of Fig. 12A according to at least one embodiment; Fig. 12D is a diagram illustrating a system for communication between one or more cloud-based servers and the autonomous vehicle of Fig. 12A according to at least one embodiment; Fig. 13 is a block diagram illustrating a computer system according to at least one embodiment; Fig. 14 is a block diagram illustrating a computer system according to at least one embodiment; Fig. 15 shows a computer system according to at least one embodiment; Fig. 16 shows a computer system according to at least one embodiment; Fig. 17A shows a computer system according to at least one embodiment; Fig. 17B shows a computer system according to at least one embodiment; Fig. 17C shows a computer system according to at least one embodiment; Fig. 17D shows a computer system according to at least one embodiment; Fig. 17E and Fig. 17F illustrate a common programming model according to at least one embodiment; Fig. 18 shows exemplary integrated circuits and associated graphics processors according to at least one embodiment; Fig. 19A-19B illustrate exemplary integrated circuits and associated graphics processors according to at least one embodiment; Fig. 20A-20B illustrate additional exemplary graphics processor logic according to at least one embodiment; Fig. 21 shows a computer system according to at least one embodiment; Fig. 22A shows a parallel processor according to at least one embodiment; Fig. 22B shows a partition unit according to at least one embodiment; Fig. 22C shows a processing cluster, according to at least one embodiment; Fig. 22D shows a graphics multiprocessor according to at least one embodiment; Fig. 23 shows a system with multiple graphics processing units (GPU) according to at least one embodiment; Fig. 24 shows a graphics processor according to at least one embodiment; Fig. 25 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment; Fig. 26 shows a deep learning application processor according to at least one embodiment; Fig. 27 is a block diagram illustrating an exemplary neuromorphic processor according to at least one embodiment; Fig. 28 shows at least portions of a graphics processor according to one or more embodiments; Fig. 29 shows at least portions of a graphics processor according to one or more embodiments; Fig. 30 shows at least portions of a graphics processor according to one or more embodiments; Fig. 31 is a block diagram of a graphics processing engine of a graphics processor in accordance with at least one embodiment; Fig. 32 is a block diagram of at least portions of a graphics processor core according to at least one embodiment; Fig. 33A-33B illustrates thread execution logic including an array of processing elements of a graphics processor core according to at least one embodiment; Fig. 34 shows a parallel processing unit (“PPU”) according to at least one embodiment; Fig. 35 shows a general processing cluster (“GPC”) according to at least one embodiment; Fig. 36 shows a memory partition unit of a parallel processing unit ("PPU") according to at least one embodiment; Fig. 37 shows a streaming multiprocessor according to at least one embodiment; Fig. 38 is an example data flow diagram for an advanced computing pipeline according to at least one embodiment; Fig. 39 is a system diagram for an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment; Fig. 40 includes an example illustration of an advanced computer pipeline 3910A for processing image data in accordance with at least one embodiment; Fig. 41A includes an example data flow diagram of a virtual instrument supporting an ultrasound device, according to at least one embodiment; Fig. 41B includes an example data flow diagram of a virtual instrument supporting a CT scanner, in accordance with at least one embodiment; Fig. 42A shows a data flow diagram for a process for training a machine learning model in accordance with at least one embodiment; Fig. 42B is an example illustration of a client-server architecture for enhancing annotation tools with pre-trained annotation models according to at least one embodiment; and Fig. 43 shows components of a system for accessing a large language model according to at least one embodiment. DETAILED DESCRIPTION

[0004] In at least one embodiment, systems and methods implemented according to this disclosure are used to adjust information resolution used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks and / or to otherwise perform operations described herein.

[0005] Fig. 1 is a block diagram illustrating a training circuit 102 communicating with a neural network 116 in accordance with at least one embodiment. In at least one embodiment, the system 100 includes one or more training circuits 102 (e.g., training circuit 202), one or more processors 110 (e.g., processor 210, 302, 502, and / or 602), one or more image processors 112 (e.g., image processor 212), one or more result processors 114 (e.g., result processor 214), one or more neural networks 116 (e.g., neural network 216, 510, 610, and / or 816), and / or combinations thereof.In at least one embodiment, the system 100 receives and / or uses as input one or more data sets (e.g., one or more low-resolution data sets 104, one or more medium-resolution data sets 106, and / or one or more high-resolution data sets 108).

[0006] Neural network training can use a large number of images to improve inference accuracy, and each pixel of these images requires additional computational resources to process, making it costly to train neural networks on higher-resolution images (e.g., 1080 × 1080 pixels). Neural networks trained on lower-resolution images are simpler and less expensive than those trained on higher-resolution images, but they cannot detect finer details or accurately examine detailed images, such as images with text.In at least one embodiment, system 100 includes a neural network 116 for performing image inference trained on a series of images, starting with low-resolution images (e.g., low-resolution dataset) and progressing with higher-resolution images (e.g., high-resolution dataset 108) until a model reaches a desired level of resolution (e.g., parity and / or sufficient results 512 and / or 612). For example, in at least one embodiment, one or more neural networks 510 are trained on one or more datasets 104-108 (e.g., including information such as images) with a low resolution (e.g., 224 × 224 pixels) for the first 80% of training of neural networks 116.In at least one embodiment, the system 100 trains the neural network 116 with one or more second data sets 104-108 (e.g., including information such as the same images from the first 80% of training) at a higher resolution, e.g., 448 × 448 pixels. In at least one embodiment, as the training of the neural network 116 progresses, additional data sets (e.g., including image information) at increasingly higher resolution are used to train the neural network 116 until a final resolution (e.g., 1120 × 1120 pixels) is reached. In at least one embodiment, a final resolution is reached when parity exists to achieve a desired level of similarity between a ground truth image and a generated image.In at least one embodiment, with each increase in resolution, the amount of data in a dataset (e.g., including image data) of each dataset may decrease, resulting in fewer resources and time required to train a neural network to perform image generation tasks. In at least one embodiment, a low-resolution neural network encoder 116 is evolved to a high-resolution encoder based at least in part on one or more training methods described herein.In at least one embodiment, system 100 trains a neural network based at least in part on adjusting the resolution of one or more data sets, for example, by increasing (e.g., adjusting) the resolution while decreasing the time spent training at that resolution, thereby reducing the overall resource expenditure but achieving a similar model for a target resolution at the end of training.

[0007] In at least one embodiment, system 100 comprises a collection of one or more hardware and / or software computing resources having instructions that, when executed, perform one or more communication processes such as those described herein. In at least one embodiment, system 100 is a software program executing on computer hardware, an application executing on computer hardware, and / or variations thereof. In at least one embodiment, one or more processes of system 100 are executed by a suitable processing system or processing unit (e.g., graphics processing unit (GPU), general-purpose GPU (GPGPU), parallel processing unit (PPU), central processing unit (CPU)), a data processing unit (DPU), as described below, and in any suitable manner, including sequentially, in parallel, and / or variations thereof.In at least one embodiment, the system 100 uses a machine learning training framework such as PYTORCH, TENSORFLOW, BOOST, CAFFE, MICROSOFT COGNITIVE TOOLKIT / CNTK, MXNET, CHAINER, KERAS, DEEPLEARNING4J, and / or another training framework to implement and perform the operations described herein to adjust a resolution of information to be used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or otherwise perform the operations described herein.In at least one embodiment, training a neural network comprises at least using a server (e.g., NVIDIA DGX Server) further comprising at least one graphics processor (e.g., AMD MI200, VEGAL10, VEGO20, and ARCTURUS), an optimizer (e.g., ADAM OPTIMIZER), or a discriminator architecture (e.g., facevid2vid's discriminator architecture for GAN loss training).

[0008] In at least one embodiment, system 100 is comprised of modules (e.g., modules 304-310) such that the system adjusts a resolution of information used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks and / or otherwise performs operations described herein. In at least one embodiment, a module includes any combination of any type of logic (e.g., software, hardware, firmware) and / or circuitry configured to perform a function as described. In at least one embodiment, a module includes one or more circuits that are part of a larger system (e.g., an integrated circuit (IC), a system on a chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), etc.).In at least one embodiment, a controller comprises any combination of any type of logic (e.g., software, hardware, firmware) and / or circuitry configured to perform a function as described. In at least one embodiment, the software comprises software packages, code, programming language, drivers, instructions, instruction sets, or a combination thereof. In at least one embodiment, the hardware comprises hardwired circuitry, programmable circuitry, state machine circuitry, fixed function circuitry, execution unit circuitry, firmware with stored instructions executed by programmable circuitry, or a combination thereof.

[0009] In at least one embodiment, system 100 includes one or more logic units. In at least one embodiment, a logic unit includes firmware logic, hardware logic, or a combination thereof configured to provide any function, as described below. In at least one embodiment, a logic unit includes circuitry that is part of a larger system (e.g., IC, SoC, CPU, GPU, DPU). In at least one embodiment, a logic unit includes logic circuitry for implementing firmware and / or hardware to adjust a resolution of information used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein.

[0010] In at least one embodiment, system 100 includes one or more engines. In at least one embodiment, an engine includes a module and / or a logic unit, as further described herein. In at least one embodiment, a component includes a module and / or a logic unit, as further described herein. In at least one embodiment, an engine includes software logic, firmware logic, hardware logic, or a combination thereof, configured to provide any function, as further described herein. In at least one embodiment, a component includes software logic, firmware logic, hardware logic, or a combination thereof, configured to provide any function, as further described herein.In at least one embodiment, operations performed by the hardware and / or firmware may alternatively be implemented via a software module, which may be embodied as a software package, code, and / or instruction set. In at least one embodiment, a logic unit may also use a portion of the software to implement its function.

[0011] In at least one embodiment, system 100 receives one or more inputs, such as one or more data sets 104-108. In at least one embodiment, system 100 receives an input comprising one or more data sets with information about one or more ground truth images 104, masked ground truth images, labels, videos, frames of a video, images in sequence, audio, text, symbols, previous inputs, trained neural networks, expert neural networks, feature maps, and / or other inputs described herein. In at least one embodiment, one or more neural networks 116 receive one or more data sets 104-108 comprising information such as one or more ground truth images, feature maps, and / or labels (e.g., embedded information).In at least one embodiment, the neural network 116 is a basic neural network, such as an encoder, that uses or does not use one or more labels.

[0012] In at least one embodiment, one or more data sets 104-108 include information, such as data for one or more images, audio data, video data, and / or other inputs described herein. In at least one embodiment, one or more low-resolution data sets 104 have a relatively lower resolution than the medium-resolution data set 106, such as a low resolution of 224×224 (e.g., a matrix representing pixels and / or features in an image) and / or 300×300 pixels. In at least one embodiment, one or more medium-resolution data sets 106 have a relatively lower resolution than the high-resolution data set 108, such as a medium resolution of 400×400, 448×448, 512×512, 700×700, and / or 896×896 pixels.In at least one embodiment, one or more high-resolution data sets 108 have a relatively higher resolution than the medium-resolution data set 106, for example, 1024×1024 and / or 1120×1120 pixels. In at least one embodiment, one or more data sets 104-108 are used for one or more resolutions (for example, a matrix representing one or more pixels of an image). In at least one embodiment, a matrix is otherwise referred to as a tensor.

[0013] In at least one embodiment, system 100, including neural network 116, uses data sets 104-108 to perform data processing (e.g., image processing). In at least one embodiment, image processing, or in other words, processing an image, is the analysis or manipulation of a digitized image, for example, to generate an image from a noisy image, to enhance the quality, and / or to generate an image in a form that can be received as input. In at least one embodiment, an image may include a digital image, a photograph, a training image, frames of a video, frames of a video game, and / or a set of frames for a video or a video game. In at least one embodiment, an image is a collection of pixels, features, data, tensors, and / or other representative forms of an image.In at least one embodiment, a pixel is a point on an image that takes on a hue, opacity, or color. In at least one embodiment, a pixel is represented in a data form (e.g., grayscale, RGB, RGBA, or other variants). In at least one embodiment, one or more pixels are represented as one or more matrices (e.g., tensor). In at least one embodiment, image processing is performed by a processor including circuitry for analyzing or manipulating an image. In at least one embodiment, image processing is performed by a neural network. In at least one embodiment, examples of image processing include scaling, defusing, cropping, visualizing, detecting, sharpening, restoring, pattern recognition, and / or retrieving an image.In at least one embodiment, the neural network 116 is one or more neural networks described in . Fig. 9-43 are described.

[0014] In at least one embodiment, the processor 110 (e.g., one or more in Fig. 9-43) includes the image processor 112 and / or the result processor 114. In at least one embodiment, the image processor 112 receives input from one or more data sets (e.g., data sets 104-108) and modifies data in that data set to produce the data at an adapted resolution for a processor.For example, in at least one embodiment, the image processor 114 receives a high-resolution data set 108 (e.g., 1200×1200) comprising one or more images and generates a lower-resolution data set (e.g., 400×400) by cropping the images to only comprise a generated resolution (e.g., 400×400 pixels) and then converting them into a data format that can be received by a neural network 116 (e.g., so that the same encoder can use pixelated, low-resolution images and high-resolution images received in the same data format). In at least one embodiment, the image processor 114 adjusts the resolution of one or more images, for example, by performing one or more of the steps described in FIG. Fig. 4 described operations.

[0015] In at least one embodiment, the processor 110 provides data, such as one or more images, for training a neural network 116 (e.g., neural network 216, 510, 610, and / or 816; see Fig. 1, Fig. 5, Fig. 6 and / or 8) for inference and / or to determine the capability of the neural network 116 (e.g., sufficient results 512). In at least one embodiment, the processor 110 receives inputs from the neural network 116 (e.g., inference data) and / or training data sets (e.g., resolution data sets 104-108). In at least one embodiment, the processor 110 internally provides these inputs to the image processor 112 and / or the results processor 114. In at least one embodiment, the processor 110 provides outputs to the neural network 116 (e.g., training data sets). In at least one embodiment, the results processor 114 determines whether the results of the neural network 116 are sufficient (e.g., sufficient results 512 and / or 612) to further evolve the neural network 116 to a higher resolution training data set than the one currently being used.In at least one embodiment, a result is sufficient if the data generated by a neural network meets a threshold for similarity to an expert for a ground truth (e.g., parity). In at least one embodiment, processor 110 performs one or more processes (e.g., process 700, see . Fig. 7)

[0016] In at least one embodiment, system 100 adjusts an information resolution to be used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or otherwise performs operations described herein. In at least one embodiment, system 100 is a system embodied in the Fig. 1-8, to adjust information resolution used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein. In at least one embodiment, the system 100 executes one or more Fig. 1-8, for example, to adjust an information resolution to be used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or otherwise performs operations described herein. In at least one embodiment, the system 100 includes one or more Fig. 9-43 to adjust a resolution of information used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein.

[0017] Fig. 2 is a block diagram illustrating the flow of information within a training circuit 202 in communication with a neural network 216, in accordance with at least one embodiment. In at least one embodiment, system 200 includes one or more training circuits 202 (e.g., training circuit 102), one or more processors 210 (e.g., processors 110, 302, 502, and / or 602), one or more image processors 212 (e.g., image processor 112), one or more result processors 214 (e.g., result processor 114), one or more neural networks 216 (e.g., neural network 116, 510, 610, and / or 816), and / or combinations thereof.In at least one embodiment, the system 200 receives and / or uses as input one or more data sets (e.g., one or more low-resolution data sets 204, one or more medium-resolution data sets 206, and / or one or more high-resolution data sets 208).

[0018] In at least one embodiment, system 200 uses one or more processes to gradually train a low-resolution encoder to become high-resolution capable. In at least one embodiment, system 200 builds a high-resolution capable visual encoder based at least in part on starting with a low-resolution encoder and periodically increases the resolution of the training of neural network 216 once the results have converged with the lower-resolution results. For example, in at least one embodiment, results processor 214 determines that the results are sufficient (e.g., sufficient results 512 and / or 612) to increase the resolution when a threshold of similarity to the results previously obtained at a lower resolution is reached.To this end, in at least one embodiment, system 200 begins training with a low-resolution dataset 204 comprising images (e.g., 224×224 pixels), then doubles the resolution to a medium resolution 206 (e.g., 448×448 pixels), then doubles the resolution to a medium and / or high resolution dataset 206 and / or 208 (896×896), and finally increases to a high resolution dataset 208 (e.g., 1120×1120). In at least one embodiment, datasets 204-208 are generated based at least in part on an image dataset received from an image processor 212.

[0019] In at least one embodiment, training circuitry 102 trains neural network 116 to perform data processing tasks, such as processing an image. In at least one embodiment, this training circuitry is provided with, for example, four progressively scaling image resolution datasets 104-108 (e.g., dataset A may consist of 360×360 pixel images. Dataset B may consist of 720×720 pixel images. Dataset C may consist of 1440×1140 pixel images, and dataset D may consist of 2280×2280 pixel images). For example, in at least one embodiment, each progressive dataset (e.g., datasets 104-108) includes fewer data points than a previous dataset (e.g., dataset A includes 10,000 images. Dataset B includes 1,000 images. Dataset C includes 100 images, and dataset D includes 10 images).For example, in at least one embodiment, the training circuit 102 trains one or more neural networks 116 on a given data set until a predetermined level of skill is achieved (e.g., a neural network 116 intended for image reconstruction may require an average of 80% of the image pixels). In at least one embodiment, the system 100, for example, tests the neural network 116 for image reconstruction until the training circuit 102 calculates a skill of 80% for a first data set (e.g., data set 104), after which the training circuit 102 moves on to a next data set (e.g., data sets 106 and / or 108) and performs higher-resolution inference.In at least one embodiment, the system 100 performing a process described herein iterates until a desired resolution and suitability is achieved, after which a process performs one or more operations described herein and / or terminates. In at least one embodiment, the system 100 uses fewer computational resources to train the neural network 116 to the same suitability and / or resolution in the same or less time. For example, in at least one embodiment, the processor 110 includes circuitry utilizing one or more processors based at least in part on the neural network 116 image training circuitry 102 to train the neural network 116 for high-resolution image-based tasks and / or otherwise perform operations described herein.

[0020] In at least one embodiment, system 200 adjusts an information resolution to be used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or otherwise performs operations described herein. In at least one embodiment, system 200 is a system embodied in the Fig. 1-8, to adjust information resolution used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein. In at least one embodiment, the system 200 executes one or more Fig. 1-8, such as adjusting an information resolution to be used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or otherwise performs operations described herein. In at least one embodiment, the system 200 includes one or more of the Fig. 9-43 to adjust a resolution of information to be used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein.

[0021] Fig. 3 is a block diagram showing a processor 302 and modules 304-310 in accordance with at least one embodiment. In at least one embodiment, the system 300 includes the processor 302 and modules 304-312. In at least one embodiment, a processor 302 performs one or more processes as described herein to adjust a resolution of information to be used by one or more neural networks based at least in part on one or more performance metrics (e.g., sufficiency scores 512 and / or 612) of one or more neural networks, and / or otherwise performs operations described herein. In at least one embodiment, the processor 302 performs neural network training and / or image generation, as described above in connection with Fig. 1-8 described.

[0022] In at least one embodiment, processor 302 includes one or more circuits to perform one or more operations as described below. In at least one embodiment, processor 302 is any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variations thereof, including those further described herein. In at least one embodiment, processor 302 includes one or more neural network training modules 304, encoder modules 306, training convergence modules 308, and / or image resolution modules 310.

[0023] In at least one embodiment, the neural network training module 304, the encoder module 306, the training convergence module 308, and / or the resolution adaptation module 310 comprise one or more circuits of a processor 302 and / or one or more other processors. In at least one embodiment, the neural network training module 304, the encoder module 306, the training convergence module 308, and / or the resolution adaptation module 310 are distributed among multiple processors that communicate via a bus, a network, by writing to shared memory, and / or any suitable communication method, such as those described herein.

[0024] In at least one embodiment, as used in an implementation described herein, unless the context otherwise indicates or expressly stated otherwise, a module refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functions described herein. In at least one embodiment, software is embodied as a software package, code, and / or instruction set or instructions, and "hardware" as used in any implementation described herein includes, for example, individually or in any combination, hardwired circuitry, programmable circuitry, state machine circuitry, fixed-function circuitry, execution units, and / or firmware that stores instructions executed by programmable circuitry.In at least one embodiment, the modules are embodied collectively or individually as circuits that are part of a larger system, such as an integrated circuit (IC), a system-on-chip (SoC), etc. In at least one embodiment, a module performs one or more processes in conjunction with a suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variations thereof, including those further described herein.

[0025] In at least one embodiment, the neural network training module 304 (e.g., the neural network training module 402) is a module that, when executed, causes one or more processors 302 to train one or more neural networks in performing one or more processing tasks, for example, by adjusting a resolution of information used (e.g., during training) by a neural network based at least in part on one or more performance metrics. In at least one embodiment, the neural network training module 304 causes one or more processors 302 to perform one or more processes as described herein by at least including or otherwise encoding instructions that cause one or more processors in 302 to perform, or can otherwise be used to perform, the one or more processes.For example, in at least one embodiment, a neural network training module 304 causes one or more processors 302 to perform neural network training to perform image processing and / or generate an image, a video, and / or an image sequence. In at least one embodiment, the neural network training module 304 includes a resolution adaptation module 310 and / or a training convergence module 308. In at least one embodiment, a neural network training module 304 receives one or more instructions and / or an identifier of one or more instructions that include the instructions in . Fig. 1, or is otherwise provided with it. For example, in at least one embodiment, a neural network training module 304 trains a neural network (e.g., a basic neural network or a vision model) that includes one or more encoders to generate labels for images based at least in part on adjusting information resolution using performance metrics and / or to otherwise perform operations described herein.

[0026] In at least one embodiment, the encoder module 306 is a module that causes one or more processors to generate and / or execute one or more software instructions, such as software instructions of an executable software program, including executable code, to utilize a basic neural network (e.g., vision). For example, in at least one embodiment, the encoder module 306 causes one or more processors 302 to utilize one or more neural networks to encode information into one or more data sets (e.g., a data set representing an image) and / or otherwise perform operations described herein.In at least one embodiment, the encoder module 306 causes one or more processors 302 to execute an encoding neural network, such as a pixel masking and encoding neural network used by the neural network training module 304 (e.g., to train or be trained by a neural network). In at least one embodiment, the encoder module 306 causes one or more processors 302 to perform one or more processes, such as those described herein, by at least including or otherwise encoding instructions that cause the performance of the one or more processes or can otherwise be used to perform them. For example, in at least one embodiment, software causes one or more processors 302 to use an encoding neural network, such as a transformer.

[0027] In at least one embodiment, the training convergence module 308 is a module that causes one or more processors 302 to determine whether training has converged (e.g., parity) at a resolution with a previous resolution (e.g., a lower resolution). For example, in at least one embodiment, the indication that a neural network is to be trained at a higher resolution is performed by a training convergence module 308, as described in connection with Fig. 1-8. In at least one embodiment, the training convergence module 308 causes one or more processors 302 to perform one or more processes such as those described herein, at least by including or otherwise encoding instructions that cause or can otherwise be used to perform the one or more processes. For example, in at least one embodiment, the training convergence module 308 causes one or more processors 302 to calculate whether a neural network achieves sufficient results 512 and / or 612 at a training resolution, for example, by using the results of the encoder 306 and / or by determining that a neural network needs to be adapted to a higher resolution adaptation module in conjunction with the resolution adaptation module 310.In at least one embodiment, the training convergence module 308 is a module that causes one or more processors to generate and / or execute one or more software instructions, such as determining whether one or more results of a neural network using a loss function are sufficient using one or more performance characteristics.

[0028] In at least one embodiment, the resolution adjustment module 310 is a module that causes one or more processors 302 to adjust the information resolution, such as when training a neural network in conjunction with the neural network training module 304. For example, in at least one embodiment, a processor uses the resolution adjustment module 310 to adjust the resolution based at least in part on one or more performance characteristics of a neural network (e.g., parity, similarity of the generated image to a ground truth, accuracy, and / or one or more loss calculations), as in Fig. 1-8. In at least one embodiment, the resolution adjustment module 310 causes one or more processors 302 to execute one or more instructions to perform one or more processes as described herein by executing at least instructions that cause or can otherwise be used to perform the one or more processes. In at least one embodiment, the resolution adjustment module 310 causes one or more processors 302 to execute one or more instructions of a software program, such as increasing the use of a neural network to a higher resolution based at least in part on slicing an original image to a desired resolution and changing the data format of an image at a desired resolution.In at least one embodiment, the resolution adjustment module 310 causes one or more processors 302 to execute one or more instructions to perform one or more processes as described in connection with the . Fig. 1-8. In at least one embodiment, the resolution adjustment module 310 causes one or more processors 302 to adjust the information resolution (e.g., data sets including information such as images) based at least in part on the performance characteristics of a neural network, for example, by applying one or more loss functions to the results of an encoder in conjunction with the encoder module 306.

[0029] In at least one embodiment, system 300 adjusts an information resolution to be used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or otherwise performs operations described herein. In at least one embodiment, system 300 is a system implemented in the Fig. 1-8, to adjust information resolution used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein. In at least one embodiment, the system 300 executes one or more Fig. 1-8, such as adjusting an information resolution to be used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or otherwise performs operations described herein. In at least one embodiment, system 300 includes one or more Fig. 9-43 to adjust a resolution of information used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein.

[0030] Fig. Figure 4 is a block diagram illustrating the neural network training module 402 in accordance with at least one embodiment. In at least one embodiment, the neural network training module 402 (e.g., the neural network training module 304) includes the training convergence module 308. In at least one embodiment, the system 400 executes the neural network training module 402.

[0031] In at least one embodiment, the neural network training module 402 is a module that causes one or more processors 302 to perform the training of a neural network by adjusting the information resolution (e.g., image information) based at least in part on performance characteristics, such as when the neural network training module 402 determines whether training has converged at a resolution with a previous resolution (e.g., a lower resolution) (e.g., parity). For example, in at least one embodiment, the training of one or more neural networks at one or more information resolutions is performed by a neural network training module 402, as described in connection with Fig. 1-8. In at least one embodiment, the neural network training module 402 causes one or more processors 302 to perform one or more processes such as those described herein by at least including or otherwise encoding instructions that cause or can otherwise be used to perform the one or more processes. For example, in at least one embodiment, the neural network training module 402 causes one or more processors 302 to calculate whether a neural network achieves sufficient results 512 and / or 612 at a training resolution, for example, by using results from the encoder module 306 and / or by determining that a neural network should be adapted to a higher resolution module in conjunction with the resolution adaptation module 310.In at least one embodiment, the neural network training module 402 is a module that causes one or more processors to generate and / or execute one or more software instructions to train a neural network by adjusting the resolution of information based at least in part on one or more performance characteristics, such as one or more loss functions (e.g., visual reconstruction loss, contrastive label loss, feature reconstruction loss, object identification loss correction, text identification loss correction, and / or generative label loss).

[0032] In at least one embodiment, the neural network training module 402 includes training one or more neural network encoders to receive one or more images with a lower resolution pixelization 404 and a higher resolution pixelization 406 when the training of the lower resolution pixelization at a lower resolution has converged with a desired result (e.g., using one or more performance characteristics). In at least one embodiment, the neural network training module 402 generates information at one or more resolutions by using a dataset with a smaller amount of training data sets 410 (e.g., a relatively smaller amount of training data sets 410 than a low-resolution dataset with a larger amount of training data 408) with a high resolution, such as 1200×1200 pixelization.For example, in at least one embodiment, in a first training set, for a low resolution resolution pixelization 404, an image is cropped to 224x224, for a medium resolution, the same original image (e.g., 1000x1000) is cropped to 448x448, and this is repeated for higher resolution resolution pixelizations 406 (e.g., 896x896 and 1120x1120) as training converges at the lower resolution, which is determined based on one or more performance metrics.

[0033] In at least one embodiment, system 400 uses a low-resolution encoder that is further developed into a high-resolution capable encoder through one or more described training processes. In at least one embodiment, the data format of a received image remains consistent even though the image is received at different resolutions. In at least one embodiment, neural network training module 402 takes a cropped 224x224 portion of an image and enlarges the data format of an image to match a preferred data format of an encoder (e.g., a matrix size to be used for highest resolution). For example, in at least one embodiment, for a high-resolution image of a road and sky, the image would be cropped to 224x224 and then enlarged, thereby decreasing the resolution (e.g., becoming more pixelated).In at least one embodiment, in this more pixelated version of a portion of a road and sky, a data format received from an encoder would still have a high resolution (e.g., 1120x1120), but when creating a feature map, one or more assigned values for a group of pixels could be repeated according to the 224x224 resolution.

[0034] In at least one embodiment, one or more neural networks are a trusted neural network, where the data format received is a sum of filters learned, for example, by automatic tuning through training. In at least one embodiment, one or more neural networks are a transformer neural network that adapts a data format for resolution pixelization (e.g., 404 and / or 406) by interpolating position embeddings learned from one resolution to another, such as performing interpolation operations when adapting (e.g., switching) to a higher resolution.For example, in at least one embodiment, when changing resolution from a resolution pixelization with a 10x10 grid to a 20x20 grid (e.g., higher resolution pixelization 406), the image information is stretched and one or more embeddings are relearned (e.g., extraction of previously learned embeddings and position within one or more new embeddings). In at least one embodiment, a transformer neural network learns scale invariance. In at least one embodiment, a neural network adapts the representations to one or more higher resolutions. In at least one embodiment, one or more neural networks use bilinear interpolation of pixels, such as performing an average and / or approximation (e.g., linear) between two pixels.

[0035] In at least one embodiment, a data format of one or more convolutions may obtain one or more data formats that vary with resolution, with an encoder adapted to a data format. In at least one embodiment, an interpolation is added to an original tensor and treated as a bilinear interpolation to higher resolutions. In at least one embodiment, another variation is to add zero values (e.g., 0) to a matrix to account for a change in resolution and achieve a sufficient data format, although this would rely on differential gradients to change the bias away from zero. In at least one embodiment, a neural network may also replicate nearest neighbor values when converting (e.g., adapting) between one or more resolutions.In at least one embodiment, convolutional neural networks adapt processing to an input dimension and / or one or more parameters of one or more matrices. In at least one embodiment, one or more neural networks include a vision transformer to interpolate one or more position embeddings.

[0036] In at least one embodiment, the neural network training module 412 adjusts the resolution, for example, through progressive scaling, upscaling, downscaling, variable scaling (for example, combinations of upscaling and / or downscaling), cyclic scaling (for example, moving the resolution from low to medium to high resolutions, then from high to medium to low resolutions), repeated progressive scaling, or combinations thereof. In at least one embodiment, the neural network training module 412 performs a training round, for example, using 100 lower-resolution images, 20 higher-resolution images, and repeats this for one or more iterations.In at least one embodiment, the amount of training data varies at least in part based on information resolution; for example, a lower resolution pixelization 404 uses a greater amount of training data 408 than a lower resolution pixelization 405 with a lesser amount of training data 410 (e.g., less than a low-resolution dataset). Otherwise, in at least one embodiment, using is generating, training, performing, and / or executing.

[0037] In at least one embodiment, system 400 adjusts an information resolution to be used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or otherwise performs operations described herein. In at least one embodiment, system 400 is a system embodied in the Fig. 1-8 to adjust information resolution used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein. In at least one embodiment, system 400 executes one or more Fig. 1-8, such as adjusting an information resolution to be used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or otherwise performs operations described herein. In at least one embodiment, system 400 includes one or more Fig. 9-43 to adjust a resolution of information used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein.

[0038] Fig. 5 is a block diagram illustrating one or more resolution-adjusting neural networks 510, in accordance with at least one embodiment. In at least one embodiment, system 500 includes one or more processors 502 (e.g., one or more processors 110, 210, 302, 502A-C, and / or 602) and one or more neural networks 510 (e.g., neural network 116, 216, 610, and / or 816). In at least one embodiment, the neural network 510 comprises one or more neural networks shown herein, such as one or more neural networks comprising a transformer, an image and / or text encoder, contrastive loss operations, pixel masking, an object depth identifier, a text identifier, an object identifier, a task expert neural network, an image and / or text decoder, or combinations thereof.

[0039] In at least one embodiment, neural network 510 includes a decoder. In at least one embodiment, a decoder, upon receiving inputs, decodes the video frames or images of inputs 104 (e.g., visual decoder). In at least one embodiment, decoding an image consists of converting an encoded image back to an uncompressed bitmap, where it can then be rendered. In at least one embodiment, the steps for decoding an image are a reverse process for encoding an image. In at least one embodiment, a processor (e.g., an image processing engine, an image processing unit, or an image signal processor) includes circuitry for decoding an image. In at least one embodiment, decoding an image is performed by at least one neural network.

[0040] In at least one embodiment, system 500 includes one or more data sets (e.g., data set 504-508) generated at one or more resolutions, e.g., from an original data set. In at least one embodiment, one or more data sets 504-508 (e.g., data sets 604-608 and / or 104-108) include information such as data for one or more images, audio data, video data, and / or other inputs described herein. In at least one embodiment, one or more low-resolution data sets 504 have a relatively lower resolution than medium-resolution data set 506, such as a low resolution of 224x224 (e.g., a matrix representing pixels and / or features in an image) and / or 300x300 pixels.In at least one embodiment, one or more medium-resolution data sets 506 have a relatively lower resolution than the high-resolution data set 508, for example, a medium resolution of 400x400, 448x448, 512x512, 700x700, and / or 896x896 pixels. In at least one embodiment, one or more high-resolution data sets 508 have a relatively higher resolution than the medium-resolution data set 506, for example, 1024x1024 and / or 1120x1120 pixels. In at least one embodiment, one or more data sets 104-108 are used for one or more resolutions (for example, a matrix representing one or more pixels of an image). In at least one embodiment, a matrix is also referred to as a tensor.

[0041] In at least one embodiment, the neural network 510 is located in a cloud processing environment (e.g., a cloud network) where one or more processors access the neural network 510. In at least one embodiment, 502A-C are all the same processor executing the neural network 510. In at least one embodiment, one or more processors 502A-C invoke a neural network stored on another processor, for example, by using one or more APIs.For example, in at least one embodiment, one or more processors 502 execute one or more data sets 504-508 to train the neural network 510 and measure performance using one or more performance metrics (e.g., accuracy, convergence to ground truth, and / or loss functions) of the results 514 of the neural network 510 on the low-resolution data set 504 until the achieved results 514 are sufficient results 512 (e.g., reaching a threshold for one or more performance metrics).For example, in at least one embodiment, processor 502A executes a low-resolution dataset to train neural network 510 and measures performance using one or more performance metrics (e.g., accuracy, convergence to ground truth, and / or loss functions) of the results 514A of neural network 510 with low-resolution dataset 504 until the achieved results 514A are used to calculate sufficient performance results 512A (e.g., reaching a threshold for one or more performance metrics). In at least one embodiment, system 100, including neural network 116, includes datasets 104-108 to perform data processing (e.g., image processing).

[0042] In at least one embodiment, system 500 adjusts an information resolution to be used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or otherwise performs operations described herein. In at least one embodiment, system 500 is a system implemented in the Fig. 1-8 to adjust information resolution used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein. In at least one embodiment, system 500 executes one or more Fig. 1-8, for example, to adjust an information resolution to be used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or otherwise performs operations described herein. In at least one embodiment, the system 500 includes one or more processes shown in the Fig. 9-43 to adjust a resolution of information to be used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein.

[0043] Fig. 6 is a block diagram illustrating one or more neural networks 610 adapting to a higher resolution using one or more results 614 of the neural network 610, in accordance with at least one embodiment. In at least one embodiment, the system 600 includes one or more processors 602 (e.g., one or more processors 110, 210, 302, 502, and / or 602A-C) and one or more neural networks 610.In at least one embodiment, neural network 610 includes one or more neural networks shown herein (e.g., neural network 116, 216, 510, and / or 816), such as one or more neural networks including a transformer, an image and / or text encoder, contrastive loss operations, pixel masking, an object depth identifier, a text identifier, an object identifier, a task expert neural network, an image and / or text decoder, or combinations thereof.

[0044] In at least one embodiment, system 600 includes one or more data sets (e.g., data sets 604-508) generated at one or more resolutions, e.g., from an original data set. In at least one embodiment, one or more data sets 604-508 include information, such as data for one or more images, audio data, video data, and / or other inputs described herein. In at least one embodiment, one or more low-resolution data sets 604 have a relatively lower resolution than medium-resolution data set 606, such as a low resolution of 224×224 (e.g., a matrix representing pixels and / or features in an image) and / or 300×300 pixels.In at least one embodiment, one or more medium-resolution data sets 606 have a relatively lower resolution than the high-resolution data set 608, for example, a medium resolution of 400×400, 448×448, 612×512, 700×700, and / or 896×896 pixels. In at least one embodiment, one or more high-resolution data sets 608 have a relatively higher resolution than the medium-resolution data set 606, for example, 1024×1024 and / or 1120×1120 pixels. In at least one embodiment, one or more data sets 104-108 are used for one or more resolutions (for example, a matrix representing one or more pixels of an image). In at least one embodiment, a matrix is otherwise described as a tensor.

[0045] In at least one embodiment, the neural network 610 is located in a cloud processing environment (e.g., cloud network), for example, where one or more processors access the neural network 610. In at least one embodiment, 602A-C are all the same processor executing the neural network 610. In at least one embodiment, one or more processors 602A-C invoke a neural network stored on another processor, for example, by using one or more APIs.For example, in at least one embodiment, one or more processors 602 execute one or more data sets 604-508 to train the neural network 610 and measure performance using one or more performance metrics (e.g., accuracy, convergence to ground truth, and / or loss functions) of the results 614 of the neural network 610 on the low-resolution data set 604 until the achieved results 614 are sufficient results 612 (e.g., reaching a threshold for one or more performance metrics).For example, in at least one embodiment, processor 602A executes a low-resolution dataset to train neural network 610 and measures performance using one or more performance metrics (e.g., accuracy, convergence to ground truth, and / or loss functions) of the results 614A of neural network 610 on low-resolution dataset 604 until the achieved results 614A are used to calculate sufficient performance results 612A (e.g., reaching a threshold for one or more performance metrics). In at least one embodiment, system 100, including neural network 116, includes datasets 104-108 to perform data processing (e.g., image processing).

[0046] In at least one embodiment, one or more neural networks 610 receive a masked input 616 (e.g., an image with randomization of one or more pixel values), a ground truth input 618, and / or one or more inputs described herein. In at least one embodiment, the neural network 610 includes one or more differentiable expert systems 624 (e.g., one or more vision fundamental models) to perform training of the neural network 610 based at least in part on comparing generated information to information generated or contained in a ground truth using one or more loss functions. In at least one embodiment, the differentiable expert system 624 includes one or more neural networks described herein.In at least one embodiment, the differentiable expert system receives one or more inputs from one or more visual decoders 622. In at least one embodiment, the system 600 uses a neural network 610 that uses one or more loss computations 630 (e.g., visual reconstruction loss, contrastive label loss, feature matching loss, object identification loss correction, text identification loss correction, and / or generative label loss) to generate one or more outputs 614, such as a neural network 610 with or without a differentiable expert system 624.

[0047] In at least one embodiment, the neural network 610 includes one or more visual decoders 622. In at least one embodiment, upon receiving inputs (e.g., images and / or video frames) from the visual encoder 620, the visual decoder 622 will decode 104 the inputs (e.g., visual decoder). In at least one embodiment, decoding an image consists of converting an encoded image back into an uncompressed bitmap, which can then be rendered. In at least one embodiment, the steps for decoding an image are a reverse process for encoding an image. In at least one embodiment, a processor (e.g., an image processing engine, an image processing unit, or an image signal processor) includes circuitry for decoding an image. In at least one embodiment, decoding an image is performed by at least one neural network 610.

[0048] In at least one embodiment, the differentiable expert system 624 receives an output from the visual decoder 622 and uses the masked input generated output 626 and the ground truth generated output 628 to perform one or more loss calculations 630 described herein, such as the feature matching loss 632. In at least one embodiment, one or more values of the loss calculation 630 are used as results 614 for one or more processors 602. In at least one embodiment, the processor 602 uses the results 614 to then perform one or more performance calculations (e.g., comparison to a desired result) to generate one or more performance metrics to determine whether the neural network 610 has achieved sufficient results to move on to a higher resolution dataset.For example, in at least one embodiment, the results 614B of the neural network 610 executing the medium resolution data set 606 are determined by the processor 602B to be sufficient results 612B to proceed to training with the high resolution data set 608 by the processor 602C.

[0049] In at least one embodiment, system 600 adjusts an information resolution to be used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or otherwise performs operations described herein. In at least one embodiment, system 600 is a system embodied in the Fig. 1-8 to adjust information resolution used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein. In at least one embodiment, system 600 performs one or more of the Fig. 1-8, for example, to adjust an information resolution to be used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or otherwise performs operations described herein. In at least one embodiment, the system 600 includes one or more of the Fig. 9-43 to adjust a resolution of information to be used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein.

[0050] Fig. 7 is a flowchart of process 700 illustrating adjusting resolution according to at least one embodiment. In at least one embodiment, process 700 starts (e.g., begins) when invoked, for example, by one or more processors (e.g., using an API 810). In at least one embodiment, process 700 includes one or more steps of training with a low-resolution dataset 705, training with a high-resolution dataset 515, performing one or more operations described herein, or combinations thereof.

[0051] In at least one embodiment, part or all of process 700 (or other processes described herein or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with computer-executable instructions implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) that collectively execute on one or more processors, by hardware, software, or combinations thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program that includes a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium.In at least one embodiment, at least some computer-readable instructions that may be used to perform process 700 are stored using more than just transient signals (e.g., propagating transient electrical or electromagnetic transmission). In at least one embodiment, a non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) in transient signal transceivers. In at least one embodiment, process 700 is performed at least in part on a computer system as described elsewhere in this disclosure. In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) performs process 700.

[0052] In at least one embodiment, a low-resolution dataset is a dataset with a lower pixel resolution than subsequent datasets, such as low-resolution datasets 104, 204, 504, and / or 604. In at least one embodiment, a high-resolution dataset is a dataset with a higher pixel resolution than previous datasets used in training, such as high-resolution datasets 108, 208, 508, and / or 608. In at least one embodiment, the processor performs process 700, which includes training on lower-resolution dataset 705 and generating results (e.g., results 514 and / or 614) of one or more neural networks (e.g., neural networks 116, 216, 510, 610, and / or 816) that are received by decision block 710.In at least one embodiment, a decision in decision block 710 is "YES" if the desired results (e.g., performance metric, fitness, convergence, and / or parity) are achieved; otherwise, a decision is "NO." In at least one embodiment, if a decision in decision block 710 is "NO," a processor proceeds to training with the low-resolution dataset 705 to generate one or more results. In at least one embodiment, if a decision in decision block 710 is "YES," the processor proceeds to training a neural network with the high-resolution dataset 715.In at least one embodiment, the processor performs process 700, which includes training with the high-resolution dataset 715 and generating results (e.g., results 514 and / or 614) of one or more neural networks (e.g., neural networks 116, 216, 510, 610, and / or 816) that are received at decision block 720. In at least one embodiment, a decision at decision block 720 is "YES" if the desired results (e.g., performance metric, fitness, convergence, and / or parity) are achieved; otherwise, a decision is "NO." In at least one embodiment, if a decision at decision block 720 is "NO," a processor continues training with the high-resolution dataset 715 to generate one or more results.In at least one embodiment, if a decision in decision block 720 is "YES," the processor continues to perform one or more operations described herein (e.g., training at a different resolution) and / or exits 725.

[0053] In at least one embodiment, one or more processors use process 700 to, for example, adjust a resolution of information to be used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein. In at least one embodiment, for example, a machine-readable medium (e.g., non-transitory) having a set of instructions that, when executed by one or more processors, causes one or more processors to perform process 700 to, for example, adjust a resolution of information to be used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein.In at least one embodiment, the process 700 is shown in FIGS. Fig. 1-8, includes, and / or otherwise performs processes to adjust information resolution used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or otherwise performs operations described herein. In at least one embodiment, one or more of the Fig. 1-8 perform process 700, for example, to adjust a resolution of information to be used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or otherwise perform operations described herein. In at least one embodiment, one or more systems shown in Fig. 9-43, the hardware shown performs the process 700 to, for example, adjust a resolution of information to be used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein.

[0054] Fig. 8 is a block diagram illustrating a driver and / or runtime including one or more libraries to provide one or more APIs in accordance with at least one embodiment;

[0055] Fig. 8 is a block diagram 800 illustrating a driver and / or runtime including one or more libraries to provide one or more application programming interfaces (APIs) according to at least one embodiment. In at least one embodiment, a software program 802 is a software module. In at least one embodiment, the software program 802 includes one or more software modules. In at least one embodiment, a software module is as in Fig. 8 is not exhaustively described. In at least one embodiment, one or more APIs 810 are sets of software instructions that, when executed, instruct one or more processors (e.g., processor 502, Fig. 5) cause one or more computational operations to be performed. In at least one embodiment, one or more APIs 810 are distributed or otherwise provided as part of one or more libraries 806, drivers / runtimes 804, and / or other grouping of software and / or executable code, further described herein. In at least one embodiment, one or more APIs 810 perform one or more computational operations in response to being invoked by software programs 802. In at least one embodiment, a software program 802 is a collection of software code, commands, instructions, or other text strings to instruct a computing device to perform one or more computational operations and / or to invoke one or more other sets of instructions, such as APIs 810 or API functions 812, for execution.In at least one embodiment, the functionality provided by one or more APIs 810 includes software functions 812, such as those that can be used to accelerate one or more portions of software programs 802 using one or more parallel processing units (PPUs), such as graphics processing units (GPUs).

[0056] In at least one embodiment, APIs 810 are hardware interfaces to one or more circuits to perform one or more computational operations. In at least one embodiment, one or more software APIs 810 described herein are implemented as one or more circuits to perform one or more of the operations described below in connection with Fig. 1-8. In at least one embodiment, one or more software programs 802 include instructions that, when executed, cause one or more hardware devices and / or circuits to perform one or more techniques described further in connection with Fig. 1-8 are described.

[0057] In at least one embodiment, software programs 802, such as user-implemented software programs, use one or more application programming interfaces (APIs) 810 to perform various computational operations, such as memory allocation, matrix multiplication, arithmetic operations, or any computational operation performed by parallel processing units (PPUs), such as graphics processing units (GPUs), as further described herein. In at least one embodiment, one or more APIs 810 provide a set of callable functions 812, referred to herein as APIs, API functions, and / or functions, that individually perform one or more computational operations, such as computational operations related to parallel computing.For example, in one embodiment, one or more APls 810 provide functions 812 to cause a neural network to generate one or more images using one or more images with or without annotations and / or to otherwise perform operations described herein.

[0058] In at least one embodiment, one or more software programs 802 interact or communicate with one or more APIs 810 to perform one or more computational operations using one or more PPUs, such as GPUs. In at least one embodiment, one or more computational operations using one or more PPUs include at least one or more groups of computational operations that are accelerated by being executed at least in part by the one or more PPUs. In at least one embodiment, one or more software programs 802 interact with one or more APIs 810 to perform audio-to-text processing.

[0059] In at least one embodiment, an interface consists of software instructions that, when executed, provide access to one or more functions 812 provided by one or more APIs 810. In at least one embodiment, a software program 802 uses a local interface when a software developer compiles one or more software programs 802 in conjunction with one or more libraries 806 that include or otherwise provide access to one or more APIs 810. In at least one embodiment, one or more software programs 802 are statically compiled in conjunction with precompiled libraries 806 or uncompiled source code that includes instructions for executing one or more APIs 810.In at least one embodiment, one or more software programs 802 are dynamically compiled, and the one or more software programs use a linker to link to one or more precompiled libraries 806 that include one or more APIs 810.

[0060] In at least one embodiment, a software program 802 uses a remote interface when a software developer executes a software program that uses or otherwise communicates with a library 806 comprising one or more APIs 810 over a network or other remote communication medium. In at least one embodiment, one or more libraries 806 comprising one or more APIs 810 are executed by a remote computing service, such as a computing resource service provider. In another embodiment, one or more libraries 806 comprising one or more APIs 810 are executed by another computer host that provides the one or more APIs 810 to one or more software programs 802.

[0061] In at least one embodiment, a processor (e.g., In at least one embodiment, one or more software programs 802 use one or more APIs 810 to allocate and otherwise manage memory 814 to be used by the software programs 802. In at least one embodiment, one or more software programs 802 use one or more APIs 810 to allocate and otherwise manage memory 814 to be used by one or more portions of the software programs 802 to be accelerated using one or more PPUs, such as GPUs or another accelerator or processor described further herein. These software programs 802 request a neural network to perform signal processing using functions 812 that, in one embodiment, are provided by one or more APIs 810.

[0062] In at least one embodiment, API 810 is an API for facilitating parallel computing. In at least one embodiment, API 810 is any other API further described herein. In at least one embodiment, API 810 is provided by a driver and / or runtime 804. In at least one embodiment, API 810 is provided by a CUDA user-mode driver. In at least one embodiment, API 810 is provided by a CUDA runtime. In at least one embodiment, a driver (e.g., driver / runtime 804) provides data values and software instructions that, when executed, perform or otherwise facilitate the operation of one or more functions 812 of API 810 during the loading and execution of one or more portions of a software program 802.In at least one embodiment, a runtime 804 consists of data values and software instructions that, when executed, perform or otherwise facilitate the operation of one or more functions 812 of an API 810 during execution of a software program 802. In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 implemented or otherwise provided by a driver and / or runtime 804 to perform combined arithmetic operations by the one or more software programs 802 during execution by one or more PPUs, such as GPUs.

[0063] In at least one embodiment, one or more software programs 802 use one or more APIs 810 provided by a driver and / or runtime 804 to perform combined arithmetic operations of one or more PPUs, such as GPUs. In at least one embodiment, one or more APIs 810 provide combined arithmetic operations via a driver and / or runtime 804, as described above. In at least one embodiment, one or more software programs 802 use one or more APIs 810 provided by a driver and / or runtime 804 to allocate or otherwise reserve one or more memory blocks 814 of one or more PPUs, such as GPUs.In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 provided by a driver and / or runtime 804 to allocate or otherwise reserve memory blocks 814. In at least one embodiment, one or more APIs 810 invoke a neural network to generate a neural network 816, such as a neural network used in conjunction with the . Fig. 1-8 is described.

[0064] To improve the usability of software programs 802 and / or the optimization of one or more portions of the software programs 802 to be accelerated by one or more PPUs, such as GPUs, in one embodiment, one or more APIs 810 provide one or more API functions 812 to cause a neural network 816 as described herein, such as in connection with Fig. 1-8. In at least one embodiment, an example block diagram 800 depicts a processor (e.g., processor 106) including one or more circuits for causing one or more neural networks, such as a task-based neural network and / or a basic neural network, to generate one or more images.

[0065] In the preceding and following descriptions, various techniques are described. For explanatory purposes, specific configurations and details are set forth to provide a thorough understanding of possible ways to implement techniques. However, it is also understood that the techniques described below may be implemented in various configurations without specific details. Furthermore, well-known features may be omitted or simplified so as not to obscure the described techniques. LOGIC

[0066] Fig. 9A shows logic 915, which, as described elsewhere herein, may be used in one or more devices to perform operations such as those discussed herein, according to at least one embodiment. In at least one embodiment, logic 915 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, logic 915 is inference and / or training logic. Details of logic 915 are described below in connection with Fig. 9A and / or 9B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic to provide the functions or operations described herein, where the logic may be embodied, in whole or in part, as circuitry that forms part of a larger system, such as an integrated circuit (IC), a system-on-chip (SoC), or one or more processors (e.g., CPU, GPU).

[0067] In at least one embodiment, logic 915 may include, without limitation, code and / or data storage 901 to store the feedforward and / or output weights and / or input / output data and / or other parameters to configure neurons or layers of a neural network that is trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, logic 915 may include or be coupled to code and / or data storage 901 to store graph code or other software that controls the timing and / or order in which information about weights and / or other parameters is loaded to configure logic, including integer and / or floating-point units (collectively referred to as arithmetic logic units (ALUs)).In at least one embodiment, code, such as graph code, loads weights or other parameter information into processor ALUs based on a neural network architecture to which such code conforms. In at least one embodiment, code and / or data storage 901 stores weight parameters and / or input / output data of each layer of a neural network being trained or used in connection with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, each portion of code and / or data storage 901 may include other on-chip or off-chip data stores, including a processor's L1, L2, or L3 cache or system memory.

[0068] In at least one embodiment, any portion of the code and / or data storage 901 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 901 may be cache memory, dynamic random addressable memory ("DRAM"), static random addressable memory ("SRAM"), non-volatile memory (e.g., flash memory), or other memory.In at least one embodiment, the choice of whether the code and / or code and / or data memory 901 is, for example, internal or external to a processor or comprises DRAM, SRAM, flash, or another type of memory may depend on the available on-chip versus off-chip memory, the latency requirements of the training and / or inference functions performed, the batch size of the data used in the inference and / or training of a neural network, or a combination of these factors.

[0069] In at least one embodiment, logic 915 may include, without limitation, a code and / or data storage 905 to store backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network being trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 905 stores weighting parameters and / or input / output data of each layer of a neural network being trained or used in connection with one or more embodiments during backpropagation of input / output data and / or weighting parameters during training and / or inferencing using aspects of one or more embodiments.In at least one embodiment, logic 915 may include or be coupled to code and / or data memory 905 to store graph code or other software to control the timing and / or order in which information about weights and / or other parameters is loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)).

[0070] In at least one embodiment, code, such as graph code, causes information about weights or other parameters to be loaded into processor ALUs based on a neural network architecture to which such code corresponds. In at least one embodiment, any portion of code and / or data storage 905 may include other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 905 may be internal or external to one or more processors or other hardware logic devices or circuitry. In at least one embodiment, code and / or data storage 905 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory.In at least one embodiment, the choice of whether the code and / or data memory 905 is, for example, internal or external to a processor, or comprises DRAM, SRAM, flash memory, or another type of memory, may depend on the available on-chip versus off-chip memory, the latency requirements of the training and / or inference functions performed, the batch size of the data used in inference and / or training of a neural network, or a combination of these factors.

[0071] In at least one embodiment, code and / or data memory 901 and code and / or data memory 905 may be separate memory structures. In at least one embodiment, code and / or data memory 901 and code and / or data memory 905 may be a combined memory structure. In at least one embodiment, code and / or data memory 901 and code and / or data memory 905 may be partially combined and partially separate. In at least one embodiment, each portion of code and / or data memory 901 and code and / or data memory 905 may include other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0072] In at least one embodiment, logic 915 may include, without limitation, one or more arithmetic logic unit(s) ("ALU(s)") 910, including integer and / or floating point units, to perform logical and / or mathematical operations based at least in part on or specified by training and / or inference code (e.g., graph code), the result of which may produce activations stored in activation memory 920 (e.g., output values of layers or neurons within a neural network) that are functions of input / output and / or weighting parameter data stored in code and / or data memory 901 and / or code and / or data memory 905.In at least one embodiment, activations stored in an activation memory 920 are generated according to linear algebraic and / or matrix-based mathematics executed by ALU(s) 910 in response to execution instructions or other code, using weight values stored in code and / or data memory 905 and / or data memory 901 as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data memory 905 or code and / or data memory 901 or other on-chip or off-chip memory.

[0073] In at least one embodiment, ALU(s) 910 are included in one or more processors or other logical hardware devices or circuits, while in another embodiment, ALU(s) 910 may be external to a processor or other logical hardware device or circuit that uses them (e.g., a co-processor). In at least one embodiment, ALU(s) 910 may be included in the execution units of a processor or otherwise in a bank of ALUs that can be accessed by the execution units of a processor, either within the same processor or distributed among different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.).In at least one embodiment, code and / or data storage 901, code and / or data storage 905, and enablement storage 920 may share a processor or other logical hardware device or circuitry, while in another embodiment, they may be located in different processors or other logical hardware devices or circuitry, or in a combination of the same and different processors or other logical hardware devices or circuitry. In at least one embodiment, each portion of enablement storage 920 may include other on-chip or off-chip data stores, including a processor's L1, L2, or L3 cache or system memory.Furthermore, the inference and / or training code may be stored along with other code accessible by a processor or other hardware logic or circuitry, and retrieved and / or processed using the fetch, decode, schedule, execute, retire, and / or other logic circuitry of a processor.

[0074] In at least one embodiment, the activation memory 920 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the activation memory 920 may be located entirely or partially within or external to one or more processors or other logic circuitry. In at least one embodiment, the choice of whether the activation memory 920 is, for example, internal or external to a processor, or comprises DRAM, SRAM, flash memory, or another type of memory, may depend on the available on-chip versus off-chip memory, the latency requirements of the training and / or inference functions performed, the batch size of the data used in inference and / or training of a neural network, or a combination of these factors.

[0075] In at least one embodiment, the Fig. 9A may be used in conjunction with an application-specific integrated circuit (“ASIC”), such as a TensorFlow® Processing Unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp. In at least one embodiment, the logic shown in Fig. 9A may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as field programmable gate arrays (“FPGAs”).

[0076] Fig. 9B shows logic 915 according to at least one embodiment. In at least one embodiment, logic 915 is inference and / or training logic. In at least one embodiment, logic 915 may include, without limitation, hardware logic that dedicates or otherwise exclusively uses computational resources associated with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, the logic shown in Fig. 9B may be used in conjunction with an application-specific integrated circuit (ASIC), such as Google's TensorFlow® Processing Unit, a Graphcore™ Inference Processing Unit (IPU), or a Nervana® processor (e.g., "Lake Crest") from Intel Corp. In at least one embodiment, the logic 915 shown in Fig. 9B may be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU), or other hardware, such as field-programmable gate arrays (FPGAs). In at least one embodiment, logic 915 includes, without limitation, code and / or data memory 901 and code and / or data memory 905, which may be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, pulse values, and / or other parameter or hyperparameter information. In at least one embodiment, Fig. 9B, each code and / or data memory 901 and each code and / or data memory 905 is connected to a dedicated computing resource, such as computer hardware 902 and computer hardware 906, respectively. In at least one embodiment, each computer hardware 902 and computer hardware 906 includes one or more ALUs that perform mathematical functions, such as linear algebraic functions, only on information stored in the code and / or data memory 901 and the code and / or data memory 905, respectively, and the result of which is stored in the activation memory 920.

[0077] In at least one embodiment, code and / or data storage 901 and 905 and the corresponding computer hardware 902 and 906 each correspond to different layers of a neural network, such that the activation resulting from one memory / computing pair 901 / 902 comprising code and / or data storage 901 and computer hardware 902 is provided as input to a next memory / computing pair 905 / 906 comprising code and / or data storage 905 and computer hardware 906 to reflect a conceptual organization of a neural network. In at least one embodiment, each of the memory / computing pairs 901 / 902 and 905 / 906 may correspond to more than one layer of the neural network. In at least one embodiment, additional memory / compute pairs (not shown) may be included in logic 915 subsequent to or in parallel with memory / compute pairs 901 / 902 and 905 / 906. TRAINING AND DEPLOYMENT OF A NEURAL NETWORK

[0078] Fig. 10 illustrates the training and deployment of a deep neural network according to at least one embodiment. In at least one embodiment, the untrained neural network 1006 is trained using a training dataset 1002. In at least one embodiment, the training framework 1004 is a PyTorch framework, while in other embodiments, the training framework 1004 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or another training framework. In at least one embodiment, the training framework 1004 trains an untrained neural network 1006 and facilitates its training using the processing resources described herein to produce a trained neural network 1008. In at least one embodiment, the weights may be selected randomly or by pre-training using a deep belief network.In at least one embodiment, the training may be performed in either a supervised, semi-supervised, or unsupervised manner.

[0079] In at least one embodiment, the untrained neural network 1006 is trained using supervised learning, where the training data set 1002 has an input paired with a desired output for an input, or where the training data set 1002 has an input with a known output and an output of the neural network 1006 is manually evaluated. In at least one embodiment, the untrained neural network 1006 is trained in a supervised manner and processes inputs from the training data set 1002 and compares the resulting outputs to a set of expected or desired outputs. In at least one embodiment, the errors are then backtracked through the untrained neural network 1006. In at least one embodiment, the training framework 1004 adjusts the weights that control the untrained neural network 1006.In at least one embodiment, the training framework 1004 includes tools for monitoring the convergence of the untrained neural network 1006 into a model, such as the trained neural network 1008, that can generate correct answers, such as in the output 1014, based on input data, such as a new data set 1012. In at least one embodiment, the training framework 1004 repeatedly trains the untrained neural network 1006 while adjusting the weights to refine an output of the untrained neural network 1006 using a loss function and an adaptation algorithm, such as stochastic gradient descent. In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 until the untrained neural network 1006 achieves a desired accuracy.In at least one embodiment, the trained neural network 1008 may then be used to implement any number of machine learning operations.

[0080] In at least one embodiment, the untrained neural network 1006 is trained using unsupervised learning, where the untrained neural network 1006 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 1002 comprises input data without associated output data, or "ground truth" data. In at least one embodiment, the untrained neural network 1006 can learn groupings within the training dataset 1002 and determine how individual inputs are related to the untrained dataset 1002. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in a trained neural network 1008 capable of performing operations useful in reducing the dimensionality of the new dataset 1012.In at least one embodiment, unsupervised training may also be used to perform anomaly detection, which enables the identification of data points in the new data set 1012 that deviate from normal patterns of the new data set 1012.

[0081] In at least one embodiment, semi-supervised learning may be used, i.e., a technique in which the training dataset 1002 comprises a mixture of labeled and unlabeled data. In at least one embodiment, the training framework 1004 may be used to perform incremental learning, for example, through transfer learning techniques. In at least one embodiment, incremental learning allows the trained neural network 1008 to adapt to a new dataset 1012 without forgetting the knowledge instilled in the trained neural network 1008 during initial training.

[0082] In at least one embodiment, the training framework 1004 is a framework processed in conjunction with a software development toolkit such as OpenVINO (Open Visual Inference and Neural Network Optimization). In at least one embodiment, an OpenVINO toolkit is a toolkit such as that developed by Intel Corporation of Santa Clara, CA. In at least one embodiment, OpenVINO includes logic 915 or uses logic 915 to perform the operations described herein. In at least one embodiment, an SoC, integrated circuit, or processor uses OpenVINO to perform the operations described herein.

[0083] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications, in particular neural network applications, for various tasks and operations, such as human vision emulation, speech recognition, natural language processing, recommender systems, and / or variations thereof. In at least one embodiment, OpenVINO supports neural networks such as convolutional neural networks (CNNs), recurrent and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries such as OpenCV, OpenCL, and / or variants thereof.

[0084] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations, such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., humans and / or objects), monocular depth estimation, image colorization, style transfer, action recognition, colorization, and / or variations thereof.

[0085] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as model optimizers. In at least one embodiment, a model optimizer is a command-line tool that facilitates the transitions between training and deployment of neural network models. In at least one embodiment, a model optimizer optimizes neural network models for execution on different devices and / or processing units, such as GPU, CPU, PPU, GPGPU, and / or variants thereof. In at least one embodiment, a model optimizer generates an internal representation of a model and optimizes the model to generate an intermediate representation. In at least one embodiment, a model optimizer reduces a number of layers of a model. In at least one embodiment, a model optimizer removes layers of a model used for training.In at least one embodiment, a model optimizer performs various operations of a neural network, such as changing the inputs to a model (e.g., changing the size of the inputs to a model), changing the size of the inputs of a model (e.g., changing the batch size of a model), changing a model structure (e.g., modifying layers of a model), normalization, standardization, quantization (e.g., converting weights of a model from a first representation, such as floating point, to a second representation, such as integer), and / or variations thereof.

[0086] In at least one embodiment, OpenVINO includes one or more software libraries for inference, also referred to as an inference engine.

[0087] In at least one embodiment, an inference engine is a C++ library or other suitable library in a programming language. In at least one embodiment, an inference engine is used to derive input data. In at least one embodiment, an inference engine implements various classes for deriving input data and producing one or more results. In at least one embodiment, an inference engine implements one or more API functions to process an intermediate representation, specify input and / or output formats, and / or execute a model on one or more devices.

[0088] In at least one embodiment, OpenVINO provides various capabilities for heterogeneously executing one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems using one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions for executing a program on one or more devices. In at least one embodiment, OpenVINO provides various software functions for executing a program and / or portions of a program on different devices. In at least one embodiment, OpenVINO provides various software functions for executing, for example, a first portion of the code on a CPU and a second portion of the code on a GPU and / or FPGA.In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., a first set of layers on a first device, such as a GPU, and a second set of layers on a second device, such as a CPU).

[0089] In at least one embodiment, OpenVINO includes various functionalities similar to those associated with a CUDA programming model, for example, various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or variants thereof. In at least one embodiment, one or more CUDA programming model operations are performed with OpenVINO. In at least one embodiment, various systems, methods, and / or techniques described herein are implemented using OpenVINO. DATA CENTER

[0090] Fig. 11 shows an exemplary data center 1100 in which at least one embodiment may be used. In at least one embodiment, the data center 1100 includes a data center infrastructure layer 1110, a framework layer 1120, a software layer 1130, and an application layer 1140.

[0091] In at least one embodiment, as in Fig. 11, the data center infrastructure layer 1110 may include a resource orchestrator 1112, clustered compute resources 1114, and node compute resources (“Node CRs”) 1116(1)-1116(N), where “N” represents a positive integer (which may be a different integer “N” than used in other figures). In at least one embodiment, the node CRs 1116(1)-1116(N) may include any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), storage devices 1118(1)-1118(N) (e.g., dynamic read-only memory, solid-state storage, or hard disk drives), network input / output devices (“NW I / O”), network switches, virtual machines (“VMs”), power modules and cooling modules, etc. In at least one embodiment, one or more node CRs may be selected from the node CRs 1116(1)-1116(N) may be a server that has one or more of the computing resources listed above.

[0092] In at least one embodiment, the grouped computing resources 1114 may include separate groupings of node CRs housed in one or more racks (not shown) or multiple racks housed in data centers in different geographic locations (also not shown). In at least one embodiment, separate groupings of node CRs within grouped computing resources 1114 may include grouped computing, networking, memory, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, multiple node CRs, including CPUs or processors, may be grouped in one or more racks to provide computing resources to support one or more workloads.In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0093] In at least one embodiment, resource orchestrator 1112 may configure or otherwise control one or more node CRs 1116(1)-1116(N) and / or clustered computing resources 1114. In at least one embodiment, resource orchestrator 1112 may include a software design infrastructure ("SDI") management entity for data center 1100. In at least one embodiment, resource orchestrator 1112 may include hardware, software, or a combination thereof.

[0094] In at least one embodiment, as in Fig. 11, the framework layer 1120 includes a job scheduler 1122, a configuration manager 1124, a resource manager 1126, and a distributed file system 1128. In at least one embodiment, the framework layer 1120 may include a framework for supporting the software 1132 of the software layer 1130 and / or one or more applications 1142 of the application layer 1140. In at least one embodiment, the software 1132 or the application(s) 1142 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1120 may be, but is not limited to, a free and open source software web application framework such as Apache Spark™ (hereinafter "Spark"), which may utilize a distributed file system 1128 for processing large amounts of data (e.g., "Big Data").In at least one embodiment, job scheduler 1122 may include a Spark driver to facilitate scheduling workloads supported by different layers of data center 1100. In at least one embodiment, configuration manager 1124 may be capable of configuring different layers, such as software layer 1130 and framework layer 1120, which include Spark and distributed file system 1128 to support processing large amounts of data. In at least one embodiment, resource manager 1126 may be capable of managing clustered or grouped compute resources allocated to support distributed file system 1128 and job scheduler 1122. In at least one embodiment, the clustered or grouped compute resources may include grouped compute resources 1114 in data center infrastructure layer 1110.In at least one embodiment, the resource manager 1126 may be coordinated with the resource orchestrator 1112 to manage these allocated or assigned computing resources.

[0095] In at least one embodiment, the software 1132 included in software layer 1130 may include software used by at least portions of node CRs 1116(1)-1116(N), clustered computing resources 1114, and / or distributed file system 1128 of framework layer 1120. In at least one embodiment, one or more types of software may include, but are not limited to, Internet website search software, email virus scanning software, database software, and streaming video content software.

[0096] In at least one embodiment, the application(s) 1142 included in the application layer 1140 may include one or more types of applications used by at least portions of the node CRs 1116(1)-1116(N) of clustered computing resources 1114 and / or the distributed file system 1128 of the framework layer 1120. In at least one embodiment, one or more types of applications may include any number of a genomic application, a cognitive computing application, and a machine learning application, including, but not limited to, training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in connection with one or more embodiments.

[0097] In at least one embodiment, configuration manager 1124, resource manager 1126, and resource orchestrator 1112 may implement any number and type of self-modifying actions based on any amount and type of data collected in any technically feasible manner. In at least one embodiment, self-modifying actions may relieve an operator of a data center 1100 from potentially making poor configuration decisions and potentially avoiding underutilized and / or poorly performing portions of a data center.

[0098] In at least one embodiment, data center 1100 may include tools, services, software, or other resources to train one or more machine learning models or to predict or infer information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weighting parameters according to a neural network architecture using software and computational resources described above with respect to data center 1100.In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 1100 by using weighting parameters calculated by one or more training techniques described herein.

[0099] In at least one embodiment, the data center may use CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and / or deriving information using the resources described above. Furthermore, one or more of the software and / or hardware resources described above may be configured as a service to enable users to train or derive information, such as image recognition, speech recognition, or other artificial intelligence services.

[0100] Logic 915 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 915 are described herein in connection with Fig. 9A and / or 9B. In at least one embodiment, logic 915 in data center 1100 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0101] In at least one embodiment, one or more Fig. 9A and / or B are used to implement one or more neural networks with various algorithms, formulas and processes as used in connection with Fig. 1 and / or to otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 9A and / or B are used to implement one or more systems and / or processes as used in connection with Fig. 1-8, for example, to adjust a resolution of information used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein. AUTONOMOUS VEHICLE

[0102] Fig. 12A shows an example of an autonomous vehicle 1200 according to at least one embodiment. In at least one embodiment, the autonomous vehicle 1200 (alternatively referred to herein as "vehicle 1200") may be, without limitation, a passenger vehicle, such as a car, a truck, a bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, the vehicle 1200 may be a semi-trailer truck used for transporting goods. In at least one embodiment, the vehicle 1200 may be an aircraft, a robotic vehicle, or another type of vehicle.

[0103] Autonomous vehicles may be described in terms of automation levels defined by the National Highway Traffic Safety Administration ("NHTSA"), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers ("SAE") "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016-201806, published June 15, 2018, Standard No. J3016-201609, published September 30, 2016, and prior and future versions of this standard). In at least one embodiment, the vehicle 1200 may be capable of performing functions according to one or more of Levels 1 through Level 5 of autonomous driving. For example, in at least one embodiment, the vehicle 1200 may be capable of conditionally automated (Level 3), highly automated (Level 4), and / or fully automated (Level 5), depending on the embodiment.

[0104] In at least one embodiment, vehicle 1200 may include, without limitation, components such as a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1200 may include, without limitation, a propulsion system 1250, such as an internal combustion engine, a hybrid electric power plant, an all-electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1250 may be connected to a drivetrain of vehicle 1200, which may include, without limitation, a transmission, to facilitate propulsion of vehicle 1200. In at least one embodiment, propulsion system 1250 may be controlled in response to receiving signals from one or more gas pedals / accelerators 1252.

[0105] In at least one embodiment, a steering system 1254, which may include, without limitation, a steering wheel, is used to steer the vehicle 1200 (e.g., along a desired path or route) when the propulsion system 1250 is operating (e.g., when the vehicle 1200 is in motion). In at least one embodiment, the steering system 1254 may receive signals from the steering actuator(s) 1256. In at least one embodiment, a steering wheel may be optional for full automation functionality (Level 5). In at least one embodiment, a brake sensor system 1246 may be used to apply the vehicle brakes in response to receiving signals from brake actuator(s) 1248 and / or brake sensors.

[0106] In at least one embodiment, the controller(s) 1236, which may include, without limitation, one or more system-on-chips (“SoCs”), not Fig. 12A) and / or graphics processing unit(s) ("GPU(s)"), send signals (e.g., representative of commands) to one or more components and / or systems of the vehicle 1200. For example, in at least one embodiment, the controller(s) 1236 may send signals to actuate the vehicle brakes via the brake actuator(s) 1248, to actuate the steering system 1254 via the steering actuator(s) 1256, and to actuate the propulsion system 1250 via the accelerator pedal(s) 1252. In at least one embodiment, the controller(s) 1236 may include one or more built-in (e.g., integrated) computing devices that process sensor signals and issue operational commands (e.g., signals representing commands) to enable autonomous driving and / or to assist a human driver in operating the vehicle 1200.In at least one embodiment, controller(s) 1236 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for emergency redundancy, and / or other controllers. In at least one embodiment, a single controller may perform two or more of the above functions, two or more controllers may perform a single function, and / or any combination thereof.

[0107] In at least one embodiment, the controller(s) 1236 provide signals to control one or more components and / or systems of the vehicle 1200 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be received, for example and without limitation, from one or more of GNSS sensor(s) 1258 (e.g., Global Positioning System sensor(s)), RADAR sensor(s) 1260, ultrasonic sensor(s) 1262, LIDAR sensor(s) 1264, inertial measurement unit (“IMU”) sensor(s) 1266 (e.g., accelerometer(s), gyroscope(s), magnetic compass(es), magnetometer(s), etc.), microphone(s) 1296, stereo camera(s) 1268, wide-angle camera(s) 1270 (e.g., fisheye cameras), infrared camera(s) 1272, environmental camera(s) 1274 (e.g., 360-degree cameras), long-range cameras (in Fig. 12A not shown), mid-range camera(s) (in Fig. 12A not shown), speed sensor(s) 1244 (e.g., for measuring the speed of the vehicle 1200), vibration sensor(s) 1242, steering sensor(s) 1240, brake sensor(s) (e.g., as part of the brake sensor system 1246), and / or other types of sensors.

[0108] In at least one embodiment, one or more of the controller(s) 1236 may receive inputs (e.g., represented by input data) from an instrument cluster 1232 of the vehicle 1200 and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface ("HMI") display 1234, an audible annunciator, a speaker, and / or via other components of the vehicle 1200. In at least one embodiment, the outputs may include information such as vehicle speed, RPM, time, map information (e.g., a high-resolution map (in Fig. 12A not shown)), location data (e.g., the location of the vehicle 1200, as on a map), direction, location of other vehicles (e.g., an occupancy grid), information about objects and the status of objects as perceived by the controller(s) 1236, etc. For example, in at least one embodiment, the HMI display 1234 may include information about the presence of one or more objects (e.g., a road sign, a warning sign, a changing traffic light, etc.) and / or information about maneuvers the vehicle has performed, is performing, or will perform (e.g., lane change now, exit 34B in two miles, etc.).

[0109] In at least one embodiment, the vehicle 1200 further includes a network interface 1224 that may utilize wireless antenna(s) 1226 and / or modem(s) to communicate over one or more networks. For example, in at least one embodiment, the network interface 1224 may be capable of communicating over Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communication ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, etc. In at least one embodiment, the wireless antenna(s) 1226 may also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using local area networks such as Bluetooth, Bluetooth Low Energy ("LE"), Z-Wave, ZigBee, etc., and / or low-power wide area networks ("LPWANs") such as LoRaWAN, SigFox, etc.

[0110] Logic 915 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 915 are described herein in connection with Fig. 9A and / or 9B. In at least one embodiment, logic 915 in vehicle 1200 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0111] In at least one embodiment, one or more Fig. 11 systems shown are used to create one or more neural networks with different algorithms, formulas and processes as used in conjunction with Fig. 1 and / or to otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 11 systems depicted are used to implement one or more systems and / or processes as used in connection with Fig. 1-8, for example, to adjust a resolution of information used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein.

[0112] Fig. 12B shows an example of camera positions and fields of view for the autonomous vehicle 1200 of Fig. 12A according to at least one embodiment. In at least one embodiment, the cameras and the respective fields of view represent an exemplary embodiment and are not to be considered limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be arranged at different locations on the vehicle 1200.

[0113] In at least one embodiment, the camera types for cameras may include, but are not limited to, digital cameras that may be adapted for use with components and / or systems of the vehicle 1200. In at least one embodiment, the camera(s) may operate at the Automotive Safety Integrity Level ("ASIL" IB) and / or another ASIL. In at least one embodiment, the camera types may achieve any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the cameras may use rolling shutter, global shutter, another shutter type, or a combination thereof.In at least one embodiment, the color filter array may comprise a red-clear-clear color filter array ("RCCC"), a red-clear-blue color filter array ("RCCB"), a red-blue-green clear color filter array ("RBGC"), a Foveon X3 color filter array, a Bayer sensor color filter array ("RGGB"), a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, clear-pixel cameras, such as cameras with an RCCC, an RCCB, and / or an RBGC color filter array, may be used to increase light sensitivity.

[0114] In at least one embodiment, one or more cameras may be used to implement advanced driver assistance systems ("ADAS") (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multifunction mono camera may be installed to enable features such as lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more of the cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0115] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (three-dimensionally ("3D") printed) assembly, to eliminate stray light and reflections from the vehicle 1200 (e.g., reflections from the dashboard reflected in the windshield mirrors) that may impair the camera's ability to capture images. In at least one embodiment, exterior mirror assemblies may be custom 3D printed so that a camera mounting plate conforms to the shape of an exterior mirror. In at least one embodiment, camera(s) may be integrated into the exterior mirrors. In at least one embodiment, for side-facing cameras, the camera(s) may also be integrated into four pillars at each corner of the cabin.

[0116] In at least one embodiment, cameras with a field of view encompassing portions of an environment in front of the vehicle 1200 (e.g., forward-facing cameras) may be used for the environmental view to help identify forward paths and obstacles, and to provide information critical to establishing an occupancy grid and / or determining preferred vehicle paths with the aid of one or more controllers 1236 and / or control SoCs. In at least one embodiment, forward-facing cameras may be used to perform many similar ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance.In at least one embodiment, forward-facing cameras may also be used for ADAS features and systems, including, without limitation, lane departure warnings (“LDW”), autonomous cruise control (“ACC”), and / or other features such as traffic sign recognition.

[0117] In at least one embodiment, a plurality of cameras may be used in a forward-facing configuration, including, for example, a monocular camera platform comprising a CMOS (complementary metal oxide semiconductor) color imager. In at least one embodiment, a wide-angle camera 1270 may be used to detect objects entering view from the periphery (e.g., pedestrians, crossing traffic, or bicycles). Although in Fig. 12B shows only one wide-angle camera 1270, in other embodiments, the vehicle 1200 may include any number (including zero) of wide-angle cameras. In at least one embodiment, any number of long-range cameras 1298 (e.g., a long-range stereo camera pair) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the long-range camera(s) 1298 may also be used for object detection and classification, as well as basic object tracking.

[0118] In at least one embodiment, any number of stereo cameras 1268 may also be in a forward-facing configuration. In at least one embodiment, one or more of the stereo cameras 1268 may include an integrated controller unit comprising a scalable programmable logic processing unit ("FPGA") and a multi-core microprocessor with an integrated Controller Area Network ("CAN") or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to create a 3D map of the environment of the vehicle 1200 that includes a distance estimate for all points in an image.In at least one embodiment, one or more of the stereo camera(s) 1268 may comprise, without limitation, compact stereo vision sensors, which may comprise, without limitation, two camera lenses (one each on the left and right) and an image processing chip that can measure the distance between the vehicle 1200 and the target object and use generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo camera(s) 1268 may be used in addition to or alternatively to those described herein.

[0119] In at least one embodiment, cameras with a field of view that includes portions of the environment on the sides of the vehicle 1200 (e.g., side cameras) may be used for the environment view and provide information used to create and update an occupancy grid and to generate side impact warnings. In at least one embodiment, for example, environment camera(s) 1274 (e.g., four environment cameras, as in Fig. 12B) may be positioned on the vehicle 1200. In at least one embodiment, the surround camera(s) 1274 may include, without limitation, any number and combination of wide-angle cameras, fisheye cameras, 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye cameras may be positioned on the front, rear, and sides of the vehicle 1200. In at least one embodiment, the vehicle 1200 may utilize three surround camera(s) 1274 (e.g., left, right, and rear) and utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround camera.

[0120] In at least one embodiment, cameras with a field of view encompassing portions of an environment behind the vehicle 1200 (e.g., rearview cameras) may be used for parking assistance, surround view, rear collision warnings, and creating and updating an occupancy grid. In at least one embodiment, a variety of cameras may be used, including, but not limited to, cameras that are also suitable as forward-facing cameras (e.g., long-range cameras 1298 and / or mid-range camera(s) 1276, stereo camera(s) 1268, infrared camera(s) 1272, etc.), as described herein.

[0121] In at least one embodiment, one or more Fig. 12B are used to simulate one or more neural networks with various algorithms, formulas and processes as used in conjunction with Fig. 1 and / or to otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 12B are used to implement one or more systems and / or processes as used in connection with Fig. 1-8, for example, to adjust a resolution of information used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein.

[0122] Fig. 12C is a block diagram illustrating an example system architecture for the autonomous vehicle 1200 of Fig. 12A according to at least one embodiment. In at least one embodiment, each of the components, features, and systems of the vehicle 1200 is Fig. 12C as connected via a bus 1202. In at least one embodiment, bus 1202 may include, without limitation, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, a CAN may be a network within vehicle 1200 used to support the control of various features and functions of vehicle 1200, such as brake application, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus 1202 may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1202 may be read to determine steering wheel angle, vehicle speed, engine speed, button positions, and / or other indications of vehicle status.In at least one embodiment, bus 1202 may be a CAN bus that is ASIL B compliant.

[0123] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or alternatively to CAN. In at least one embodiment, there may be any number of buses forming bus 1202, which may include, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses with different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for collision avoidance functionality and a second bus may be used for actuation control.In at least one embodiment, each bus of bus 1202 may communicate with any components of vehicle 1200, and two or more buses of bus 1202 may communicate with corresponding components. In at least one embodiment, each of any number of system(s) on chip(s) ("SoC(s)") 1204 (such as SoC 1204(A) and SoC 1204(B)), each of controllers 1236, and / or each computer within the vehicle may have access to the same input data (e.g., inputs from sensors of vehicle 1200) and be connected to a common bus, such as the CAN bus.

[0124] In at least one embodiment, the vehicle 1200 may include one or more controllers 1236 as described herein with respect to Fig. 12A. In at least one embodiment, the controller(s) 1236 may be used for a variety of functions. In at least one embodiment, the controller(s) 1236 may be coupled to various other components and systems of the vehicle 1200 and used for control of the vehicle 1200, the artificial intelligence of the vehicle 1200, the infotainment of the vehicle 1200, and / or other functions.

[0125] In at least one embodiment, the vehicle 1200 may include any number of SoCs 1204. In at least one embodiment, each of the SoCs 1204 may include, without limitation, central processing units ("CPU(s)") 1206, graphics processing units ("GPU(s)") 1208, processor(s) 1210, cache(s) 1212, accelerators 1214, data storage 1216, and / or other components and features not shown. In at least one embodiment, SoC(s) 1204 may be used to control the vehicle 1200 in a variety of platforms and systems. For example, in at least one embodiment, SoC(s) 1204 may be combined in a system (e.g., system of the vehicle 1200) with a high-definition ("HD") card 1222 that may be accessed via the network interface 1224 from one or more servers (in Fig. 12C not shown) can receive map updates and / or updates.

[0126] In at least one embodiment, the CPU(s) 1206 may comprise a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, the CPU(s) 1206 may comprise multiple cores and / or level two ("L2") caches. For example, in at least one embodiment, the CPU(s) 1206 may comprise eight cores in a coherent multiprocessor configuration. In at least one embodiment, the CPU(s) 1206 may comprise four dual-core clusters, each cluster having a dedicated L2 cache (e.g., a 2-megabyte (MB) L2 cache). In at least one embodiment, the CPU(s) 1206 (e.g., CCPLEX) may be configured to support concurrent cluster operations such that any combination of clusters of CPU(s) 1206 may be active at any given time.

[0127] In at least one embodiment, one or more of the CPU(s) 1206 may implement power management features, including, without limitation, one or more of the following features: Individual hardware blocks may be automatically clocked when idle to conserve dynamic power; each core clock may be clocked when such core is not actively executing instructions due to the execution of Wait for Interrupt ("WFI") / Wait for Event ("WFE") instructions; each core may be independently power-driven; each core cluster may be independently clock-driven if all cores are clock-driven or power-driven; and / or each core cluster may be independently power-driven if all cores are power-driven.In at least one embodiment, the CPU(s) 1206 may further implement an advanced power state management algorithm, where allowable power states and expected wake-up times are specified, and the hardware / microcode determines which power state is best for the core, cluster, and CCPLEX. In at least one embodiment, the processor cores may support simplified power state entry sequences in software, offloading the work to the microcode.

[0128] In at least one embodiment, GPU(s) 1208 may comprise an integrated GPU (alternatively referred to herein as an "iGPU"). In at least one embodiment, GPU(s) 1208 may be programmable and efficient for parallel workloads. In at least one embodiment, GPU(s) 1208 may utilize an extended tensor instruction set. In at least one embodiment, GPU(s) 1208 may comprise one or more streaming microprocessors, where each streaming microprocessor may comprise a Level 1 ("EI") cache (e.g., an El cache with a memory capacity of at least 96 KB), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with a memory capacity of 512 KB). In at least one embodiment, GPU(s) 1208 may comprise at least eight streaming microprocessors.In at least one embodiment, the GPU(s) 1208 may use one or more application programming interfaces (API(s)) for computation. In at least one embodiment, the GPU(s) 1208 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0129] In at least one embodiment, one or more of the GPU(s) 1208 may be power-optimized for best performance in automotive and embedded use cases. For example, in at least one embodiment, the GPU(s) 1208 may be fabricated on fin field-effect transistor ("FinFET") circuits. In at least one embodiment, each streaming microprocessor may include a number of mixed-precision compute cores divided into multiple blocks. For example, 64 PF32 cores and 32 FP64 cores could be divided into four processing blocks. In at least one embodiment, each processing block could be assigned 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two NVIDIA mixed-precision Tensor cores for deep learning matrix arithmetic, a level zero ("L0") instruction cache, a scheduler (e.g., warp scheduler) or sequencer, a dispatch unit, and / or a 64 KB register file.In at least one embodiment, streaming microprocessors may include independent parallel integer and floating-point datapaths to enable efficient execution of workloads with a mix of computations and addressing calculations. In at least one embodiment, streaming microprocessors may include independent thread scheduling capability to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, streaming microprocessors may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0130] In at least one embodiment, one or more of the GPU(s) 1208 may include high-bandwidth memory ("HBM") and / or a 16 GB HBM2 memory subsystem to provide, in some examples, a peak memory bandwidth of approximately 900 GB / second. In at least one embodiment, in addition to or alternatively to the HBM memory, a synchronous graphics random-access memory ("SGRAM") may be used, such as a synchronous graphics double-data-rate random-access memory type 5 ("GDDR5").

[0131] In at least one embodiment, the GPU(s) 1208 may include unified memory technology. In at least one embodiment, address translation services ("ATS") support may be used to allow the GPU(s) 1208 to directly access page tables of the CPU(s) 1206. In at least one embodiment, an address translation request may be communicated to the CPU(s) 1206 when a GPU of the GPU(s) 1208 memory management unit ("MMU") experiences a fault. In at least one embodiment, unified memory technology may enable a single unified virtual address space for the memory of both the CPU(s) 1206 and the GPU(s) 1208, thereby simplifying programming of the GPU(s) 1208 and porting applications to the GPU(s) 1208.

[0132] In at least one embodiment, the GPU(s) 1208 may include any number of access counters that may track the frequency of access by the GPU(s) 1208 to the memory of other processors. In at least one embodiment, access counters may help ensure that memory pages are moved to the physical memory of a processor that accesses pages most frequently, thereby improving the efficiency of memory regions shared between processors.

[0133] In at least one embodiment, one or more of the SoC(s) 1204 may include any number of cache(s) 1212, including those described herein. For example, in at least one embodiment, the cache(s) 1212 could include a Level 3 ("L3") cache available to both the CPU(s) 1206 and the GPU(s) 1208 (e.g., connected to the UPI(s) 1206 and the GPU(s) 1208). In at least one embodiment, the cache(s) 1212 may include a write-back cache that can track the states of lines, for example, by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, an L3 cache may comprise 4 MB of memory or more, depending on the embodiment, although smaller cache sizes may also be used.

[0134] In at least one embodiment, one or more of the SoC(s) 1204 may include one or more accelerators 1214 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoC(s) 1204 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4 MB of SRAM) may enable a hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, a hardware acceleration cluster may be used to supplement the GPU(s) 1208 and offload some tasks from the GPU(s) 1208 (e.g., to free up more cycles of the GPU(s) 1208 to perform other tasks).In at least one embodiment, the accelerator(s) 1214 could be used for targeted workloads (e.g., perception, convolutional neural networks ("CNNs"), recurrent neural networks ("RNNs"), etc.) that are robust enough to be suitable for acceleration. In at least one embodiment, a CNN may include a region-based or regional neural network ("RCNNs") and fast RCNNs (e.g., for object detection), or another type of CNN.

[0135] In at least one embodiment, the accelerator(s) 1214 (e.g., hardware acceleration clusters) may include one or more deep learning accelerators ("DLAs"). In at least one embodiment, the DLA(s) may include, without limitation, one or more tensor processing units ("TPUs") that may be configured to provide an additional tens of trillion operations per second for deep learning applications and inferences. In at least one embodiment, TPUs may be accelerators configured and optimized to perform image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, the DLA(s) may be further optimized for a particular set of neural network types and floating-point operations, as well as for inferencing.In at least one embodiment, the design of DLA(s) can provide more performance per millimeter than a typical general-purpose GPU, typically far exceeding the performance of a CPU. In at least one embodiment, the TPU(s) can perform multiple functions, including a single-instance convolution function, supporting, for example, INT8, INT16, and FP16 data types for both features and weights, as well as post-processing functions.In at least one embodiment, DLA(s) can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for a variety of functions, including, for example and without limitation: a CNN for object identification and recognition using data from camera sensors; a CNN for distance estimation using data from camera sensors; a CNN for emergency vehicle detection and identification and recognition using data from microphones; a CNN for facial recognition and vehicle owner identification using data from camera sensors; and / or a CNN for safety-relevant and / or security-related events.

[0136] In at least one embodiment, the DLA(s) may perform any function of the GPU(s) 1208, and by using an inference accelerator, a developer may, for example, dedicate either the DLA(s) or the GPU(s) 1208 to each function. For example, in at least one embodiment, a developer may focus the processing of CNNs and floating-point operations on the DLA(s) and leave other functions to the GPU(s) 1208 and / or the accelerator(s) 1214.

[0137] In at least one embodiment, the accelerator(s) 1214 may comprise a programmable image processing accelerator ("PVA"), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate image processing algorithms for advanced driver assistance systems ("ADAS") 1238, autonomous driving, augmented reality ("AR"), and / or virtual reality ("VR") applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may comprise, without limitation, any number of reduced instruction set ("RISC") cores, direct memory access ("DMA") cores, and / or any number of vector processors.

[0138] In at least one embodiment, RISC cores may interact with image sensors (e.g., image sensors of all cameras described herein), image signal processor(s), etc. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, the RISC cores may use a variety of protocols depending on the embodiment. In at least one embodiment, the RISC cores may execute a real-time operating system ("RTOS"). In at least one embodiment, RISC cores may be implemented with one or more integrated circuits, application-specific integrated circuits ("ASICs"), and / or memory devices. In at least one embodiment, RISC cores could, for example, include an instruction cache and / or tightly coupled RAM.

[0139] In at least one embodiment, DMA may enable components of the PVA to access system memory independently of the CPU(s) 1206. In at least one embodiment, DMA may support any number of features used to optimize a PVA, including, but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, DMA may support up to six or more dimensions of addressing, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0140] In at least one embodiment, vector processors may be programmable processors that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing functions. In at least one embodiment, a PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, a PVA core may include a processor subsystem, DMA engine(s) (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, a vector processing subsystem may operate as the primary processing engine of a PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM").In at least one embodiment, the VPU core may include a digital signal processor, such as a single instruction multiple data ("SIMD") and very long instruction word ("VLIW") digital signal processor. In at least one embodiment, a combination of SIMD and VLIW may increase throughput and speed.

[0141] In at least one embodiment, each of the vector processors may include an instruction cache and be connected to dedicated memory. Consequently, in at least one embodiment, each of the vector processors may be configured to operate independently of other vector processors. In at least one embodiment, vector processors included in a particular PVA may be configured to use data parallelism. For example, in at least one embodiment, a plurality of vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image.In at least one embodiment, the vector processors included in a particular PVA may simultaneously execute different image processing algorithms for an image, or even different algorithms for successive images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in a hardware acceleration cluster, and each PVA may include any number of vector processors. In at least one embodiment, the PVA may include additional error-correcting code ("ECC") memory to increase the security of the overall system.

[0142] In at least one embodiment, the accelerator(s) 1214 may include an on-chip computer vision network and static random access memory ("SRAM") to provide high-bandwidth, low-latency SRAM for the accelerator(s) 1214. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, including, for example and without limitation, eight field-configurable memory blocks accessible by both a PVA and a DLA. In at least one embodiment, each pair of memory blocks may include an extended peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used.In at least one embodiment, a PVA and a DLA may access the memory via a backbone that provides high-speed access to the memory for a PVA and a DLA. In at least one embodiment, a backbone may include an on-chip computer vision network that interconnects a PVA and a DLA to the memory (e.g., using APB).

[0143] In at least one embodiment, an on-chip computer vision network may include an interface that determines that both a PVA and a DLA are providing ready and valid signals before transmitting control signals / addresses / data. In at least one embodiment, an interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst communication for continuous data transmission. In at least one embodiment, an interface may conform to International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("EC") 61508 standards, although other standards and protocols may be used.

[0144] In at least one embodiment, one or more of the SoC(s) 1204 may include a hardware accelerator for real-time ray tracing. In at least one embodiment, the real-time ray tracing hardware accelerator may be used for quickly and efficiently determining positions and extents of objects (e.g., within a world model), generating real-time visualization simulations, radar signal interpretation, sound propagation synthesis and / or analysis, simulating sonar systems, general wave propagation simulation, comparing with lidar data for localization and / or other functions, and / or for other purposes.

[0145] In at least one embodiment, the accelerator(s) 1214 may have a wide range of uses for autonomous driving. In at least one embodiment, a PVA may be used for critical processing steps in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of a PVA are well suited to algorithmic domains that require predictable, low-power, and low-latency processing. In other words, a PVA is well suited for semi-dense or dense regular computations, even on small datasets, that require predictable, low-latency, and low-power runtimes. In at least one embodiment, such as in vehicle 1200, PVAs may be designed to execute classical computer vision algorithms because of their efficiency in object detection and processing integer mathematical data.

[0146] For example, according to at least one embodiment of the technology, a PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, Level 3-5 autonomous driving applications utilize motion estimation / stereo matching while driving (e.g., structure from motion, pedestrian detection, lane detection, etc.). In at least one embodiment, a PVA may perform computer stereo vision functions on inputs from two monocular cameras.

[0147] In at least one embodiment, a PVA may be used to perform dense optical flow. In at least one embodiment, a PVA could, for example, process raw radar data (e.g., using a 4D Fast Fourier Transform) to provide processed radar data. In at least one embodiment, a PVA is used for depth-of-flight processing, processing raw time-of-flight data to provide, for example, processed time-of-flight data.

[0148] In at least one embodiment, a DLA may be used to power any type of network to improve control and driving safety, including, for example and without limitation, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, confidence may be represented or interpreted as a probability, or as the relative "weight" of each detection compared to other detections. In at least one embodiment, a confidence measure allows the system to make further decisions about which detections should be considered true positives and which should be considered false positives. In at least one embodiment, a system may set a threshold for the confidence measure and consider only detections that exceed the threshold to be true positives.In an embodiment using an automatic emergency braking ("AEB") system, false positive detections would cause the vehicle to automatically perform emergency braking, which is clearly undesirable. In at least one embodiment, highly confident detections can be considered as triggers for AEB. In at least one embodiment, a DLA can employ a neural network to regress the confidence value.In at least one embodiment, the neural network may use as input at least a subset of parameters, such as the dimensions of the bounding box, the ground plane estimate obtained (e.g., from another subsystem), the output of the IMU sensor(s) 1266 correlated with the orientation of the vehicle 1200, the range, the 3D position estimates of the object obtained from the neural network and / or other sensors (e.g., LIDAR sensor(s) 1264 or RADAR sensor(s) 1260), and others.

[0149] In at least one embodiment, one or more SoC(s) 1204 may include one or more data stores 1216 (e.g., memories). In at least one embodiment, the data stores 1216 may be on-chip memory of the SoC(s) 1204, which may store neural networks to be executed on the GPU(s) 1208 and / or a DLA. In at least one embodiment, the data stores 1216 may be large enough to store multiple neural network instances for redundancy and security. In at least one embodiment, the data stores 1216 may include L2 or L3 cache(s).

[0150] In at least one embodiment, one or more of the SoC(s) 1204 may include any number of processor(s) 1210 (e.g., embedded processors). In at least one embodiment, the processor(s) 1210 may include a boot and power management processor, which may be a dedicated processor and subsystem to handle boot power and management functions and associated security enforcement. In at least one embodiment, a boot and power management processor may be part of a boot sequence of SoC(s) 1204 and provide runtime power management services.In at least one embodiment, a boot power and management processor may perform clock and voltage programming, assist with low-power state transitions, manage the thermal and temperature sensors of the SoC(s) 1204, and / or manage the power states of the SoC(s) 1204. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and SoC(s) 1204 may use ring oscillators to sense temperatures of CPU(s) 1206, GPU(s) 1208, and / or accelerator(s) 1214.In at least one embodiment, if temperatures are determined to exceed a threshold, a boot and power management processor may enter a temperature fault routine and place SoCfs 1204 into a lower power state and / or place vehicle 1200 into a chauffeur-to-safe stop mode (e.g., bring vehicle 1200 to a safe stop).

[0151] In at least one embodiment, processor(s) 1210 may further include a set of embedded processors that may serve as an audio processing engine, which may be an audio subsystem enabling full hardware support for multi-channel audio across multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, an audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM.

[0152] In at least one embodiment, the processor(s) 1210 may further include an always-on processor engine that may provide the necessary hardware functions to support low-power sensor management and wake use cases. In at least one embodiment, an always-on processor engine may include, without limitation, a processor core, tightly coupled memory, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0153] In at least one embodiment, the processor(s) 1210 may further comprise a safety cluster engine, including, without limitation, a dedicated processor subsystem for handling safety management for automotive applications. In at least one embodiment, a safety cluster engine may include, without limitation, two or more processor cores, tightly coupled memory, supporting peripherals (e.g., timers, an interrupt controller, etc.), and / or routing logic. In a safety mode, in at least one embodiment, two or more cores may operate in a lockstep mode, functioning as a single core with comparison logic to detect any differences between their operations.In at least one embodiment, the processor(s) 1210 may further comprise a real-time camera engine, which may, without limitation, include a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, the processor(s) 1210 may further comprise a high dynamic range signal processor, which may, without limitation, include an image signal processor that is a hardware engine that is part of a camera processing pipeline.

[0154] In at least one embodiment, processor(s) 1210 may include a video image compositor, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by a video playback application to generate a final image for a player window. In at least one embodiment, a video image compositor may perform lens distortion correction on the wide-angle camera(s) 1270, the surround camera(s) 1274, and / or the sensors of the in-cabin surveillance camera(s). In at least one embodiment, the sensor(s) of the in-cabin surveillance camera(s) is / are preferably monitored by a neural network running on another instance of SoC 1204 and configured to detect and respond to events in the cabin.In at least one embodiment, an in-cabin system may perform lip reading without limitation to activate cellular service and place a call, dictate emails, change a vehicle's destination, activate or change a vehicle's infotainment system and settings, or enable voice-activated web browsing. In at least one embodiment, certain functions are available to the driver when a vehicle is operating in an autonomous mode and are disabled otherwise.

[0155] In at least one embodiment, a video image compositor may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment where motion occurs in a video, the noise reduction appropriately weights spatial information and reduces the weight of information provided by neighboring frames. In at least one embodiment where an image or a portion of an image does not include motion, the temporal noise reduction performed by the video image compositor may use information from a previous image to reduce noise in the current image.

[0156] In at least one embodiment, a video image compositor may also be configured to perform stereo rectification on the input stereo lens images. In at least one embodiment, a video image compositor may further be used for user interface composition when an operating system desktop is in use and the GPU(s) 1208 are not required to continuously render new surfaces. In at least one embodiment, a video image compositor may be used to offload the GPU(s) 1208 to improve performance and responsiveness when the GPU(s) 1208 are turned on and actively performing 3D rendering.

[0157] In at least one embodiment, one or more of SoC(s) 1204 may further include a Mobile Industrial Processor Serial Interface ("MIPI") for receiving video and input from cameras, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functions. In at least one embodiment, one or more of SoC(s) 1204 may further include one or more input / output controllers that may be controlled by software and may be used to receive I / O signals that are not tied to a specific role.

[0158] In at least one embodiment, one or more of SoC(s) 1204 may further include a wide range of peripheral interfaces to enable communication with peripherals, audio encoders / decoders ("codecs"), power management, and / or other devices. In at least one embodiment, SoC(s) 1204 may be used to receive data from cameras (e.g., via Gigabit Multimedia Serial Link and Ethernet channels), sensors (e.g., LIDAR sensor(s) 1264, RADAR sensor(s) 1260, etc., which may be connected via Ethernet channels), data from bus 1202 (e.g., speed of vehicle 1200, steering wheel position, etc.), data from GNSS sensor(s) 1258 (e.g., connected via an Ethernet bus or a CAN bus), etc.In at least one embodiment, one or more of SoC(s) 1204 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and which may be used to free CPU(s) 1206 from routine data management tasks.

[0159] In at least one embodiment, the SoC(s) 1204 may be an end-to-end platform with a flexible architecture spanning automation levels 3-5, thereby providing a comprehensive functional safety architecture, leveraging computer vision and ADAS techniques for diversity and redundancy, and providing a platform for a flexible, reliable driving software stack along with deep learning tools. In at least one embodiment, the SoC(s) 1204 may be faster, more reliable, and even more power and space efficient than conventional systems. For example, in at least one embodiment, the accelerator(s) 1214, in combination with the CPU(s) 1206, the GPU(s) 1208, and the data memory(s) 1216, may form a fast, efficient platform for Level 3-5 autonomous vehicles.

[0160] In at least one embodiment, computer vision algorithms may be executed on CPUs that can be configured using a high-level programming language, such as C, to execute a variety of processing algorithms on a wide variety of visual data. However, in at least one embodiment, CPUs are often unable to meet the performance requirements of many image processing applications, such as execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and in practical Level 3-5 autonomous vehicles.

[0161] The embodiments described herein enable multiple neural networks to be executed simultaneously and / or sequentially and the results to be combined to enable Level 3 to Level 5 autonomous driving functionality. For example, in at least one embodiment, a CNN executing on a DLA or a discrete GPU (e.g., GPU(s) 1220) may include text and word recognition that enables the reading and understanding of traffic signs, including signs for which a neural network has not been specifically trained. In at least one embodiment, a DLA may further include a neural network capable of identifying, interpreting, and semantically understanding a sign and passing this semantic understanding to path planning modules running on a CPU complex.

[0162] In at least one embodiment, multiple neural networks may run simultaneously, such as in Level 3, 4, or 5 driving. For example, in at least one embodiment, a warning sign reading "Caution: Flashing lights indicate icy conditions" along with an electric light may be interpreted independently or jointly by multiple neural networks. At least in one embodiment, such a warning sign may itself be identified as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text "Flashing lights indicate icy conditions" may be interpreted by a second deployed neural network, which informs a vehicle's path planning software (preferably running on a CPU complex) that, when flashing lights are detected, icy conditions are present.In at least one embodiment, a turn signal may be identified by operating a third neural network over multiple frames, which informs a vehicle's path planning software of the presence (or absence) of turn signals. In at least one embodiment, all three neural networks may run concurrently, for example, within a DLA and / or on GPU(s) 1208.

[0163] In at least one embodiment, a facial recognition and vehicle owner identification CNN may use data from camera sensors to identify the presence of an authorized driver and / or owner of the vehicle 1200. In at least one embodiment, an always-on sensor processing engine may be used to unlock a vehicle when an owner approaches a driver's door and turns on the lights, and to disable such a vehicle in a security mode when an owner exits such a vehicle. In this way, the SoC(s) 1204 provide security against theft and / or carjacking.

[0164] In at least one embodiment, a CNN for detecting and identifying emergency vehicles may use data from microphones 1296 to detect and identify emergency vehicle sirens. In at least one embodiment, the SoC(s) 1204 use a CNN to classify environmental and urban sounds, as well as to classify visual data. In at least one embodiment, a CNN running on a DLA is trained to detect a relative approach speed of an emergency vehicle (e.g., using a Doppler effect). In at least one embodiment, a CNN may also be trained to identify emergency vehicles specific to a local area in which a vehicle is traveling, as identified by GNSS sensor(s) 1258.In at least one embodiment, when deployed in Europe, a CNN will attempt to detect European sirens, and when deployed in North America, a CNN will attempt to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program may be used to execute an emergency vehicle safety routine, slow a vehicle, pull over to the side of the road, park a vehicle, and / or idle a vehicle using the ultrasonic sensor(s) 1262 until the emergency vehicles have passed.

[0165] In at least one embodiment, the vehicle 1200 may include one or more CPU(s) 1218 (e.g., discrete CPU(s) or dCPU(s)) that may be connected to the SoC(s) 1204 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the CPU(s) 1218 may include, for example, an x86 processor. The CPU(s) 1218 may be used to perform a variety of functions, including reconciling potentially conflicting results between ADAS sensors and SoC(s) 1204 and / or monitoring the status and health of the controller(s) 1236 and / or an infotainment system on a chip (“infotainment SoC”) 1230, for example. In at least one embodiment, the SoC(s) 1204 includes one or more interconnects, and an interconnect may include a Peripheral Component Interconnect Express (PCIe).

[0166] In at least one embodiment, vehicle 1200 may include GPU(s) 1220 (e.g., discrete GPU(s) or dGPU(s)) that may be coupled to SoC(s) 1204 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, GPU(s) 1220 may provide additional artificial intelligence functionality, for example, by executing redundant and / or distinct neural networks, and may be used to train and / or update neural networks based at least in part on inputs (e.g., sensor data) from sensors of vehicle 1200.

[0167] In at least one embodiment, the vehicle 1200 may further include a network interface 1224, which may include, without limitation, one or more wireless antennas 1226 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, the network interface 1224 may be used to enable wireless connection to internet cloud services (e.g., to server(s) and / or other network devices), to other vehicles, and / or to computing devices (e.g., passenger client devices). In at least one embodiment, a direct connection between the vehicle 1200 and another vehicle and / or an indirect connection (e.g., via networks and the internet) may be established to communicate with other vehicles.In at least one embodiment, direct connections may be established via a vehicle-to-vehicle communication link. In at least one embodiment, a vehicle-to-vehicle communication link may provide vehicle 1200 with information about vehicles in the vicinity of vehicle 1200 (e.g., vehicles in front of, beside, and / or behind vehicle 1200). In at least one embodiment, such aforementioned functionality may be part of a cooperative adaptive cruise control function of vehicle 1200.

[0168] In at least one embodiment, the network interface 1224 may include an SoC that provides modulation and demodulation functions and enables the controller(s) 1236 to communicate over wireless networks. In at least one embodiment, the network interface 1224 may include a radio frequency front-end for upconversion from baseband to radio frequency and downconversion from radio frequency to baseband. In at least one embodiment, the frequency conversions may be performed in any technically feasible manner. For example, frequency conversions may be performed by known methods and / or using superheterodyne techniques. In at least one embodiment, the radio frequency front-end functionality may be provided by a separate chip.In at least one embodiment, the network interfaces may include wireless capabilities for communication via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0169] In at least one embodiment, the vehicle 1200 may further include one or more data stores 1228, which may include, without limitation, off-chip memory (e.g., outside of the SoC(s) 1204). In at least one embodiment, the data store(s) 1228 may include, without limitation, one or more memory elements, including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, hard drives, and / or other components and / or devices capable of storing at least one bit of data.

[0170] In at least one embodiment, the vehicle 1200 may further include GNSS sensor(s) 1258 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, sensing, occupancy grid generation, and / or path planning. In at least one embodiment, any number of GNSS sensor(s) 1258 may be used, including, for example, and without limitation, a GPS using a USB port with an Ethernet-to-serial bridge (e.g., RS-232).

[0171] In at least one embodiment, the vehicle 1200 may further include RADAR sensor(s) 1260. In at least one embodiment, the RADAR sensor(s) 1260 may be used by the vehicle 1200 for long-range vehicle detection, even in darkness and / or adverse weather conditions. In at least one embodiment, the RADAR functional safety levels may be ASIL B. In at least one embodiment, the RADAR sensor(s) 1260 may use a CAN bus and / or bus 1202 (e.g., for transmitting data generated by the RADAR sensor(s) 1260) for control and access to object tracking data, with raw data being accessed via Ethernet channels in some examples. In at least one embodiment, a wide range of RADAR sensors may be used.For example, and without limitation, radar sensor(s) 1260 may be suitable for use as front, rear, and side radar. In at least one embodiment, one or more sensors of radar sensor(s) 1260 is a pulse-Doppler radar sensor.

[0172] In at least one embodiment, the RADAR sensor(s) 1260 may include different configurations, such as long range with a narrow field of view, short range with a wide field of view, short range side coverage, etc. In at least one embodiment, long range RADAR may be used for adaptive cruise control functionality. In at least one embodiment, long range RADAR systems may provide a wide field of view realized by two or more independent scans, for example, within a range of 250 m (meters). In at least one embodiment, RADAR sensor(s) 1260 may assist in distinguishing between static and moving objects and may be used by the ADAS system 1238 for emergency braking assistance and forward collision warning.In at least one embodiment, the sensor(s) 1260 included in a long-range radar system may include, without limitation, a monostatic multimodal radar with multiple (e.g., six or more) fixed radar antennas and a high-speed CAN and FlexRay interface. In at least one embodiment with six antennas, four antennas in the center may create a focused beam pattern useful for detecting the vehicle's surroundings at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, two additional antennas may expand the field of view, allowing for rapid detection of vehicles entering or exiting a lane of vehicle 1200.

[0173] For example, in at least one embodiment, medium-range radar systems may include a range of up to 160 m (front) or 80 m (rear) and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, short-range radar systems may include, without limitation, any number of radar sensors 1260 that may be installed at either end of a rear bumper. In at least one embodiment, a radar sensor system, when installed at either end of a rear bumper, may create two beams that continuously monitor blind spots to the rear and to the side of a vehicle. In at least one embodiment, short-range radar systems may be used in ADAS system 1238 for blind spot detection and / or lane change assistance.

[0174] In at least one embodiment, the vehicle 1200 may further include ultrasonic sensor(s) 1262. In at least one embodiment, the ultrasonic sensor(s) 1262, which may be arranged at a front, rear, and / or side location of the vehicle 1200, may be used for parking assistance and / or for creating and updating an occupancy grid. In at least one embodiment, a plurality of ultrasonic sensor(s) 1262 may be used, and different ultrasonic sensors 1262 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensor(s) 1262 may operate at functional safety levels of ASIL B.

[0175] In at least one embodiment, the vehicle 1200 may include the LIDAR sensor(s) 1264. In at least one embodiment, the LIDAR sensor(s) 1264 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the LIDAR sensor(s) 1264 may operate at the ASIL B functional safety level. In at least one embodiment, the vehicle 1200 may include multiple LIDAR sensors 1264 (e.g., two, four, six, etc.) that may utilize an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0176] In at least one embodiment, the LIDAR sensor(s) 1264 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, the commercially available LIDAR sensor(s) 1264 may have an advertised range of approximately 100 m, with an accuracy of 2 cm to 3 cm, and with support for a 100 Mbps Ethernet connection, for example. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, the LIDAR sensor(s) 1264 may comprise a small device that can be embedded in a front, rear, side, and / or corner location of the vehicle 1200.In at least one embodiment, the LIDAR sensor(s) 1264 in such an embodiment may provide a horizontal field of view of up to 120 degrees and a vertical field of view of up to 35 degrees with a range of 200 m, even for low-reflectivity objects. In at least one embodiment, the front-mounted LIDAR sensor(s) 1264 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0177] In at least one embodiment, LIDAR technologies, such as 3D flash LIDAR, may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as the transmission source to illuminate the surroundings of the vehicle 1200 up to a distance of approximately 200 m. In at least one embodiment, a flash LIDAR unit includes, without limitation, a receptor that records the time of flight of the laser pulse and the reflected light at each pixel, which in turn corresponds to a distance from the vehicle 1200 to objects. In at least one embodiment, flash LIDAR may enable highly accurate and distortion-free images of the surroundings to be generated with each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of the vehicle 1200.In at least one embodiment, 3D flash LIDAR systems include, without limitation, a solid-state 3D star array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device may use a 5-nanosecond Class I (eye-safe) laser pulse per image and collect the reflected laser light as a 3D range point cloud and co-registered intensity data.

[0178] In at least one embodiment, the vehicle 1200 may further include one or more IMU sensors 1266. In at least one embodiment, the IMU sensor(s) 1266 may be located in the center of a rear axle of the vehicle 1200. In at least one embodiment, the IMU sensor(s) 1266 may include, for example, and without limitation, accelerometers, magnetometers, gyroscopes, a magnetic compass, magnetic compasses, and / or other types of sensors. In at least one embodiment, such as in six-axis applications, the IMU sensor(s) 1266 may include, without limitation, accelerometers and gyroscopes. In at least one embodiment, such as in nine-axis applications, the IMU sensor(s) 1266 may include, without limitation, accelerometers, gyroscopes, and magnetometers.

[0179] In at least one embodiment, the IMU sensor(s) 1266 may be implemented as a miniaturized, high-performance GPS-based inertial navigation system ("GPS / INS") that combines microelectromechanical systems ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filter algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, the IMU sensor(s) 1266 may enable the vehicle 1200 to estimate its heading without requiring input from a magnetic sensor by directly observing velocity changes from a GPS and correlating them with the IMU sensor(s) 1266. In at least one embodiment, the IMU sensor(s) 1266 and the GNSS sensor(s) 1258 may be combined into a single integrated unit.

[0180] In at least one embodiment, the vehicle 1200 may include one or more microphones 1296 disposed in and / or around the vehicle 1200. In at least one embodiment, the microphone(s) 1296 may be used, among other things, for detecting and identifying emergency vehicles.

[0181] In at least one embodiment, the vehicle 1200 may further include any number of camera types, including stereo camera(s) 1268, wide-angle camera(s) 1270, infrared camera(s) 1272, surround camera(s) 1274, long-range camera(s) 1298, medium-range camera(s) 1276, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around the entire perimeter of the vehicle 1200. In at least one embodiment, the types of cameras used depend on the vehicle 1200. In at least one embodiment, any combination of camera types may be used to provide the required coverage around the vehicle 1200. In at least one embodiment, the number of cameras employed may vary depending on the embodiment.In at least one embodiment, the vehicle 1200 may include, for example, six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may support, by way of example and without limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, each camera may be configured as previously described herein with respect to . Fig. 12A and Fig. 12B is described in more detail.

[0182] In at least one embodiment, the vehicle 1200 may further include one or more vibration sensors 1242. In at least one embodiment, the vibration sensor(s) 1242 may measure vibrations of components of the vehicle 1200, such as the axle(s). For example, in at least one embodiment, changes in vibrations may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1242 are used, differences between vibrations may be used to determine friction or slippage of the road surface (e.g., when there is a difference in vibration between a driven axle and a free-spinning axle).

[0183] In at least one embodiment, the vehicle 1200 may include the ADAS system 1238. In at least one embodiment, the ADAS system 1238 may include, in some examples, without limitation, an SoC. In at least one embodiment, the ADAS system 1238 may include, without limitation, any number and combination of an autonomous / adaptive / automatic cruise control (“ACC”) system, a cooperative adaptive cruise control (“CACC”) system, a forward crash warning (“FCW”) system, an automatic emergency braking (“AEB”) system, a lane departure warning (“LDW”) system, a lane keep assist (“LKA”) system, a blind spot warning (“BSW”) system, a rear cross traffic warning (“RCTW”) system, a forward collision warning (“CW”) system, a lane centering (“LC”) system, and / or other systems, features, and / or functions.

[0184] In at least one embodiment, the ACC system may use RADAR sensor(s) 1260, LIDAR sensor(s) 1264, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, a longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of the vehicle 1200 and automatically adjusts the speed of the vehicle 1200 to maintain a safe distance from preceding vehicles. In at least one embodiment, a lateral ACC system provides follow-through and advises the vehicle 1200 to change lanes if necessary. In at least one embodiment, a lateral ACC is connected to other ADAS applications, such as LC and CW.

[0185] In at least one embodiment, a CACC system utilizes information from other vehicles that may be received via a network interface 1224 and / or wireless antenna(s) 1226 from other vehicles over a wireless connection or indirectly via a network connection (e.g., over the Internet). In at least one embodiment, direct connections may be provided by a vehicle-to-vehicle ("V2V") communication link, while indirect connections may be provided by an infrastructure-to-vehicle ("I2V") communication link. Generally, V2V communication provides information about immediately ahead vehicles (e.g., vehicles immediately in front of and in the same lane as vehicle 1200), while I2V communication provides information about traffic further ahead.In at least one embodiment, a CACC system may include either one or both I2V and V2V information sources. In at least one embodiment, a CACC system may be more reliable given information about vehicles ahead of vehicle 1200 and has the potential to improve traffic flow and reduce congestion on the road.

[0186] In at least one embodiment, an FCW system is configured to warn a driver of a hazard so that the driver can take corrective action. In at least one embodiment, an FCW system utilizes a forward-facing camera and / or RADAR sensor(s) 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibrating component. In at least one embodiment, an FCW system may provide a warning, such as a sound, a visual warning, a vibration, and / or a rapid braking pulse.

[0187] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object and may automatically apply the brakes if a driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system may utilize forward-facing camera(s) and / or RADAR sensor(s) 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when an AEB system detects a hazard, it will typically first alert a driver to take corrective action to avoid a collision, and if that driver does not take corrective action, the AEB system may automatically apply the brakes to prevent or at least mitigate the effects of a predicted collision.In at least one embodiment, an AEB system may include techniques such as dynamic brake assistance and / or crash-imminent braking.

[0188] In at least one embodiment, an LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle 1200 crosses lane markings. In at least one embodiment, an LDW system is not activated when a driver indicates an intentional lane departure, for example, by activating a turn signal. In at least one embodiment, an LDW system may utilize forward-facing cameras coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide feedback to the driver, for example, via a display, speaker, and / or vibrating component. In at least one embodiment, an LKA system is a variant of an LDW system.In at least one embodiment, an LKA system provides a steering input or braking to correct the vehicle 1200 when the vehicle 1200 begins to depart from its lane.

[0189] In at least one embodiment, a BSW system detects and warns the driver of vehicles in the vehicle's blind spot. In at least one embodiment, a BSW system may provide a visual, audible, and / or tactile warning to indicate that merging or changing lanes is unsafe. In at least one embodiment, a BSW system may provide an additional warning when a driver activates a turn signal. In at least one embodiment, a BSW system may utilize rear-facing camera(s) and / or RADAR sensor(s) 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to feedback to the driver, such as a display, speaker, and / or vibrating component.

[0190] In at least one embodiment, an RCTW system may provide visual, audible, and / or tactile notification when an object is detected outside the range of the rearview camera when the vehicle 1200 is reversing. In at least one embodiment, an RCTW system includes an AEB system to ensure that the vehicle brakes are applied to avoid a crash. In at least one embodiment, an RCTW system may utilize one or more rear-facing RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibrating component.

[0191] In at least one embodiment, conventional ADAS systems may be prone to false positive results, which can be annoying and distracting for a driver, but are typically not catastrophic because conventional ADAS systems alert a driver and allow that driver to decide whether a safety condition truly exists and act accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 1200 itself decides whether to consider the result of a primary computer or a secondary computer (e.g., a first controller or a second controller of the controllers 1236). In at least one embodiment, the ADAS system 1238 may, for example, be a backup and / or secondary computer that provides perception information to a rationality module of the backup computer.In at least one embodiment, a backup computer rationality monitor may run redundant, diverse software on hardware components to detect errors in perception and dynamic driving tasks. In at least one embodiment, the outputs of the ADAS system 1238 may be forwarded to a supervisory MCU. In at least one embodiment, if the outputs of a primary computer and the outputs of a secondary computer conflict, a supervisory MCU determines how to resolve the conflict to ensure safe operation.

[0192] In at least one embodiment, a primary computer may be configured to provide a score to a supervising MCU indicating the primary computer's confidence in a particular result. In at least one embodiment, the supervising MCU may follow the primary computer's instruction if that confidence score exceeds a threshold, regardless of whether the secondary computer provides a conflicting or inconsistent result. In at least one embodiment, in cases where a confidence score does not meet a threshold and where primary and secondary computers report different results (e.g., a conflict), a supervising MCU may arbitrate between the computers to determine an appropriate result.

[0193] In at least one embodiment, a monitoring MCU may be configured to execute a neural network(s) trained and configured to determine, based at least in part on the outputs of a primary computer and the outputs of a secondary computer, the conditions under which the secondary computer provides false alarms. In at least one embodiment, the neural network(s) in a monitoring MCU may learn when the output of a secondary computer can and cannot be trusted. In at least one embodiment, when the secondary computer is a RADAR-based FCW system, a neural network(s) mayNeural networks in this monitoring MCU can learn when an FCW system identifies metallic objects that are not actually hazards, such as a drain grate or manhole cover that triggers an alarm. In at least one embodiment, when a secondary computer is a camera-based LDW system, a neural network in a monitoring MCU can learn to override the LDW system when cyclists or pedestrians are present and leaving the lane is actually the safest maneuver. In at least one embodiment, a monitoring MCU can include at least one DLA or GPU suitable for executing neural networks with associated memory. In at least one embodiment, a monitoring MCU can comprise and / or be included as a component of the SoC(s) 1204.

[0194] In at least one embodiment, ADAS system 1238 may include a secondary computer that performs ADAS functions using conventional computer vision rules. In at least one embodiment, this secondary computer may use classic computer vision (if-then) rules, and the presence of a neural network(s) in a higher-level MCU may improve reliability, safety, and performance. In at least one embodiment, the different implementation and intentional non-identity make the overall system more fault-tolerant, particularly against errors caused by software functions (or software-hardware interfaces).For example, in at least one embodiment, if a software error occurs in the software running on a primary computer and non-identical software code runs on a secondary computer that produces a consistent overall result, then a supervising MCU may have greater confidence that an overall result is correct and an error in the software or hardware on that primary computer does not cause a significant error.

[0195] In at least one embodiment, an output of the ADAS system 1238 may be fed to the perception block of a primary computer and / or the dynamic driving task block of a primary computer. For example, in at least one embodiment, if the ADAS system 1238 indicates a forward crash warning due to an object immediately ahead, a perception block may use this information in identifying objects. In at least one embodiment, a secondary computer may have its own neural network trained, thus reducing the risk of false alarms, as described herein.

[0196] In at least one embodiment, the vehicle 1200 may further include an infotainment SoC 1230 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 1230 may not be an SoC and may include, without limitation, two or more discrete components. In at least one embodiment, the infotainment SoC 1230 may include, without limitation, a combination of hardware and software that may be used to provide audio (e.g., music, a personal digital assistant, navigation commands, news, radio, etc.), video (e.g., television, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.).) and / or information services (e.g., navigation systems, rear parking assistance, a radio data system, vehicle-related information such as fuel level, total distance traveled, brake fuel level, oil level, door open / close, air filter information, etc.) to the vehicle 1200. The infotainment SoC 1230 could include, for example, radios, record players, navigation systems, video players, USB and Bluetooth connectivity, car computers, in-car entertainment, WiFi, steering wheel audio controls, hands-free calling, a heads-up display (“HUD”), an HMI display 1234, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, functions, and / or systems), and / or other components.In at least one embodiment, the infotainment SoC 1230 may be further used to provide information (e.g., visual and / or audible) to the user(s) of the vehicle 1200, such as information from the ADAS system 1238, autonomous driving information such as planned vehicle maneuvers, trajectories, environmental information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0197] In at least one embodiment, the infotainment SoC 1230 may include any amount and type of GPU functionality. In at least one embodiment, the infotainment SoC 1230 may communicate with other devices, systems, and / or components of the vehicle 1200 via the bus 1202. In at least one embodiment, the infotainment SoC 1230 may be coupled to a supervisory MCU so that a GPU of an infotainment system may perform some self-driving functions if the primary controller(s) 1236 (e.g., primary and / or backup computers of the vehicle 1200) fail. In at least one embodiment, the infotainment SoC 1230 may place the vehicle 1200 into a chauffeur-to-safe-stop mode, as described herein.

[0198] In at least one embodiment, the vehicle 1200 may further include an instrument cluster 1232 (e.g., a digital instrument cluster, an electronic instrument cluster, a digital instrument panel, etc.). In at least one embodiment, the instrument cluster 1232 may include, without limitation, a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, the instrument cluster 1232 may include, without limitation, any number and combination of instruments, such as, but not limited to, speedometer, fuel level, oil pressure, tachometer, odometer, turn signals, shift position indicator, seat belt warning light(s), parking brake warning light(s), engine malfunction light(s), supplemental restraint system information (e.g., airbags), lighting controls, safety system controls, navigation information, etc.In some examples, information may be displayed and / or shared between infotainment SoC 1230 and instrument cluster 1232. In at least one embodiment, instrument cluster 1232 may be included as part of infotainment SoC 1230, or vice versa.

[0199] In at least one embodiment, one or more Fig. 12C are used to simulate one or more neural networks with various algorithms, formulas and processes as used in conjunction with Fig. 1 and / or to otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 12C are used to implement one or more systems and / or processes as used in connection with Fig. 1-8, for example, to adjust a resolution of information used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein.

[0200] Fig. 12D is a diagram of a system for communication between the cloud-based server(s) and the autonomous vehicle 1200 of Fig. 12A, according to at least one embodiment. In at least one embodiment, the system may include, without limitation, server(s) 1278, network(s) 1290, and any number and type of vehicles, including vehicle 1200. In at least one embodiment, server(s) 1278 may include, without limitation, a plurality of GPUs 1284(A)-1284(H) (collectively referred to herein as GPUs 1284), PCIe switches 1282(A)-1282(D) (collectively referred to herein as PCIe switches 1282), and / or CPUs 1280(A)-1280(B) (collectively referred to herein as CPUs 1280). In at least one embodiment, the GPUs 1284, the CPUs 1280, and the PCIe switches 1282 may be interconnected with high-speed interconnects, such as, for example, and without limitation, the NVLink interfaces 1288 and / or PCIe interconnects 1286 developed by NVIDIA.In at least one embodiment, the GPUs 1284 are connected via an NVLink and / or NVSwitch SoC, and the GPUs 1284 and PCIe switches 1282 are connected via PCIe interconnects. Although eight GPUs 1284, two CPUs 1280, and four PCIe switches 1282 are shown, this is not intended to be limiting. In at least one embodiment, each of the servers 1278 may include, without limitation, any number of GPUs 1284, CPUs 1280, and / or PCIe switches 1282 in any combination. For example, in at least one embodiment, the server(s) 1278 could each include eight, sixteen, thirty-two, and / or more GPUs 1284.

[0201] In at least one embodiment, the server(s) 1278 may receive, via the network(s) 1290 and from the vehicles, image data representative of images depicting unexpected or changed road conditions, such as recently commenced road construction. In at least one embodiment, the server(s) 1278 may transmit, via the network(s) 1290 and to the vehicles, updated or other neural network 1292 and / or map information 1294 including, among other things, information about traffic and road conditions. In at least one embodiment, the updates to the map information 1294 may include, without limitation, updates to the HD map 1222, such as information about construction, potholes, detours, flooding, and / or other obstacles.In at least one embodiment, the neural networks 1292 and / or the map information 1294 may be a result of recent training and / or experience represented in data received from any number of vehicles in an environment and / or based at least in part on training performed in a data center (e.g., using server(s) 1278 and / or other servers).

[0202] In at least one embodiment, the server(s) 1278 may be used to train machine learning models (e.g., neural networks) based at least in part on training data. In at least one embodiment, the training data may be generated by vehicles and / or generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., if the associated neural network benefits from supervised learning) and / or subjected to other preprocessing. In at least one embodiment, any amount of training data is unlabeled and / or preprocessed (e.g., if the associated neural network does not require supervised learning).In at least one embodiment, machine learning models, once trained, may be used by vehicles (e.g., transmitted to vehicles via network(s) 1290), and / or machine learning models may be used by server(s) 1278 to remotely monitor vehicles.

[0203] In at least one embodiment, the server(s) 1278 may receive data from vehicles and apply data to real-time, real-time neural networks for intelligent inference. In at least one embodiment, the server(s) 1278 may include deep learning supercomputers and / or dedicated AI computers powered by GPU(s) 1284, such as DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, the server(s) 1278 may also include a deep learning infrastructure using CPU-powered data centers.

[0204] In at least one embodiment, the deep learning infrastructure of the server(s) 1278 may be capable of rapidly and in real-time inferring and leveraging this capability to assess and verify the health of processors, software, and / or associated hardware in the vehicle 1200. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 1200, such as a sequence of images and / or objects that the vehicle 1200 has located in that sequence of images (e.g., via computer vision and / or other machine object classification techniques).In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to the objects identified by the vehicle 1200, and if the results do not match and the deep learning infrastructure concludes that the AI in the vehicle 1200 is malfunctioning, then the server(s) 1278 may send a signal to the vehicle 1200 instructing a fail-safe computer of the vehicle 1200 to take over control, notify the passengers, and perform a safe parking maneuver.

[0205] In at least one embodiment, the server(s) 1278 may include GPU(s) 1284 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, a combination of GPU-based servers and inference accelerators may enable real-time responsiveness. In at least one embodiment, for example, when performance is less critical, servers with CPUs, FPGAs, and other processors may be used for inference derivation. In at least one embodiment, hardware structure(s) 915 are used to perform one or more embodiments. Details of the hardware structure(s) 915 are described herein in connection with Fig. 9A and / or 9B. COMPUTER SYSTEMS

[0206] Fig. 13 is a block diagram illustrating an exemplary computer system, which may be a system of interconnected devices and components, a system-on-a-chip (SOC), or a combination thereof, formed with a processor that may include execution units for executing an instruction, according to at least one embodiment. In at least one embodiment, a computer system 1300 may include, without limitation, a component such as a processor 1302 to employ execution units including logic for performing algorithms for processing data in accordance with the present disclosure, as in the embodiment described herein.In at least one embodiment, computer system 1300 may include processors such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including personal computers with other microprocessors, technical workstations, set-top boxes, and the like) may be used. In at least one embodiment, computer system 1300 may run a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical interfaces may also be used.

[0207] Embodiments may be used in other devices such as handheld devices and embedded applications. Some examples of portable devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system capable of executing one or more instructions according to at least one embodiment.

[0208] In at least one embodiment, computer system 1300 may include, without limitation, a processor 1302, which may include, without limitation, one or more execution units 1308 to perform machine learning model training and / or inferencing according to the techniques described herein. In at least one embodiment, computer system 1300 is a desktop or server system having a processor, but in another embodiment, computer system 1300 may be a multiprocessor system. In at least one embodiment, processor 1302 may include, without limitation, a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or any other device, such as a digital signal processor.In at least one embodiment, the processor 1302 may be connected to a processor bus 1310 that may transmit data signals between the processor 1302 and other components in the computer system 1300.

[0209] In at least one embodiment, processor 1302 may include, without limitation, an internal Level 1 ("L1") cache ("cache") 1304. In at least one embodiment, processor 1302 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache may be external to processor 1302. Other embodiments may also include a combination of internal and external caches, depending on the particular implementation and needs. In at least one embodiment, a register file 1306 may store different data types in various registers, including, without limitation, integer registers, floating-point registers, status registers, and an instruction pointer register.

[0210] In at least one embodiment, execution unit 1308, which includes, without limitation, logic for performing integer and floating-point operations, is also located in processor 1302. In at least one embodiment, processor 1302 may also include microcode read-only memory ("ROM") ("ucode") that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 1308 may include logic for handling a packed instruction set 1309. In at least one embodiment, by including a packed instruction set 1309 in an instruction set of a general-purpose processor, along with associated instruction execution circuitry, operations used by many multimedia applications may be performed using packed data in processor 1302.In at least one embodiment, many multimedia applications can be accelerated and executed more efficiently by utilizing the full width of a processor's data bus to perform operations on packed data, thereby eliminating the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0211] In at least one embodiment, execution unit 1308 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1300 may include, without limitation, a memory 1320. In at least one embodiment, memory 1320 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, or other storage device. In at least one embodiment, memory 1320 may store instruction(s) 1319 and / or data 1321 represented by data signals that may be executed by processor 1302.

[0212] In at least one embodiment, a system logic chip may be connected to the processor bus 1310 and the memory 1320. In at least one embodiment, a system logic chip may include, without limitation, a memory control hub ("MCH") 1316, and the processor 1302 may communicate with the MCH 1316 via the processor bus 1310. In at least one embodiment, the MCH 1316 may provide a high-bandwidth memory path 1318 to the memory 1320 for instruction and data storage, as well as for graphics command, data, and texture storage. In at least one embodiment, the MCH 1316 may route data signals between the processor 1302, the memory 1320, and other components in the computer system 1300, and may bridge data signals between the processor bus 1310, the memory 1320, and a system I / O interface 1322.In at least one embodiment, a system logic chip may provide a graphics port for connection to a graphics controller. In at least one embodiment, MCH 1316 may be coupled to memory 1320 via a high-bandwidth memory path 1318, and a graphics / video card 1312 may be coupled to MCH 1316 via an Accelerated Graphics Port ("AGP") interconnect 1314.

[0213] In at least one embodiment, computer system 1300 may use system I / O interface 1322 as a proprietary hub interface bus to connect MCH 1316 to an I / O control hub ("ICH") 1330. In at least one embodiment, ICH 1330 may provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, a local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 1320, a chipset, and processor 1302. Examples may include, without limitation, an audio controller 1329, a firmware hub (“Flash BIOS”) 1328, a wireless transceiver 1326, a data store 1324, a legacy I / O controller 1323 with user input and keyboard interfaces 1325, a serial expansion port 1327, such as a Universal Serial Bus (“USB”) interface, and a network controller 1334.In at least one embodiment, data storage 1324 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0214] In at least one embodiment, Fig. 13 a system comprising interconnected hardware devices or “chips”, while in other embodiments Fig. 13 may show an exemplary SoC. In at least one embodiment, the Fig. 13 may be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of computer system 1300 are interconnected using Compute Express Link (CXL) connections.

[0215] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details of logic 915 are described herein in connection with Fig. 9A and / or 9B. In at least one embodiment, logic 915 in computer system 1300 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0216] In at least one embodiment, one or more Fig. 13 systems shown are used to create one or more neural networks with different algorithms, formulas and processes as used in conjunction with Fig. 1 and / or to otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 13 depicted systems are used to implement one or more systems and / or processes as used in connection with Fig. 1-8, for example, to adjust a resolution of information used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein.

[0217] Fig. 14 is a block diagram illustrating an electronic device 1400 for using a processor 1410 according to at least one embodiment. In at least one embodiment, the electronic device 1400 may be, for example and without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0218] In at least one embodiment, the electronic device 1400 may include, without limitation, a processor 1410 communicatively connected to any number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1410 is coupled via a bus or interface, such as an I2C bus, a System Management Bus ("SMBus"), a Low Pin Count (LPC) bus, a Serial Peripheral Interface ("SPI"), a High Definition Audio (HDA) bus, a Serial Advance Technology Attachment (SATA) bus, a Universal Serial Bus ("USB") (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter (UART) bus. In at least one embodiment, Fig. 14 a system comprising interconnected hardware devices or “chips”, while in other embodiments Fig. 14 may show an exemplary SoC. In at least one embodiment, the Fig. 14 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of Fig. 14 interconnected using CXL (Compute Express Link) connections.

[0219] At least in one embodiment, Fig. 14 a display 1424, a touchscreen 1425, a touchpad 1430, a Near Field Communications unit (“NFC”) 1445, a sensor hub 1440, a thermal sensor 1446, an Express Chipset (“EC”) 1435, a Trusted Platform Module (“TPM”) 1438, BIOS / Firmware / Flash Memory (“BIOS, FW Flash”) 1422, a DSP 1460, a drive 1420 such as a Solid State Disk (“SSD”) or a Hard Drive (“HDD”), a Wireless Local Area Network unit (“WLAN”) 1450, a Bluetooth unit 1452, a Wireless Wide Area Network unit (“WWAN”) 1456, a Global Positioning System (GPS) unit 1455, a camera (“USB 3.0 Camera”) 1454, such as a USB 3.0 camera, and / or a Low Power Double Data Rate ("LPDDR") memory unit ("LPDDR3") 1415, implemented, for example, according to an LPDDR3 standard. These components may each be implemented in any suitable manner.

[0220] In at least one embodiment, other components may be communicatively coupled to the processor 1410 through components described herein. In at least one embodiment, an accelerometer 1441, an ambient light sensor ("ALS") 1442, a compass 1443, and a gyroscope 1444 may be communicatively coupled to the sensor hub 1440. In at least one embodiment, a thermal sensor 1439, a fan 1437, a keyboard 1436, and a touchpad 1430 may be communicatively coupled to the EC 1435. In at least one embodiment, speakers 1463, headphones 1464, and a microphone ("mic") 1465 may be communicatively coupled to an audio unit ("audio codec and class D amp") 1462, which in turn may be communicatively coupled to the DSP 1460. In at least one embodiment, the audio unit 1462 may include, for example and without limitation, an audio encoder / decoder ("codec") and a Class D amplifier.In at least one embodiment, a SIM card ("SIM") 1457 may be communicatively coupled to the WWAN unit 1456. In at least one embodiment, components such as the WLAN unit 1450 and the Bluetooth unit 1452, as well as the WWAN unit 1456, may be implemented in a Next Generation Form Factor ("NGFF").

[0221] Logic 915 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 915 are described herein in connection with Fig. 9A and / or 9B. In at least one embodiment, logic 915 in electronic device 1400 may be used for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0222] In at least one embodiment, one or more Fig. 14 systems shown are used to create one or more neural networks with different algorithms, formulas and processes as used in conjunction with Fig. 1 and / or to otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 14 systems shown are used to implement one or more systems and / or processes as used in connection with Fig. 1-8, for example, to adjust a resolution of information used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein.

[0223] Fig. 15 illustrates a computer system 1500 according to at least one embodiment. In at least one embodiment, the computer system 1500 is configured to implement various processes and methods described in this disclosure.

[0224] In at least one embodiment, computer system 1500 includes, without limitation, at least one central processing unit ("CPU") 1502 connected to a communications bus 1510 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or other bus or point-to-point communications protocol. In at least one embodiment, computer system 1500 includes, without limitation, main memory 1504 and control logic (e.g., in the form of hardware, software, or a combination thereof), and data is stored in main memory 1504, which may take the form of random access memory ("RAM").In at least one embodiment, a network interface subsystem (“network interface”) 1522 provides an interface to other computing devices and networks to receive and transmit data from and to other systems with the computing system 1500.

[0225] In at least one embodiment, computer system 1500 includes, without limitation, input devices 1508, a parallel processing system 1512, and display devices 1506, which may be implemented using a conventional cathode ray tube ("CRT"), a liquid crystal display ("LCD"), a light-emitting diode ("LED"), a plasma display, or other suitable display technology. In at least one embodiment, user input is provided via input devices 1508 such as a keyboard, mouse, touchpad, microphone, etc. In at least one embodiment, each module described herein may be packaged on a single semiconductor platform to form a processing system.

[0226] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details of inference and / or training logic 915 are described herein in connection with Fig. 9A and / or 9B. In at least one embodiment, logic 915 in computer system 1500 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0227] In at least one embodiment, one or more Fig. 15 systems shown are used to create one or more neural networks with different algorithms, formulas and processes as used in conjunction with Fig. 1 and / or to otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 15 systems shown are used to implement one or more systems and / or processes as used in connection with Fig. 1-8, for example, to adjust a resolution of information used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein.

[0228] Fig. 16 shows a computer system 1600 according to at least one embodiment. In at least one embodiment, the computer system 1600 includes, without limitation, a computer 1610 and a USB flash drive 1620. In at least one embodiment, the computer 1610 may include, without limitation, any number and type of processor(s) (not shown) and memory (not shown). In at least one embodiment, the computer 1610 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer.

[0229] In at least one embodiment, USB flash drive 1620 includes, without limitation, a processing unit 1630, a USB interface 1640, and USB interface logic 1650. In at least one embodiment, processing unit 1630 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1630 may include, without limitation, any number and type of compute cores (not shown). In at least one embodiment, processing unit 1630 includes an application-specific integrated circuit ("ASIC") optimized to perform any number and type of machine learning-related operations.For example, in at least one embodiment, processing unit 1630 is a tensor processing unit ("TPC") optimized for performing machine learning inference operations. In at least one embodiment, processing unit 1630 is a video processing unit ("VPU") optimized for performing video processing and machine learning operations.

[0230] In at least one embodiment, USB interface 1640 may be any type of USB plug or receptacle. For example, in at least one embodiment, USB interface 1640 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1640 is a USB 3.0 Type-A plug. In at least one embodiment, the logic of USB interface 1650 may include any amount and type of logic that enables processing unit 1630 to communicate with devices (e.g., computer 1610) via USB port 1640.

[0231] Logic 915 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 915 are described herein in connection with Fig. 9A and / or 9B. In at least one embodiment, logic 915 in computer system 1600 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0232] In at least one embodiment, one or more Fig. 16 systems shown are used to create one or more neural networks with different algorithms, formulas and processes as used in conjunction with Fig. 1 and / or to otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 16 depicted systems are used to implement one or more systems and / or processes as used in connection with Fig. 1-8, for example, to adjust a resolution of information used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein.

[0233] Fig. 17A illustrates an example architecture in which a plurality of GPUs 1710(1)-1710(N) are communicatively coupled to a plurality of multi-core processors 1705(1)-1705(M) via high-speed interconnects 1740(1)-1740(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, the high-speed interconnects 1740(1)-1740(N) support communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or greater. In at least one embodiment, various interconnect protocols may be used, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In various figures, "N" and "M" represent positive integers, the values of which may vary from figure to figure. In at least one embodiment, one or more GPUs in a plurality of GPUs 1710(1)-1710(N) includes one or more graphics cores (also referred to simply as “cores”) 2000, as shown in the Fig. 20A and Fig. 20B. In at least one embodiment, one or more graphics cores 2000 may be referred to as streaming multiprocessors ("SMs"), stream processors ("SPs"), stream processing units ("SPUs"), compute units ("CUs"), execution units ("EUs"), and / or slices, where a slice in this context may refer to a portion of processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread director, or scheduler).

[0234] Additionally, and in at least one embodiment, two or more GPUs 1710 are interconnected via high-speed interconnects 1729(1)-1729(2), which may be implemented using similar or different protocols / connections than those used for high-speed interconnects 1740(I)-1740(N). Similarly, two or more multi-core processors 1705 may be interconnected via a high-speed interconnect 1728, which may be symmetric multiprocessor (SMP) buses operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, all communication between the various Fig. 17A using similar protocols / connections (e.g., via a common connection structure).

[0235] In at least one embodiment, each multi-core processor 1705 is communicatively connected to a processor memory 1701(1)-1701(M) via memory interconnects 1726(1)-1726(M), and each GPU 1710(1)-1710(N) is communicatively connected to GPU memory 1720(1)-1720(N) via GPU memory interconnects 1750(1)-1750(N). In at least one embodiment, memory interconnects 1726 and 1750 may use similar or different memory access technologies. For example, the processor memories 1701(I)-1701(M) and the GPU memories 1720 may be volatile memories, such as dynamic random access memories (DRAMs) (including stacked DRAMs), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or they may be non-volatile memories, such as 3D XPoint or Nano-Ram.In at least one embodiment, a portion of processor memory 1701 may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory hierarchy (2LM)).

[0236] As described herein, various multi-core processors 1705 and GPUs 1710 may be physically connected to a particular memory 1701 or 1720, respectively, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as "effective address space") is distributed across different physical memories. For example, processor memories 1701(1)-1701(M) may each comprise 64 GB of system address space, and GPU memories 1720(1)-1720(N) may each comprise 32 GB of system address space, resulting in a total of 256 GB of addressable memory when M=2 and N=4. Other values for N and M are possible.

[0237] Fig. 17B shows additional details for an interconnect between a multi-core processor 1707 and a graphics acceleration module 1746 in accordance with an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1746 may include one or more GPU chips integrated on a line card connected to the processor 1707 via a high-speed interconnect 1740 (e.g., PCIe bus, NVLink, etc.). Alternatively, in at least one embodiment, the graphics acceleration module 1746 may be integrated on a package or die with the processor 1707.

[0238] In at least one embodiment, processor 1707 includes a plurality of cores 1760A-1760D (which may be referred to as "execution units"), each having a translation lookaside buffer ("TLB") 1761A-1761D and one or more caches 1762A-1762D. In at least one embodiment, cores 1760A-1760D may include various other components for executing instructions and processing data, not shown. In at least one embodiment, caches 1762A-1762D may include Level 1 (L1) and Level 2 (L2) caches. Additionally, one or more shared caches 1756 may be included in caches 1762A-1762D and shared by groups of cores 1760A-1760D. For example, one embodiment of processor 1707 includes 24 cores, each with its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches.In this embodiment, one or more L2 and L3 caches are shared between two adjacent cores. In at least one embodiment, processor 1707 and graphics acceleration module 1746 are coupled to system memory 1714, which includes processor memories 1701(1)-1701(M) of FIG. Fig. 17A may include.

[0239] In at least one embodiment, coherency for data and instructions stored in various caches 1762A-1762D, 1756, and system memory 1714 is maintained via inter-core communication over a coherency bus 1764. For example, in at least one embodiment, each cache may have cache coherency logic / circuitry associated with it to communicate over the coherency bus 1764 in response to detected reads or writes to specific cache lines. In at least one embodiment, a cache coherency protocol is implemented over the coherency bus 1764 to sniff out cache accesses.

[0240] In at least one embodiment, a proxy circuit 1725 communicatively couples the graphics acceleration module 1746 to the coherence bus 1764, allowing the graphics acceleration module 1746 to participate in a cache coherence protocol as a peer of the cores 1760A-1760D. Specifically, in at least one embodiment, an interface 1735 provides connectivity to the proxy circuit 1725 via the high-speed interconnect 1740, and an interface 1737 connects the graphics acceleration module 1746 to the high-speed interconnect 1740.

[0241] In at least one embodiment, an accelerator integration circuit 1736 provides cache management, memory access, context management, and interrupt management services for a plurality of graphics processing engines 1731(1)-1731(N) of the graphics acceleration module 1746. In at least one embodiment, the graphics processing engines 1731(1)-1731(N) may each comprise a separate graphics processing unit (GPU). In at least one embodiment, a plurality of graphics processing engines 1731(1)-1731(N) of the graphics acceleration module 1746 comprise one or more graphics cores 2000, as described in connection with the Fig. 20A and Fig. 20B. In at least one embodiment, the graphics processing engines 1731(1)-1731(N) may alternatively comprise different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1746 may be a GPU with a plurality of graphics processing engines 1731(1)-1731(N), or the graphics processing engines 1731(1)-1731(N) may be individual GPUs integrated on a common package, line card, or die.

[0242] In at least one embodiment, accelerator integration circuitry 1736 includes a memory management unit (MMU) 1739 for performing various memory management functions, such as virtual-to-physical memory translations (also referred to as effective-to-real memory translations) and memory access protocols for accessing system memory 1714. In at least one embodiment, MMU 1739 may also include a translation lookaside buffer (TLB) (not shown) to cache virtual / effective to physical / real address translations. In at least one embodiment, a cache 1738 may store instructions and data for efficient access by graphics processing engines 1731(1)-1731(N).In at least one embodiment, the data stored in cache 1738 and graphics memories 1733(1)-1733(M) is kept coherent with core caches 1762A-1762D, 1756, and system memory 1714, possibly using a fetch unit 1744. As noted, this may be done via proxy circuitry 1725 on behalf of cache 1738 and memories 1733(1)-1733(M) (e.g., sending updates to cache 1738 regarding changes / accesses to cache lines in processor caches 1762A-1762D, 1756 and receiving updates from cache 1738).

[0243] In at least one embodiment, a set of registers 1745 stores context data for threads executed by graphics processing engines 1731(1)-1731(N), and a context management circuit 1748 manages thread contexts. For example, context management circuit 1748 may perform save and restore operations to save and restore the contexts of various threads during context switches (e.g., when a first thread is saved and a second thread is saved to allow a second thread to be executed by a graphics processing engine). For example, upon a context switch, context management circuit 1748 may save the current register values to a specific region of memory (e.g., identified by a context pointer). The register values may then be restored upon return to a context.In at least one embodiment, an interrupt management circuit 1747 receives and processes interrupts received from system devices.

[0244] In at least one embodiment, virtual / effective addresses from a graphics processing engine 1731 are translated by the MMU 1739 into real / physical addresses in system memory 1714. In at least one embodiment, the accelerator integration circuit 1736 supports multiple (e.g., 4, 8, 16) graphics acceleration modules 1746 and / or other acceleration devices. In at least one embodiment, the graphics acceleration module 1746 may be dedicated to a single application executing on the processor 1707 or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is illustrated in which the resources of the graphics processing engines 1731(1)-1731(N) are shared among multiple applications or virtual machines (VMs).In at least one embodiment, the resources may be divided into slices that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0245] In at least one embodiment, accelerator integration circuitry 1736 acts as a bridge to a system for graphics acceleration module 1746 and provides address translation and system memory caching services. Furthermore, in at least one embodiment, accelerator integration circuitry 1736 may provide virtualization facilities to a host processor to manage the virtualization of graphics processing engines 1731(1)-1731(N), interrupts, and memory management.

[0246] Because, in at least one embodiment, the hardware resources of graphics processing engines 1731(1)-1731(N) are explicitly mapped to a real address space seen by host processor 1707, each host processor can directly address these resources via an effective address value. In at least one embodiment, a function of accelerator integration circuit 1736 is to physically separate graphics processing engines 1731(1)-1731(N) so that they appear to a system as independent entities.

[0247] In at least one embodiment, one or more graphics memories 1733(1)-1733(M) are coupled to each of the graphics processing engines 1731(1)-1731(N), where N=M. In at least one embodiment, the graphics memories 1733(1)-1733(M) store instructions and data processed by each of the graphics processing engines 1731(1)-1731(N). In at least one embodiment, the graphics memories 1733(1)-1733(M) may be volatile memories such as DRAMs (including stacked DRAMs), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or they may be non-volatile memories such as 3D XPoint or Nano-Ram.

[0248] In at least one embodiment, bias techniques may be used to reduce data traffic over high-speed interconnect 1740 to ensure that the data stored in graphics memories 1733(1)-1733(M) is data most frequently used by graphics processing engines 1731(1)-1731(N) and preferably not used (at least not frequently) by cores 1760A-1760D. Similarly, in at least one embodiment, a bias mechanism attempts to keep data needed by cores (and preferably not by graphics processing engines 1731(1)-1731(N)) in caches 1762A-1762D, 1756, and system memory 1714.

[0249] Fig. 17C shows another exemplary embodiment in which accelerator integration circuitry 1736 is integrated with processor 1707. In this embodiment, graphics processing engines 1731(1)-1731(N) communicate directly over high-speed interconnect 1740 with accelerator integration circuitry 1736 via interface 1737 and interface 1735 (which may again be any form of bus or interface protocol). In at least one embodiment, accelerator integration circuitry 1736 may perform operations similar to those described in Fig. 17B, but possibly with higher throughput due to its proximity to the coherence bus 1764 and caches 1762A-1762D, 1756. In at least one embodiment, an accelerator integration circuit supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and shared programming models (with virtualization), which may include programming models controlled by the accelerator integration circuit 1736 and programming models controlled by the graphics acceleration module 1746.

[0250] In at least one embodiment, graphics processing engines 1731(1)-1731(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can forward other application requests to graphics processing engines 1731(1)-1731(N), thereby enabling virtualization within a VM / partition.

[0251] In at least one embodiment, the graphics processing engines 1731(1)-1731(N) may be shared between multiple VM / application partitions. In at least one embodiment, shared models may use a system hypervisor to virtualize the graphics processing engines 1731(1)-1731(N) to allow access by any operating system. In at least one embodiment, for systems with a single partition without a hypervisor, the graphics processing engines 1731(1)-1731(N) are owned by an operating system. In at least one embodiment, an operating system may virtualize the graphics processing engines 1731(1)-1731(N) to allow access to any process or application.

[0252] In at least one embodiment, the graphics acceleration module 1746 or an individual graphics processing engine 1731(1)-1731(N) selects a process element using a process handle. In at least one embodiment, process elements are stored in system memory 1714 and are addressable using an effective address to real address translation technique described herein. In at least one embodiment, a process handle may be an implementation-specific value provided to a host process when it registers its context with the graphics processing engine 1731(1)-1731(N) (i.e., when it calls system software to add a process element to a linked process element list). In at least one embodiment, the lower 16 bits of a process handle may be an offset of a process element within a process element list.

[0253] Fig. 17D shows an exemplary accelerator integration slice 1790. In at least one embodiment, a "slice" comprises a particular portion of the processing resources of accelerator integration circuitry 1736. In at least one embodiment, an application stores process elements 1783 in an effective address space 1782 within system memory 1714. In at least one embodiment, process elements 1783 are stored in response to GPU calls 1781 from applications 1780 executing on processor 1707. In at least one embodiment, a process element 1783 contains the state of the corresponding application 1780. In at least one embodiment, a work description (WD) 1784 contained in process element 1783 may be a single job requested by an application or may contain a pointer to a queue of jobs.In at least one embodiment, the WD 1784 is a pointer to a job request queue in the effective address space 1782 of an application.

[0254] In at least one embodiment, the graphics acceleration module 1746 and / or individual graphics processing engines 1731(1)-1731(N) may be shared by all or a subset of the processes in a system. In at least one embodiment, an infrastructure for establishing process states and sending a WD 1784 to a graphics acceleration module 1746 to start a job in a virtualized environment may be included.

[0255] In at least one embodiment, a dedicated process programming model is implementation-specific. In at least one embodiment, in this model, a single process owns a graphics acceleration module 1746 or an individual graphics processing engine 1731. In at least one embodiment, when the graphics acceleration module 1746 is owned by a single process, a hypervisor initializes the accelerator integration circuit 1736 for an owning partition, and an operating system initializes the accelerator integration circuit 1736 for an owning process when the graphics acceleration module 1746 is allocated.

[0256] In at least one embodiment, a WD fetch unit 1791 in accelerator integration slice 1790 operatively fetches the next WD 1784, which includes an indication of the work to be performed by one or more graphics processing engines of graphics acceleration module 1746. In at least one embodiment, the data from WD 1784 may be stored in registers 1745 and used by MMU 1739, interrupt management circuitry 1747, and / or context management circuitry 1748, as shown. For example, one embodiment of MMU 1739 includes segment / page walkup circuitry for accessing segment / page tables 1786 within an OS virtual address space 1785. In at least one embodiment, circuitry 1747 may process interrupt events 1792 received from graphics acceleration module 1746.In at least one embodiment, when performing graphics operations, an effective address 1793 generated by a graphics processing engine 1731(1)-1731(N) is translated into a real address by the MMU 1739.

[0257] In at least one embodiment, registers 1745 are duplicated for each graphics processing engine 1731(11-1731(N)) and / or each graphics acceleration module 1746 and may be initialized by a hypervisor or an operating system. In at least one embodiment, each of these duplicated registers may be included in an accelerator integration slice 1790. Example registers that may be initialized by a hypervisor are shown in Table 1. Table 1 - Initialized hypervisor registers Register # Beschreibung 1 Slice-Steuerregister (Slice-Steuerregister) 2 Reale Adresse (RA) Zeiger für den Bereich „Geplante Prozesse 3 Autoritätsmasken-Überschreibungsregister 4 Interrupt vector table entry offset 5 Interrupt vector table entry boundary 6 Condition register 7 Logical partition ID 8 Real Address (RA) Hypervisor Accelerator Workload Set Pointer 9 Memory description register

[0258] Example registers that can be initialized by an operating system are listed in Table 2. Table 2 - Initialized operating system registers Register # Description 1 Process and thread identification 2 Effective Address (EA) Context Store / Restore Pointer 3 Virtual address (VAI accelerator workload set pointer) 4 Virtual address (pointer to VAI memory segment table) 5 Authority mask 6 Job description

[0259] In at least one embodiment, each WD 1784 is specific to a particular graphics acceleration module 1746 and / or graphics processing engines 1731(1)-1731(N). In at least one embodiment, it contains all the information needed by a graphics processing engine 1731(1)-1731(N) to perform work, or it may be a pointer to a memory location where an application has established a command queue of work to be performed.

[0260] Fig.17E shows additional details for an exemplary embodiment of a joint model. This embodiment includes a real hypervisor address space 1798 in which a process element list 1799 is stored. In at least one embodiment, the real hypervisor address space 1798 is accessible via a hypervisor 1796 that virtualizes graphics acceleration engine engines for the operating system 1795.

[0261] In at least one embodiment, shared programming models allow all or a subset of processes from all or a subset of partitions in a system to use a graphics acceleration module 1746. In at least one embodiment, there are two programming models in which the graphics acceleration module 1746 is shared among multiple processes and partitions: time-slice sharing and graphics sharing.

[0262] In at least one embodiment, in this model, the system hypervisor 1796 has the graphics acceleration module 1746 and makes its functionality available to all operating systems 1795. In at least one embodiment, a graphics acceleration module 1746 may meet certain requirements to support virtualization by the system hypervisor 1796, such as (1) the job request of an application must be autonomous (i.e.the state does not need to be maintained between jobs), or the graphics acceleration module 1746 must provide a mechanism for saving and restoring the context, (2) the graphics acceleration module 1746 guarantees that an application's job request will be completed in a specified amount of time, including any translation errors, or the graphics acceleration module 1746 provides the ability to preempt the processing of a job, and (3) the graphics acceleration module 1746 must be guaranteed fairness between processes when operating in a directed joint programming model.

[0263] In at least one embodiment, application 1780 must execute an operating system 1795 system call with a graphics acceleration module type, a work description (WD), an authority mask register (AMR) value, and a context save / restore pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes a targeted acceleration function for a system call. In at least one embodiment, the graphics acceleration module type may be a system-specific value. In at least one embodiment, WD is formatted specifically for graphics acceleration module 1746 and may be in the form of a graphics acceleration module 1746 instruction, a pointer to the effective address of a user-defined structure, a pointer to the effective address of an instruction queue, or another data structure describing the work to be performed by graphics acceleration module 1746.

[0264] In at least one embodiment, an AMR value is an AMR state to be used for a current process. In at least one embodiment, a value passed to an operating system is comparable to an application setting an AMR. In at least one embodiment, if accelerator integration circuitry 1736 (not shown) and graphics acceleration module 1746 do not support an authority mask override register (UAMOR), an operating system may apply a current UAMOR value to an AMR value before passing an AMR in a hypervisor call. In at least one embodiment, hypervisor 1796 may optionally apply a current authority mask override register (AMOR) value before placing an AMR in process element 1783.In at least one embodiment, CSRP is one of the registers 1745 that contain an effective address of a region in an application's effective address space 1782 for the graphics acceleration module 1746 to save and restore state. In at least one embodiment, this pointer is optional if no state needs to be saved between jobs or if a job aborts prematurely. In at least one embodiment, the context save / restore region may be embedded in system memory.

[0265] Upon receiving a system call, the operating system 1795 may verify whether the application 1780 has and has been granted permission to use the graphics acceleration module 1746. In at least one embodiment, the operating system 1795 then invokes the hypervisor 1796 with the information shown in Table 3. Table 3 - Parameters for calling the operating system to the hypervisor Parameters # Description 1 A job description (WD) 2 An Authority Mask Register (AMR) value (potentially masked) 3 An effective address (EA) Context save / restore pointer (CSRP) 4 A process ID (PIP) and optionally a thread ID (TIP) 5 A virtual address (VA) accelerator utilization set pointer (AURP) 6 Virtual address of the pointer to the memory segment table (SSTP) 7 A logical interrupt service number (LISN)

[0266] In at least one embodiment, upon receiving a hypervisor call, hypervisor 1796 checks whether operating system 1795 has and has been granted permission to use graphics acceleration module 1746. In at least one embodiment, hypervisor 1796 then places process element 1783 in a process element list for a corresponding type of graphics acceleration module 1746. In at least one embodiment, a process element may include the information shown in Table 4. Table 4 - Process element information Item # Description 1 A job description (WP) 2 An Authority Mask Register (AMR) value (possibly masked). 3 An effective address (EA) Context save / restore pointer (CSRP) 4 A process ID (PIP) and optionally a thread ID (TIP) 5 A virtual address (VA) accelerator utilization set pointer (AURP) 6 Virtual address of the pointer to the memory segment table (SSTP) 7 A logical interrupt service number (LISN) 8 Interrupt vector table derived from hypervisor call parameters 9 A status register value (SR) 10 A logical partition IP (LPIP) 11 A pointer to the hypervisor's accelerator utilization set with real address (RA) 12 Memory Rescriptor Register (SPR)

[0267] In at least one embodiment, the hypervisor initializes a plurality of accelerator integration slice 1790 registers 1745.

[0268] As in Fig.17F, in at least one embodiment, a unified memory addressable via a common virtual memory address space is used to access physical processor memories 1701(1)-1701(N) and GPU memories 1720(1)-1720(N). In this implementation, operations executing on GPUs 1710(1)-1710(N) use the same virtual / effective address space to access processor memories 1701(1)-1701(M) and vice versa, simplifying programmability. In at least one embodiment, a first portion of a virtual / effective address space is assigned to processor memory 1701(1), a second portion is assigned to second processor memory 1701(N), a third portion is assigned to GPU memory 1720(1), and so on.In at least one embodiment, this distributes an entire virtual / effective memory space (sometimes referred to as effective address space) across each of the processor memories 1701 and GPU memories 1720, such that each processor or GPU can access each physical memory with a virtual address associated with that memory.

[0269] In at least one embodiment, bias / coherence management circuitry 1794A-1794E within one or more MMUs 1739A-1739E ensures cache coherence between the caches of one or more host processors (e.g., 1705) and GPUs 1710 and implements bias techniques that indicate in which physical memories certain data types should be stored. In at least one embodiment, while multiple instances of bias / coherence management circuitry 1794A-1794E in Fig.17F, bias / coherence circuits may be implemented within an MMU of one or more host processors 1705 and / or within the accelerator integration circuit 1736.

[0270] In one embodiment, GPU memories 1720 may be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without the performance penalty associated with full system cache coherence. In at least one embodiment, the ability to access GPU memories 1720 as system memory without burdensome cache coherence overhead provides a favorable operating environment for GPU offload. In at least one embodiment, this arrangement allows host processor 1705 software to set operands and access computation results without the overhead of traditional I / O DMA data copies. In at least one embodiment, such traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient compared to simple memory accesses.In at least one embodiment, the ability to access GPU memory 1720 without cache coherence overheads may be critical to the execution time of an offloaded computation. For example, in at least one embodiment, cache coherence overhead may significantly reduce the effective write bandwidth of a GPU 1710 in cases with significant streaming write memory traffic. In at least one embodiment, operand construction efficiency, result access efficiency, and GPU computation efficiency may play a role in determining the effectiveness of a GPU offload.

[0271] In at least one embodiment, the selection of the GPU bias and the host processor bias is controlled by a bias tracker data structure. For example, in at least one embodiment, a bias table may be used, which may be a page-granular structure (e.g., controlled at the granularity of a memory page) comprising 1 or 2 bits per GPU-attached memory page. In at least one embodiment, a bias table may be implemented in a stolen memory region of one or more GPU memories 1720, with or without a bias cache in a GPU 1710 (e.g., to cache frequently / recently used entries of a bias table). Alternatively, in at least one embodiment, an entire bias table may be maintained in a GPU.

[0272] In at least one embodiment, prior to the actual access to GPU memory, a bias table entry associated with each access to GPU memory 1720 is accessed, triggering the following operations. In at least one embodiment, local requests from a GPU 1710 that find their page in GPU-biased are forwarded directly to a corresponding GPU memory 1720. In at least one embodiment, local requests from a GPU that find its page in the host's bias are forwarded to processor 1705 (e.g., over a high-speed connection as described herein). In at least one embodiment, a request from processor 1705 that finds a requested page in the host processor's bias is completed like a normal memory read. Alternatively, requests directed to a GPU-biased page may be forwarded to GPU 1710.In at least one embodiment, a GPU may forward a page to a host processor bias when it is not currently using the page. In at least one embodiment, the bias state of a page may be changed either by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited number of cases, by a purely hardware-based mechanism.

[0273] In at least one embodiment, a mechanism for changing bias state uses an API call (e.g., OpenCL), which in turn calls a graphics processor's device driver, which in turn sends a message (or command descriptor) to a graphics processor instructing it to change a bias state and, on some transitions, perform a cache flush operation in a host. In at least one embodiment, a cache flush operation is used for a transition from the host processor 1705 bias to the GPU bias, but not for an opposite transition.

[0274] In at least one embodiment, cache coherence is maintained by temporarily making GPU-biased pages uncacheable by the host processor 1705. In at least one embodiment, to access these pages, the processor 1705 may request access from the GPU 1710, which may or may not grant access immediately. Therefore, in at least one embodiment, to reduce communication between the processor 1705 and the GPU 1710, it is advantageous to ensure that GPU-biased pages are those required by a GPU but not by the host processor 1705, and vice versa.

[0275] Hardware structure(s) 915 are used to perform one or more embodiments. Details of a hardware structure (or more hardware structures) 915 may be described herein in connection with Fig. 9A and / or 9B must be specified.

[0276] Fig.Figure 18 illustrates exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores according to various embodiments described herein. In addition to the illustrated embodiments, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0277] Fig.18 is a block diagram illustrating an exemplary system-on-chip integrated circuit 1800 that may be fabricated using one or more IP cores, in accordance with at least one embodiment. In at least one embodiment, the integrated circuit 1800 includes one or more application processors 1805 (e.g., CPUs), at least one graphics processor 1810, and may additionally include an image processor 1815 and / or a video processor 1820, each of which may be a modular IP core. In at least one embodiment, the integrated circuit 1800 includes peripheral or bus logic, including a USB controller 1825, a UART controller 1830, an SPI / SDIO controller 1835, and a P2S / F2C controller 1840.In at least one embodiment, integrated circuit 1800 may include a display device 1845 coupled to one or more of the following interfaces: a High Definition Multimedia Interface (HDMI) controller 1850 and a Mobile Industry Processor Interface (MIPI) display interface 1855. In at least one embodiment, memory may be provided by a flash memory subsystem 1860 comprising flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1865 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1870.

[0278] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details of logic 915 are described herein in connection with Fig. 9A and / or 9B. In at least one embodiment, logic 915 in integrated circuit 1800 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or the neural network use cases described herein.

[0279] In at least one embodiment, one or more Fig. 18 systems shown are used to create one or more neural networks with different algorithms, formulas and processes as used in conjunction with Fig.1 and / or to otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 18 depicted systems are used to implement one or more systems and / or processes as used in connection with Fig. 1-8, for example, to adjust a resolution of information used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein.

[0280] Fig.19A-19B illustrate exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores according to various embodiments described herein. In addition to the illustrated embodiments, other logic and circuitry may also be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0281] Fig. 19A-19B are block diagrams illustrating example graphics processors for use in an SoC according to the embodiments described herein. Fig. 19A shows an exemplary system-on-chip integrated circuit graphics processor 1910 that may be manufactured using one or more IP cores, in accordance with at least one embodiment. Fig.19B shows another exemplary graphics processor 1940 of an integrated circuit for a system on a chip that can be manufactured with one or more IP cores in accordance with at least one embodiment. In at least one embodiment, the graphics processor 1910 is Fig. 19A, a low-power graphics processor core. In at least one embodiment, the graphics processor 1940 is Fig. 19B, a higher performance graphics processor core. In at least one embodiment, each of the graphics processors 1910, 1940 may be a variant of the graphics processor 1810 of Fig. be 18.

[0282] In at least one embodiment, graphics processor 1910 includes a vertex processor 1905 and one or more fragment processors 1915A-1915N (e.g., 1915A, 1915B, 1915C, 1915D, 1915N-1, and 1915N). In at least one embodiment, graphics processor 1910 may execute different shader programs via separate logic, such that vertex processor 1905 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1915A-1915N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1905 executes a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data.In at least one embodiment, the fragment processor(s) 1915A-1915N use the primitive and vertex data generated by the vertex processor 1905 to generate a framebuffer displayed on a display device. In at least one embodiment, the fragment processor(s) 1915A-1915N are optimized for executing fragment shader programs as provided in an OpenGL API, which can be used to perform similar operations as a pixel shader program as provided in a Direct 3D API.

[0283] In at least one embodiment, graphics processor 1910 additionally includes one or more memory management units (MMUs) 1920A-1920B, cache(s) 1925A-1925B, and circuit interconnect(s) 1930A-1930B. In at least one embodiment, one or more MMU(s) 1920A-1920B provide virtual to physical address mapping for graphics processor 1910, including vertex processor 1905 and / or fragment processor(s) 1915A-1915N, which may reference vertex or image / texture data stored in memory in addition to the vertex or image / texture data stored in one or more cache(s) 1925A-1925B. In at least one embodiment, one or more MMU(s) 1920A-1920B may be synchronized with other MMUs within a system, including one or more MMUs associated with one or more application processor(s) 1805, image processor(s) 1815, and / or video processor(s) 1820 of Fig.18, so that each processor 1805-1820 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1930A-1930B enable the graphics processor 1910 to interface with other IP cores within the SoC, either via an internal bus of the SoC or via a direct connection.

[0284] In at least one embodiment, the graphics processor 1940 includes one or more shader cores 1955A-1955N (e.g., 1955A, 1955B, 1955C, 1955D, 1955E, 1955F, through 1955N-1 and 1955N), as shown in Fig.19B, which provides a unified shader core architecture in which a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1940 includes an inter-core task manager 1945 acting as a thread dispatcher to distribute execution threads to one or more shader cores 1955A-1955N, and a tiling unit 1958 to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are divided in image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0285] Logic 915 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 915 are described herein in connection with Fig. 9A and / or 9B. In at least one embodiment, logic 915 in graphics processor 1910 and / or 1940 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0286] In at least one embodiment, one or more Fig. 19A and B are used to implement one or more neural networks with various algorithms, formulas and processes as used in conjunction with Fig.1 and / or to otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 19A and B are used to implement one or more systems and / or processes as used in connection with Fig. 1-8, for example, to adjust a resolution of information used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein.

[0287] Fig. 20A-20B illustrate additional exemplary graphics processor logic according to the embodiments described herein. In at least one embodiment, the Fig.20A-20B are integrated into a single system, such as a graphics processing unit (GPU), an SoC, or other type of processor. Fig. 20A shows a graphics core 2000 that, in at least one embodiment, includes the graphics processor 1810 of Fig. 18 and a unified shader core 1955A-1955N as in Fig.19B. FIG. 20B shows a highly parallel general-purpose graphics processing unit ("GPGPU", which may also be referred to as a "graphics processing unit") 2030 suitable for deployment on a multi-chip module. In at least one embodiment, the graphics processing unit 2030 is a GPGPU that includes a graphics processor. In at least one embodiment, the integrated circuit 1800 includes the graphics core 2000, for example, to form an integrated circuit and / or an SoC, such an integrated circuit and / or SoC performing the operations described herein.

[0288] In at least one embodiment, the graphics core 2000 includes a shared instruction cache 2002, a texture unit 2018, and a cache / shared memory 2020 (e.g., including L1, L2, L3, last-level cache, or other caches) common to the execution resources within the graphics core 2000. In at least one embodiment, the graphics core 2000 may include multiple slices 2001A-2001N or a partition for each core, and a graphics processor may include multiple instances of the graphics core 2000. In at least one embodiment, each slice 2001A-2001N refers to the graphics core 2000. In at least one embodiment, the slices 2001A-2001N include sub-slices that are part of a slice 2001A-2001N. In at least one embodiment, slices 2001A-2001N are independent of other slices or dependent on other slices.In at least one embodiment, slices 2001A-2001N may include support logic including a local instruction cache 2004A-2004N, a thread scheduler (sequencer) 2006A-2006N, a thread dispatcher 2008A-2008N, and a set of registers 2010A-2010N. In at least one embodiment, slices 2001A-2001N may include a set of additional functional units (AFUs 2012A-2012N), floating-point units (FPUs 2014A-2014N), integer arithmetic logic units (ALUs 2016A-2016N), address calculation units (ACUs 2013A-2013N), double-precision floating-point units (DPFPUs 2015A-2015N), and matrix processing units (MPUs 2017A-2017N). In at least one embodiment, MPUs 2017A-2017N are referred to as matrix engines.

[0289] In at least one embodiment, each slice 2001A-2001N includes one or more engines for floating-point and integer vector operations and one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large datasets. In at least one embodiment, one or more slices 2001A-2001N include one or more vector engines for computing a vector (e.g., computing mathematical operations on vectors). In at least one embodiment, a vector engine can compute a vector operation in 16-bit floating point (also referred to as "FP16"), 32-bit floating point (also referred to as "FP32"), or 64-bit floating point (also referred to as "FP64").In at least one embodiment, one or more slices 2001A-2001N comprise 16 vector engines paired with 16 matrix math units to compute matrix / tensor operations, where the vector engines and math units are accessible via matrix extensions. In at least one embodiment, a slice comprises a particular portion of a processor's processing resources, for example, 16 cores and a ray tracing unit, or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units for a processor. In at least one embodiment, the graphics core 2000 comprises one or more matrix engines for computing matrix operations, for example, in computing tensor operations.

[0290] In at least one embodiment, one or more slices 2001A-2001N include one or more ray tracing units for computing ray tracing operations (e.g., 16 ray tracing units per slice 2001A-2001N). In at least one embodiment, a ray tracing unit computes ray crossings, triangle intersections, bounding box intersections, or other ray tracing operations.

[0291] In at least one embodiment, one or more slice(s) 2001A-2001N comprise a media slice that encodes, decodes, and / or transcodes data, scales and / or formats data, and / or performs video quality operations on video data.

[0292] In at least one embodiment, one or more slices 2001A-2001N are connected to L2 cache and memory fabric, interconnect ports, HBM stacks (e.g., HBM2e, HDM3), and a media engine. In at least one embodiment, one or more slices 2001A-2001N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 2001A-2001N include one or more L1 caches. In at least one embodiment, one or more slices 2001A-2001N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing data, e.g.,B, corresponding instructions; one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometries for performing operations in geometry pipelines and / or for applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector graphics format (e.g., shape) and converting it into a raster image (e.g., a series of pixels, points, or lines that, when displayed, combine to form an image represented by shapes); one or more hierarchical depth buffers (Hiz) for buffering data; and / or one or more pixel backends. In at least one embodiment, a slice 2001A-2001N includes a memory structure, such as an L2 cache.

[0293] In at least one embodiment, the FPUs 2014A-2014N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 2015A-2015N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 2016A-2016N can perform variable-precision integer operations at 8-bit, 16-bit, and 32-bit precision and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 2017A-2017N can also be configured for mixed-precision matrix operations, including half-precision floating-point and 8-bit integer operations. In at least one embodiment, the MPUs 2017-2017N may perform a variety of matrix operations to accelerate machine learning frameworks, including support for accelerated general matrix-matrix multiplication (GEMM).In at least one embodiment, the AFUs 2012A-2012N may perform additional logical operations not supported by floating point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0294] Logic 915 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 915 are described herein in connection with Fig. 9A and / or 9B. In at least one embodiment, logic 915 in graphics core 2000 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0295] In at least one embodiment, the graphics core 2000 includes an interconnect and a link fabric sublayer connected to a switch and a GPU-to-GPU bridge that enables multiple graphics processors 2000 (e.g., 8) to be interconnected without gluing load / store units (LSUs), data transfer units, and synchronization semantics across multiple graphics processors 2000. In at least one embodiment, the interconnects include standardized interconnects (e.g., PCIe) or a combination thereof.

[0296] In at least one embodiment, the graphics core 2000 includes multiple tiles. In at least one embodiment, a tile is a single die or one or more dies, where individual dies may be connected with an interconnect (e.g., Embedded Multi-Die Interconnect Bridge (EMIB)). In at least one embodiment, the graphics core 2000 includes a compute tile, a memory tile (e.g., where a memory tile may be exclusively accessed by different tiles or different chipsets, such as a Rambo tile), a substrate tile, a base tile, an HMB tile, a link tile, and an EMIB tile, all of which tiles are packaged together in the graphics core 2000 as part of a GPU. In at least one embodiment, the graphics core 2000 may include multiple tiles in a single package (also referred to as a "multi-tile package").In at least one embodiment, a compute tile may include 8 graphics cores 2000, an L1 cache, and a base tile; a host interface with PCIe 5.0, HBM2e, MDFI, and EMIB; and a link tile with 8 links, 8 ports, and an embedded switch. In at least one embodiment, the tiles are connected using face-to-face (F2F) chip-on-chip bonding via finely pitched 36-micrometer microbumps (e.g., copper pillars). In at least one embodiment, the graphics core 2000 includes a memory structure that includes memory and is a tile accessible by multiple tiles. In at least one embodiment, the graphics core 2000 stores, accesses, or loads its own hardware contexts in memory. A hardware context is a set of data loaded from registers before a process continues, and a hardware context may indicate a state of the hardware (e.g., the state of a GPU).

[0297] In at least one embodiment, the graphics core 2000 includes a serialization / deserialization circuit (SERDES) that converts a serial data stream to a parallel data stream or converts a parallel data stream to a serial data stream.

[0298] In at least one embodiment, the graphics core 2000 includes a coherent high-speed unified fabric (GPU to GPU), load / store units, bulk data transfer and sync semantics, and GPUs connected via an embedded switch, with a GPU-GPU bridge controlled by a controller.

[0299] In at least one embodiment, the graphics core 2000 executes an API, where the API abstracts the hardware of the graphics core 2000 and accesses libraries of instructions for performing mathematical operations (e.g., math kernel library), deep neural network operations (e.g., deep neural network library), vector operations, collective communication, threading building blocks, video processing, data analysis library, and / or ray tracing operations.

[0300] In at least one embodiment, one or more Fig. 19B are used to simulate one or more neural networks with various algorithms, formulas and processes as used in conjunction with Fig. 1 and / or to otherwise perform operations described herein. In at least one embodiment, one or more of the Fig.19B are used to implement one or more systems and / or processes as used in connection with Fig. 1-8, for example, to adjust a resolution of information used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein.

[0301] Fig.Figure 20B shows GPGPU 2030, which can be configured to enable highly parallel computational operations performed by an array of graphics processing units. In at least one embodiment, GPGPU 2030 can be directly connected to other instances of GPGPU 2030 to create a multi-GPU cluster to improve training speed for deep neural networks. In at least one embodiment, GPGPU 2030 includes a host interface 2032 to enable connection to a host processor. In at least one embodiment, host interface 2032 is a PCI Express interface. In at least one embodiment, host interface 2032 can be a vendor-specific communication interface or communication fabric.In at least one embodiment, GPGPU 2030 receives instructions from a host processor and uses a global scheduler 2034 (which may be referred to as a thread sequencer and / or asynchronous compute engine) to distribute the execution threads associated with those instructions among a number of compute clusters 2036A-2036H. In at least one embodiment, compute clusters 2036A-2036H share a cache 2038. In at least one embodiment, cache 2038 may serve as a parent-level cache for caches in compute clusters 2036A-2036H. In at least one embodiment, compute clusters 2036A-2036H comprise a slice or are referred to as "slices." In at least one embodiment, the GPGPU 2030 is part of a SoC, such as part of the integrated circuit 1800 (FIG.

[0302] In at least one embodiment, GPGPU 2030 includes memory 2044A-2044B coupled to compute clusters 2036A-2036H via a set of memory controllers 2042A-2042B (e.g., one or more controllers for HBM2e). In at least one embodiment, memory 2044A-2044B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate memory (GDDR).

[0303] In at least one embodiment, the compute clusters 2036A-2036H each comprise a set of graphics cores, such as the graphics core 2000 of Fig.20A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with a range of precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of floating-point units in each of compute clusters 2036A-2036H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of floating-point units may be configured to perform 64-bit floating-point operations.

[0304] In at least one embodiment, multiple instances of GPGPU 2030 can be configured to operate as a compute cluster. In at least one embodiment, the communication used by compute clusters 2036A-2036H for synchronization and data exchange varies between embodiments. In at least one embodiment, multiple instances of GPGPU 2030 communicate via host interface 2032. In at least one embodiment, GPGPU 2030 includes an I / O hub 2039 that couples GPGPU 2030 to a GPU interconnect 2040 that enables direct connection to other instances of GPGPU 2030. In at least one embodiment, GPU interconnect 2040 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 2030.In at least one embodiment, GPU interconnect 2040 is coupled to a high-speed interconnect for sending and receiving data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2030 are located in separate computing systems and communicate via a network interface accessible via host interface 2032. In at least one embodiment, GPU interconnect 2040 may be configured to enable connection to a processor in addition to or as an alternative to host interface 2032.

[0305] In at least one embodiment, the GPGPU 2030 may be configured to train neural networks. In at least one embodiment, the GPGPU 2030 may be used within an inference platform. In at least one embodiment where the GPGPU 2030 is used for inference, the GPGPU 2030 may include fewer compute clusters 2036A-2036H than when the GPGPU 2030 is used for training a neural network. In at least one embodiment, the memory technology associated with the memory 2044A-2044B may differ between inference and training configurations, with higher bandwidth memory technologies being allocated to the training configurations. In at least one embodiment, an inference configuration of the GPGPU 2030 may support the inference of specific instructions.For example, in at least one embodiment, an inference configuration may provide support for one or more 8-bit integer dot product instructions that may be used during inference operations for deployed neural networks.

[0306] Logic 915 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 915 are described herein in connection with Fig. 9A and / or 9B. In at least one embodiment, logic 915 in GPGPU 2030 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0307] In at least one embodiment, one or more Fig. 20 systems shown are used to create one or more neural networks with different algorithms, formulas and processes as used in conjunction with Fig. 1 and / or to otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 20 systems shown are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-8, for example, to adjust a resolution of information used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein.

[0308] Fig.21 is a block diagram illustrating a computer system 2100 according to at least one embodiment. In at least one embodiment, the computer system 2100 includes a processing subsystem 2101 having one or more processors 2102 and a system memory 2104 communicating via an interconnect path that may include a memory hub 2105. In at least one embodiment, the memory hub 2105 may be a separate component within a chipset component or integrated with one or more processors 2102. In at least one embodiment, the memory hub 2105 is coupled to an I / O subsystem 2111 via a communication link 2106. In at least one embodiment, the I / O subsystem 2111 includes an I / O hub 2107, which may enable the computer system 2100 to receive input from one or more input devices 2108.In at least one embodiment, the I / O hub 2107 may enable a display controller, which may be included in one or more processors 2102, to provide outputs to one or more display devices 2110A. In at least one embodiment, one or more display devices 2110A coupled to the I / O hub 2107 may comprise a local, internal, or embedded display device.

[0309] In at least one embodiment, the processing subsystem 2101 includes one or more parallel processors 2112 connected to the storage hub 2105 via a bus or other communication link 2113. In at least one embodiment, the communication link 2113 may use any number of standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or communication structure. In at least one embodiment, one or more parallel processors 2112 form a compute-centric parallel or vector processing system, which may include a large number of compute cores and / or processing clusters, such as a Many Integrated Core (MIC) processor.In at least one embodiment, some or all of the parallel processors 2112 form a graphics processing subsystem that can output pixels to one or more display devices 2110A coupled via the I / O hub 2107. In at least one embodiment, the parallel processor(s) 2112 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 2110B. In at least one embodiment, the parallel processor(s) 2112 include one or more cores, such as the graphics cores 2000 discussed herein.

[0310] In at least one embodiment, a system storage unit 2114 may be coupled to the I / O hub 2107 to provide a storage mechanism for the computer system 2100. In at least one embodiment, an I / O switch 2116 may be used to provide an interface enabling connections between the I / O hub 2107 and other components, such as a network adapter 2118 and / or a wireless network adapter 2119 that may be integrated into the platform, and various other devices that may be added via one or more add-in devices 2120. In at least one embodiment, the network adapter 2118 may be an Ethernet adapter or other wired network adapter.In at least one embodiment, the wireless network adapter 2119 may include one or more of the following devices: Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices that include one or more wireless radios.

[0311] In at least one embodiment, computer system 2100 may include other components not explicitly shown, including USB or other connectors, optical storage devices, video capture devices, and the like, which may also be connected to I / O hub 2107. In at least one embodiment, communication paths connecting various components in Fig.21 interconnection may be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect)-based protocols (e.g., PCI Express) or other bus or point-to-point communication links and / or protocols, such as NV-Link high-speed links or interconnection protocols.

[0312] In at least one embodiment, the parallel processor(s) 2112 include circuitry optimized for graphics and video processing, such as video output circuitry, and form a graphics processing unit (GPU). For example, the parallel processor(s) 2112 includes a graphics core 2000. In at least one embodiment, the parallel processor(s) 2112 include circuitry optimized for general processing. In at least one embodiment, the components of the computer system 2100 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, the parallel processor(s) 2112, the memory hub 2105, the processor(s) 2102, and the I / O hub 2107 may be integrated into a system-on-a-chip (SoC) integrated circuit.In at least one embodiment, the components of computer system 2100 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computer system 2100 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computer system.

[0313] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details of logic 915 are described herein in connection with Fig.9A and / or 9B. In at least one embodiment, logic 915 in computer system 2100 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0314] In at least one embodiment, one or more Fig. 21 systems shown are used to create one or more neural networks with various algorithms, formulas and processes as used in conjunction with Fig. 1 and / or to otherwise perform operations described herein. In at least one embodiment, one or more of the Fig.21 systems are used to implement one or more systems and / or processes as used in connection with Fig. 1-8, for example, to adjust a resolution of information used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks, and / or to otherwise perform operations described herein. PROCESSORS

[0315] Fig.22A shows a parallel processor 2200 according to at least one embodiment. In at least one embodiment, various components of the parallel processor 2200 may be implemented using one or more integrated circuits, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the parallel processor 2200 shown is a variant of one or more parallel processors 2112 described in Fig. 21 according to an exemplary embodiment. In at least one embodiment, a parallel processor 2200 includes one or more graphics cores 2000.

[0316] In at least one embodiment, parallel processor 2200 includes a parallel processing unit 2202. In at least one embodiment, parallel processing unit 2202 includes an I / O unit 2204 that enables communication with other devices, including other instances of parallel processing unit 2202. In at least one embodiment, I / O unit 2204 can be directly connected to other devices. In at least one embodiment, I / O unit 2204 is connected to other devices via a hub or switch interface, such as a storage hub 2205. In at least one embodiment, the connections between storage hub 2205 and I / O unit 2204 form a communication link 2213.In at least one embodiment, the I / O unit 2204 is coupled to a host interface 2206 and a memory crossbar 2216, where the host interface 2206 receives commands to perform processing operations and the memory crossbar 2216 receives commands to perform memory operations.

[0317] In at least one embodiment, when host interface 2206 receives a command buffer via I / O unit 2204, host interface 2206 may direct work operations to a front end 2208 to execute those commands. In at least one embodiment, front end 2208 is coupled to a scheduler 2210 (which may also be referred to as a sequencer) configured to dispatch commands or other work items to a processing cluster array 2212. In at least one embodiment, scheduler 2210 ensures that processing array 2212 is properly configured and in a valid state before dispatching tasks to a cluster of processing array 2212. In at least one embodiment, scheduler 2210 is implemented via firmware logic executing on a microcontroller.In at least one embodiment, the microcontroller-implemented scheduler 2210 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling fast preemption and context switching of threads executing on the processing array 2212. In at least one embodiment, host software may allocate workloads for scheduling on the processing cluster array 2212 via one of several graphics processing paths. In at least one embodiment, the workloads may then be automatically distributed across the processing array cluster 2212 by the logic of the scheduler 2210 within a microcontroller that includes the scheduler 2210.

[0318] In at least one embodiment, processing array 2212 may include up to "N" processing clusters (e.g., cluster 2214A, cluster 2214B, and finally cluster 2214N), where "N" represents a positive integer (which may be a different integer "N" than used in other figures). In at least one embodiment, each processing cluster 2214A-2214N of processing array 2212 may execute a large number of concurrent threads. In at least one embodiment, scheduler 2210 may allocate work to clusters 2214A-2214N of processing array 2212 using various scheduling and / or work distribution algorithms, which may vary depending on the workload incurred for each type of program or computation.In at least one embodiment, scheduling may be performed dynamically by scheduler 2210 or assisted at least in part by compiler logic during compilation of program logic configured for execution by processing cluster array 2212. In at least one embodiment, different clusters 2214A-2214N of processing cluster array 2212 may be allocated for processing different types of programs or for performing different types of computations.

[0319] In at least one embodiment, processing cluster array 2212 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2212 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing cluster array 2212 may include logic to perform processing tasks, including filtering video and / or audio data, performing modeling operations, including physics operations, and performing data transformations.

[0320] In at least one embodiment, processing cluster array 2212 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 2212 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 2212 may be configured to execute graphics processing-related shader programs, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 2202 may transfer data from system memory via I / O unit 2204 for processing.In at least one embodiment, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2222) during processing and then written back to system memory.

[0321] In at least one embodiment, when parallel processing unit 2202 is used to perform graphics processing, scheduler 2210 may be configured to divide a processing load into approximately equal-sized tasks to enable better distribution of graphics processing operations across multiple clusters 2214A-2214N of processing cluster array 2212. In at least one embodiment, portions of processing cluster array 2212 may be configured to perform different types of processing.For example, in at least one embodiment, a first section may be configured to perform vertex shading and topology generation, a second section may be configured to perform tessellation and geometry shading, and a third section may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more clusters 2214A-2214N may be stored in buffers to enable the transfer of intermediate data between clusters 2214A-2214N for further processing.

[0322] In at least one embodiment, processing cluster array 2212 may receive processing tasks to be executed via scheduler 2210, which receives commands defining processing tasks from frontend 2208. In at least one embodiment, the processing tasks may include indices of the data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands that specify how the data should be processed (e.g., which program should be executed). In at least one embodiment, scheduler 2210 may be configured to retrieve indices corresponding to the tasks or may receive indices from frontend 2208.In at least one embodiment, the front end 2208 may be configured to ensure that the processing cluster array 2212 is configured in a valid state before initiating a workload specified by incoming command buffers (e.g., batch buffers, push buffers, etc.).

[0323] In at least one embodiment, each of one or more instances of parallel processing unit 2202 may be coupled to a parallel processor memory 2222. In at least one embodiment, parallel processor memory 2222 may be accessed via a memory crossbar 2216, which may receive memory requests from processing cluster array 2212 as well as from I / O unit 2204. In at least one embodiment, memory crossbar 2216 may access parallel processor memory 2222 via a memory interface 2218. In at least one embodiment, memory interface 2218 may include multiple partition units (e.g., partition unit 2220A, partition unit 2220B, through partition unit 2220N), each of which may be coupled to a portion (e.g., memory unit) of parallel processor memory 2222.In at least one embodiment, a number of partition units 2220A-2220N is configured to be equal to a number of storage units, such that a first partition unit 2220A has a corresponding first storage unit 2224A, a second partition unit 2220B has a corresponding storage unit 2224B, and an Nth partition unit 2220N has a corresponding Nth storage unit 2224N. In at least one embodiment, a number of partition units 2220A-2220N may not be equal to a number of storage units.

[0324] In at least one embodiment, memory units 2224A-2224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate memory (GDDR). In at least one embodiment, memory units 2224A-2224N may also include 3D stack memories, including, but not limited to, high width memory (HBM), HBM2e, or HDM3. In at least one embodiment, rendering targets, such as frame buffers or texture units, may be stored in multiple memory units 2224A-2224N so that partition units 2220A-2220N can write portions of each rendering target in parallel to efficiently utilize the available bandwidth of parallel processor memory 2222.In at least one embodiment, a local instance of parallel processor memory 2222 may be eliminated in favor of a unified memory design that utilizes system memory in conjunction with the local cache memory.

[0325] In at least one embodiment, each of the clusters 2214A-2214N of the processing array 2212 can process data written to each of the memory units 2224A-2224N within the parallel processor memory 2222. In at least one embodiment, the memory crossbar 2216 can be configured to transfer an output of each cluster 2214A-2214N to any partition unit 2220A-2220N or to another cluster 2214A-2214N that can perform additional processing on an output. In at least one embodiment, each cluster 2214A-2214N can communicate with the memory interface 2218 via the memory crossbar 2216 to read from or write to various external devices.In at least one embodiment, the memory crossbar 2216 includes a connection to the memory interface 2218 to communicate with the I / O unit 2204, as well as a connection to a local instance of the parallel processor memory 2222, which enables the processing units in the different processing clusters 2214A-2214N to communicate with system memory or other memory not local to the parallel processing unit 2202. In at least one embodiment, the memory crossbar 2216 may use virtual channels to separate traffic flows between clusters 2214A-2214N and partition units 2220A-2220N.

[0326] In at least one embodiment, multiple instances of the parallel processing unit 2202 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2202 may be configured to interoperate, even if different instances have different numbers of processor cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2202 may include higher-precision floating-point units compared to other instances.In at least one embodiment, systems including one or more instances of the parallel processing unit 2202 or the parallel processor 2200 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0327] Fig. 22B is a block diagram of a partition unit 2220 according to at least one embodiment. In at least one embodiment, the partition unit 2220 is an example of one of the partition units 2220A-2220N of Fig.22A. In at least one embodiment, partition unit 2220 includes an L2 cache 2221, a frame buffer interface 2225, and a Raster Operations Unit (ROP) 2226. In at least one embodiment, L2 cache 2221 is a read / write cache configured to perform load and store operations received from memory crossbar 2216 and ROP 2226. In at least one embodiment, read misses and urgent writeback requests are issued from L2 cache 2221 to frame buffer interface 2225 for processing. In at least one embodiment, updates may also be sent to a frame buffer via frame buffer interface 2225 for processing. In at least one embodiment, frame buffer interface 2225 interfaces to one of the memory units in parallel processor memory, such as memory units 2224A-2224N of Fig.22A (for example, within the parallel processor memory 2222).

[0328] In at least one embodiment, ROP 2226 is a processing unit that performs raster operations such as stenciling, Z-testing, blending, etc. In at least one embodiment, ROP 2226 then outputs processed graphics data, which is stored in graphics memory. In at least one embodiment, ROP 2226 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic using one or more of several compression algorithms. In at least one embodiment, the type of compression performed by ROP 2226 may vary based on the statistical properties of the data to be compressed.For example, in at least one embodiment, delta color compression is performed on depth and color data on a per-tile basis.

[0329] In at least one embodiment, ROP 2226 is in each processing cluster (e.g., clusters 2214A-2214N of Fig. 22A) instead of in the partition unit 2220. In at least one embodiment, read and write requests for pixel data are transmitted via the memory crossbar 2216 instead of pixel fragment data. In at least one embodiment, processed graphics data may be displayed on a display device, such as one or more display devices 2110 of Fig. 21, for further processing by processor(s) 2102 or for further processing by one of the processing units within the parallel processor 2200 of Fig. 22A.

[0330] Fig.22C is a block diagram of a processing cluster 2214 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is an instance of one of the processing clusters 2214A-2214N of Fig.22A. In at least one embodiment, processing cluster 2214 may be configured to execute many threads in parallel, where "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single instruction, multiple data (SIMD) instruction dispatch techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single-instruction-multiple-thread (SIMT) techniques are used to support parallel execution of a large number of generally synchronized threads using a common instruction unit configured to dispatch instructions to a set of processing engines within each processing cluster.

[0331] In at least one embodiment, the operation of the processing cluster 2214 may be controlled by a pipeline manager 2232, which distributes the processing tasks among parallel SIMT processors. In at least one embodiment, the pipeline manager 2232 receives instructions from the scheduler 2210 of the Fig.22A and manages the execution of these instructions via a graphics multiprocessor 2234 and / or a texture unit 2236. In at least one embodiment, the graphics multiprocessor 2234 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included in the processing cluster 2214. In at least one embodiment, one or more instances of the graphics multiprocessor 2234 may be included in a processing cluster 2214. In at least one embodiment, the graphics multiprocessor 2234 may process data, and a data crossbar 2240 may be used to distribute the processed data to one of several possible destinations, including other shader units.In at least one embodiment, the pipeline manager 2232 may facilitate the distribution of processed data by specifying destinations for processed data to be distributed across the data crossbar 2240.

[0332] In at least one embodiment, each graphics multiprocessor 2234 within the processing cluster 2214 may include an identical set of functional execution logic (e.g., arithmetic logic units, load / store units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipeline in which new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and the computation of various algebraic functions. In at least one embodiment, the same hardware with functional units may be used to perform different operations, and any combination of functional units may be present.

[0333] In at least one embodiment, the instructions transferred to the processing cluster 2214 form a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a common program on different input data. In at least one embodiment, each thread within a thread group may be assigned to a different engine within a graphics multiprocessor 2234. In at least one embodiment, a thread group may include fewer threads than a number of processing engines within the graphics multiprocessor 2234.In at least one embodiment, when a thread group includes fewer threads than a number of processing engines, one or more of the processing engines may be idle during the cycles in which that thread group is processing. In at least one embodiment, a thread group may also include more threads than a number of processing engines within the graphics multiprocessor 2234. In at least one embodiment, when a thread group includes more threads than the number of processing engines in the graphics multiprocessor 2234, processing may occur in consecutive clock cycles. In at least one embodiment, multiple thread groups may execute concurrently on a graphics multiprocessor 2234.

[0334] In at least one embodiment, the graphics multiprocessor 2234 includes an internal cache for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2234 may forgo an internal cache and utilize a cache (e.g., L1 cache 2248) within the processing cluster 2214. In at least one embodiment, each graphics multiprocessor 2234 also has access to L2 caches within partition units (e.g., partition units 2220A-2220N of Fig.22A) that are shared by all processing clusters 2214 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2234 can also access off-chip global memory, which can include one or more of the parallel processor local memories and / or system memories. In at least one embodiment, any memory external to parallel processing unit 2202 can be used as global memory. In at least one embodiment, processing cluster 2214 includes multiple instances of graphics multiprocessor 2234 and can share common instructions and data that can be stored in L1 cache 2248.

[0335] In at least one embodiment, each processing cluster 2214 may include a memory ...

Claims

[1] Processor comprising: one or more circuits for adjusting an information resolution to be used by one or more neural networks based at least in part on one or more performance metrics of the one or more neural networks. [2] The processor of claim 1, wherein the information resolution is used to train one or more neural networks to generate one or more images. [3] The processor of claim 1, wherein the one or more performance metrics comprise one or more loss operations. [4] The processor of claim 1, wherein the one or more neural networks comprise one or more encoders. [5] The processor of claim 1, wherein the one or more neural networks comprise one or more transformer neural networks to perform bilinear interpolation when adjusting the resolution. [6] A processor according to claim 1, wherein the information resolution is represented by a matrix of pixels of one or more images. [7] The processor of claim 1, wherein the information resolution is adjusted to be increased. [8] System comprising: one or more processors for adjusting an information resolution to be used by one or more neural networks based at least in part on one or more performance metrics of the one or more neural networks. [9] The system of claim 8, wherein the information resolution is used to train one or more neural networks to generate one or more images. [10] The system of claim 8, wherein the one or more performance metrics comprise one or more loss operations. [11] The system of claim 8, wherein the one or more neural networks comprise one or more encoders. [12] The system of claim 8, wherein the one or more neural networks comprise one or more transformer neural networks to perform bilinear interpolation when adjusting the resolution. [13] The system of claim 8, wherein the information resolution is represented using a pixel matrix of one or more images. [14] The system of claim 8, wherein the information resolution is adjusted to be increased. [15] Procedure comprising: Adjusting an information resolution to be used by one or more neural networks based at least in part on one or more performance metrics of the one or more neural networks. [16] The method of claim 15, wherein the information resolution is used to train one or more neural networks to generate one or more images. [17] The method of claim 15, wherein the one or more performance metrics comprise one or more loss operations. [18] The method of claim 15, wherein the one or more neural networks comprise one or more encoders. [19] The method of claim 15, wherein the one or more neural networks comprise one or more transformer neural networks to perform bilinear interpolation when adjusting the resolution. [20] The method of claim 15, wherein the information resolution is adjusted to be increased.

Images