METHOD FOR MANUFACTURING A POWER INVERTER

Abstract

A method for manufacturing a power inverter may include determining several electrical properties of both a first and a second power switch chip. These several electrical properties include at least a conduction loss and a switching loss. Furthermore, the method may include manufacturing the power inverter at least partially using both the first and second power switch chips based on the several electrical properties of both.

Description

INTRODUCTION

[0001] The present invention relates to a method for manufacturing a power inverter, of a type essentially known from JP 2014 - 96 968 A.

[0002] Further state of the art can also be found in the publications DE 10 2023 100 167 A1, DE 10 2018 131 999 A1, DE 693 29 916 T2, JP 2010 - 199 362 A and JP 2002 - 315 356 A.

[0003] Power modules can be used to convert power in vehicle applications. Power modules are self-contained power electronic devices, typically containing semiconductor switches configured to be controllable for power conversion tasks such as DC / AC conversion, AC / DC conversion, DC / DC conversion, and / or the like. In some examples, power modules are configured as a half-bridge with four semiconductor devices that enable DC / AC conversion. Multiple power modules can be used together to provide multiphase AC power to a load, such as a vehicle's traction motor.The design of power modules is complicated by high current requirements, high voltage requirements, high efficiency requirements, strict size, weight, and equipment usage restrictions, strict electromagnetic interference (EMI) restrictions, challenging environmental conditions, and various other factors. Current power module and inverter manufacturing processes may not be able to utilize components with electrical characteristics outside of normal ranges.

[0004] Although current methods for manufacturing power conversion devices fulfill their intended purpose, there is therefore a need for a new and improved method for manufacturing power inverters. SUMMARY

[0005] According to the invention, a method for manufacturing a power inverter is presented, characterized by the features of claim 1.

[0006] According to another aspect of the present invention, determining the multiple electrical properties may further include testing both the first power switch chip and the second power switch chip in order to determine the multiple electrical properties of both the first power switch chip and the second power switch chip.

[0007] According to another aspect of the present invention, the assembly of the at least one power module may further include the assembly of the at least one power module wherein a switching loss of the first power switch chip is greater than or equal to a predetermined chip switching loss threshold and wherein a total switching loss of the first power switch chip and the second power switch chip is less than or equal to a predetermined total switching loss threshold.

[0008] According to another aspect of the present invention, the assembly of at least one power module can further comprise the assembly of the at least one power module, wherein the at least one power module further comprises a first gate driver for controlling the first power switch chip and a second gate driver for controlling the second power switch chip. Furthermore, the assembly of at least one power module can comprise configuring the first gate driver for controlling the first power switch chip with a first switching rate. Furthermore, the assembly of at least one power module can comprise configuring the second gate driver for controlling the second power switch chip with a second switching rate. The second switching rate is lower than the first switching rate.

[0009] According to another aspect of the present invention, configuring the first gate driver and configuring the second gate driver may further include determining the first switching slew rate and the second switching slew rate such that the total switching loss of the first power switch chip and the second power switch chip is less than or equal to a predetermined total switching loss threshold, and such that a first voltage overshoot of the first power switch chip and a second voltage overshoot of the second power switch chip are less than or equal to a predetermined voltage overshoot threshold.

[0010] According to another aspect of the present invention, the assembly of at least one power module can further comprise the assembly of the at least one power module wherein a conduction loss of the first power switch chip is greater than or equal to a predetermined chip conduction loss threshold. A conduction loss of the second power switch chip is less than or equal to the predetermined chip conduction loss threshold. A total conduction loss of the first power switch chip and the second power switch chip is less than or equal to a predetermined total conduction loss threshold.

[0011] According to another aspect of the present invention, the manufacture of the power inverter can further include determining the total power loss of the at least one power module, at least partially, based on the electrical properties of the first power switch chip and the electrical properties of the second power switch chip. Furthermore, the manufacture of the power inverter can include attaching the at least one power module to a heat sink, at least partially, based on the total power loss of the at least one power module.

[0012] According to another aspect of the present invention, attaching the at least one power module to a heat sink can further include determining an optimal attachment location of the at least one power module on the heat sink with respect to a coolant inlet and a coolant outlet of the heat sink. A distance between the coolant inlet and the optimal attachment location is negatively correlated with the overall power loss of the at least one power module.

[0013] According to several aspects, a power inverter for a vehicle can include a heat sink comprising a coolant inlet and a coolant outlet. Furthermore, the power inverter can include a power module attached to the heat sink, which contains at least a first power switch chip and a second power switch chip, selected at least partially based on several electrical properties of both the first and second power switch chips.

[0014] According to another aspect of the present invention, the multiple electrical properties include at least one power loss. The power loss is the sum of a switching loss and a conduction loss. The total power loss of the first power switch chip of the power module and the second power switch chip of the power module is less than or equal to a predetermined total power loss threshold.

[0015] According to another aspect of the present invention, the power module can further include a first gate driver for controlling the first power switch chip. The first gate driver is configured to control the first power switch chip with a first switching rate. Furthermore, the power module can include a second gate driver for controlling the second power switch chip. The second gate driver is configured to control the second power switch chip with a second switching rate. The second switching rate is lower than the first switching rate.

[0016] According to another aspect of the present invention, the first switching rate and the second switching rate are determined in such a way that the total power loss of the first power switch chip and the second power switch chip is less than or equal to a predetermined total power loss threshold, and in such a way that a first voltage overshoot of the first power switch chip and a second voltage overshoot of the second power switch chip are less than or equal to a predetermined voltage overshoot threshold.

[0017] According to another aspect of the present invention, the first switching rate and the second switching rate are determined in response to the finding that the total power loss of the first power switch chip and the second power switch chip is less than or equal to the predetermined total power loss threshold, in such a way that the first voltage overshoot of the first power switch chip and the second voltage overshoot of the second power switch chip are less than or equal to the predetermined voltage overshoot threshold.

[0018] According to another aspect of the present invention, the power module is at least partially attached to the heat sink at an optimal mounting location with respect to the coolant inlet, based on a total power loss of the power module.

[0019] According to another aspect of the distance at hand, a distance between the coolant inlet and the optimal mounting location is negatively correlated with the overall power loss of the power module.

[0020] A method for manufacturing a power inverter for a vehicle is provided according to several aspects. The method can include testing both a first power switch chip and a second power switch chip to determine several electrical properties of both. These electrical properties include at least conduction loss and switching loss. Furthermore, the method can include assembling at least one power module, at least partially, based on the electrical properties of both the first and second power switch chips. The at least one power module includes at least the first and second power switch chips.Furthermore, the method may include the manufacture of the power inverter, which contains the at least one power module, at least partially based on the multiple electrical properties of both the first power switch chip and the second power switch chip.

[0021] According to another aspect of the present invention, the assembly of at least one power module can further comprise the assembly of the at least one power module wherein a switching loss of the first power switch chip is greater than or equal to a predetermined chip switching loss threshold. Furthermore, the at least one power module comprises a first gate driver for controlling the first power switch chip and a second gate driver for controlling the second power switch chip.Furthermore, assembling at least one power module can include determining a first switching slew rate and a second switching slew rate such that the total switching loss of the first power switch chip and the second power switch chip is less than or equal to a predetermined total switching loss threshold, and such that the first voltage overshoot of the first power switch chip and the second voltage overshoot of the second power switch chip are less than or equal to a predetermined voltage overshoot threshold. Furthermore, assembling at least one power module can include configuring the first gate driver to control the first power switch chip with the first switching slew rate.Furthermore, assembling at least one power module can include configuring the second gate driver to control the second power switch chip with the second switching rate. The second switching rate is lower than the first switching rate.

[0022] According to another aspect of the present invention, the manufacture of the power inverter can further include determining the total power loss of the at least one power module, at least partially, based on the electrical properties of the first power switch chip and the electrical properties of the second power switch chip. Furthermore, the manufacture of the power inverter can include determining an optimal mounting location for the at least one power module on a heat sink with respect to a coolant inlet and a coolant outlet of the heat sink. A distance between the coolant inlet and the optimal mounting location is negatively correlated with the total power loss of the at least one power module. The mounting of the at least one power module on a heat sink is based, at least partially, on the optimal mounting location.

[0023] Further areas of application will become apparent from the description given here. It should be understood that the description and the specific examples are for illustrative purposes only. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings described here are for illustrative purposes only; they show: Fig. 1. A circuit diagram of a power system for a vehicle according to an exemplary embodiment; Fig. 2 a circuit diagram of a power inverter of the power system according to an exemplary embodiment; Fig. 3 a circuit diagram of a first power module of the power inverter according to an exemplary embodiment; and Fig. 4 a flow chart of a procedure for manufacturing the power inverter according to an exemplary embodiment. DETAILED DESCRIPTION

[0025] The following description is essentially only exemplary.

[0026] When manufacturing power electronic devices such as power inverters for vehicles, it is advantageous, according to aspects of the present invention, to use components with known electrical properties within acceptable ranges. However, electrical properties can vary in component batches due to manufacturing variations, which can lead to components with properties outside normal ranges. The present invention provides a new and improved method for manufacturing power inverters for vehicles that enables the use of components with non-ideal electrical properties.

[0027] In Fig. Figure 1 represents a power system for a vehicle and is generally designated by reference numeral 10. The system 10 is shown with an exemplary vehicle 12. Although a passenger car is depicted, it should be noted that the vehicle 12 can be any type of vehicle. Generally, the system 10 includes a controller 14, a rechargeable energy storage system (RESS) 16, a traction motor 18, and a power inverter 20.

[0028] The controller 14 is used to control the RESS 16, the traction motor 18, and the power inverter 20. The controller 14 includes at least one processor 22 and a non-transient computer-readable storage device or non-transient computer-readable storage media 24. The processor 22 can be a custom or commercially available processor, a central processing unit (CPU), a graphics processing unit (GPU), an auxiliary processor among several processors associated with the controller 14, a semiconductor-based microprocessor (in the form of a microchip or chipset), a macroprocessor, a combination thereof, or, more generally, an instruction-executing device.

[0029] The computer-readable storage device or computer-readable storage media 24 can contain volatile and non-volatile storage memory, e.g., in read-only memory (ROM), read / write memory (RAM), and hold memory (KAM). A KAM is persistent or non-volatile memory that can be used to store various working variables while the processor 22 is shut down.The computer-readable storage device or computer-readable storage media 24 can be implemented using a number of storage devices such as PROMs (programmable read-only memory), EPROMs (electrical PROMs), EEPROMs (electrically erasable PROMs), flash memory, or other electrical, magnetic, optical, or combination storage devices capable of storing data, some of which represent executable instructions used by the controller 14 to control various systems of the vehicle 12. Furthermore, the controller 14 can consist of multiple controllers that are in electrical communication with each other.

[0030] The controller 14 communicates electrically with the RESS 16, the traction motor 18, and the power inverter 20. Furthermore, the controller 14 can be connected to additional systems and / or controllers of the vehicle 12, enabling it to access data such as the vehicle 12's speed, acceleration, braking, and steering angle. According to one exemplary embodiment, electrical communication is established, for example, using a CAN network, a FLEXRAY network, a local area network (e.g., Wi-Fi, Ethernet, etc.), a Serial Peripheral Interface (SPI) network, or similar. It should be understood that various additional wired and wireless technologies and communication protocols are possible for communicating with the controller 14.Furthermore, it should be understood that electrical communication also involves the transfer of power and / or energy between electrical devices (e.g., using conductor wires and / or wireless power transmission techniques).

[0031] The RESS 16 stores and provides electrical energy in the form of direct current (DC) energy for propelling the vehicle 12. According to one exemplary embodiment, the RESS 16 contains multiple battery cells (e.g., lithium-ion battery cells) that are electrically connected in series and / or parallel to provide increased voltage and / or current capability. In another example, the multiple battery cells are enclosed in a housing configured to protect them from mechanical vibration, water ingress, and dust ingress. Furthermore, the housing is configured (e.g., using a liquid cooling system, a resistance heating system, and / or the like) to provide temperature control.

[0032] According to one exemplary embodiment, the RESS 16 further includes a battery management system (BMS) in electrical communication with the controller 14, configured to monitor battery characteristics such as state of charge (SOC), state of health (SOH), temperature, and / or the like, and to transmit these characteristics to the controller 14. According to another example, the BMS includes a BMS controller in electrical communication with multiple BMS sensors arranged within the housing of the RESS 16. According to another example, the BMS further includes one or more electronic switches (e.g., relays, contactors, semiconductor-based switches, and / or the like) that are operable to interrupt the current flow through the multiple battery cells of the RESS 16 in response to commands received from the BMS controller and / or the controller 14.According to an exemplary embodiment, the RESS 16 provides a DC voltage via a positive and a negative output terminal. As discussed in more detail below, the positive and negative output terminals are electrically connected to the power inverter 20.

[0033] The traction motor 18 is used to convert electrical energy from the RESS 16 into mechanical energy (i.e., rotational energy) to propel the vehicle 12 forward. According to one exemplary embodiment, the traction motor 18 is a three-phase alternating current induction motor (three-phase AC induction motor) capable of converting AC energy into mechanical energy. In this example, the traction motor 18 comprises a stator with multiple stator windings and a rotor with multiple rotor windings rotatably mounted within the stator. The stator windings are energized by three-phase AC supplied by the power inverter 20 to generate a rotating stator magnetic field. The rotating stator magnetic field induces currents in the rotor windings, which in turn generate a rotor magnetic field that interacts with the rotating stator magnetic field, causing the rotor to rotate.The amplitude, frequency and / or relative phase shift of applying a voltage to each of the three phases of the stator windings controls the speed, direction and / or torque of the traction motor 18. The controller 14 communicates electrically with the traction motor 18 for monitoring and / or controlling the traction motor 18, for example to measure a temperature, a speed and / or the like of the traction motor 18.

[0034] The power inverter 20 is used to convert the direct current (DC) power supplied by the RESS 16 into three-phase alternating current (three-phase AC) power for use by the traction motor 18. According to one exemplary embodiment, the power inverter 20 includes several power semiconductor devices, such as insulated-layer bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and / or the like, configured to convert DC to three-phase AC. According to one example, the power inverter 20 operates by switching the multiple power semiconductor devices in a pattern to produce an AC sine wave output for each of the three phases.The pattern can be set to vary the amplitude, frequency, and / or relative phase shift of each of the three phases based on signals from the controller 14, in order to control the speed, direction, and / or torque of the traction motor 18. The power inverter 20 includes a positive DC terminal 26a and a negative DC terminal 26b, which are electrically connected to the RESS 16. Furthermore, the power inverter 20 includes a first AC terminal 28a, a second AC terminal 28b, and a third AC terminal 28c, which are electrically connected to the traction motor 18. The power inverter 20 communicates electrically with the controller, allowing the controller 14 to enable, disable, and otherwise adjust the operation of the power inverter 20. It should be understood that various types of inverters, including, for example, multi-level inverters, are possible.

[0035] In Fig. Figure 2 shows a circuit diagram of the power inverter 20. According to an exemplary embodiment, the power inverter 20 includes a heat sink 30 and several power modules 32.

[0036] The heat sink 30 is used to transfer heat away from the multiple power modules 32 during the operation of the power inverter 20. According to an exemplary embodiment, the heat sink 30 includes a cooling plate with one or more internal liquid-tight channels for transferring coolant through the heat sink 30. Furthermore, the heat sink 30 includes a coolant inlet 34a, through which coolant enters the heat sink 30, and a coolant outlet 34b, through which coolant exits the heat sink 30. As the coolant flows through the heat sink 30 and absorbs heat from each of the multiple power modules 32, the temperature of the coolant increases.Thus, the temperature of the coolant entering at coolant inlet 34a is generally lower than the temperature of the coolant exiting at coolant outlet 34b, with a corresponding temperature gradient in the heat sink 30 between coolant inlet 34a and coolant outlet 34b. For example, after exiting the heat sink 30 through coolant outlet 34b, the coolant flows through a radiator to release heat absorbed by the multiple power modules 32.

[0037] The multiple power modules 32 are independent modules for converting DC power to AC power. According to an example that is in Fig. As shown in Figure 2, the power inverter 20 comprises a first power module 32a, a second power module 32b, and a third power module 32c. It should be understood that the power inverter 20 can contain any number of power modules. According to an exemplary embodiment, the multiple power modules 32 are attached to the heat sink 30, for example, using thermal paste, thermal adhesive, and / or the like.

[0038] Now in Fig. Figure 3 shows a circuit diagram of the first power module 32a. It should be understood that the following invention is also applicable to any number of additional power modules of the power inverter 20, including, for example, the second power module 32b and the third power module 32c. According to an exemplary embodiment, the first power module 32a includes a first power switch chip 36a and a second power switch chip 36b, which are selected from several power switch chips 36. Furthermore, the first power module 32a includes several gate drivers 38 for controlling each of the several power switch chips 36. According to an example, the several gate drivers 38 include a first gate driver 38a and a second gate driver 38b. It should be understood that each of the several power modules 32 can contain any number of power switch chips and gate drivers.

[0039] Each of the multiple power switch chips 36 contains one or more semiconductor devices such as transistors, thyristors, triacs, GTOs (turn-off thyristors), IGBTs (insulated-layer bipolar transistors), MOSFETs (metal-oxide-semiconductor field-effect transistors), SCRs (silicon-controlled rectifiers), and / or the like. The first power switch chip 36a is connected to the positive DC terminal 26a and is thus referred to as a "high-side" chip. The second power switch chip 36b is connected to the negative DC terminal 26b and is thus referred to as a "low-side" chip.

[0040] According to an exemplary embodiment, each of the multiple power switch chips 36 is characterized by several electrical properties. According to one example, the multiple electrical properties include at least: a conduction loss and a switching loss. The conduction loss is caused at least partially by an on-resistance of the power switch chip. The switching loss is caused at least partially by a switching energy of the power switch chip. According to one example, the multiple power switch chips 36 are provided in large quantities for the manufacturing process of the multiple power modules 32. Thus, the electrical properties of the multiple power switch chips 36 can vary.

[0041] To ensure the proper operation of the multiple power modules 32 of the power inverter 20, predefined threshold values ​​are defined. According to an exemplary embodiment, a predefined chip line loss threshold is defined as a maximum permissible line loss for any single power switch chip. A predefined total line loss threshold is defined as a maximum permissible total line loss across all power switch chips in a power module.

[0042] A predetermined chip switching loss threshold is defined as the maximum permissible switching loss for any single power switch chip. A predetermined total switching loss threshold is defined as the maximum permissible total switching loss across all power switch chips in a power module. The present invention provides a new and improved method for manufacturing the power inverter 20, which allows the use of power switch chips that exceed one or more of the thresholds discussed above, thus increasing manufacturing efficiency.

[0043] Each of the multiple gate drivers 38 controls the switching activity of one of the multiple power switch chips 36. For example, the first gate driver 38a controls the first power switch chip 36a, and the second gate driver 38b controls the second power switch chip 36b. According to an exemplary embodiment, each of the multiple gate drivers 38 includes a digital and / or analog circuit arrangement that is capable of receiving control signals from an inverter controller (not shown) or from the controller 14 and providing corresponding voltage and / or current pulses to one of the power switch chips 36 to turn the power switch chip on or off.According to an example, one or more of the multiple gate drivers 38 are a voltage source gate driver (VSGD), a variable voltage source gate driver (WSGD), a current source gate driver (CSGD) or a variable current source gate driver (VCSGD), which, as discussed in more detail below, can be operated to vary the switch characteristics such as a slew rate.

[0044] In Fig.Figure 4 shows a flowchart of a method 100 for manufacturing a power inverter. The method 100 begins in block 102 and proceeds to block 104. In block 104, the multiple electrical properties of each of the multiple power switch chips 36 are determined. According to one exemplary embodiment, the multiple electrical properties include at least the conduction loss and the switching loss. According to another example, the multiple electrical properties are determined by electrical testing of each of the multiple power switch chips 36 (e.g., measuring the voltage and current during switching and the on-state current flow). According to yet another example, the multiple electrical properties of each of the multiple power switch chips 36 are provided by the manufacturer of each of the multiple power switch chips 36.According to an exemplary embodiment, the method 100 can holistically consider the electrical properties of chips that are available from multiple suppliers and / or in stock in order to optimize the procurement of the multiple power switch chips 36. Following block 104, the method 100 proceeds to block 106.

[0045] In block 106, the first circuit breaker chip 36a and the second circuit breaker chip 36 are selected from the multiple circuit breaker chips 36b such that the total line loss (i.e., the sum of the line losses of the first circuit breaker chip 36a and the second circuit breaker chip 36b) is less than or equal to the specified total line loss threshold. For example, the line loss of the first circuit breaker chip 36a is greater than or equal to a specified chip line loss threshold. Therefore, the second circuit breaker chip 36b is selected from the multiple circuit breaker chips 36 as a circuit breaker chip with a line loss less than or equal to the specified total line loss threshold to compensate for the increased line loss of the first circuit breaker chip 36a.Thus, the first power switch chip 36a continues to be used in the manufacturing process, even though the line loss of the first power switch chip 36a exceeds the specified chip line loss threshold.

[0046] According to another exemplary embodiment, the first power switch chip 36a and the second power switch chip 36b are selected from the multiple power switch chips 36 such that the total switching loss (i.e., the sum of the switching losses of the first power switch chip 36a and the second power switch chip 36b) is less than or equal to the predetermined total switching loss threshold. In one example, the switching loss of the first power switch chip 36a is greater than or equal to a predetermined chip switching loss threshold. Therefore, the second power switch chip 36b is selected from the multiple power switch chips 36 as a power switch chip with a switching loss less than or equal to the predetermined chip switching loss threshold, for example, to compensate for the increased switching loss of the first power switch chip 36a.Thus, the first power switch chip 36a continues to be used in production, even though the switching loss of the first power switch chip 36a exceeds the specified chip switching loss threshold.

[0047] According to another exemplary embodiment, the first circuit breaker chip 36a and the second circuit breaker chip 36b are selected from the multiple circuit breaker chips 36 such that the total power loss (i.e., a sum of the conduction and switching losses of the first circuit breaker chip 36a and the second circuit breaker chip 36b) is less than or equal to a predetermined total power loss threshold. In one example, the total loss of the first circuit breaker chip 36a is greater than or equal to a predetermined chip total power loss threshold. Therefore, the second circuit breaker chip 36b is selected from the multiple circuit breaker chips 36 as a circuit breaker chip with a total power loss less than or equal to the predetermined total power loss threshold, for example, to compensate for the increased total power loss of the first circuit breaker chip 36a.

[0048] According to an exemplary embodiment, method 100 holistically considers the electrical properties of chips available from and / or in stock from multiple suppliers to optimize the procurement of the multiple circuit breaker chips 36. For example, suppliers can be selected to provide low-conduction circuit breaker chips, which are used to compensate for high-conduction chips if one or more of the multiple circuit breaker chips 36 exhibit high conduction loss. Conversely, suppliers can be selected to provide high-conduction circuit breaker chips, which are used to compensate for high-conduction chips if one or more of the multiple circuit breaker chips 36 exhibit low conduction loss, thereby utilizing chips that would otherwise be rejected.

[0049] According to an example, the line loss of the first circuit breaker chip 36a and the second circuit breaker chip 36b are compared with the predetermined chip line loss threshold. If the line loss of the first circuit breaker chip 36a and the second circuit breaker chip 36b is greater than the predetermined chip line loss threshold, one or more additional circuit breaker chips with a line loss less than or equal to the predetermined chip line loss threshold are provided. The one or more additional circuit breaker chips are provided, at least in part, by one of the several suppliers based on an inventory (i.e., line loss characteristics of circuit breaker chips in stock) of each of the several suppliers. After block 106, procedure 100 proceeds to block 108.

[0050] In Block 108, the total switching loss of the first power switch chip 36a and the second power switch chip 36b (i.e., the sum of the switching losses of the first power switch chip 36a and the second power switch chip 36b) is determined. According to an exemplary embodiment, the total switching loss is determined at least partially based on the several electrical properties determined in Block 104. In one example, the switching loss of the first power switch chip 36a is greater than or equal to the specified chip switching loss threshold, and the switching loss of the second power switch chip 36b is greater than or equal to the specified chip switching loss threshold, resulting in a total switching loss that is greater than or equal to the specified total switching loss threshold.

[0051] If the total switching loss of the first circuit breaker chip 36a and the second circuit breaker chip 36b is less than or equal to the specified total switching loss threshold, the method 100 proceeds to block 110, as discussed in more detail below. If the total switching loss of the first circuit breaker chip 36a and the second circuit breaker chip 36b is greater than the specified total switching loss threshold, the method 100 proceeds to block 112. According to another exemplary embodiment, the method 100 also proceeds to block 112 if the total power loss of the first circuit breaker chip 36a and the second circuit breaker chip 36b is greater than the specified total power loss threshold.

[0052] In block 112, a first switching rate and a second switching rate are determined. The first switching rate is the switching rate for the first power switch chip 36a. The second switching rate is the switching rate for the second power switch chip 36b. According to an exemplary embodiment, the switching loss of the power switch chip is negatively correlated with the switching rate (i.e., increasing the switching rate leads to a reduced switching loss). Conversely, voltage overshoot (i.e., voltage spikes caused by leakage inductances in the power module) of the power switch chip is positively correlated with the switching rate (i.e., increasing the switching rate leads to an increased voltage overshoot).According to an example, both the first switching rate and the second switching rate are determined in such a way that the total switching loss is less than or equal to the specified total switching loss threshold, and in such a way that both a first voltage overshoot of the first power switch chip 36a and a second voltage overshoot of the second power switch chip 36b are less than or equal to a specified voltage overshoot threshold.

[0053] According to another example, both the first switching rate and the second switching rate are determined such that the total power loss is less than or equal to the specified total power loss threshold, and such that both the first voltage overshoot of the first circuit breaker chip 36a and the second voltage overshoot of the second circuit breaker chip 36b are less than or equal to the specified voltage overshoot threshold. For example, the first switching rate and / or the second switching rate can be increased to reduce the total switching loss, ensuring that the total power loss is less than or equal to the specified total power loss threshold if the total line loss is greater than the specified total line loss threshold.

[0054] According to an exemplary embodiment, the first switching rate and the second switching rate are calculated at least partially on the basis of the several electrical properties of the first power switch chip 36a and the second power switch chip 36b, which are determined in Block 104, using a mathematical and / or electrical circuit model of the first power switch chip 36a and the second power switch chip 36b.

[0055] In an example where the switching loss of the first power switch chip 36a is greater than or equal to the specified chip switching loss threshold, and the switching loss of the second power switch chip 36b is less than the specified chip switching loss threshold, the first switching slew rate is set higher than the second switching slew rate to compensate for the increased switching loss of the first power switch chip 36a, ensuring that the total switching loss remains less than or equal to the specified total switching loss threshold. Furthermore, the second switching slew rate can be decreased to reduce the drain-source voltage overshoot across the second power switch chip 36b. After block 112, procedure 100 proceeds to block 110.

[0056] In block 110, the first power module 32a is assembled using at least the first power switch chip 36a, the second power switch chip 36b, the first gate driver 38a, and the second gate driver 38b. As discussed above, it should be understood that each of the multiple power modules 32 can contain any number of power switch chips and gate drivers. By way of example, the first power switch chip 36a, the second power switch chip 36b, the first gate driver 38a, and the second gate driver 38b are mounted on a dielectric substrate (i.e., a directly bonded copper substrate). Electrical connections are made between the components using several conductors (e.g., busbars, bond wires, bond clamps, bond tapes, and / or the like).Control connections for connecting the gate drivers to the inverter controller (not shown) and / or to the controller 14 are implemented as connection pins extending orthogonally from the dielectric substrate and electrically connected to the first gate driver 38a and the second gate driver 38b using bond wires. It should be understood that, according to some embodiments, the first gate driver 38a and the second gate driver 38b may be located on a circuit board separate from the first power module 32a and may be connected to the first power module 32a via wires, contacts, or other conductors.

[0057] According to an exemplary embodiment, the first gate driver 38a is configured to control the first power switch chip 36a with a first switching rate as determined in block 112. The second gate driver 38b is configured to control the second power switch chip 36b with the second switching rate as determined in block 112. If block 112 is bypassed after block 108, default switching rates are configured. According to an example, the first switching rate and the second switching rate are stored in a non-transient memory of the first gate driver 38a and the second gate driver 38b for configuration using a programming device.According to another example, the first switching rate and the second switching rate are stored in the media 24 of the controller 14 for later reading and transmission to the first gate driver 38a and the second gate driver 38b. After block 110, the procedure 100 proceeds to block 114.

[0058] In block 114, the total power loss of the first power module 32a is determined. According to an exemplary embodiment, the total power loss is the sum of the total switching loss and the total conduction loss of the first power switch chip 36a and the second power switch chip 36b. Thus, the total power loss is determined at least partially based on the electrical characteristics of the first power switch chip 36a and the second power switch chip 36b, which are determined in block 104. After block 114, method 100 proceeds to block 116.

[0059] In block 116, an optimal mounting location for the first power module 32a is determined, at least partially, based on the total power loss of the first power module 32a, which is determined in block 114. The optimal mounting location is a location on the heat sink 30 that provides optimal cooling capacity for the first power module 32a. For example, the optimal mounting location is defined with respect to the coolant inlet 34a and the coolant outlet 34b of the heat sink 30. As discussed above, the temperature of the coolant entering at the coolant inlet 34a is lower than the temperature of the coolant exiting at the coolant outlet 34b, and there is a corresponding temperature gradient between the coolant inlet 34a and the coolant outlet 34b in the heat sink 30.According to an exemplary embodiment, the distance between the coolant inlet 34a and the optimal mounting location is negatively correlated with the total power loss of the power module 32a. In other words, if the first power module 32a has a high total power loss, the optimal mounting location is near the coolant inlet 34a, so that the first power module 32a is exposed to cooler coolant, which reduces the operating temperature of the first power module 32a. Reducing the operating temperature of the first power module 32a also reduces its total power loss. Thus, power switch chips with a total power loss greater than the specified chip total power loss threshold can be used to build the first power module 32a. After block 116, method 100 proceeds to block 118.

[0060] In block 118, the first power module 32a is attached to the heat sink 30 at the optimal mounting location determined in block 116. It should be understood that procedure 100 may also include additional steps, such as electrical connection of components, component testing, housing, encapsulation or uniform coating of components, quality assurance, and / or the like. After block 118, procedure 100 transitions to a ready state in block 120.

[0061] According to an exemplary embodiment, the method 100 is repeatedly restarted in block 102 to manufacture the multiple power modules 32 (e.g. the second power module 32b and the third power module 32c) and to attach each of the multiple power modules 32 to the heat sink 30 to complete the power inverter 20.

[0062] The method 100 of the present invention offers several advantages. By manufacturing the power inverter 20 according to the method 100, power switch chips can be used even if these have electrical properties outside of normally acceptable ranges, which increases manufacturing efficiency and reduces material usage while maintaining suitable cooling performance of the power inverter 20.

Claims

Method for manufacturing a power inverter (20), comprising: determining several electrical properties of both a first power switch chip (36a) and a second power switch chip (36b), wherein the several electrical properties include at least a conduction loss and a switching loss; and manufacturing the power inverter (20) at least using the first power switch chip (36a) and the second power switch chip (36b) at least partially based on the several electrical properties of both the first power switch chip (36a) and the second power switch chip (36b);wherein the manufacture of the power inverter (20) further comprises assembling at least one power module (32) containing the first power switch chip (36a) and the second power switch chip (36b), and manufacturing the power inverter (20) containing the at least one power module (32); characterized in that the assembly of the at least one power module (32) further comprises: comparing the line loss of the first power switch chip (36a) with a predetermined chip line loss threshold; comparing the line loss of the second power switch chip (36b) with the predetermined chip line loss threshold;Procuring one or more additional circuit breaker chips with a line loss less than or equal to the specified chip line loss threshold in response to the finding that the line loss of the first circuit breaker chip (36a) and the line loss of the second circuit breaker chip (36b) are greater than the specified chip line loss threshold, wherein the one or more additional circuit breaker chips are at least partially supplied by one of several suppliers on the basis of an inventory of each of the several suppliers, and assembling the at least one power module (32) using one or more of the additional circuit breaker chips. The method of claim 1, wherein determining the multiple electrical properties further comprises: testing both the first power switch chip (36a) and the second power switch chip (36b) to determine the multiple electrical properties of both the first power switch chip (36a) and the second power switch chip (36b). Method according to claim 1, wherein the assembly of the at least one power module (32) further comprises: assembling the at least one power module (32), wherein a switching loss of the first power switch chip (36a) is greater than or equal to a predetermined chip switching loss threshold and wherein a total switching loss of the first power switch chip (36a) and the second power switch chip (36b) is less than or equal to a predetermined total switching loss threshold. The method of claim 3, wherein the assembly of at least one power module (32) further comprises: assembling the at least one power module (32), wherein the at least one power module (32) further comprises a first gate driver (38a) for controlling the first power switch chip (36a) and a second gate driver (38b) for controlling the second power switch chip (36b); configuring the first gate driver (38a) for controlling the first power switch chip (36a) with a first switching rate; and configuring the second gate driver (38b) for controlling the second power switch chip (36b) with a second switching rate, wherein the second switching rate is lower than the first switching rate. The method of claim 4, wherein configuring the first gate driver (38a) and configuring the second gate driver (38b) further comprises: determining the first switching slew rate and the second switching slew rate such that the total switching loss of the first power switch chip (36a) and the second power switch chip (36b) is less than or equal to a predetermined total switching loss threshold, and such that a first voltage overshoot of the first power switch chip (36a) and a second voltage overshoot of the second power switch chip (36b) are less than or equal to a predetermined voltage overshoot threshold. The method of claim 1, wherein the assembly of at least one power module (32) further comprises: assembling the at least one power module (32), wherein a line loss of the first power switch chip (36a) is greater than or equal to a predetermined chip line loss threshold, wherein a line loss of the second power switch chip (36b) is less than or equal to the predetermined chip line loss threshold, and wherein a total line loss of the first power switch chip (36a) and the second power switch chip (36b) is less than or equal to a predetermined total line loss threshold. The method of claim 1, wherein the manufacture of the power inverter (20) further comprises: determining a total power loss of the at least one power module (32) at least partially based on the electrical properties of the first power switch chip (36a) and the electrical properties of the second power switch chip (36b); and attaching the at least one power module (32) to a heat sink (30) at least partially based on the total power loss of the at least one power module (32). The method according to claim 7, wherein attaching the at least one power module (32) to the heat sink (30) further comprises: determining an optimal attachment location of the at least one power module (32) to the heat sink (30) with respect to a coolant inlet (34a) of the heat sink (30) and a coolant outlet of the heat sink (30), wherein a distance between the coolant inlet (34a) and the optimal attachment location is negatively correlated with the total power loss of the at least one power module (32).

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