BIASING TECHNIQUES FOR LOW-DISTORTION AMPLIFIERS

Abstract

Biasing techniques for reducing distortion in amplifiers are described. A control loop is used to keep the sum of the collector currents of the input differential pair constant. The control loop includes an error correction amplifier that compares the sum of the input differential pair collector current with a reference current and adjusts a control voltage at a control terminal of a transistor to keep the current equal to or proportional to the reference current.

Description

AREA OF REVELATION

[0001] This document concerns the design of electronic circuits and, in particular, techniques for biasing amplifier circuits. BACKGROUND

[0002] Low-distortion amplifiers are critical components in many analog and mixed-signal systems. They are widely used, for example, in the analog front end of high-resolution ADCs and DACs. In these applications, the amplifier must faithfully preserve the signal's amplitude and phase information without introducing additional harmonics.

[0003] There are several non-idealities that can cause an amplifier to distort the signal, such as bias current modulation, nonlinearity in the transistors, noise, etc. Bias current modulation is one of the dominant distortion mechanisms in certain amplifier topologies. It arises because the bias current of the input differential pair can modulate with the input signal or other signals, resulting in signal-dependent distortion.

[0004] To mitigate this problem, certain biasing techniques and compensation schemes have been developed. These techniques typically aim to keep the bias current and / or the operating points of the critical transistors constant across the signal swing. Some common approaches include the use of regulated cascode circuits, the inclusion of negative feedback, and the addition of correction circuits to cancel distortion-causing mechanisms.

[0005] By carefully analyzing the underlying causes of distortion and designing compensation techniques, the THD (Total Harmonic Distortion) performance of amplifiers can be drastically improved. Low-distortion amplifiers with THD in the range of -100 dB or below have been demonstrated. These ultra-low-distortion amplifiers enable high-performance data conversion and signal conditioning systems. SUMMARY OF REVELATION

[0006] This disclosure relates to biasing techniques for reducing distortion in amplifiers. The inventors of the present invention have recognized that a control loop can be used to maintain the sum of the collector currents of the input differential pair constant. The control loop includes an error correction amplifier that compares the sum of the input differential pair collector current to a reference current and adjusts a control voltage at a control terminal of a transistor to maintain the current equal to or proportional to the reference current.

[0007] In some aspects, this disclosure relates to an amplifier circuit comprising: a differential pair of transistors configured and arranged to generate a summed current from individual ones of the differential pair of transistors; a transistor coupled to the differential pair of transistors; and an error correction amplifier coupled to a control terminal of the transistor and configured to: compare a representation of the summed current with a representation of a reference current; and adjust, based on the comparison, a voltage at the control terminal of the transistor.

[0008] In some aspects, this disclosure relates to a method for biasing an amplifier circuit, the method comprising: coupling a transistor to a differential pair of transistors; generating a summed current from the differential pair of transistors; comparing, with an error correction amplifier coupled to a control terminal of the transistor, a representation of the summed current with a representation of a reference current; and adjusting, based on the comparison and with the error correction amplifier, a voltage at the control terminal of the transistor.

[0009] In some aspects, this disclosure relates to an amplifier circuit comprising: a differential pair of transistors configured and arranged to generate a summed current from individuals of the differential pair of transistors, the differential pair of transistors having a first control terminal for receiving a first input signal and a second control terminal for receiving a second input signal, the differential pair of transistors configured and arranged to generate a summed current; a transistor coupled to the differential pair of transistors, the transistor having a third control terminal; a first sense resistor coupled to the differential pair of transistors, the first sense resistor configured to generate a first voltage in response to the summed current from the differential pair of transistors;a reference current source coupled to the transistor and configured to generate a reference current; a second sense resistor coupled to the reference current source, the second sense resistor configured to generate a second voltage in response to the reference current; and an error correction amplifier comprising: a non-inverting input coupled to the first sense resistor and configured to receive the first voltage generated by the first sense resistor; and an inverting input coupled to the second sense resistor and configured to receive the second voltage generated by the second sense resistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals with different letter suffixes may represent different instances of similar components. The drawings generally illustrate, by way of example but not limitation, various embodiments discussed in this document. Fig. 1 is a circuit diagram of an example operational amplifier circuit. Fig. 2 is an example of an existing amplifier circuit. Fig. 3 is a circuit diagram of an example amplifier circuit that may implement various techniques of this disclosure. Fig. 4 is a circuit diagram of another example of an amplifier circuit that may implement various techniques of this disclosure. Fig. 5 is a circuit diagram of another example of an amplifier circuit that may implement various techniques of this disclosure. Fig. 6 illustrates an aspect of the subject matter according to one embodiment. Fig. 7 is a flowchart of an example of a method for operating an amplifier circuit. DETAILED DESCRIPTION

[0011] The present inventors have recognized that amplifier distortion can occur when a bias current of an input differential pair modulates with an input signal. This modulation is caused by a finite output impedance of a bias current source and parasitic capacitances that couple signals into the bias node.

[0012] This disclosure relates to biasing techniques for reducing distortion in amplifiers. The inventors of the present invention have recognized that a control loop can be used to maintain the sum of the collector currents of the input differential pair constant. The control loop includes an error correction amplifier that compares the sum of the input differential pair collector current to a reference current and adjusts a control voltage at a control terminal of a transistor to maintain the current equal to or proportional to the reference current.

[0013] Fig. Figure 1 is a circuit diagram of an exemplary operational amplifier circuit. The operational amplifier circuit 100 is configured for single-ended to differential conversion. In such a configuration, the reference voltage VREF is a fixed DC voltage, and the input node receives a time-varying input signal VIN. Thus, both the VP and VN nodes vary with the input signal VIN. Although many nonidealities can cause distortion, bias current modulation is one of the dominant sources of distortion in this configuration.

[0014] Fig. Figure 2 is an example of an existing amplifier circuit. The origin of the tail current modulation and distortion is explained as follows with reference to the amplifier circuit 200 of Fig. 2. For simplicity, the following is assumed: Vin(t)=Vincos(ωt) where V inis the amplitude of the input signal and ω is the signal frequency. The voltage of the non-inverting node of the operational amplifier is given by: Vp(t)=Vpcos(ωt) where V p is the amplitude, which is a scaled version of V in depends on R G , R F and V ocm .

[0015] Furthermore, the differential voltage at the non-inverting node and the inverting node is approximately Vdm(t)=Vdmcos(ωt) where V dm is the amplitude of the differential signal, which is a function of the output voltage V (vop, von) and the loop gain A L (s) at the signal frequency. Vdm=|V(vop,von)(t)AL(s)|

[0016] For simplicity, assume that V in (t), V p (t), and V dm(t) are in phase, ie the phase shift is ignored. To maintain a reasonably low distortion, V dm usually less than ten millivolts. The voltage V p is usually much larger than V dm , and thus the op-amp common-mode voltage can be approximated as the voltage at the non-inverting node, or: Vcm(t)=Vpcos(ωt)

[0017] Collector currents of the transistors Q1 and Q2 of the input stage of Fig. 2 are given as follows: Ic1=β1+βItail(t)1+e−Vdm(t)VT Ic2=β1+βItail(t)1+eVdm(t)VT

[0018] Therefore, the output voltage of the first stage is given by: Vod(t)=β1+βItail(t)RceVdm(t)2VT−e−Vdm(t)2VTeVdm(t)2VT+e−Vdm(t)2VT

[0019] The exponential function expansion formula leads to the following: e−Vdm(t)2VT=1−Vdm(t)2VT+12(Vdm(t)2VT)2−16(Vdm(t)2VT)3+124(Vdm(t)2VT)4+... eVdm(t)2VT=1+Vdm(t)2VT+12(Vdm(t)2VT)2+16(Vdm(t)2VT)3+124(Vdm(t)2VT)4+...

[0020] Using equations [9] and

[10] we get the following: e−Vdm(t)2VT−e−Vdm(t)2VT=Vdm(t)VT+124(Vdm(t)2VT)4+... eVdm(t)2VT+e−Vdm(t)2VT=2+14(Vdm(t)VT)2+1192(Vdm(t)VT)4+...

[0021] Will V dm << V T assumed, it follows eVdm(t)2VT−e−Vdm(t)2VT≈Vdm(t)VT eVdm(t)2VT+e−Vdm(t)2VT≈2

[0022] Using equations [8],

[13] ,

[14] , and assuming that β >> 1, one obtains Vod(t)≈Itail(t)RcVdm(t)2VT

[0023] The above approximation given by equations

[13] and

[14] leads to a negligible error as long as V dm (t) compared to the threshold voltage V Tis sufficiently small. In a non-restrictive numerical example, assuming that V dm (t) = 10 mV at room temperature, eVdm(t)2VT−eVdm(t)2VT=e1052−e−1052=0.387 and Vdm(t)VT=0.385, and the error is only 0.5%. However, eVdm(t)2VT+e−Vdm(t)2VT=e1052+e−1052=2.037, which only results in an error of 1.8%.

[0024] Due to the finite Early voltage of Q3 and the parasitic capacitance at node E, the bias current of the input differential pair is a nonlinear function of the common-mode voltage V cm (t) with a coefficient of g1, g2, ... , g n The tail current is given by the following: Itail(t)=Idc+g1Vcm(t)+g2Vcm(t)+g2Vcm2(t)+g3Vcm3(t)+...

[0025] For simplicity, ignore higher order harmonic components for a moment and assume the following: Itail(t)≈Idc+g1Vcm(t)

[0026] The combination of equations

[15] and

[17] leads to the following: Vod(t)=[Idc+g1Vcm(t)]cVdm(t)2VT

[0027] Using equations [3], [5] and

[18] we get Vod(t)=IdcRcVdm2VTcos(ωt)+g1RcVdmVp2VTcos2(ωt)

[0028] Therefore, Vod(t)=IdcRcVdm2VTcos(ωt)+g1RcVdmVp4VT+g1RcVdmVp4VTcos(2ωt)

[0029] Thus, the intermodulation between the bias current and the voltage across the input differential pair leads to second-order harmonics and a DC offset. The above derivation considers only the DC and fundamental components of the bias current. If higher-order harmonics are included in the analysis, the overall harmonic distortion will be even worse. Therefore, suppressing bias current modulation is essential for the design of low-distortion amplifiers.

[0030] In the above analysis, the base-collector capacitance C µ of the input transistor is ignored. In addition to being process-dependent, the capacitance is linearly proportional to the device size and nonlinearly dependent on the reverse bias of the base-collector junction.

[0031] Fig. Figure 3 is a circuit diagram of an example of an amplifier circuit that can implement various techniques of this disclosure. In the input stage, a control loop is used to keep the sum of the collector current of the input differential pair constant. The control loop includes at least one input differential pair, a reference current, a sense resistor, an error correction amplifier, and a transistor, e.g., a pass transistor. The Fig. The amplifier circuit 300 shown in Figure 3 comprises bipolar transistors.

[0032] Amplifier circuit 300 includes a differential pair of transistors including transistor Q1 and transistor Q2. Transistor Q1 is configured to receive a positive input voltage Vp, and transistor Q2 is configured to receive a negative input voltage Vn. The differential pair of transistors Q1, Q2 is configured and arranged to generate a summed current from individual ones of the differential pair of transistors at node 302.

[0033] In some examples, amplifier circuit 300 includes a first sense resistor Rs coupled to the differential pair of transistors, wherein the first sense resistor Rs is configured to generate the representation of the summed current at node 302 from the differential pair of transistors.

[0034] Amplifier circuit 300 further includes a transistor Q3, e.g., a pass transistor, coupled to the differential pair of transistors. For example, the emitter terminals of the differential pair of transistors are coupled together at node E, and node E is further coupled to the collector terminal of transistor Q3.

[0035] An error correction amplifier 304 is coupled to a control terminal 310 of transistor Q3, e.g., a base terminal. The summed current of the input differential pair of transistors is sensed, such as through sense resistor Rs, and applied to the non-inverting input of error correction amplifier 304. Error correction amplifier 304 compares a representation of the summed current to a representation of a reference current, such as generated by a reference current source 306, which is applied to an inverting input of error correction amplifier 304. In some examples, amplifier circuit 300 includes a second sense resistor Rr coupled to reference current source 306, wherein the second sense resistor is configured to generate the representation of the reference current.

[0036] As in the Fig. As shown in the example shown in Figure 3, the reference current source 306 is coupled to the control terminal 310 of transistor Q3, e.g., the emitter of the transistor. The error correction amplifier 304 then adjusts the control voltage, e.g., base voltage, of transistor Q3 based on the comparison to keep the current equal to or proportional to the reference current.

[0037] In some examples, the collector of transistor Q1 is coupled to a first resistor Rd, and the collector of transistor Q2 is coupled to a second resistor Rd.

[0038] The amplifier circuit 300 further includes a gain stage 308 configured to receive a differential output voltage Vod generated between the collector of transistor Q1 and the collector of transistor Q2. The gain stage 308 generates differential output voltages Vop and Von.

[0039] In this way, the amplifier circuit 300 of Fig. 3 provides a low-distortion input stage with bias current control and has at least three advantages over existing techniques: 1) higher output impedance; 2) wider input common-mode range; 3) insensitive to the parasitic capacitances on the emitters of Q1, Q2 and the collector of Q3.

[0040] The displacement current through the capacitance is outside the control loop in Fig. 2, which worsens the total harmonic distortion (THD). To further improve the THD, as shown in Fig. 5, a second pair of transistors, e.g., replicas of the input transistors Q1 and Q2, may be included. The replicas remodulate the reference current of the control loop, thereby canceling the capacitive base-collector current of the input differential pair.

[0041] Fig. 4 is a circuit diagram of another example of an amplifier circuit that may implement various techniques of this disclosure. Fig. 4 has features similar to those described above with reference to Fig. 3, and similar reference numerals are used for such features. For the sake of brevity, these features will not be described again in detail.

[0042] In the Fig. 4, the amplifier circuit 400 comprises field effect transistors (FET) in contrast to the bipolar transistors (BJT) of the amplifier circuit 300 of Fig. 3. In particular, the differential pair of transistors in Fig. 4 FETs M1 and M2, and the BJT Q3 of Fig. 3 is replaced by FET M3. The source terminals of FETs M1 and M2 are connected to node E, and node E is coupled to the drain terminal of FET M3.

[0043] The error correction amplifier 304 is coupled to the control terminal 310 of the FET M3, e.g., the gate terminal. The amplifier circuit 400 operates similarly to the amplifier circuit 300 of Fig. 3 and will not be described in detail again for the sake of brevity.

[0044] Fig. 5 is a circuit diagram of another example of an amplifier circuit that may implement various techniques of this disclosure. Fig. 5 has features similar to those described above with reference to Fig. 3, and similar reference numerals are used for such features. For the sake of brevity, these features will not be described again in detail.

[0045] Amplifier circuit 500 includes a second pair of transistors Q1d and Q2d. Transistor Q1d has a control terminal 502 coupled to a control terminal 504 of transistor Q1 of the differential pair of transistors. Transistor Q2d has a control terminal 506 coupled to a control terminal 508 of transistor Q2 of the differential pair of transistors. Control terminal 502 of transistor Q1d is configured to receive input signal Vp, and control terminal 506 of transistor Q2d is configured to receive input signal Vn.

[0046] A first summed current generated by the input differential pair of transistors is sensed, such as through sense resistor Rs, and applied to the non-inverting input of error correction amplifier 304. Similar to the differential pair of transistors Q1 and Q2, the pair of transistors Q1d and Q2d is configured and arranged to generate a second summed current at node 510 from individual ones of transistors Q1d and Q2d. The summed current at node 510, along with the reference current from reference current source 306, is applied to the inverting input of error correction amplifier 304.

[0047] The error correction amplifier 304 compares a representation of the first summed current with a sum of a representation of the reference current and the second summed current. As in the Fig. As shown in the example shown in Figure 5, the reference current source 306 is coupled to the control terminal 310 of transistor Q3, e.g., the emitter of the transistor. The error correction amplifier 304 then adjusts the control voltage, e.g., base voltage, of transistor Q3 based on the comparison to keep the current equal to or proportional to the reference current.

[0048] In some examples, amplifier circuit 300 includes a second sense resistor Rr coupled to reference current source 306, wherein the second sense resistor is configured to generate the representation of the reference current.

[0049] In some examples, individual ones of the second pair of transistors are replicas of individual ones of the first differential pair of transistors. That is, transistors Q1d and Q2d are replica transistors of transistors Q1 and Q2. A "replica transistor" refers to a transistor designed and configured to mirror the electrical characteristics and behavior of another transistor within a circuit. This includes having substantially identical dimensions and layout to the target transistor, thereby ensuring that the behavior of the replica transistor closely matches that of the target transistor under various operating conditions.

[0050] The pair of transistors Q1d and Q2d are included, for example, as replicas of the input transistors Q1 and Q2 to further improve the THD. The replicas remodulate the control loop's reference current, thereby canceling the capacitive base-collector current of the input differential pair Q1 and Q2.

[0051] Fig. 6 is a circuit diagram of another example of an amplifier circuit that may implement various techniques of this disclosure. Fig. 6 has features which correspond to the features described above with reference to Fig. 5, and similar reference numerals are used for such features. For the sake of brevity, these features will not be described again in detail.

[0052] In the Fig. 6, the amplifier circuit 600 comprises field effect transistors (FET) in contrast to the bipolar transistors (BJT) of the amplifier circuit 500 of Fig. 5. In particular, the differential pair of transistors in Fig. 6 FETs M1 and M2, which are coupled to FETs M1d and M2d respectively, and the BJT Q3 of Fig. 5 is replaced by FET M3. The source terminals of FETs M1 and M2 are connected to node E, and node E is coupled to the drain terminal of FET M3.

[0053] The error correction amplifier 304 is coupled to the control terminal 310 of the FET M3, e.g., the gate terminal. The amplifier circuit 600 operates similarly to the amplifier circuit 500 of Fig. 5 and will not be described in detail again for the sake of brevity.

[0054] Fig. 7 is a flowchart of an example method 700 for operating an amplifier circuit. At block 702, the method 700 includes coupling a transistor to a differential pair of transistors.

[0055] At block 704, the method 700 includes generating a summed current from the differential pair of transistors.

[0056] At block 706, the method 700 includes comparing, with an error correction amplifier coupled to a control terminal of the transistor, a representation of the summed current with a representation of a reference current.

[0057] At block 708, the method 700 includes adjusting, based on the comparison and with the error correction amplifier, a voltage at the control terminal of the transistor.

[0058] In some examples, method 700 includes coupling a first sense resistor to the differential pair of transistors to generate the representation of the summed current from the differential pair of transistors.

[0059] In some examples, the method 700 includes coupling a reference current source to the transistor and generating, via the reference current source, the reference current.

[0060] In some examples, method 700 includes coupling a second sense resistor to the reference current source to generate the representation of the reference current.

[0061] In some examples, the differential pair of transistors is a first differential pair of transistors, the first differential pair of transistors having a first control terminal for receiving a first input signal and a second control terminal for receiving a second input signal, and the summed current is a first summed current, and the method 700 further includes: coupling a second pair of transistors having a first control terminal to the first control terminal of the first differential pair of transistors; coupling a second control terminal to the second control terminal of the first differential pair of transistors; receiving, via the first control terminal of the second pair of transistors, the first input signal; receiving, via the second control terminal of the second pair of transistors, the second input signal;generating, via the second pair of transistors, a second summed current from individual ones of the second pair of transistors, wherein comparing, with the error correction amplifier, the representation of the summed current with the representation of the reference current includes: ; Comparing a representation of the first summed current with a sum of the representation of the reference current and the second summed current.

[0062] In some examples, coupling the transistor to the differential pair of transistors includes coupling a bipolar transistor to a differential pair of bipolar transistors.

[0063] In some examples, coupling the transistor to the differential pair of transistors includes coupling a field effect transistor to a differential pair of field effect transistors. Various comments

[0064] Each of the non-limiting claims or examples described herein may stand alone or may be combined in various permutations or combinations with one or more of the other examples.

[0065] The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples." Such examples may include elements in addition to those shown or described. However, the inventors of the present invention also contemplate examples in which only the elements shown or described are provided.In addition, the inventors of the present invention also contemplate examples that use any combination or permutation of the elements shown or described (or one or more claims thereof), either with reference to a particular example (or one or more claims thereof) or with reference to other examples (or one or more claims thereof) shown or described herein.

[0066] In the event of any inconsistency between the use of this document and any other documents incorporated by reference, the use in this document shall prevail.

[0067] Throughout this document, the terms "a" or "an" are used, as is customary in patent documents, to include one or more than one, regardless of any other instances or uses of "at least one" or "one or more." Throughout this document, the term "or" is used to refer to a non-exclusive or, such that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise specified. Throughout this document, the terms "including" and "in which" are used as the plain English equivalents of the respective terms "having" and "wherein."Furthermore, the terms "including" and "comprising" in the following claims are open-ended terms, meaning that a system, apparatus, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim is still considered within the scope of that claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc., are used merely as labels and are not intended to be numerically specific to their objects.

[0068] Method examples described herein may be at least partially machine- or computer-implemented. Some examples may include a computer-readable medium or a machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. Implementation of such methods may include code such as microcode, assembly language code, high-level language code, or the like. Such code may include computer-readable instructions for performing various methods. The code may form portions of computer program products. Further, in one example, the code may be tangibly stored on one or more transient, non-transitory, or non-transitory tangible computer-readable media, such as during execution or at other times.Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact discs and digital video discs), magnetic cartridges, memory cards or flash drives, random access memories (RAMs), read-only memories (ROMs), and the like.

[0069] The above description is intended to be illustrative and not restrictive. For example, the examples described above (or one or more claims thereof) may be used in combination with one another. Other embodiments may, for example, be utilized by those of ordinary skill in the art after reviewing the above description. The Abstract is provided to comply with 37 CFR §1.72(b) to enable the reader to quickly appreciate the nature of the technical disclosure. It is presented with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as an intent that any unclaimed disclosed feature is essential to any claim.Rather, the subject matter of the invention may lie in fewer than all features of a particular disclosed embodiment. Accordingly, the following claims are hereby incorporated into the Detailed Description as examples or embodiments, each claim standing on its own as a separate embodiment, and it is intended that such embodiments may be combined with one another in various combinations and permutations. The scope of the invention should be determined by reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0070] Aspects of the present disclosure relate to biasing techniques for reducing distortion in amplifiers. A control loop is used to maintain the sum of the input differential pair collector currents constant. The control loop includes an error correction amplifier that compares the sum of the input differential pair collector current to a reference current and adjusts a control voltage at a control terminal of a transistor to maintain the current equal to or proportional to the reference current.

Claims

[1] Amplifier circuit comprising: a differential pair of transistors constructed and arranged to generate a summed current from individual ones of the differential pair of transistors; a transistor coupled to the differential pair of transistors; and an error correction amplifier coupled to a control terminal of the transistor and configured to: Comparing a representation of the summed current with a representation of a reference current; and Adjusting, based on the comparison, a voltage at the control terminal of the transistor. [2] An amplifier circuit according to claim 1, comprising: a first sense resistor coupled to the differential pair of transistors, the first sense resistor configured to generate the representation of the summed current from the differential pair of transistors. [3] An amplifier circuit according to claim 1 or 2, comprising: a reference current source coupled to the transistor and configured to generate the reference current. [4] An amplifier circuit according to claim 3, comprising: a second sense resistor coupled to the reference current source, the second sense resistor configured to generate the representation of the reference current. [5] An amplifier circuit according to any one of claims 1 to 4, wherein the differential pair of transistors comprises bipolar transistors. [6] An amplifier circuit according to any one of claims 1 to 4, wherein the differential pair of transistors comprises field effect transistors. [7] The amplifier circuit of any one of claims 1 to 6, wherein the differential pair of transistors is a first differential pair of transistors, the first differential pair of transistors having a first control terminal for receiving a first input signal and a second control terminal for receiving a second input signal, and the summed current is a first summed current, the amplifier circuit further comprising: a second pair of transistors having a first control terminal coupled to the first control terminal of the first differential pair of transistors and a second control terminal coupled to the second control terminal of the first differential pair of transistors, the first control terminal of the second pair of transistors being for receiving the first input signal and the second control terminal of the second pair of transistors being for receiving the second input signal, wherein the second pair of transistors is configured and arranged to generate a second summed current from individual ones of the second pair of transistors, and wherein the error correction amplifier, which is configured to compare the representation of the summed current with the representation of the reference current, is configured to: Comparing a representation of the first summed current with a sum of the representation of the reference current and the second summed current. [8] An amplifier circuit according to claim 7, wherein individual ones of the second pair of transistors are replicas of individual ones of the first differential pair of transistors. [9] A method for biasing an amplifier circuit, the method comprising: Coupling a transistor to a differential pair of transistors; Generating a summed current from the differential pair of transistors; Comparing, with an error correction amplifier coupled to a control terminal of the transistor, a representation of the summed current with a representation of a reference current; and Adjusting, based on the comparison and with the error correction amplifier, a voltage at the control terminal of the transistor. [10] A method according to claim 9, comprising: Coupling a first sense resistor to the differential pair of transistors to generate the representation of the summed current from the differential pair of transistors. [11] A method according to claim 9 or 10, comprising: coupling a reference current source to the transistor; and Generating the reference current via the reference current source. [12] A method according to any one of claims 9 to 11, comprising: Coupling a second sense resistor to a reference current source to generate the representation of the reference current. [13] The method of any one of claims 9 to 12, wherein the differential pair of transistors is a first differential pair of transistors, the first differential pair of transistors having a first control terminal for receiving a first input signal and a second control terminal for receiving a second input signal, and the summed current is a first summed current, the method further comprising: coupling a second pair of transistors having a first control terminal to the first control terminal of the first differential pair of transistors; coupling a second control terminal to the second control terminal of the first differential pair of transistors; Receiving, via the first control terminal of the second pair of transistors, the first input signal; Receiving, via the second control terminal of the second pair of transistors, the second input signal; generating, via the second pair of transistors, a second summed current from individual ones of the second pair of transistors; wherein comparing, with the error correction amplifier, the representation of the summed current with the representation of the reference current includes: Comparing a representation of the first summed current with a sum of the representation of the reference current and the second summed current. [14] The method of claim 13, wherein individual ones of the second pair of transistors are replicas of individual ones of the first differential pair of transistors. [15] The method of any one of claims 9 to 14, wherein coupling the transistor to the differential pair of transistors includes: Coupling a bipolar transistor with a differential pair of bipolar transistors. [16] The method of any one of claims 9 to 14, wherein coupling the transistor to the differential pair of transistors includes: Coupling a field-effect transistor with a differential pair of field-effect transistors. [17] Amplifier circuit comprising: a differential pair of transistors configured and arranged to generate a summed current from individual ones of the differential pair of transistors, the differential pair of transistors having a first control terminal for receiving a first input signal and a second control terminal for receiving a second input signal, the differential pair of transistors configured and arranged to generate a summed current; a transistor coupled to the differential pair of transistors, the transistor having a third control terminal; a first sense resistor coupled to the differential pair of transistors, the first sense resistor configured to generate a first voltage in response to the summed current from the differential pair of transistors; a reference current source coupled to the transistor and configured to generate a reference current; a second sense resistor coupled to the reference current source, the second sense resistor configured to generate a second voltage in response to the reference current; and an error correction amplifier with: a non-inverting input coupled to the first sense resistor and configured to receive the first voltage generated by the first sense resistor; and an inverting input coupled to the second sense resistor and configured to receive the second voltage generated by the second sense resistor. [18] The amplifier circuit of claim 17, wherein the differential pair of transistors is a first differential pair of transistors, the first differential pair of transistors having a first control terminal for receiving a first input signal and a second control terminal for receiving a second input signal, and the summed current is a first summed current, the amplifier circuit further comprising: a second pair of transistors having a first control terminal coupled to the first control terminal of the first differential pair of transistors and a second control terminal coupled to the second control terminal of the first differential pair of transistors, the first control terminal of the second pair of transistors being for receiving the first input signal and the second control terminal of the second pair of transistors being for receiving the second input signal, wherein the second pair of transistors is configured and arranged to generate a second summed current from individual ones of the second pair of transistors, and wherein the error correction amplifier, which is configured to compare the representation of the summed current with the representation of the reference current, is configured to: Comparing a representation of the first summed current with a sum of the representation of the reference current and the second summed current. [19] An amplifier circuit according to claim 18, wherein individual ones of the second pair of transistors are replicas of individual ones of the first differential pair of transistors. [20] An amplifier circuit according to any one of claims 17 to 19, wherein the differential pair of transistors comprises bipolar transistors.

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