Integrated circuit (IC) with corrugated channel structures with controlled doping profile via channel topography

Abstract

An integrated circuit (IC) device including one or more corrugated channel structures formed in or over a semiconductor substrate, wherein a corrugated channel structure includes a first sidewall, a second sidewall, and a top surface. In one example, the corrugated channel structure is provided with a substantially uniform distribution profile of a dopant across a horizontal plane from the first sidewall to the second sidewall.

Claims

[1] A method of manufacturing an integrated circuit (IC), comprising: Forming a corrugated channel structure over a semiconductor substrate, the corrugated channel structure including a sidewall and a top surface; Forming an upper oxide cap over the upper surface; implanting a first dopant into the sidewall in a first implantation; Removing the upper oxide cap; and Implanting a second dopant into the upper surface. [2] The method of claim 1, wherein the corrugated channel structure is one of a first corrugated channel structure and an adjacent second corrugated channel separated by a trench including a bottom surface, and further comprising forming a bottom oxide cap covering the bottom surface concurrently with forming the top oxide cap. [3] The method of claim 2, further comprising removing the lower oxide cap simultaneously with removing the upper oxide cap. [4] The method of claim 1, wherein the top oxide cap is formed by first forming a conformal oxide layer over the top surface and the sidewall surface and then selectively removing the conformal oxide layer over the sidewall surface. [5] The method of claim 4, wherein the conformal oxide layer is removed selectively over the sidewall surface by a wet etch. [6] The method of claim 4, wherein the conformal oxide layer is formed by atomic layer deposition (ALD). [7] The method of claim 1, wherein the upper oxide cap is formed by selective physical vapor deposition (PVD) of the upper surface. [8] The method of claim 2, wherein the upper oxide cap and the lower oxide cap are removed by a wet etch. [9] The method of claim 2, wherein the upper oxide cap and the lower oxide cap are removed by plasma etching. [10] A method of manufacturing an integrated circuit (IC), comprising: Forming a plurality of corrugated channel structures over a semiconductor substrate, the plurality of corrugated channel structures separated by respective trenches formed between adjacent corrugated channel structures, each trench including a bottom surface and each corrugated channel structure including a first sidewall, a second sidewall, and a top surface; Forming a conformal oxide layer over the corrugated channel structures; selectively removing the conformal oxide layer from the first and second sidewalls of the respective corrugated channel structures, wherein a remaining portion of the conformal oxide layer forms an upper oxide cap over the upper surface of each respective corrugated channel structure and a lower oxide cap over the lower surface of each respective trench; Implanting a first dopant into the first and second sidewalls of the respective corrugated channel structures using a non-zero beamline tilt angle with respect to a surface normal of the semiconductor substrate; Removing the upper and lower oxide caps; and Implanting a second dopant into the upper surfaces of the respective corrugated channel structures and into the lower surfaces of the respective trenches using a beamline tilt angle approximately parallel to the surface normal of the semiconductor substrate. [11] The method of claim 10, wherein the conformal oxide layer is formed by atomic layer deposition (ALD). [12] The method of claim 10, wherein the conformal oxide layer is formed of horizontal portions having a first density formed over the top surfaces and the bottom surfaces and vertical portions having a second density less than the first density formed over the first and second sidewalls of the respective corrugated channel structures. [13] The method of claim 10, wherein the conformal oxide layer is selectively removed from the first and second sidewalls of the respective corrugated channel structures using a wet etch. [14] The method of claim 10, wherein the upper oxide cap and the lower oxide cap are removed by a wet etch. [15] The method of claim 13, wherein the upper oxide cap and the lower oxide cap are removed by a plasma etch. [16] A method of manufacturing an integrated circuit (IC), comprising: Forming a plurality of corrugated channel structures over a semiconductor substrate, the plurality of corrugated channel structures separated by respective trenches formed between adjacent corrugated channel structures, each trench including a bottom side and each corrugated channel structure including a first sidewall, a second sidewall, and a top surface; selectively forming an upper oxide cap over the upper surface of each respective corrugated channel structure and a lower oxide cap over the lower side of each respective trench; Implanting one or more dopants into the first and second sidewalls of the respective corrugated channel structures using one or more beamline tilt angles with respect to a surface normal of the semiconductor substrate; Removing the upper and lower oxide caps; and Implanting, in a vertical implantation, one or more dopants into the upper surfaces of the respective corrugated channel structures and into the lower sides of the respective trenches. [17] The method of claim 16, wherein the upper oxide cap and the lower oxide cap are removed by physical vapor deposition (PVD). [18] The method of claim 16, wherein the upper oxide caps and the lower oxide caps have a first thickness that is greater than a second thickness of sidewall oxide portions formed over the first and second sidewalls of the respective corrugated channel structures. [19] The method of claim 18, wherein the upper oxide cap and the lower oxide cap are removed by a wet etch. [20] The method of claim 19, wherein the sidewall oxide portions are removed by a plasma etch.

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