Semiconductor device structure with nanostructure and method for its formation

Abstract

A method for forming a semiconductor device structure is described. The method comprises providing a substrate, a first nanostructure, a second nanostructure, and a first gate stack. The first nanostructure is located between the substrate and the second nanostructure, and the first gate stack encloses both the first and second nanostructures. The method includes removing the first gate stack and end sections of the first nanostructure. The method includes partially removing the second nanostructure to round off a first corner of the second nanostructure. The first corner becomes a first rounded corner after the second nanostructure has been partially removed. The method includes removing the first nanostructure. The method includes forming a second gate stack above the substrate and enclosing the second nanostructure.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority over the preliminary US patent application No. 63 / 655,147, filed on June 3, 2024, entitled “Sheet Rounding Tuning by Multi Step Sheet Formation”, which is incorporated by reference into the present application. BACKGROUND OF THE INVENTION

[0002] The integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have spawned generations of ICs, each featuring smaller and more complex circuits than the previous one. However, these advances have also increased the complexity of IC processing and manufacturing.

[0003] Over the course of IC evolution, functional density (i.e., the number of interconnected components per chip area) has generally increased, while geometric size (i.e., the smallest component (or trace) that can be manufactured using a fabrication process) has decreased. This miniaturization process generally offers advantages by increasing production efficiency and reducing associated costs.

[0004] However, as element sizes become ever smaller, manufacturing processes become increasingly difficult. Therefore, producing reliable semiconductor devices in ever smaller sizes is a challenge. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figures 1A-1E are cross-sectional views of different stages of a process for forming a semiconductor device structure according to some embodiments. Fig. 1A-1 is a top view of the semiconductor device structure of Fig. 1A according to some embodiments. Fig. 1A-2 is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 1A-1 illustrated. Fig. 1E-1 is a top view of the semiconductor device structure of Fig. 1E according to some embodiments. Fig. 2A is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 1E-1 illustrated. Fig. Figures 2A-2C are cross-sectional views of different stages of a process for forming a semiconductor device structure according to some embodiments. Fig. 2C-1 is a top view of the semiconductor device structure of Fig. 2C according to some embodiments. Fig. 2C-2 is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line YY' in Fig. 2C-1 illustrated. Fig. 3A-3D are cross-sectional views of different stages of a process for forming a semiconductor device structure according to some embodiments. Fig. 3C-1 is a top view of the semiconductor device structure of Fig. 3C according to some embodiments. Fig. 3C-2 is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 3C-1 illustrated. Fig. 3D-1 is a top view of the semiconductor device structure of Fig. 3D according to some embodiments. Fig. 3D-2 is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 3D-1 illustrated. Fig. Figures 4A-4H are cross-sectional views of different stages of a process for forming a semiconductor device structure according to some embodiments. Fig. 4A-1 is a top view of the semiconductor device structure of Fig. 4A according to some embodiments. Fig. 4A-2 is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 4A-1 illustrated. Fig. 4G-1 is a top view of the semiconductor device structure of Fig. 4G according to some embodiments. Fig. 4G-2 is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 4G-1 illustrated. Fig. 4H-1 is a top view of the semiconductor device structure of Fig. 4H according to some embodiments. Fig. 4H-2 is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 4H-1 illustrated. Fig. Figures 5A-5D are cross-sectional views of different stages of a process for forming a semiconductor device structure according to some embodiments. Fig. 5C-1 is a top view of the semiconductor device structure of Fig. 5C according to some embodiments. Fig. 5C-2 is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 5C-1 illustrated. Fig. 5D-1 is a top view of the semiconductor device structure of Fig. 5D according to some embodiments. Fig. 5D-2 is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 5D-1 illustrated. Fig. Figures 6A-6D are cross-sectional views of different stages of a process for forming a semiconductor device structure according to some embodiments. Fig. 6C-1 is a top view of the semiconductor device structure of Fig. 6C according to some embodiments. Fig. 6C-2 is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 6C-1 illustrates. Fig. 6D-1 is a top view of the semiconductor device structure of Fig. 6D according to some embodiments. Fig. 6D-2 is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 6D-1 illustrated. Fig. Figure 7A is a cross-sectional view of a semiconductor device structure according to some embodiments. Fig. Figure 7B is a top view of the semiconductor device structure of Fig. 7A according to some embodiments. Fig. 7C is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 7B illustrates this. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and are not to be understood as limiting. For example, the formation of a first element above or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements may not be in direct contact.Furthermore, reference numerals and / or letters may be repeated in the various examples in this disclosure. This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, to simplify the description, spatially related terms such as "under," "below," "lower," "above," "upper," and the like may be used to describe the relationship of one element or feature to another, as illustrated in the figures. These spatially related terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially related terms used herein may be interpreted accordingly.

[0008] The term "essentially" in the description, such as "essentially planar" or "essentially coplanar," etc., is understood by those skilled in the field. In some embodiments, the expression "essentially" may be omitted. Where appropriate, the term "essentially" may also encompass embodiments with "entirely," "completely," "all," etc. The term "essentially" can be varied in different technologies and may fall within the range of interpretation as understood by those skilled in the field. For example, the term "essentially" may also refer to 90% or more of what is specified, such as 95% or more, in particular 99% or more, including 100%, although the present invention is not limited to such interpretations. Furthermore, terms such as...The terms "essentially parallel" or "essentially perpendicular" should be interpreted as not excluding minor deviations from the specified arrangement and may, for example, include deviations of up to 10°. The expression "essentially" does not exclude "completely"; thus, for example, a composition that is "essentially free" of Y may be completely free of Y.

[0009] The term "approximately" can be varied in different technologies and may fall within the range of deviation as understood by a person skilled in the art. The term "approximately" in conjunction with a specific distance or size is to be interpreted as not excluding immaterial deviations from the specified distance or size. For example, the term "approximately" may include deviations of up to 10% of the specified value, but the present invention is not limited to this. The term "approximately" in relation to a numerical value x may mean x ±5 or 10% of the specified value, but the present invention is not limited to this.

[0010] Several embodiments of the disclosure are described. Additional processes may be provided before, during, and / or after the stages described in these embodiments. Some of the described stages may be replaced or eliminated in other embodiments. The semiconductor device structure may be augmented with additional features. Some of the features described below may be replaced or eliminated in different embodiments. Although some embodiments are described with processes performed in a specific sequence, these processes may also be carried out in a different logical order.

[0011] Gate-all-around transistor (GAA) structures can be structured by any suitable method. For example, the structures can be structured using one or more photolithography processes, including dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithography and self-aligning processes, enabling the creation of structures with, for example, smaller spacing than would be possible with a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are then formed along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers can be used to structure the GAA structure.

[0012] Fig. Figures 1A-1E are cross-sectional views of different stages of a process for forming a semiconductor device structure according to some embodiments. Fig. 1A-1 is a top view of the semiconductor device structure of Fig. 1A according to some embodiments. Fig. 1A is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line YY' in Fig. 1A-1 illustrated. Fig. 1A-2 is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 1A-1 illustrated.

[0013] As in Fig. As shown in Figures 1A, 1A-1 and 1A-2, a substrate 110 is provided according to some embodiments. According to some embodiments, the substrate 110 has a base 112 and a fin 114 above the base 112. The substrate 110 is, for example, a semiconductor substrate. The substrate 110 is, for example, a semiconductor wafer (such as a silicon wafer) or a section of a semiconductor wafer.

[0014] In some embodiments, the substrate 110 is made of an elemental semiconductor material, including silicon or germanium in a single-crystal, polycrystalline, or amorphous structure. In some other embodiments, the substrate 110 is made of a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, an alloy semiconductor, such as SiGe or GaAsP, or a combination thereof. The substrate 110 may also comprise multilayer semiconductors, semiconductor-on-insulator (SOI) (such as silicon-on-insulator or germanium-on-insulator), or a combination thereof.

[0015] In some embodiments, the substrate 110 is a device wafer comprising various device elements. In some embodiments, the various device elements are formed in and / or on the substrate 110. For the sake of simplicity and clarity, the device elements are not shown in the figures. Examples of the various device elements include active devices, passive devices, other suitable elements, or a combination thereof. Active devices may include transistors or diodes (not shown) formed on a surface of the substrate 110. Passive devices include resistors, capacitors, or other suitable passive devices.

[0016] For example, the transistors can be metal oxide semiconductor field-effect transistors (MOSFETs), complementary metal oxide semiconductor transistors (CMOS transistors), bipolar transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field-effect transistors (PFETs / NFETs), etc.

[0017] Various processes are used to form the different device elements, such as front-end-of-line semiconductor fabrication (FEOL) processes. FEOL semiconductor fabrication processes can include deposition, etching, implantation, photolithography, annealing, planarization, one or more other applicable processes, or a combination thereof.

[0018] In some embodiments, insulating elements (not shown) are formed in the substrate 110. The insulating elements are used to surround active regions and to electrically insulate various device elements formed in and / or above the active regions of the substrate 110. In some embodiments, the insulating elements comprise shallow trench insulating elements (STI elements), local silicon oxidation elements (LOCOS elements), other suitable insulating elements, or a combination thereof.

[0019] As in Fig. Figures 1A, 1A-1, and 1A-2 show that, according to some embodiments, a nanostructure stack 120 is formed above the fin 114. According to some embodiments, the nanostructure stack 120 comprises nanostructures 122 and 124. According to some embodiments, the nanostructures 122 and 124 are stacked sequentially above the fin 114. According to some embodiments, the nanostructures 122 and 124 comprise nanowires or nanosheets.

[0020] As in Fig. As shown in Figure 1A-2, the nanostructure stack 120 has recesses 120r according to some embodiments. According to some embodiments, the recess 120r is surrounded by the nanostructures 122 and 124 or by the nanostructures 122 and 124 and the fin 114.

[0021] According to some embodiments, the nanostructures 122 are made from the same first material. According to some embodiments, the first material differs from the material of the substrate 110. According to some embodiments, the first material contains an oxide-containing material such as silicon oxide.

[0022] According to some embodiments, the nanostructures 124 are made of the same second material. According to some embodiments, the second material differs from the first material. According to some embodiments, the second material is the same as the material of the substrate 110. According to some embodiments, the second material contains an elemental semiconductor material, including silicon or germanium in a single-crystal, polycrystalline, or amorphous structure.

[0023] According to some embodiments, the second material contains a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, an alloy semiconductor, such as SiGe or GaAsP, or a combination thereof.

[0024] As in Fig. As shown in Figures 1A, 1A-1 and 1A-2, an insulating layer 130 is formed over the base 112 according to some embodiments. According to some embodiments, the fin 114 is partially embedded in the insulating layer 130. According to some embodiments, the fin 114 is surrounded by the insulating layer 130.

[0025] According to some embodiments, the insulating layer 130 is made of a dielectric material such as an oxide-containing material (e.g., silicon oxide), an oxynitride-containing material (e.g., silicon oxynitride), a material with a low dielectric constant, a porous dielectric material, glass, or a combination thereof. According to some embodiments, the glass includes borosilicate glass (BSG), phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), fluorinated silicate glass (FSG), or a combination thereof.

[0026] According to some embodiments, the insulating layer 130 is formed using a deposition process or a spin-on process, a chemical-mechanical polishing process, and a re-etching process. According to some embodiments, the deposition process comprises a chemical vapor deposition (CVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a flowable chemical vapor deposition (FCVD) process, a sputtering process, or a combination thereof.

[0027] As in Fig. As shown in Figures 1A, 1A-1 and 1A-2, according to some embodiments a gate stack 140 is formed above the nanostructure stack 120, the fin 114 and the insulating layer 130. According to some embodiments, the gate stack 140 encloses the nanostructure stack 120 and the fin 114.

[0028] According to some embodiments, the gate stack 140 comprises a dielectric gate layer 142 and a gate electrode 144. According to some embodiments, the gate electrode 144 is located above the dielectric gate layer 142. According to some embodiments, the dielectric gate layer 142 is positioned between the gate electrode 144 and the nanostructure stack 120.

[0029] According to some embodiments, the dielectric gate layer 142 is also positioned between the gate electrode 144 and the fin 114. According to some embodiments, the dielectric gate layer 142 is positioned between the gate electrode 144 and the insulating layer 130.

[0030] According to some embodiments, the dielectric gate layer 142 is made of an oxide-containing material such as silicon oxide. In some embodiments, the dielectric gate layer 142 and the nanostructures 122 are made of the same material, such as an oxide-containing material (e.g., silicon oxide). According to some embodiments, the dielectric gate layer 142 is formed using a chemical vapor deposition process and an etching process.

[0031] According to some embodiments, the gate electrode 144 is made of a semiconductor material such as polysilicon. According to some embodiments, the gate electrode 144 is formed using a chemical vapor deposition process and an etching process.

[0032] As in Fig. As shown in Figures 1A, 1A-1 and 1A-2, a mask layer 150 is formed over the gate stack 140 according to some embodiments. According to some embodiments, the mask layer 150 is made of a material that differs from the materials of the gate stack 140. According to some embodiments, the mask layer 150 is made of nitrides (e.g., silicon nitride) or oxynitrides (e.g., silicon oxynitride).

[0033] As in Fig. As shown in Figures 1A-1 and 1A-2, according to some embodiments, a spacer structure 160 is formed over the side walls of the gate stack 140 and the mask layer 150. According to some embodiments, the spacer structure 160 surrounds the gate stack 140 and the mask layer 150. According to some embodiments, the spacer structure 160 is positioned over the nanostructure stack 120, the fin structure 114, and the insulation layer 130.

[0034] According to some embodiments, the spacer structure 160 comprises insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide. According to some embodiments, the spacer structure 160 is made of a material different from that of the gate stack 140 and the mask layer 150. According to some embodiments, the formation of the spacer structure 160 involves deposition processes and an anisotropic etching process.

[0035] As in Fig. As shown in 1A-2, according to some embodiments an inner spacer layer 170 is formed in the recesses 120r of the nanostructure stack 120.

[0036] According to some embodiments, the recesses 120r are filled with the inner spacer layer 170. According to some embodiments, the inner spacer layer 170 is in direct contact with sidewalls of the nanostructures 122.

[0037] According to some embodiments, the inner spacer layer 170 is made of an insulating material such as an oxide-containing material (e.g. silicon oxide), a nitride-containing material (e.g. silicon nitride), an oxynitride-containing material (e.g. silicon oxynitride), a carbide-containing material (e.g. silicon carbide), or a material with a high dielectric constant (e.g. HfO₂). 2, ZrO2, HfZrO2 or Al2O3) or a material with a low dielectric constant.

[0038] According to some embodiments, the term "material with a high dielectric constant" refers to a material that has a dielectric constant greater than that of silicon dioxide. According to some embodiments, the term "material with a low dielectric constant" refers to a material that has a dielectric constant less than that of silicon dioxide.

[0039] According to some embodiments, the inner spacer layer 170 is formed using a deposition process and an etching process. According to some embodiments, the deposition process includes a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like.

[0040] As in Fig. As shown in Figures 1A-1 and 1A-2, source / drain structures 180 are formed above the fin 114 according to some embodiments. According to some embodiments, the nanostructure stack 120, the inner spacer layer 170, and the gate stack 140 are located between the source / drain structures 180.

[0041] According to some embodiments, the source / drain structures 180 are connected to the nanostructures 124. According to some embodiments, the source / drain structures 180 are in direct contact with the nanostructures 124, the inner spacer layer 170, and the fin 114.

[0042] In some embodiments, the source / drain structures 180 are made of a semiconductor material (e.g., silicon germanium) with phosphorus dopants, such as a group IIIA element. Group IIIA elements include boron or another suitable material.

[0043] In some other embodiments, the source / drain structures 180 are made from a semiconductor material (e.g., silicon) with N dopants, such as an element of group VA. Elements of group VA include phosphorus (P), antimony (Sb), or another suitable material of group VA. According to some embodiments, the source / drain structures 180 are formed using an epitaxial process.

[0044] As in Fig. As shown in Figures 1A-1 and 1A-2, according to some embodiments a dielectric layer 190 is formed over the source / drain structures 180 and the insulating layer 130. According to some embodiments, the gate stack 140 and the spacer structure 160 are located in the dielectric layer 190.

[0045] According to some embodiments, the dielectric layer 190 contains a dielectric material such as an oxide-containing material (e.g. silicon oxide), an oxynitride-containing material (e.g. silicon oxynitride), a material with a low dielectric constant, a porous dielectric material, glass or a combination thereof.

[0046] According to some embodiments, the glass includes borosilicate glass (BSG), phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), fluorinated silicate glass (FSG), or a combination thereof. According to some embodiments, the dielectric layer 190 is formed by a deposition process (e.g., a chemical vapor deposition process) and a planarization process (e.g., a chemical-mechanical polishing process).

[0047] As in Fig. As shown in Figure 1B, according to some embodiments, the mask layer 150 and the gate electrode 144 are removed. According to some embodiments, the removal process includes an etching process, such as a wet etching process or a dry etching process.

[0048] As in Fig. As shown in Figure 1C, according to some embodiments, the dielectric gate layer 142 and end sections of the nanostructures 122 are removed. Since, according to some embodiments, the dielectric gate layer 142 and the nanostructures 122 are both made of an oxide-containing material, the dielectric gate layer 142 and the end sections of the nanostructures 122 are removed by an etching process.

[0049] After the removal process has been carried out, according to some embodiments, recesses r1 are formed in the nanostructure stack 120. According to some embodiments, the recess r1 is surrounded by the nanostructures 122 and 124 or by the nanostructures 122 and 124 and the fin 114.

[0050] According to some embodiments, the nanostructure 124 has a bottom surface 124a, side walls 124b, and a top surface 124c. According to some embodiments, the side walls 124b form the connection between the bottom surface 124a and the top surface 124c. According to some embodiments, the bottom surface 124a and the top surface 124c are essentially flat surfaces.

[0051] According to some embodiments, the nanostructure has 124 vertices C1 and C2. According to some embodiments, each vertex C1 is located between the corresponding side wall 124b and the bottom surface 124a. According to some embodiments, each vertex C2 is located between the corresponding side wall 124b and the top surface 124c.

[0052] According to some embodiments, the fin 114 has a top surface 114a, side walls 114b, and corners C3. According to some embodiments, each corner C3 is located between the corresponding side wall 114b and the top surface 114a.

[0053] As in Fig. 1C and Fig. As shown in Figure 1D, according to some embodiments an oxidation process is carried out on the fin 114 and the nanostructures 124 to form an oxide layer 210 on the fin 114 and the nanostructures 124. According to some embodiments, the oxide layer 210 has sections 212 and 214.

[0054] According to some embodiments, sections 212 and 214 are located above the fin 114 and above the nanostructures 124, respectively. According to some embodiments, sections 212 and 214 are spaced apart from each other.

[0055] According to some embodiments, section 212 is made from an oxide of the material of fin 114. According to some embodiments, sections 214 are made from an oxide of the material of nanostructures 124. Therefore, the formation of the oxide layer 210 according to some embodiments consumes surface sections of the nanostructures 124 and the fin 114.

[0056] Since the oxidation rate of corners C1, C2 and C3 is greater according to some embodiments than that of the top 124c, the side walls 124b and the bottom 124a of the nanostructures 124 and the top 114a and the side walls 114b of the fin 114, the oxidation process rounds off corners C1, C2 and C3.

[0057] According to some embodiments, after the oxidation process, corners C1 become rounded corners C1'. According to some embodiments, after the oxidation process, corners C2 become rounded corners C2' or C2". According to some embodiments, after the oxidation process, corners C3 become rounded corners C3'.

[0058] Since the formation of the oxide layer 210 according to some embodiments consumes surface sections of the nanostructures 124 and the fin 114, the nanostructure 124 has concave lower surfaces 124d and concave upper surfaces 124e after the oxidation process has been carried out, and the fin 114 has concave upper surfaces 114c after the oxidation process has been carried out.

[0059] According to some embodiments, each concave lower surface 124d forms the connection between the bottom surface 124a and the corresponding side wall 124b. According to some embodiments, each rounded corner C1' is located between the corresponding side wall 124b and the corresponding concave lower surface 124d.

[0060] According to some embodiments, each concave upper surface 124e forms the connection between the top surface 124c and the corresponding side wall 124b. According to some embodiments, each rounded corner C2' is located between the corresponding side wall 124b and the corresponding concave upper surface 124e. According to some embodiments, the uppermost of the nanostructures 124 has rounded corners C2'. According to some embodiments, each rounded corner C2' is located between the corresponding side wall 124b and the top surface 124c.

[0061] According to some embodiments, each concave upper surface 114c forms the connection between the top surface 114a and the corresponding side wall 114b of the fin 114. According to some embodiments, each rounded corner C3' is located between the corresponding side wall 114b and the corresponding concave upper surface 114c.

[0062] According to some embodiments, the concave upper surface 114c of the fin 114 is located below the corresponding concave lower surface 124d of the nanostructure 124. According to some embodiments, the concave lower surface 124d of the nanostructure 124 is located between the corresponding concave upper surface 124e of the nanostructure 124 and the corresponding concave upper surface 114c of the fin 114. According to some embodiments, the side wall 114b of the fin 114 is located below the side wall 124b of the nanostructure 124.

[0063] Since the formation of section 212 of the oxide layer 210 according to some embodiments consumes the surface sections of the fin 114, the fin 114 has an upper surface 114d after the oxidation process has been carried out, which forms the connection between the side wall 114b and a lower side wall 114e of the fin 114.

[0064] According to some embodiments, the upper surface 114d is essentially at the same level as a top surface 132 of the insulation layer 130. According to some embodiments, the side wall 114b is not flush with the lower side wall 114e of the fin 114.

[0065] According to some embodiments, the average thickness of the oxide layer 210 is in the range of approximately 5 Å to approximately 3 nm. If the average thickness of the oxide layer 210 is less than 5 Å, the corners C1, C2, and C3 may not be sufficiently rounded. If the average thickness of the oxide layer 210 is more than 3 nm, the oxidation process may consume too much of the nanostructures 124, which could increase the resistance of the nanostructures 124.

[0066] According to some embodiments, the oxidation process includes a chemical oxidation process. According to some embodiments, the chemical oxidation process includes immersion of the semiconductor device structure of Fig. 1C into an oxidation solution. According to some embodiments, the oxidation solution contains liquid ozone (O3) or NH4OH and hydrogen peroxide (H2O2).

[0067] Fig. 1E-1 is a top view of the semiconductor device structure of Fig. 1E according to some embodiments. Fig. 1E is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line YY' in Fig. 1E-1 illustrated.

[0068] Fig. 2A is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 1E-1 illustrates. As in Fig. As shown in 1E, 1E-1 and 2A, according to some embodiments the oxide layer 210 and the nanostructures 122 are removed.

[0069] As in Fig. 1E and Fig. As shown in Figure 2A, according to some embodiments, the nanostructures 124 and the fin 114 are separated from each other by gaps GA1. As shown in Fig. As shown in Figures 1E, 1E-1 and 2A, the spacer structure 160 according to some embodiments has a trench 162 which exposes the nanostructures 124.

[0070] As in Fig. As shown in Figure 1E, the nanostructure 124, according to some embodiments, has a central section 124f and a peripheral section 124g. According to some embodiments, the central section 124f is the section of the nanostructure 124 between the bottom surface 124a and the top surface 124c. According to some embodiments, the peripheral section 124g is the section of the nanostructure 124 between the concave bottom surface 124d and the concave top surface 124e.

[0071] According to some embodiments, the central section 124f is thicker than the peripheral section 124g. According to some embodiments, the ratio of the thickness T1 of the peripheral section 124g to the thickness T2 of the central section 124f is in a range of about 0.2 to about 0.99.

[0072] According to some embodiments, the removal process includes an etching process, such as a wet etching process or a dry etching process. According to some embodiments, the etchant for the wet etching process contains diluted HF. According to some embodiments, the etchant for the dry etching process contains NH3 and HF.

[0073] Fig. Figures 2A-2C are cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments. As shown in Fig. As shown in Figure 2B, according to some embodiments a dielectric gate layer 222 is formed over the nanostructures 124, the fin 114, the spacer structure 160, the inner spacer layer 170 and the dielectric layer 190.

[0074] According to some embodiments, the dielectric gate layer 222 conformally covers the nanostructures 124, the fin 114, the spacer structure 160, the inner spacer layer 170, and the dielectric layer 190. According to some embodiments, the dielectric gate layer 222 surrounds the nanostructures 124 and the fin 114.

[0075] According to some embodiments, the dielectric gate layer 222 is made of a material with a high dielectric constant, such as HfO2, La2O3, CaO, ZrO2, HfZrO2, or Al2O3. According to some embodiments, the dielectric gate layer 222 is formed using an atomic layer deposition process or another suitable process.

[0076] As in Fig. As shown in Figure 2B, according to some embodiments, a work function metal layer 224 is conformally formed over the dielectric gate layer 222. The work function metal layer 224 provides a desired work function for transistors to increase device performance, including an improved threshold voltage.

[0077] In embodiments of the NMOS transistor configuration, the work function metal layer 224 can be a metal capable of providing a work function suitable for the device, such as equal to or less than approximately 4.5 eV. According to some embodiments, the work function metal layer 224 is made of metal, metal carbide, metal nitride, or a combination thereof. For example, the work function metal layer 224 is made of tantalum, hafnium carbide, zirconium carbide, tantalum nitride, or a combination thereof.

[0078] In embodiments of the PMOS transistor configuration, the work function metal layer 224 can be a metal capable of providing a work function suitable for the device, such as equal to or greater than approximately 4.8 eV. According to some embodiments, the work function metal layer 224 is made of metal, metal carbide, metal nitride, another suitable material, or a combination thereof. For example, the work function metal layer 224 is made of titanium, titanium nitride, another suitable material, or a combination thereof.

[0079] According to some embodiments, the work function metal layer 224 is formed using a deposition process, a photolithography process, and an etching process. According to some embodiments, the deposition process includes a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or a combination thereof.

[0080] As in Fig. As shown in Figure 2B, according to some embodiments a gate electrode layer 226a is formed above the work function metal layer 224. According to some embodiments, the groove 162 of the spacer structure 160 and the gaps GA1 between the fin 114 and the nanostructures 124 are completely filled with the gate electrode layer 226a.

[0081] According to some embodiments, the gate electrode layer 226a is made of metal, metal nitride, or metal carbide. According to some embodiments, the gate electrode layer 226a is made of tungsten, titanium nitride, tantalum nitride, titanium aluminide, titanium carbide, or a combination thereof.

[0082] According to some embodiments, the gate electrode layer 226a is formed using an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process.

[0083] Fig. 2C-1 is a top view of the semiconductor device structure of Fig. 2C according to some embodiments. Fig. 2C is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 2C-1 illustrated. Fig. 2C-2 is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line YY' in Fig. 2C-1 illustrated.

[0084] As in Fig. In 2B, 2C, 2C-1 and 2C-2, according to some embodiments, the dielectric gate layer 222, the work function metal layer 224 and the gate electrode layer 226a are removed outside the trench 162 and the gaps GA1.

[0085] According to some embodiments, the gate electrode layer 226a, which remains in the trench 162 and in the gaps GA1, forms a gate electrode 226. According to some embodiments, the gate electrode 226 surrounds the nanostructures 124. According to some embodiments, the gate electrode 226, the work function metal layer 224, and the dielectric gate layer 222 together form a gate stack G. According to some embodiments, the gate stack G encloses the nanostructures 124 and the fin 114.

[0086] According to some embodiments, the removal process includes a planarization process such as a chemical-mechanical polishing process.

[0087] According to some embodiments, a semiconductor device structure 100 is essentially formed in this step. According to some embodiments, the semiconductor device structure 100 comprises an NMOS transistor or a PMOS transistor. According to some embodiments, the semiconductor device structure 100 comprises a gate all-around transistor (GAA transistor).

[0088] As in Fig. 2C-2 shown, according to some embodiments the dielectric gate layer 222 conformally covers the bottom surfaces 124a, the side walls 124b, the top surfaces 124c, the concave lower surfaces 124d, the concave upper surfaces 124e and the rounded corners C1', C2' and C2" of the nanostructures 124 and the top surface 114a, the side walls 114b, the concave upper surfaces 114c and the rounded corners C3' of the fin 114.

[0089] Since the corners C1, C2 and C3 are in Fig. 1C is rounded according to some embodiments to form the rounded corners C1', C2', C2" and C3', improving the coverage of the dielectric gate layer 222 on the nanostructures 124 and the fin 114, which in turn improves the yield of the dielectric gate layer 222 and the reliability of the semiconductor device structure 100.

[0090] Fig. 3A-3D are cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments. As in Fig. As shown in 3A, according to some embodiments the step of Fig. 1C to remove the dielectric gate layer 142 and end sections of the nanostructures 122.

[0091] As in Fig. 3A and Fig. As shown in Figure 3B, according to some embodiments an etching process is carried out on the nanostructures 124 and the fin 114 to remove surface sections of the nanostructures 124 and the fin 114.

[0092] Since the etch rate of corners C1, C2 and C3 is greater according to some embodiments than that of the top surfaces 124c, the side walls 124b and the bottom surface 124a of the nanostructures 124 and the top surface 114a and the side walls 114b of the fin 114, the etching process rounds off corners C1, C2 and C3.

[0093] According to some embodiments, the corners C1 become rounded corners C1' after the etching process. According to some embodiments, the corners C2 become rounded corners C2' or C2' after the etching process. According to some embodiments, the corners C3 become rounded corners C3' after the etching process. According to some embodiments, the upper surface 114d of the fin 114 is formed after the etching process.

[0094] According to some embodiments, the nanostructure 124 has concave lower surfaces 124d and concave upper surfaces 124e after the etching process, and the fin 114 has concave upper surfaces 114c after the etching process. According to some embodiments, each concave lower surface 124d forms the connection between the bottom surface 124a and the corresponding side wall 124b. According to some embodiments, each rounded corner C1' is located between the corresponding side wall 124b and the corresponding concave lower surface 124d.

[0095] According to some embodiments, each concave upper surface 124e forms the connection between the top surface 124c and the corresponding side wall 124b. According to some embodiments, each rounded corner C2' is located between the corresponding side wall 124b and the corresponding concave upper surface 124e. According to some embodiments, the uppermost of the nanostructures 124 has rounded corners C2'. According to some embodiments, each rounded corner C2' is located between the corresponding side wall 124b and the top surface 124c.

[0096] According to some embodiments, each concave upper surface 114c forms the connection between the top surface 114a and the corresponding side wall 114b of the fin 114. According to some embodiments, each rounded corner C3' is located between the corresponding side wall 114b and the corresponding concave upper surface 114c.

[0097] According to some embodiments, the etching process comprises an isotropic etching process. According to some embodiments, the etching process comprises a wet etching process or a dry etching process. According to some embodiments, the etchant for the wet etching process contains NH4OH. According to some embodiments, the etchant for the dry etching process contains NH3 and F2.

[0098] Fig. 3C-1 is a top view of the semiconductor device structure of Fig. 3C according to some embodiments. Fig. 3C is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line YY' in Fig. 3C-1 illustrated.

[0099] Fig. 3C-2 is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 3C-1 illustrates this. As shown in Fig. 3C, 3C-1, and 3C-2 are shown; according to some embodiments, the step of Fig. 1E was performed to remove the nanostructures 122.

[0100] Fig. 3D-1 is a top view of the semiconductor device structure of Fig. 3D according to some embodiments. Fig. 3D is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line YY' in Fig. 3D-1 illustrated.

[0101] Fig. 3D-2 is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 3D-1 illustrated. As in Fig. 3D, 3D-1 and 3D-2 are shown; according to some embodiments, the steps of Fig. 2B and Fig. 2C is carried out to form the gate stack G. According to some embodiments, a semiconductor device structure 300 is essentially formed in this step.

[0102] Fig. Figures 4A-4H are cross-sectional views of different stages of a process for forming a semiconductor device structure according to some embodiments. Fig. 4A-1 is a top view of the semiconductor device structure of Fig. 4A according to some embodiments.

[0103] Fig. 4A is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line YY' in Fig. 4A-1 illustrated. Fig. 4A-2 is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 4A-1 illustrated.

[0104] As in Fig. As shown in 4A, 4A-1 and 4A-2, according to some embodiments the semiconductor device structure 40 is Fig. 4A, 4A-1 and 4A-2 similar to the semiconductor device structure 10 of Fig. 1A, 1A-1 and 1A-2, except that the nanostructures 122 and the dielectric gate layer 142 are made of different materials.

[0105] According to some embodiments, the nanostructures 122 are made of a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, an alloy semiconductor, such as SiGe or GaAsP, or a combination thereof. According to some embodiments, the dielectric gate layer 142 is made of an oxide-containing material, such as silicon oxide.

[0106] As in Fig. As shown in 4B, according to some embodiments the step of Fig. 1B was performed to remove the mask layer 150 and the gate electrode 144. According to some embodiments, the removal process includes an etching process, such as a wet etching process or a dry etching process.

[0107] As in Fig. As shown in Figure 4C, the dielectric gate layer 142 is removed according to some embodiments. According to some embodiments, the removal process includes an etching process, such as a wet etching process or a dry etching process.

[0108] As in Fig. As shown in Figure 4D, end sections of the nanostructures 122 are removed according to some embodiments. After the removal process has been carried out, recesses r1 are formed in the nanostructure stack 120 according to some embodiments. According to some embodiments, the recess r1 is surrounded by the nanostructures 122 and 124 or by the nanostructures 122 and 124 and the fin 114.

[0109] According to some embodiments, the nanostructure 124 has a bottom surface 124a, side walls 124b, and a top surface 124c. According to some embodiments, the side walls 124b form the connection between the bottom surface 124a and the top surface 124c.

[0110] According to some embodiments, the nanostructure has 124 vertices C1 and C2. According to some embodiments, each vertex C1 is located between the corresponding side wall 124b and the bottom surface 124a. According to some embodiments, each vertex C2 is located between the corresponding side wall 124b and the top surface 124c.

[0111] According to some embodiments, the fin 114 has a top surface 114a, side walls 114b, and corners C3. According to some embodiments, each corner C3 is located between the corresponding side wall 114b and the top surface 114a. According to some embodiments, the removal process includes an etching process, such as a wet etching process or a dry etching process.

[0112] As in Fig. 4D and Fig. As shown in Figure 4E, according to some embodiments an oxidation process is carried out on the fin 114 and the nanostructures 122 and 124 to form an oxide layer 410 on the fin 114 and the nanostructures 122 and 124. According to some embodiments, the oxide layer 410 has sections 412, 414 and 416. According to some embodiments, section 412 forms the connection between sections 414 and 416.

[0113] According to some embodiments, sections 412 are made from an oxide of the material of nanostructures 122. According to some embodiments, sections 414 are made from an oxide of the material of nanostructures 124. According to some embodiments, sections 416 are made from an oxide of the material of fin 114. Therefore, the formation of the oxide layer 410 according to some embodiments consumes surface sections of nanostructures 122 and 124 and of fin 114.

[0114] Since the oxidation rate of corners C1, C2 and C3 is greater according to some embodiments than that of the top 124c, the side walls 124b and the bottom 124a of the nanostructures 124 and the top 114a and the side walls 114b of the fin 114, the oxidation process rounds off corners C1, C2 and C3.

[0115] According to some embodiments, after the oxidation process, corners C1 become rounded corners C1'. According to some embodiments, after the oxidation process, corners C2 become rounded corners C2' or C2". According to some embodiments, after the oxidation process, corners C3 become rounded corners C3'.

[0116] Since the formation of the oxide layer 410 according to some embodiments consumes surface sections of the nanostructures 124 and the fin 114, the nanostructure 124 has concave lower surfaces 124d and concave upper surfaces 124e after the oxidation process has been carried out, and the fin 114 has concave upper surfaces 114c after the oxidation process has been carried out.

[0117] According to some embodiments, each concave lower surface 124d forms the connection between the bottom surface 124a and the corresponding side wall 124b. According to some embodiments, each rounded corner C1' is located between the corresponding side wall 124b and the corresponding concave lower surface 124d.

[0118] According to some embodiments, each concave upper surface 124e forms the connection between the top surface 124c and the corresponding side wall 124b. According to some embodiments, each rounded corner C2' is located between the corresponding side wall 124b and the corresponding concave upper surface 124e. According to some embodiments, the uppermost of the nanostructures 124 has rounded corners C2'. According to some embodiments, each rounded corner C2' is located between the corresponding side wall 124b and the top surface 124c.

[0119] According to some embodiments, each concave upper surface 114c forms the connection between the top surface 114a and the corresponding side wall 114b of the fin 114. According to some embodiments, each rounded corner C3' is located between the corresponding side wall 114b and the corresponding concave upper surface 114c.

[0120] According to some embodiments, the concave upper surface 114c of the fin 114 is located below the corresponding concave lower surface 124d of the nanostructure 124. According to some embodiments, the concave lower surface 124d of the nanostructure 124 is located between the corresponding concave upper surface 124e of the nanostructure 124 and the corresponding concave upper surface 114c of the fin 114. According to some embodiments, the side wall 114b of the fin 114 is located below the side wall 124b of the nanostructure 124.

[0121] Since the formation of section 416 of the oxide layer 410 according to some embodiments consumes the surface sections of the fin 114, the fin 114 has an upper surface 114d after the oxidation process has been carried out, which forms the connection between the side wall 114b and a lower side wall 114e of the fin 114.

[0122] According to some embodiments, the upper surface 114d is essentially at the same level as a top surface 132 of the insulation layer 130. According to some embodiments, the side wall 114b is not flush with the lower side wall 114e of the fin 114.

[0123] According to some embodiments, the average thickness of the oxide layer 410 is in the range of approximately 5 Å to approximately 3 nm. If the average thickness of the oxide layer 410 is less than 5 Å, the corners C1, C2, and C3 may not be sufficiently rounded. If the average thickness of the oxide layer 410 is more than 3 nm, the oxidation process may consume too much of the nanostructures 124, which could increase the resistance of the nanostructures 124.

[0124] According to some embodiments, the oxidation process includes a chemical oxidation process. According to some embodiments, the chemical oxidation process includes immersion of the semiconductor device structure of Fig. 4D in an oxidation solution. According to some embodiments, the oxidation solution contains liquid ozone (O3) or NH4OH and hydrogen peroxide (H2O2).

[0125] As in Fig. As shown in Figure 4F, the oxide layer 410 is removed according to some embodiments. According to some embodiments, the removal process includes an etching process, such as a wet etching process or a dry etching process. According to some embodiments, the etchant for the wet etching process contains dilute HF. According to some embodiments, the etchant for the dry etching process contains NH3 and HF.

[0126] Fig. 4G-1 is a top view of the semiconductor device structure of Fig. 4G according to some embodiments. Fig. 4G is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line YY' in Fig. 4G-1 illustrated. Fig. 4G-2 is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 4G-1 illustrated.

[0127] As in Fig. Figures 4G, 4G-1, and 4G-2 show that, according to some embodiments, the nanostructures 122 are removed. According to some embodiments, the removal process includes an etching process, such as a dry etching process. According to some embodiments, the etchant for the dry etching process contains F2 and HF.

[0128] As in Fig. As shown in Figure 4G, the nanostructure 124, according to some embodiments, has a central section 124f and a peripheral section 124g. According to some embodiments, the central section 124f is the section of the nanostructure 124 between the bottom surface 124a and the top surfaces 124c. According to some embodiments, the peripheral section 124g is the section of the nanostructure 124 between the concave bottom surfaces 124d and the concave top surfaces 124e.

[0129] According to some embodiments, the central section 124f is thicker than the peripheral section 124g. According to some embodiments, the ratio of the thickness T1 of the peripheral section 124g to the thickness T2 of the central section 124f is in a range of about 0.2 to about 0.99.

[0130] Fig. 4H-1 is a top view of the semiconductor device structure of Fig. 4H according to some embodiments. Fig. 4H is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line YY' in Fig. 4H-1 illustrated. Fig. 4H-2 is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 4H-1 illustrated.

[0131] As in Fig. 4H, 4H-1 and 4H-2 are shown; according to some embodiments, the steps of Fig. 2B and Fig. 2C is carried out to form the gate stack G. According to some embodiments, a semiconductor device structure 400 is essentially formed in this step.

[0132] Fig. Figures 5A-5D are cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments. As shown in Fig. As shown in 5A, according to some embodiments the step of Fig. 4D imaging was performed to remove end sections of the nanostructures 122.

[0133] As in Fig. 5A and Fig. As shown in Figure 5B, according to some embodiments an etching process is carried out on the nanostructures 124 and the fin 114 to remove surface sections of the nanostructures 124 and the fin 114.

[0134] Since the etch rate of corners C1, C2 and C3 is greater according to some embodiments than that of the top surfaces 124c, the side walls 124b and the bottom surfaces 124a of the nanostructures 124 and the top surface 114a and the side walls 114b of the fin 114, the etching process rounds off corners C1, C2 and C3.

[0135] According to some embodiments, corners C1 become rounded corners C1' after the etching process. According to some embodiments, corners C2 become rounded corners C2' or C2' after the etching process. According to some embodiments, corners C3 become rounded corners C3' after the etching process.

[0136] According to some embodiments, after the etching process, the nanostructure 124 has concave lower surfaces 124d and concave upper surfaces 124e, and the fin 114 has concave upper surfaces 114c and an upper surface 114d. According to some embodiments, each concave lower surface 124d forms the connection between the bottom surface 124a and the corresponding side wall 124b. According to some embodiments, each rounded corner C1' is located between the corresponding side wall 124b and the corresponding concave lower surface 124d.

[0137] According to some embodiments, each concave upper surface 124e forms the connection between the top surface 124c and the corresponding side wall 124b. According to some embodiments, each rounded corner C2' is located between the corresponding side wall 124b and the corresponding concave upper surface 124e.

[0138] According to some embodiments, the uppermost of the nanostructures 124 has rounded corners C2". According to some embodiments, each rounded corner C2" is located between the corresponding side wall 124b and the top surface 124c.

[0139] According to some embodiments, each concave upper surface 114c forms the connection between the top surface 114a and the corresponding side wall 114b of the fin 114. According to some embodiments, each rounded corner C3' is located between the corresponding side wall 114b and the corresponding concave upper surface 114c.

[0140] According to some embodiments, the upper surface 114d forms the connection between the side wall 114b and a lower side wall 114e of the fin 114. According to some embodiments, the upper surface 114d is essentially at the same level as a top surface 132 of the insulation layer 130. According to some embodiments, the side wall 114b is not flush with the lower side wall 114e of the fin 114.

[0141] According to some embodiments, the etching process comprises an isotropic etching process. According to some embodiments, the etching process comprises a wet etching process or a dry etching process. According to some embodiments, the etchant for the wet etching process contains NH4OH. According to some embodiments, the etchant for the dry etching process contains NH3 and F2.

[0142] Fig. 5C-1 is a top view of the semiconductor device structure of Fig. 5C according to some embodiments. Fig. 5C is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line YY' in Fig. 5C-1 illustrated. Fig. 5C-2 is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 5C-1 illustrated.

[0143] As in Fig. Figures 5C, 5C-1, and 5C-2 show that, according to some embodiments, the nanostructures 122 are removed. According to some embodiments, the removal process includes an etching process, such as a dry etching process. According to some embodiments, the etchant for the dry etching process contains F2 and HF.

[0144] Fig. 5D-1 is a top view of the semiconductor device structure of Fig. 5D according to some embodiments. Fig. 5D is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line YY' in Fig. 5D-1 illustrated. Fig. 5D-2 is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 5D-1 illustrated.

[0145] As in Fig. 5D, 5D-1 and 5D-2 are shown; according to some embodiments, the steps of Fig. 2B and Fig. 2C is performed to form the gate stack G. According to some embodiments, a semiconductor device structure 500 is essentially formed in this step.

[0146] Fig. Figures 6A-6D are cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments. As shown in Fig. As shown in 6A, according to some embodiments the step of Fig. 4B was performed to remove the mask layer 150 and the gate electrode 144. According to some embodiments, the removal process includes an etching process, such as a wet etching process or a dry etching process.

[0147] As in Fig. As shown in Figure 6B, the dielectric gate layer 142 is removed according to some embodiments. According to some embodiments, the nanostructure 124A is the uppermost of the nanostructures 124. According to some embodiments, the removal process can also remove sections of the nanostructure 124A. Therefore, according to some embodiments, the nanostructure 124A has rounded corners C2".

[0148] According to some embodiments, the rounded corner C2'' is located between the top surface 124c and the side wall 124b of the nanostructure 124A. According to some embodiments, the removal process includes an etching process, such as a wet etching process or a dry etching process.

[0149] Fig. 6C-1 is a top view of the semiconductor device structure of Fig. 6C according to some embodiments. Fig. 6C is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line YY' in Fig. 6C-1 illustrates. Fig. 6C-2 is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 6C-1 illustrates.

[0150] As in Fig. Figures 6C, 6C-1 and 6C-2 show that, according to some embodiments, the steps of Fig. 4D-4G or the steps of Fig. Procedures 5A-5C were performed to remove the nanostructures 122 and form the rounded corners C1', C2' and C3'.

[0151] Since, according to some embodiments, the rounded corners C2'' are formed before the rounded corners C1', C2' and C3' are formed, the rounded corners C2'' are not formed after the oxidation process of Fig. 4E or the etching process of Fig. 5B is rounder than the rounded corners C1', C2' and C3'.

[0152] Fig. 6D-1 is a top view of the semiconductor device structure of Fig. 6D according to some embodiments. Fig. 6D is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line YY' in Fig. 6D-1 illustrated. Fig. 6D-2 is a cross-sectional view showing the semiconductor device structure according to some embodiments along a section line XX' in Fig. 6D-1 illustrated.

[0153] As in Fig. As shown in 6D, 6D-1 and 6D-2, according to some embodiments the step of Fig. Step 4H is performed to form the gate stack G. According to some embodiments, a semiconductor device structure 600 is essentially formed in this step.

[0154] Fig. Figure 7A is a cross-sectional view of a semiconductor device structure 700 according to some embodiments. Fig. 7B is a top view of the semiconductor device structure 700 from Fig. 7A according to some embodiments.

[0155] Fig. 7A is a cross-sectional view showing the semiconductor device structure 700 according to some embodiments along a section line YY' in Fig. 7B illustrates this. Fig. 7C is a cross-sectional view showing the semiconductor device structure 700 according to some embodiments along a section line XX' in Fig. 7B illustrates this.

[0156] As in Fig. 7A, Fig. 7B and Fig. As shown in Figure 7C, the semiconductor device structure 700 is similar to the semiconductor device structure 100 according to some embodiments. Fig. 2C, except that the nanostructure has 124 convex curved side walls 124f.

[0157] In some embodiments, the convex curved sidewalls 124f form the connection between the concave upper surface 124e and the concave lower surface 124d of the nanostructure 124. In some embodiments, the concave upper surface 124e forms the connection between the top surface 124c and the convex curved sidewall 124f. In some other embodiments, the convex curved sidewalls 124f form the connection between the top surface 124c and the concave lower surface 124d of the nanostructure 124A.

[0158] According to some embodiments, the formation process of the semiconductor device structure 700 is similar to that of Fig. 1A-2C, 3A-3D, 4A-4H or 5A-5D, except that the formation process of the semiconductor device structure removes 700 more sections of the nanostructures 124 than that of Fig. 1A-2C, 3A-3D, 4A-4H or 5A-5D.

[0159] For example, the oxidation process used to form the semiconductor device structure 700 includes a thermal oxidation process which can oxidize more nanostructures 124 than a chemical oxidation process.

[0160] The processes and materials for forming semiconductor structures 300, 400, 500, 600, and 700 can be similar to or the same as those used to form semiconductor structure 100 described above. Elements with the same reference numbers as in Fig. Elements 1A to 7C exhibit similar or identical structures and materials. Therefore, the detailed descriptions of these elements are not repeated here.

[0161] According to some embodiments, semiconductor device structures and methods for their formation are provided. The methods (for forming the semiconductor device structure) form nanostructures and a fin with rounded corners to improve the coverage of a dielectric gate layer on the nanostructures and the fin, which in turn improves the performance of the dielectric gate layer and the reliability of the semiconductor device structures.

[0162] According to some embodiments, a method for forming a semiconductor device structure is provided. The method comprises providing a substrate, a first nanostructure, a second nanostructure, and a first gate stack. The first nanostructure is located between the substrate and the second nanostructure, and the first gate stack encloses the first and second nanostructures. The method includes removing the first gate stack and end sections of the first nanostructure. The method includes partially removing the second nanostructure to round off a first corner of the second nanostructure. The first corner becomes a first rounded corner after the second nanostructure has been partially removed. The method includes removing the first nanostructure. The method includes forming a second gate stack above the substrate and enclosing the second nanostructure.

[0163] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure comprises a substrate. The semiconductor device structure has a nanostructure overlying the substrate. The nanostructure has a bottom surface, a first side wall, and a concave lower surface, which forms the connection between the bottom surface and the first side wall. The nanostructure also has a first rounded corner between the first side wall and the concave lower surface. The semiconductor device structure includes a gate stack that surrounds the nanostructure.

[0164] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure comprises a substrate. The semiconductor device structure has a nanostructure overlying the substrate. The nanostructure has a first concave upper surface, a concave lower surface, and a convex curved side wall that connects the first concave upper surface and the concave lower surface. The semiconductor device structure includes a gate stack that encloses the nanostructure.

[0165] The foregoing descriptions outline features of various embodiments so that a person skilled in the field may better understand the aspects of the present disclosure. A person skilled in the field should understand that the present disclosure can readily be used as a basis for the development or modification of other methods and structures to achieve the same purposes and / or the same advantages as the embodiments presented herein. A person skilled in the field should also recognize that such equivalent designs do not depart from the spirit and scope of the present disclosure and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 655,147

[0001]

Claims

[1] Method for forming a semiconductor device structure comprising the following: Providing a substrate, a first nanostructure, a second nanostructure and a first gate stack, wherein the first nanostructure is located between the substrate and the second nanostructure and the first gate stack encloses the first nanostructure and the second nanostructure; Removal of the first gate stack and end sections of the first nanostructure; Partial removal of the second nanostructure to round off a first corner of the second nanostructure, wherein the first corner becomes a first rounded corner after the second nanostructure has been partially removed; Removal of the first nanostructure; and Forming a second gate stack above the substrate, with the second gate stack enclosing the second nanostructure. [2] Method according to claim 1, wherein the first gate stack comprises a dielectric gate layer and a gate electrode above the dielectric gate layer, the dielectric gate layer is made of a first oxide material and the first nanostructure is made of a second oxide material. [3] Method according to claim 2, wherein the removal of the first gate stack and the end sections of the first nanostructure comprises: Removal of the gate electrode; and Removal of the dielectric gate layer and the end sections of the first nanostructure. [4] The method of claim 3, wherein the partial removal of the second nanostructure comprises: Performing an oxidation process on the substrate and the second nanostructure to form an oxide layer on the substrate and the second nanostructure; and Removal of the oxide layer. [5] The method of claim 3, wherein the partial removal of the second nanostructure comprises: Performing an etching process on the second nanostructure. [6] Method according to claim 5, wherein the etching process comprises an isotropic etching process. [7] Method according to any one of claims 1 to 6, wherein the first gate stack comprises a dielectric gate layer and a gate electrode above the dielectric gate layer and the first nanostructure and the dielectric gate layer are made of different materials. [8] Method according to claim 7, wherein the removal of the first gate stack and the end sections of the first nanostructure comprises: Removal of the gate electrode; Removal of the dielectric gate layer; and Removal of the end sections of the first nanostructure. [9] The method of claim 8, wherein the partial removal of the second nanostructure comprises: Performing an oxidation process on the substrate, the first nanostructure, and the second nanostructure to form an oxide layer on the substrate, the first nanostructure, and the second nanostructure; and Removal of the oxide layer. [10] The method of claim 8, wherein the partial removal of the second nanostructure comprises: Performing an etching process on the second nanostructure. [11] Semiconductor structure which has the following features: a substrate; a nanostructure above the substrate, wherein the nanostructure has a bottom surface, a first side wall and a curved bottom surface which forms the connection between the bottom surface and the first side wall, and the nanostructure has a first rounded corner between the first side wall and the curved bottom surface; and a gate stack that encloses the nanostructure. [12] Semiconductor structure according to claim 11, wherein the gate stack comprises a dielectric gate layer and a gate electrode above the dielectric gate layer and the dielectric gate layer conformally covers the bottom, the first side wall and the curved lower surface of the nanostructure. [13] Semiconductor structure according to claim 11 or 12, wherein the nanostructure has a top surface and a concave top surface which forms the connection between the top surface and the first side wall. [14] Semiconductor structure according to claim 13, wherein the nanostructure has a second rounded corner between the concave upper surface and the first side wall. [15] Semiconductor structure according to claim 11, wherein the substrate has a base and a fin above the base and the fin has a top surface, a second side wall and a concave top surface which forms the connection between the top surface and the second side wall. [16] Semiconductor structure according to claim 15, wherein the fin has a second rounded corner between the second side wall and the concave upper surface. [17] Semiconductor structure according to claim 15 or 16, wherein the concave upper surface of the fin is located below the curved lower surface of the nanostructure and the second side wall of the fin is located below the first side wall of the nanostructure. [18] Semiconductor structure which has the following features: a substrate; a nanostructure above the substrate, wherein the nanostructure has a first concave upper surface, a concave lower surface and a convex curved side wall which forms the connection between the first concave upper surface and the concave lower surface; and a gate stack that encloses the nanostructure. [19] Semiconductor structure according to claim 18, wherein the nanostructure has a substantially flat top surface and the first concave top surface forms the connection between the substantially flat top surface and the convex curved side wall. [20] Semiconductor structure according to claim 18 or 19, wherein the substrate has a base and a fin above the base, the fin has a top surface, a side wall and a second concave top surface which forms the connection between the top surface and the side wall, and the concave bottom surface of the nanostructure is located between the first concave top surface of the nanostructure and the second concave top surface of the fin.

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