DEVICE AND METHOD

Abstract

Some aspects of the present disclosure relate to an apparatus comprising memory circuitry, machine-readable instructions, and processor circuitry to execute the machine-readable instructions, to obtain a physical layout of a first processor circuitry comprising a plurality of processor cores and thermal information of the plurality of processor cores, and to determine a first processor core of the plurality of processor cores to execute a first workload based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores.

Description

background

[0001] Task schedulers are a critical component in a computing environment because they organize the allocation of computing tasks to appropriate processing units to ensure efficient execution and resource utilization. A scheduler can operate at various levels within a system, such as the operating system thread level and the application level, and can be designed to optimize the performance and responsiveness of computing systems. Schedulers can be challenging to adapt to specific characteristics and configurations of underlying hardware. This limitation can lead to suboptimal task allocation, which impacts the overall performance and efficiency of the system. Short description of the characters

[0002] Some examples of devices and / or methods are described below solely by way of example and with reference to the accompanying figures, in which: Fig. 1 illustrates a block diagram of an example of a device or component; Fig. 2 illustrates a block diagram of an example of a device or component; Fig. 3 illustrates a temperature measurement distribution across processor circuitry including a plurality of processor cores by a core neighborhood ignorance scheduler; Fig. 4 illustrates a temperature measurement distribution across processor circuitry including a plurality of processor cores by a core neighborhood knowledge scheduler; Fig. Figure 5 illustrates a core temperature comparison for the system from Fig. 3 and the system from Fig. 4; Fig. 6 illustrates a flowchart of an example of a method; and Fig. 7 illustrates a flowchart of an example method. Detailed description

[0003] Some examples will now be described in more detail with reference to the accompanying figures. However, other possible examples are not limited to the features of these detailed embodiments. Other examples may include modifications of the features, as well as equivalents and alternatives to the features. Furthermore, the terminology used herein to describe specific examples is not intended to be limiting of other possible examples.

[0004] Throughout the description of the figures, identical or similar reference numerals refer to identical or similar elements and / or features, which may be implemented identically or in a modified form while providing the same or a similar function. Furthermore, in the figures, the thicknesses of lines, layers, and / or regions may be exaggerated for clarity.

[0005] When two elements A and B are combined using "or," this is to be understood as disclosing all possible combinations, i.e., only A, only B, and A and B, unless explicitly defined otherwise in the individual case. Alternative wording for the same combinations may be "at least one of A and B" or "A and / or B." This applies accordingly to combinations of more than two elements.

[0006] If a singular form is used, such as "a," "an," and "the," and the use of only a single element is neither explicitly nor implicitly defined as mandatory, further examples may also use multiple elements to implement the same function. If a function is subsequently described as being implemented using multiple elements, further examples may implement the same function using a single element or a single processing entity.It is further understood that the terms "comprises", "comprising", "has" and / or "having" when used describe the presence of the specified features, integers, steps, operations, processes, elements, components and / or a group thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, processes, elements, components and / or a group thereof.

[0007] While specific details are set forth in the following description, aspects of the technologies described herein may be practiced without these specific details. Well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring an understanding of this description. "An example," "various examples," "some examples," and the like may include features, structures, or characteristics, but not every example necessarily includes the particular features, structures, or characteristics.

[0008] Some examples may have some, all, or none of the characteristics described for other examples. "First," "second," "third," and the like describe a common element and indicate that reference is made to different instances of like elements. Such adjectives do not imply that an element so described must be in a given order, whether temporally, spatially, in rank, or in any other way. "Connected" may indicate that elements are in direct physical or electrical contact with each other, and "coupled" may indicate that elements cooperate or interact with each other, but they may or may not be in direct physical or electrical contact.

[0009] As used herein, the terms “operating,” “executing,” or “running,” as they refer to software or firmware with respect to a system, device, platform, or resource, are used interchangeably and may refer to software or firmware stored in one or more computer-readable storage media that is accessible by the system, device, platform, or resource even though the instructions contained in the software or firmware are not actively being executed by the system, device, platform, or resource.

[0010] The description may use the terms "in one example," "in examples," "in some examples," and / or "in various examples," each of which may refer to one or more of the same or different examples. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to examples of the present disclosure, are synonymous.

[0011] Task schedulers, such as operating system (OS) thread and application-level schedulers, can allocate work to compute resources. Current schedulers may be unaware of the physical layout of processor cores or their thermal characteristics. This can result in greater power consumed by a cooling system, reduced core performance, and / or greater part degradation due to inefficient distribution of temperature-increasing workloads on the die.

[0012] Regarding part degradation, some approaches involve a scheduler that assigns work using a round-robin methodology, as this can produce more even wear across cores. However, this is a blind approach, as it may not consider core layout, nor does it consider core temperatures, which could lead to greater thermal degradation if heated more frequently by neighboring cores.

[0013] Some schedulers can consider many parameters (such as Non-Uniform Memory Access, or NUMA, affinity) when assigning work to cores. According to the present disclosure, a scheduler can add the physical layout of (processor) cores and their thermal characteristics to the parameters considered. The proposed scheduler can assign work to cores that are physically distant and therefore less susceptible to performance limitations due to thermal throttling.

[0014] Fig. 1 illustrates a block diagram of an example of a device 100 or a device 100. The device 100 includes circuitry configured to provide the functionality of the device 100. For example, the device 100 of Fig. 1 an interface circuitry 120, a processor circuitry 130 and an (optional) storage circuitry 140. For example, the processor circuitry 130 may be coupled to the interface circuitry 120 and optionally to the storage circuitry 140.

[0015] For example, processor circuitry 130 may be configured to provide the functionality of device 100 in conjunction with interface circuitry 120. For example, interface circuitry 120 is configured to exchange information, e.g., with other components inside or outside device 100 and storage circuitry 140. Likewise, device 100 may include means configured to provide the functionality of device 100.

[0016] The components of the device 100 are defined as component means that correspond to or can be implemented by the respective structural components of the device 100. For example, the device 100 of Fig. 1a Means for processing 130, which correspond to or may be implemented by the processor circuitry 130, means for communicating 120, which correspond to or may be implemented by the interface circuitry 120, and (optional) means for storing information 140, which correspond to or may be implemented by the storage circuitry 140. In the following, the functionality of the component 100 is illustrated with respect to the device 100. Features described in connection with the device 100 can thus also be applied to the corresponding component 100.

[0017] In general, the functionality of the processor circuitry 130 or the means for processing 130 may be implemented by the processor circuitry 130 or the means for processing 130 executing machine-readable instructions. Accordingly, any feature attributed to the processor circuitry 130 or the means for processing 130 may be defined by one or more of a plurality of machine-readable instructions. The device 100 or component 100 may include the machine-readable instructions, e.g., within the storage circuitry 140 or the means for storing information 140.

[0018] The interface circuitry 120 or the means for communicating 120 may correspond to one or more inputs and / or outputs for receiving and / or transmitting information, which may be in digital (bit) values ​​according to a specified code, within a module, between modules, or between modules of different entities. For example, the interface circuitry 120 or the means for communicating 120 may comprise circuitry configured to receive and / or transmit information.

[0019] For example, the processor circuitry 130 or the means for processing 130 may be implemented using one or more processing units, one or more processing devices, any means for processing, such as a processor, a computer, or a programmable hardware component operable with appropriately adapted software. In other words, the described function of the processor circuitry 130 or the means for processing 130 may also be implemented in software, which is then executed on one or more programmable hardware components. Such hardware components may include a general-purpose processor, a digital signal processor (DSP), a microcontroller, etc.

[0020] For example, the storage circuitry 140 or the means for storing information 140 may comprise at least one member of the group of computer-readable storage media, such as a magnetic or optical storage medium, e.g., a hard disk drive, flash memory, a floppy disk, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electronically erasable programmable read-only memory (EEPROM), or network storage. For example, the storage circuitry 140 may store a (UEFI) BIOS.

[0021] Processor circuitry 130 is configured to obtain a physical layout of a first processor circuitry comprising a plurality of processor cores and thermal information of the plurality of processor cores. Processor circuitry 130 is configured to determine a first processor core of the plurality of processor cores to execute a first workload based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores.

[0022] In some examples, the first processor circuitry may be the same as processor circuitry 130. In this case, circuitry 130 may, for example, receive the physical layout of the first processor circuitry from storage circuitry 140. For example, the first processor core of processor circuitry 130 may execute the first workload.

[0023] In some examples, the first processor circuitry may be different from processor circuitry 130. In this case, circuitry 130 may, for example, receive the physical layout of the first processor circuitry via interface circuitry 120 from another device that includes the first processor circuitry. For example, the particular first processor core is sent to the first processor circuitry via interface circuitry 120.

[0024] The physical layout of the first processor circuitry comprising a plurality of processor cores may be a spatial representation of the processor cores within the first processor circuitry. In some examples, the physical layout of the first processor circuitry may be a spatial representation that also includes other components of the first processor circuitry, such as interconnects, memory controllers, power management, I / O interfaces, etc. In some examples, the physical layout of the first processor circuitry may be a 2-dimensional (2D) or 3-dimensional spatial representation of components of the first processor circuitry. That is, the physical layout may include components arranged in a plane or in stacked layers to represent their spatial position within the first processor circuitry.

[0025] In some examples, the physical layout includes at least a spatial positioning of the processor cores within the processor circuitry. In some examples, the physical layout includes at least a spatial positioning of the processor cores relative to each other within a 2-dimensional plane within the processor circuitry (see Fig. 3 and Fig. 4). For example, the spatial physical layout

[0026] In some examples, the physical layout of the first processor circuitry may be determined during a manufacturing process of the first processor circuitry, for example, a silicon manufacturing company. In other examples, the physical layout of the first processor circuitry may be determined by applying power-intensive workloads to the processor cores of the first processor circuitry, measuring the corresponding temperature profile of the processor cores (and, in some examples, other components), and deriving the physical layout based thereon. This is explained in more detail below. For example, the physical layout of the first processor circuitry may be determined by circuitry 130 or by another device and sent to circuitry 130.

[0027] In some examples, the thermal information of the plurality of processor cores may include a temperature measurement for each of the plurality of cores. Device 100, for example, circuitry 130, may include sensors to measure the temperature of the plurality of processor cores.

[0028] In some examples, the thermal information of the plurality of processor cores may include a thermal throttling threshold for each of the plurality of cores. The thermal throttling threshold for a processor core may indicate the maximum temperature limit beyond which the core will reduce its performance to prevent overheating. In some examples, the thermal information of the plurality of processor cores may include a heat dissipation value for each of the plurality of cores. The heat dissipation value for each core may indicate the amount of heat each core can emit during a given period of time, i.e., how quickly a processor core can cool.

[0029] Processor circuitry 130 is configured to determine the first processor core of the plurality of processor cores to execute the first workload based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores. In other words, assigning the workload to a specific processor core also takes into account (among other factors) the current temperature measurement of the processor cores and their corresponding spatial position within the physical layout of the processor circuitry.

[0030] In some examples, the workload may be a task, a process, an application, or a virtual machine. That is, the workload may refer to a single task that is a specific operation or a small sequence of operations, or it may refer to a process that is a program in execution that contains one or more tasks. The workload may also refer to an application, which may be a complete software program designed for end users. In some examples, the workload may refer to a virtual machine, which is an emulation of a computer system that provides the functionality of a physical computer, allowing multiple instances to run on a single physical hardware resource. In some examples, the processor circuitry 130 may be configured to assign the first workload to the first processor core.The first processor core can then execute the first workload.

[0031] This temperature-based scheduling of workloads, as described in this disclosure, may result in the heat generated by the workload being more evenly distributed across the first processor circuitry. Therefore, the cooling system of the first processor circuitry may require less power, resulting in increased energy efficiency. Furthermore, thermal degradation of the first processor circuitry, or portions thereof, may be more evenly distributed, increasing the longevity of the first processor circuitry. Furthermore, when a processor core hits the thermal throttling threshold, it may reduce its clock speed or power consumption to reduce heat generation, resulting in a loss of performance.Therefore, due to temperature-based scheduling of workloads as described in this disclosure, processor cores may be less likely to hit their thermal throttling threshold, which may result in better performance.

[0032] In some examples, a pre-existing scheduling algorithm may be used, incorporating the current temperature measurement of the processor cores and their corresponding spatial position within the physical layout of the processor circuitry as an additional factor to decide which processor core should execute the first workload. Determining a processor core

[0033] For example, circuitry 130 may be configured to determine the first processor core of the plurality of processor cores to execute the first workload only among the processor cores of the processor circuitry that are not currently executing a workload. For example, circuitry 130 may be configured to determine a processor core for new workloads, i.e., a workload for which execution may not have begun yet.

[0034] In some examples, circuitry 130 may be configured to determine the first processor core of the plurality of processor cores to execute the first workload, wherein the first processor core has a lowest temperature measurement among the plurality of processor cores of the processor circuitry. In some examples, circuitry 130 may be configured to determine the first processor core of the plurality of processor cores to execute the first workload, wherein the first processor has a temperature that is below a predetermined value. For example, the first processor core is selected because it has a temperature below 40°C, 50°C, 60°C, or the like.

[0035] In some examples, circuitry 130 may be configured to determine the first processor core of the plurality of processor cores to execute the first workload, wherein the first processor core has a temperature below the average temperature of the plurality of processor cores. The average temperature of the plurality of processor cores may generally refer to a representative value that summarizes the temperatures across multiple processor cores. For example, the average temperature of the plurality of processor cores may refer to the mean (the total of all core temperatures divided by the number of cores), other statistical measures such as the median (the middle value when ranking core temperatures), the mode (the most common temperature value), or the like.

[0036] In some examples, processor circuitry 130 may be configured to determine a subdivision of the physical layout of the first processor circuitry into a plurality of regions, wherein each region of the plurality of regions comprises one or more processor cores of the plurality of processor cores. For example, the physical layout may be divided into a number of equally sized regions. For example, each region of the plurality of regions comprises an equal number of processor cores of the plurality of processor cores. For example, each region of the plurality of regions comprises between 2 and 10 processor cores of the plurality of processor cores.

[0037] In another example, the one or more regions may include a different set of processor cores.

[0038] In some examples, processor circuitry 130 may be configured to designate the first processor core as part of a first region of the plurality of regions. The first region may have the lowest average processor core temperature measurement. For example, after dividing the physical layout of the first processor circuitry into a plurality of regions, each region comprising one or more processor cores, an average temperature is determined for each region. For example, the average temperature may refer to the mean temperature of all processor cores in a region (the average is understood as described above). The region with the lowest average temperature may be referred to as the first region.If there is more than one processor core in the first range, then in some examples, the first processor core is randomly selected from among the processor cores in the first range. In another example, the first processor core is determined as a processor core with the lowest processor core temperature measurement in the first range. Determining a second processor core

[0039] In some examples, processor circuitry 130 may be configured to determine a second processor core of the plurality of processor cores to execute a second workload based on the physical layout of the first processor circuitry, based on the thermal information of the plurality of processor cores, and / or based on the particular first processor core executing the first workload. In some examples, processor circuitry 130 may be configured to determine the second processor core based on the spatial position of the particular first processor core executing the first workload within the physical layout of the first processor circuitry. In other words, the assignment of the second workload to the second processor core may be further based on the previous assignment of the first workload to the first processor core (or vice versa).

[0040] For example, the second processor core may be determined such that a predetermined spatial relationship is maintained between the first processor core and the second processor core within the physical layout of the first processor circuitry. For example, the second processor core is determined such that there is a predetermined distance between the first processor core and the second processor core—i.e., a predetermined number of processor cores.

[0041] In some examples, the first processor core and / or the second processor core are determined such that the first processor core and the second processor core are not adjacent processor cores within the physical layout of the first processor circuitry. For example, the first processor core may not share a plane (in the case of a 3D layout), an edge, or a vertex. In some cases, they may share a vertex and not be considered adjacent.

[0042] In some examples, the first processor core and / or the second processor core are determined such that the first processor core and the second processor core have a predetermined spacing, with a predetermined number of processor cores between the first processor core and the second processor core. The predetermined number of processor cores between the first processor core and the second processor core can be counted as the number of processor cores that must be traversed to get from the first processor core to the second processor core.

[0043] In some examples, the first processor core and / or the second processor core are determined such that a maximum possible spacing within the physical layout lies between the first processor and the second processor. The maximum possible spacing may refer to a maximum distance measure between the two processor cores (may be from the center of the first processor core to the center of the second processor) or it may refer to a maximum number of processor cores between the two processor cores.

[0044] For example, the first processor core is first determined to execute the first workload, then the second processor core is determined such that the condition as above is met. If the second processor core is first determined to execute the second workload, then the first processor core is determined such that the condition as above is met.

[0045] In the event that the first processor core is first determined to execute the first workload, processor circuitry 130 may be configured to determine the second processor core as part of a second region of the plurality of regions, wherein the second region has the second lowest average processor core temperature measurement. The plurality of regions and the corresponding average temperature may be determined as described above. The first processor core may have been determined as part of the first region with the lowest average processor core temperature measurement.

[0046] As described with respect to the first range, in some examples, the second processor core is randomly selected from among the processor cores in the second range. In another example, the second processor core is selected as the processor core with the lowest processor core temperature measurement in the second range.

[0047] Further details and aspects are mentioned in connection with the examples described below. Fig. 1 may comprise one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described below (e.g. Fig. 2 - 7). Reassigning a workload

[0048] Fig. 2 illustrates a block diagram of an example of a device 200 or device 200. The device 200 includes circuitry configured to provide the functionality of the device 200. For example, the device 200 of Fig. 2 an interface circuitry 220, a processor circuitry 230, and an (optional) storage circuitry 240. For example, the processor circuitry 230 may be coupled to the interface circuitry 220 and optionally to the storage circuitry 240. For example, the processor circuitry 230 may be configured to provide the functionality of the device 200 in conjunction with the interface circuitry 220. For example, the interface circuitry 220 is configured to exchange information, e.g., with other components inside or outside the device 200 and the storage circuitry 240. Likewise, the device 200 may comprise means configured to provide the functionality of the device 200.

[0049] The device 200 and the interface circuitry 220, the processor circuitry 230 and the storage circuitry 240 may be identical or different from the device 100 and its circuitry.

[0050] In some examples, circuitry 230 may be configured to move the execution of workloads from a current processor core to another processor core within the processing circuitry in the event that the current processor core may be thermally throttled due to a high temperature. For example, the current processor core and the other processor core are physically separated within the physical layout and are therefore less likely to be affected by the temperature of neighboring cores.

[0051] In some examples, processor circuitry 230 may be configured to obtain a physical layout of first processor circuitry including a plurality of processor cores and thermal information of the plurality of processor cores. Further, processor circuitry 230 may be configured to identify a first processor core of the plurality of processor cores executing a first workload based on thermal information of the first processor core. For example, the first processor core is identified as the processor core with the highest current temperature among the plurality of processor cores. In another example, the first processor core is identified as the first processor core to exceed its predefined thermal throttling threshold.In another example, the first processor core is identified as the processor core that most exceeds its predefined thermal throttling threshold in percentage or absolute temperatures.

[0052] Further, processor circuitry 230 may be configured to determine a second processor core of the plurality of processor cores to execute the first workload based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores. The second processor core may be determined as described above (with respect to the first or second processor core as described above). For example, the second processor core may be the processor core with the lowest temperature measurement.

[0053] In another example, the second processor core may be determined such that a predetermined spatial relationship within the physical layout of the first processor circuitry is maintained between the first processor core and the second processor core (see above for various examples in this regard). For example, the second processor core is determined such that there is a predetermined distance between the first processor core and the second processor core—i.e., a predetermined number of processor cores.

[0054] In some examples, a temperature measurement of the first core is higher than a temperature measurement of the second core.

[0055] Furthermore, processor circuitry 230 may be configured to assign the first workload to the second processor core. In other words, the first workload executed by one processor core that causes temperature-related thermal difficulties is reassigned to another processor core that is in a more favorable thermal state.

[0056] This temperature-based reassignment of workloads, as described in this disclosure, may result in the heat generated by the workload being distributed more evenly across the first processor circuitry. Therefore, the cooling system of the first processor circuitry may require less power, resulting in increased energy efficiency. Furthermore, thermal degradation of the first processor circuitry, or portions thereof, may be more evenly distributed, increasing the longevity of the first processor circuitry. Furthermore, the temperature-based rescheduling of workloads, as described in this disclosure, increases performance by offloading processor cores that may have reached a thermal throttling threshold. Example for determining the physical layout of the first processor circuitry

[0057] As stated above, the physical layout of the first processor circuitry comprising a plurality of (processor) cores may be obtained as described in the following approach: The concept of deriving a physical layout of processor circuitry comprising a plurality of processor cores may include (one, some, or all of) the following four phases: Phase 1: Collecting temperature data (of the plurality of cores) by heating one core at a time using a power-intensive workload. When a particular core is executing this power-intensive workload, all other cores may be idle. Phase 2: Using the collected temperature data, perform a linear regression between the heated core and all other cores. Phase 3: Performing a cluster analysis on the regression data to determine the nearby cores for each heated core.Phase 4: Correlating the nearby cores of each heated core to determine the physical layout of the processor circuitry on the die. These four phases are described in more detail below.

[0058] A first phase of the disclosed technique of deriving a physical layout of processor circuitry comprising a plurality of processor cores may include collecting thermal telemetry data from each processor in the system under test. Therefore, for example, publicly available performance registers may be used to monitor core temperatures. For example, the following method may be performed in this regard: 1. Collect all individual core temperatures (of all processor cores of a processor circuitry) at a predetermined time interval, for example, every 200 milliseconds or the like. 2. Bind a power-intensive workload to a core. This may cause the core to heat up over time. 3. Stop collecting core temperatures. 4. Repeat steps 1, 2, and 3 for each core in the processor circuitry (the system).

[0059] A second phase of the disclosed technique of deriving a physical layout of processor circuitry comprising a plurality of processor cores may include performing a linear regression on the collected temperature data of Phase 1. For example, the following method may be performed in this regard: 1. Performing a linear regression between the heated core and another core of the processor circuitry and obtaining a coefficient representing the temperature relationship between the two cores. 2. Repeating step 1 for each core in the system and obtaining N-1 coefficients, where N is the number of processor cores in the processor circuitry (i.e., the system). 3. Repeating steps 1 and 2 for N data sets (where each data set is collected in Phase 1 and corresponds to a different core that is heated).After deriving the N - 1 regression coefficients for each of the N processor cores, an ordered list of coefficients (matrix) can be generated for each loaded core.

[0060] A third phase of the disclosed technique of deriving a physical layout of processor circuitry comprising a plurality of processor cores may comprise performing a cluster analysis on the table output of Phase 2. This may be performed using rule-based algorithms or machine learning algorithms known to those skilled in the art, such as a K-Means algorithm. For example, the top 4-5 clusters may be identified. The cluster analysis may be performed by a K-Means algorithm (e.g., K = 4 or 5) based on the regression coefficients of a core obtained in Phase 2. This clustering may be performed for each of the N-1 regression coefficients of the N cores obtained in Phase 2. The identified clusters may have the following definitions: Cluster 1 may be the processing core executing a performance-intensive workload.Cluster 2 may be the closest cores to the processing core running a power-intensive workload, i.e., neighboring cores sharing a surface (where the processing core is running a power-intensive workload). Cluster 3 may be the second closest processing cores, i.e., edge cores sharing an edge (where the processing core is running a power-intensive workload). Cluster 4 may be [this can only be for stacked / 3D layouts] the third closest cores, i.e., kitty-corner cores sharing a cube corner (where the processing core is running a power-intensive workload). Cluster 5 may be all other cores, likely separated from the heated core by one or more cores.

[0061] A fourth phase of the disclosed technique for deriving a physical layout of processor circuitry comprising a plurality of processor cores may involve correlating nearby cores of each heated core to determine the physical layout. This may be based on the clustering results for each loaded core obtained in Phase 3. This may programmatically generate a possible physical layout (die layout) in 1D, 2D, or 3D. For example, the process for mapping the processing cores according to their clustering coefficient may be as follows: 1. Select a loaded core X (core executing a power-intensive workload) and spatially lay out all cores into 2, 3, 4 clusters in a manner that maximizes thermal affinity and does not violate any spatial rules (e.g., no more than 6x adjacent cores, 12x edge cores, etc.). m2.Select a core from those surrounding core X, starting with cores in cluster 2, then 3, and then 4, and repeat step 1 for that core to fill in the nearby cores. This process ends when all cores in clusters 2, 3, and 4 have been mapped. 3. If there are cores not mapped in steps 1 and 2, repeat steps 1 and 2 until all cores in the system have been mapped (i.e., this can lead to many independent islands of mapped cores due to multiple tiles, or otherwise thermally isolated cores). 4. If there are multiple islands of mapped cores, orient them according to knowledge obtained from the cores that fall into cluster 5 in phase 3. Examples

[0062] Fig. 3 illustrates a temperature (measurement) distribution 300 across processor circuitry comprising a plurality of processor cores by a core neighborhood ignorance scheduler. Fig. Figure 3 shows that the farther the nuclei are from the heated nuclei 1-4, the lower the nucleus temperature (the darker the color of the nucleus, the cooler the nucleus temperature). That is, nuclei 6-10 have a higher temperature than nuclei 11-15, higher than 15-20, and higher than 21-25. As shown in Fig. As shown in Figure 3, scheduling workloads on adjacent cores can lead to larger individual core temperatures. For example, processor cores 1 and 4 each have a temperature of 55°C. For example, processor cores 2 and 3 each have a temperature of 60°C. This can lead to the following disadvantages: Higher individual core temperatures can cause thermal throttles to be triggered, resulting in reduced performance on the triggered cores. A higher concentration of heat in one area on the die can lead to less efficient passive cooling from the heat sink, which in turn can require more active cooling, which can lead to greater power consumption by the cooling system. Higher individual core temperatures can lead to greater thermal degradation and can reduce the lifetime of the affected cores (see also the left-side diagram in Fig. 5).

[0063] Further details and aspects are mentioned in connection with the examples described above or below. Fig. 3 may comprise one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described above or below.

[0064] Fig. 4 illustrates a temperature (measurement) distribution 400 across a processor circuitry comprising a plurality of processor cores by a core neighborhood awareness scheduler. The scheduler, as proposed in this disclosure, is aware of the core neighborhoods. Therefore, workloads 1 to 4 can be assigned to processor cores 1, 5, 21, and 25. These processor cores are located in the corners of the processor circuitry and can therefore have a maximum distance from each other. Therefore, the disadvantages described above can be mitigated. For example, processor cores 1, 5, 21, and 25 each have a temperature of 50°C, which is lower than Fig. 3 is lower. There may be significant performance and power improvements that a core neighborhood knowledge scheduler such as the one proposed in this disclosure can exhibit (these improvements may apply to all modern processors, and therefore the potential impact on the entire industry would be even more significant).

[0065] A variety of scheduling algorithms known to those skilled in the art may be used. These algorithms may consider resource availability and timing constraints. Any of these existing algorithms may be enhanced by considering the physical layout of all cores in a die and their thermal characteristics, as proposed in this disclosure. A core-neighborhood-aware scheduler may schedule new workloads or shift existing thermally throttled workloads to cores that are physically distant and therefore likely to be less affected by the temperature of neighboring cores.

[0066] Further details and aspects are mentioned in connection with the examples described above or below. Fig. The example shown in Figure 4 may comprise one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described above or below.

[0067] Fig. Figure 5 illustrates a core temperature comparison for the system from Fig. 3, ie diagram 510, and the system from Fig. 4, i.e., chart 520. Chart 510 shows the temperature of the cores running workloads 1 to 4, where the workloads are assigned to processor cores 1 to 4 without taking temperature into account (see Fig. 3). That is, the first core 512 (No. 1 in Fig. 3) executes workload 1, the second core 514 (No. 2 in Fig. 3) executes workload 2, the third core (No. 3 in Fig. 3) 516 executes workload 3, the fourth core (No. 4 in Fig. 3) 518 is running workload 4. Processor cores 512 and 518 each have a temperature of 55°C, and processor cores 514 and 516 each have a temperature of 60°C. All cores have a temperature above a predefined thermal throttling threshold 530.

[0068] Chart 520 shows the temperature of the cores running workloads 1 to 4, where the workloads are assigned to the processor cores by taking the temperature into account (see Fig. 4) as described in this disclosure. That is, the first core 522 (No. 1 in Fig. 3) executes workload 1, the second core 524 (No. 5 in Fig. 3) executes workload 2, the third core (No. 21 in Fig. 3) 526 executes workload 3, the fourth core (No. 25 in Fig. 3) 528 is running workload 4. The corresponding measured core temperatures are evenly distributed and therefore lower than in chart 510. All cores have a temperature above a predefined thermal throttling threshold 530.

[0069] The proposed technique can be identified by monitoring the distribution of workloads across a die. If temperature-increasing workloads are running on physically distant cores, this could indicate the use of a workload scheduler, such as the one proposed, that is aware of the physical layout of the die. Measuring the heat distribution across a die could be used to detect whether the proposed technique is being used.

[0070] Further details and aspects are mentioned in connection with the examples described above or below. Fig. The example shown in Figure 5 may comprise one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described above or below.

[0071] Fig. 6 illustrates a flowchart of an example of a method 600. The method 600 may be performed, for example, by a device as described herein, such as device 100. The method 600 includes obtaining 610 a physical layout of a first processor circuitry including a plurality of processor cores and thermal information of the plurality of processor cores. The method 600 further includes determining 620 a first processor core of the plurality of processor cores to execute a first workload based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores.

[0072] Further details and aspects of the method 600 will be described in connection with the proposed technique or one or more examples described above, e.g., with reference to Fig. 1. The method 600 may include one or more additional optional features corresponding to one or more aspects of the proposed technique or one or more of the examples described above or below.

[0073] Fig. 7 illustrates a flowchart of an example of a method 700. The method 700 may be performed, for example, by a device as described herein, such as the device 200. The method 700 includes obtaining 710 a physical layout of first processor circuitry including a plurality of processor cores and thermal information of the plurality of processor cores. The method 700 further includes identifying 720 a first processor core of the plurality of processor cores that executes a first workload based on thermal information of the first processor core. The method 700 further includes determining 730 a second processor core of the plurality of processor cores to execute the first workload based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores.A temperature measurement of the first core is higher than a temperature measurement of the second core. The method 700 further includes assigning 740 the first workload to the second processor core.

[0074] Further details and aspects of the method 700 will be described in connection with the proposed technique or one or more examples described above, e.g., with reference to Fig. 2. The method 700 may include one or more additional optional features corresponding to one or more aspects of the proposed technique or one or more of the examples described above. Some examples of the proposed technique are presented below: Some examples of the proposed concept are presented below:

[0075] One example (e.g., Example 1) relates to an apparatus comprising interface circuitry, machine-readable instructions, and processor circuitry to execute the machine-readable instructions to obtain a physical layout of a first processor circuitry comprising a plurality of processor cores and thermal information of the plurality of processor cores to determine a first processor core of the plurality of processor cores to execute a first workload based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores.

[0076] Another example (e.g., Example 2) relates to a previous example (e.g., Example 1) or any other example, further comprising the thermal information of the plurality of processor cores comprising at least one of a temperature measurement for each of the plurality of cores, a thermal throttling threshold for each of the plurality of cores, or a heat dissipation value for each of the plurality of cores.

[0077] Another example (e.g., Example 3) relates to a previous example (e.g., any of Examples 1-2) or any other example, further comprising at least the first processor core having a lowest temperature measurement among the plurality of processor cores, the first processor having a temperature that is below a predetermined value, the first processor core having a temperature below a temperature measurement of at least half of the plurality of processor cores.

[0078] Another example (e.g., Example 4) relates to a previous example (e.g., any of Examples 1-3) or any other example, further comprising the processor circuitry configured to execute the machine-readable instructions to determine a second processor core of the plurality of processor cores to execute a second workload based on the physical layout of the first processor circuitry, the thermal information of the plurality of processor cores, and / or the particular first processor core executing the first workload.

[0079] Another example (e.g., Example 5) relates to a previous example (e.g., Example 4) or any other example, further comprising determining the first processor core and / or the second processor core such that at least the first processor core and the second processor core are non-adjacent processor cores within the physical layout of the first processor circuitry, the first processor core and the second processor core have a predetermined spacing, a predetermined number of processor cores are between the first processor core and the second processor core, or a maximum possible spacing within the physical layout is between the first processor and the second processor.

[0080] Another example (e.g., Example 6) relates to a previous example (e.g., any of Examples 1 to 5) or any other example, further comprising the processor circuitry configured to execute the machine-readable instructions to determine a division of the physical layout of the first processor circuitry into a plurality of regions, each region of the plurality of regions comprising one or more processor cores of the plurality of processor cores.

[0081] Another example (e.g., Example 7) relates to a previous example (e.g., Example 6) or any other example, further comprising the processor circuitry configured to execute the machine-readable instructions to determine the first processor core as part of a first region of the plurality of regions, the first region having a lowest average processor core temperature measurement.

[0082] Another example (e.g., Example 8) relates to a previous example (e.g., Example 7) or any other example, further comprising at least the first processor core being randomly selected from among the processor cores in the first range, or the first processor core being a processor core with the lowest processor core temperature measurement in the first range.

[0083] Another example (e.g., Example 9) relates to a previous example (e.g., any of Examples 6-8) or any other example, further comprising the processor circuitry configured to execute the machine-readable instructions to determine the second processor core as part of a second region of the plurality of regions, the second region having the second lowest average processor core temperature measurement.

[0084] Another example (e.g., Example 10) relates to a previous example (e.g., Example 9) or any other example, further comprising at least the second processor core being randomly selected from among the processor cores in the second range, or the second processor core being a processor core with the lowest processor core temperature measurement in the second range.

[0085] Another example (e.g., Example 11) relates to a previous example (e.g., any of Examples 6-10) or any other example, further comprising each region of the plurality of regions comprising an equal number of processor cores of the plurality of processor cores.

[0086] Another example (e.g., Example 12) relates to a previous example (e.g., Example 11) or any other example, further comprising where each region of the plurality of regions comprises between 2 to 10 processor cores of the plurality of processor cores.

[0087] Another example (e.g., Example 13) relates to a previous example (e.g., any of Examples 1 to 12) or any other example, further comprising the processor circuitry configured to execute the machine-readable instructions to assign the first workload to the first processor core.

[0088] Another example (e.g., Example 14) relates to a previous example (e.g., any of Examples 1 to 13) or any other example, further comprising the physical layout comprising a spatial positioning of the processor cores within the processor circuitry.

[0089] Another example (e.g., Example 15) relates to a previous example (e.g., any of Examples 1 to 14) or any other example, further comprising the physical layout comprising spatial positioning of the processor cores relative to each other within a 2-dimensional plane within the processor circuit.

[0090] Another example (e.g., Example 15) relates to a previous example (e.g., any of Examples 1-15) or any other example, further including where the first workload may be a task, a process, an application, or a virtual machine.

[0091] One example (e.g., Example 16) relates to an apparatus comprising interface circuitry, machine-readable instructions, and processor circuitry to execute the machine-readable instructions, to obtain a physical layout of a first processor circuitry comprising a plurality of processor cores and thermal information of the plurality of processor cores, to identify a first processor core of the plurality of processor cores executing a first workload based on thermal information of the first processor core, to determine a second processor core of the plurality of processor cores to execute the first workload based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores, wherein a temperature measurement of the first core is higher than a temperature measurement of the second core,and to assign the first workload to the second processor core.

[0092] One example (e.g., Example 17) relates to an apparatus comprising processor circuitry configured to obtain a physical layout of a first processor circuitry comprising a plurality of processor cores and thermal information of the plurality of processor cores to determine a first processor core of the plurality of processor cores to execute a first workload based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores.

[0093] One example (e.g., Example 18) relates to a device comprising means for processing to obtain a physical layout of a first processor circuitry comprising a plurality of processor cores and thermal information of the plurality of processor cores to determine a first processor core of the plurality of processor cores to execute a first workload based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores.

[0094] One example (e.g., Example 19) relates to a method including obtaining a physical layout of a first processor circuitry including a plurality of processor cores and thermal information of the plurality of processor cores to determine a first processor core of the plurality of processor cores to execute a first workload based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores.

[0095] Another example (e.g., Example 20) relates to a previous example (e.g., Example 19) or any other example, further comprising the thermal information of the plurality of processor cores comprising at least one of a temperature measurement for each of the plurality of cores, a thermal throttling threshold for each of the plurality of cores, or a heat dissipation value for each of the plurality of cores.

[0096] Another example (e.g., Example 21) relates to a previous example (e.g., any of Examples 19-20) or any other example, further comprising at least the first processor core having a lowest temperature measurement among the plurality of processor cores, the first processor having a temperature that is below a predetermined value, the first processor core having a temperature below a temperature measurement of at least half of the plurality of processor cores.

[0097] Another example (e.g., Example 22) relates to a previous example (e.g., any of Examples 19-21) or any other example, further comprising determining a second processor core of the plurality of processor cores to execute a second workload based on the physical layout of the first processor circuitry, the thermal information of the plurality of processor cores, and / or the determined first processor core executing the first workload.

[0098] Another example (e.g., Example 23) relates to a previous example (e.g., Example 18) or any other example, further comprising determining the first processor core and / or the second processor core such that at least the first processor core and the second processor core are non-adjacent processor cores within the physical layout of the first processor circuitry, the first processor core and the second processor core have a predetermined spacing, a predetermined number of processor cores are between the first processor core and the second processor core, or a maximum possible spacing within the physical layout is between the first processor and the second processor.

[0099] Another example (e.g., Example 24) relates to a previous example (e.g., any of Examples 19-23) or any other example, further comprising determining a division of the physical layout of the first processor circuitry into a plurality of regions, each region of the plurality of regions comprising one or more processor cores of the plurality of processor cores.

[0100] Another example (e.g., Example 25) relates to a previous example (e.g., Example 24) or any other example, further comprising determining the first processor core as part of a first region of the plurality of regions, the first region having a lowest average processor core temperature measurement.

[0101] Another example (e.g., Example 26) relates to a previous example (e.g., Example 25) or any other example, further comprising at least the first processor core being randomly selected from among the processor cores in the first range, or the first processor core being a processor core with the lowest processor core temperature measurement in the first range.

[0102] Another example (e.g., Example 27) relates to a previous example (e.g., any of Examples 24-26) or any other example, further comprising determining the second processor core as part of a second region of the plurality of regions, the second region having the second lowest average processor core temperature measurement.

[0103] Another example (e.g., Example 28) relates to a previous example (e.g., Example 27) or any other example, further comprising at least the second processor core being randomly selected from among the processor cores in the second range, or the second processor core being a processor core with the lowest processor core temperature measurement in the second range.

[0104] Another example (e.g., Example 29) relates to a previous example (e.g., any of Examples 24-28) or any other example, further comprising each region of the plurality of regions comprising an equal number of processor cores of the plurality of processor cores.

[0105] Another example (e.g., Example 30) relates to a previous example (e.g., Example 29) or any other example, further comprising where each region of the plurality of regions comprises between 2 to 10 processor cores of the plurality of processor cores.

[0106] Another example (e.g., Example 31) relates to a previous example (e.g., any of Examples 19-30) or any other example, further comprising assigning the first workload to the first processor core.

[0107] Another example (e.g., Example 32) relates to a previous example (e.g., any of Examples 19-31) or any other example, further comprising the physical layout comprising a spatial positioning of the processor cores within the processor circuitry.

[0108] Another example (e.g., Example 33) relates to a previous example (e.g., any of Examples 19-32) or any other example, further comprising where the physical layout comprises spatially positioning the processor cores relative to each other within a 2-dimensional plane within the processor circuit.

[0109] Another example (e.g., Example 34) relates to a previous example (e.g., any of Examples 19-33) or any other example, further including that the first workload may be a task, a process, an application, or a virtual machine.

[0110] One example (e.g., Example 35) relates to a method comprising obtaining a physical layout of a first processor circuitry comprising a plurality of processor cores and thermal information of the plurality of processor cores, identifying a first processor core of the plurality of processor cores executing a first workload based on thermal information of the first processor core, determining a second processor core of the plurality of processor cores to execute the first workload based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores, wherein a temperature measurement of the first core is higher than a temperature measurement of the second core, and assigning the first workload to the second processor core.

[0111] Another example (e.g., Example 36) relates to a non-transitory machine-readable storage medium comprising program code that, when executed, causes a machine to perform the method of Examples 19 to 34.

[0112] Another example (e.g., Example 37) relates to a computer program having program code for performing the method of Examples 19 to 34 when the computer program is executed on a computer, a processor, or a programmable hardware component.

[0113] Another example (e.g., Example 38) relates to a machine-readable storage comprising machine-readable instructions that, when executed, implement a method or implement an apparatus as described in any pending example.

[0114] The aspects and features described in connection with a particular one of the previous examples may also be combined with one or more of the further examples to replace an identical or similar feature of that further example or to additionally introduce the features into the further example.

[0115] Examples may further be or relate to a (computer) program comprising program code for carrying out one or more of the foregoing methods, when the program is executed on a computer, a processor, or other programmable hardware component. Steps, operations, or processes of various of the methods described above may therefore also be carried out by programmed computers, processors, or other programmable hardware components. Examples may also cover program storage devices, e.g., digital data storage media, that are machine-, processor-, or computer-readable and / or encode and / or include machine-executable, processor-executable, or computer-executable programs and instructions. The program storage devices may, for example,digital storage devices, magnetic storage media, such as magnetic disks and magnetic tapes, hard disk drives, or optically readable digital data storage media. Further examples may also cover computers, processors, control units, (field-)programmable logic arrays ((F)PLAs; (field) programmable logic arrays)), (field) programmable gate arrays ((F)PGAs; (field) programmable gate arrays)), graphics processor units (GPUs), application-specific integrated circuits (ASICs), integrated circuits (ICs), or system-on-a-chip (SoCs) systems programmed to carry out the steps of the methods described above.

[0116] It is further understood that the disclosure of multiple steps, processes, operations, or functions disclosed in the specification or claims should not be construed as necessarily being in the described order, unless explicitly stated in the individual case or required for technical reasons. Therefore, the foregoing description does not limit the performance of multiple steps or functions to any particular order. Furthermore, in further examples, a single step, function, process, or operation may include and / or be broken down into multiple sub-steps, functions, processes, or operations.

[0117] If some aspects are described in connection with a component / device or a system, these aspects are also to be understood as a description of the corresponding method. For example, a block, a component, or a functional aspect of the component or system may correspond to a feature, such as a method step, of the corresponding method. Accordingly, aspects described in connection with a method are also to be understood as a description of a corresponding block, a corresponding element, a property, or a functional feature of a corresponding component or a corresponding system.

[0118] As used herein, the term "module" refers to logic that may be implemented in a hardware component or device, software or firmware running on a processing unit, or a combination thereof, to perform one or more operations consistent with the present disclosure. Software and firmware may be embodied in the form of instructions and / or data stored on non-transitory, computer-readable storage media. As used herein, the term "circuitry" may include, individually or in any combination, non-programmable hard-wired circuitry, programmable circuitry such as processing units, state machine circuitry, and / or firmware storing instructions executable by programmable circuitry.Modules described herein may be embodied collectively or individually as circuitry forming part of a computing system. Thus, any of the modules may be implemented as circuitry. A computing system referred to as being programmed to perform a method may be programmed to perform the method via software, hardware, firmware, or combinations thereof.

[0119] Any of the disclosed methods (or a portion thereof) may be implemented as computer-executable instructions or a computer program product. Such instructions may cause a computing system or one or more processing units capable of executing computer-executable instructions to perform any of the disclosed methods. As used herein, the term "computer" refers to any computing system or device described or mentioned herein. Thus, the term "computer-executable instruction" refers to instructions that can be executed by any computing system or device described or mentioned herein.

[0120] The computer-executable instructions may, for example, be part of an operating system of the computing system, an application stored locally on the computing system, or a remote application accessible to the computing system (e.g., via a web browser). Any of the methods described herein may be performed by computer-executable instructions executed by a single computing system or by one or more networked computing systems operating in a network environment. Computer-executable instructions and updates to the computer-executable instructions may be downloaded to a computing system from a remote server.

[0121] Furthermore, it should be understood that the implementation of the disclosed technology is not limited to any specific computer language or computer program. For example, the disclosed technologies may be implemented by software written in CC++, C#, Java, Perl, Python, JavaScript, Adobe Flash, C#, an assembly language, or any other programming language. Likewise, the disclosed technologies are not limited to any particular computer system or type of hardware.

[0122] Furthermore, any of the software-based examples (e.g., including computer-executable instructions for causing a computer to perform any of the disclosed methods) may be uploaded, downloaded, or remotely accessed through any suitable communication means. Such suitable communication means include, for example, the Internet, the World Wide Web, an intranet, a cable (including fiber optic cable), magnetic communication, electromagnetic communication (including RF, microwave, ultrasonic, and infrared communication), electronic communication, or other such communication means.

[0123] The disclosed methods, devices, and systems are not intended to be limiting in any way. Instead, the present disclosure is directed to all novel and non-obvious features and aspects of the various disclosed examples, alone and in various combinations and subcombinations with each other. The disclosed methods, devices, and systems are not limited to any specific aspect or feature or combination thereof, nor do the disclosed examples require any specific advantages to be present or problems to be solved.

[0124] Any operating theories, scientific principles, or other theoretical descriptions provided herein relating to the devices or methods of this disclosure are for convenience of understanding and are not to be considered limiting. The devices and methods in the appended claims are not limited to devices and methods that function in the manner described by these theories of operation.

[0125] The following claims are hereby incorporated into the Detailed Description, and each claim may stand on its own as a separate example. It should also be noted that although a dependent claim in the claims refers to a particular combination with one or more other claims, other examples may include a combination of the dependent claim with the subject matter of any other dependent or independent claim. Such combinations are hereby explicitly contemplated unless it is specifically stated that a particular combination is not intended. Furthermore, features of a claim for any other independent claim are also intended to be encompassed, even if that claim is not directly defined as dependent on that other independent claim.

Claims

[1] An apparatus comprising processor circuitry to: obtain a physical layout of a first processor circuitry comprising a plurality of processor cores and thermal information of the plurality of processor cores; determine a first processor core of the plurality of processor cores to execute a first workload based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores. [2] The apparatus of claim 1, wherein the thermal information of the plurality of processor cores comprises at least one of a temperature measurement for each of the plurality of cores, a thermal throttling threshold for each of the plurality of cores, or a heat dissipation value for each of the plurality of cores. [3] The apparatus of any one of claims 1 to 2, wherein at least: the first processor core has a lowest temperature measurement among the plurality of processor cores, the first processor has a temperature that is below a predetermined value, the first processor core has a temperature below a temperature measurement of at least half of the plurality of processor cores. [4] The apparatus of any one of claims 1 to 3, wherein the processor circuitry is further configured to determine a second processor core of the plurality of processor cores to execute a second workload based on the physical layout of the first processor circuitry, the thermal information of the plurality of processor cores, and / or the determined first processor core executing the first workload. [5] The apparatus of claim 4, wherein the first processor core and / or the second processor core are determined such that at least: the first processor core and the second processor core are non-adjacent processor cores within the physical layout of the first processor circuitry, the first processor core and the second processor core have a predetermined spacing, a predetermined number of processor cores lie between the first processor core and the second processor core, or a maximum possible spacing within the physical layout lies between the first processor and the second processor. [6] The apparatus of any one of claims 1 to 5, wherein the processor circuitry is further configured to determine a subdivision of the physical layout of the first processor circuitry into a plurality of regions, each region of the plurality of regions comprising one or more processor cores of the plurality of processor cores. [7] The apparatus of claim 6, wherein the processor circuitry is further configured to determine the first processor core as part of a first region of the plurality of regions, the first region having a lowest average processor core temperature measurement. [8] The apparatus of claim 7, wherein at least: the first processor core is randomly selected from among the processor cores in the first range, or the first processor core is a processor core having the lowest processor core temperature measurement in the first range. [9] The apparatus of any one of claims 6 to 8, wherein the processor circuitry is further configured to determine the second processor core as part of a second region of the plurality of regions, the second region having the second lowest average processor core temperature measurement. [10] The apparatus of claim 9, wherein at least: the second processor core is randomly selected from among the processor cores in the second range, or the second processor core is a processor core having the lowest processor core temperature measurement in the second range. [11] The apparatus of any one of claims 6 to 10, wherein each region of the plurality of regions comprises an equal number of processor cores of the plurality of processor cores. [12] The apparatus of claim 11, wherein each region of the plurality of regions comprises between 2 to 10 processor cores of the plurality of processor cores. [13] The apparatus of any one of claims 1 to 12, wherein the processor circuitry is further configured to assign the first workload to the first processor core. [14] The apparatus of any one of claims 1 to 13, wherein the physical layout comprises a spatial positioning of the processor cores within the processor circuitry. [15] The apparatus of any one of claims 1 to 14, wherein the physical layout comprises a spatial positioning of the processor cores relative to each other within a 2-dimensional plane within the processor circuit. [16] A method comprising: Obtaining a physical layout of a first processor circuitry comprising a plurality of processor cores and thermal information of the plurality of processor cores; Determining a first processor core of the plurality of processor cores to execute a first workload based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores. [17] The method of claim 16, wherein the thermal information of the plurality of processor cores comprises at least one of a temperature measurement for each of the plurality of cores, a thermal throttling threshold for each of the plurality of cores, or a heat dissipation value for each of the plurality of cores. [18] The method of claim 16 or 17, wherein at least: the first processor core has a lowest temperature measurement among the plurality of processor cores, the first processor has a temperature that is below a predetermined value, the first processor core has a temperature below a temperature measurement of at least half of the plurality of processor cores. [19] The method of any one of claims 16 to 18, further comprising determining a second processor core of the plurality of processor cores to execute a second workload based on the physical layout of the first processor circuitry, the thermal information of the plurality of processor cores, and / or the determined first processor core executing the first workload. [20] The method of any one of claims 16 to 19, further comprising determining a subdivision of the physical layout of the first processor circuitry into a plurality of regions, each region of the plurality of regions comprising one or more processor cores of the plurality of processor cores. [21] The method of claim 20, further comprising determining the first processor core as part of a first region of the plurality of regions, the first region having a lowest average processor core temperature measurement. [22] A device comprising processor circuitry configured to: obtain a physical layout of a first processor circuitry comprising a plurality of processor cores and thermal information of the plurality of processor cores; identify a first processor core of the plurality of processor cores executing a first workload based on thermal information of the first processor core; determine a second processor core of the plurality of processor cores to perform the first workload based on the physical layout of the first processor circuitry and the thermal information of the majority of processor cores, wherein a temperature measurement of the first core is higher than a temperature measurement of the second core; and assign the first workload to the second processor core. [23] A method comprising: Obtaining a physical layout of a first processor circuitry comprising a plurality of processor cores and thermal information of the plurality of processor cores; Identifying a first processor core of the plurality of processor cores executing a first workload based on thermal information of the first processor core; Determining a second processor core of the plurality of processor cores to execute the first workload based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores, wherein a temperature measurement of the first core is higher than a temperature measurement of the second core; and Assign the first workload to the second processor core. [24] A computer program comprising instructions which, when the program is executed by a computer, cause the computer to carry out the method according to any one of claims 16 to 21 and 23.

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