DISPLAY DEVICE

Abstract

A display device (DSP) comprises a carrier (10) having a display area (DA) in which an image is displayed and a surrounding area (SA) around the display area (DA), a plurality of display elements (DE1, DE2, DE3) arranged in the display area (DA), each including a lower electrode (LE1, LE2, LE3), an upper electrode (UE1, UE2, UE3) located above the lower electrode (LE1, LE2, LE3), and an organic layer (OR1, OR2, OR3) located between the lower electrode (LE1, LE2, LE3) and the upper electrode (UE1, UE2, UE3) and luminous in response to the application of a voltage, a first partition wall (6A) arranged in the display area (DA) and between adjacent display elements (DE1, DE2, DE3), and a second partition wall (6B) arranged in the surrounding area (SA) and connected to the first partition wall (6A) is connected.The first partition wall (6A) and the second partition wall (6B) include an electrically conductive lower portion (61) and an upper portion (62) with an end portion protruding from a side surface of the lower portion (61). Furthermore, the second partition wall (6B) has a plurality of elongated openings (APx).

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to Japanese Patent Application No. 2024-020336 filed on February 14, 2024, the entire contents of which are hereby incorporated into the present subject matter. AREA

[0002] An embodiment of the present invention relates to a display device. BACKGROUND

[0003] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put into practical use. A technology to improve yield and increase reliability is needed for such display devices. BRIEF DESCRIPTION OF THE CHARACTERS Fig. 1 is a view of a configuration example of a display device according to a first embodiment. Fig. Figure 2 is a schematic plan view showing an example of a subpixel layout. Fig. Figure 3 is a schematic sectional view of the display device along the line III-III of Fig. 2. Fig. 4 is a schematic plan view of the display device for explaining the structure of a surrounding area. Fig. Figure 5 is a schematic sectional view of a part of the surrounding area on the line VV of Fig. 4. Fig. 6 is a schematic enlarged sectional view of a part of a partition wall arranged in the surrounding area. Fig. Figure 7 is an enlarged plan view of area VII in Fig. 4. Fig. Figure 8 is an enlarged plan view of area VIII in Fig. 4. Fig. 9A is a schematic sectional view illustrating an example of a manufacturing step of the display device. Fig. Fig. 9B is a schematic sectional view showing a step subsequent to Fig. 9A shows. Fig. Figure 9C is a schematic sectional view showing a step subsequent to Fig. 9B shows. Fig. Figure 9D is a schematic sectional view showing a step subsequent to Fig. 9C shows. Fig. Figure 9E is a schematic sectional view showing a step subsequent to Fig. 9D shows. Fig. Figure 9F is a schematic sectional view showing a step subsequent to Fig. 9E shows. Fig. Figure 9G is a schematic sectional view showing a step subsequent to Fig. 9F shows. Fig. 9H is a schematic sectional view showing a step subsequent to Fig. 9G shows. Fig. 9I is a schematic sectional view showing a step subsequent to Fig. 9H shows. Fig. 10 is a schematic plan view of a surrounding area according to a comparative example. Fig. 11 is a schematic sectional view of the surrounding area according to the comparative example. Fig. 12 is a schematic enlarged sectional view of a surrounding area according to a second embodiment. Fig. 13 is another schematic enlarged sectional view of the surrounding area according to the second embodiment. DETAILED DESCRIPTION

[0004] According to one embodiment, a display device comprises a substrate having a display region in which an image is displayed and a surrounding region around the display region; a plurality of display elements arranged in the display region, each including a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode that illuminates in response to the application of a voltage; a first partition wall arranged in the display region and disposed between adjacent display elements; and a second partition wall arranged in the surrounding region and connected to the first partition wall. The first partition wall and the second partition wall include a lower portion having electrical conductivity and an upper portion having an end portion protruding from a side surface of the lower portion.In addition, the second partition wall has several openings of elongated shape.

[0005] According to the embodiment, a display device capable of improving yield and increasing reliability can be provided.

[0006] Some embodiments are described below with reference to the figures.

[0007] The disclosure is merely exemplary, and any modifications made as needed by a person skilled in the art while maintaining the essence of the invention, which modifications would readily occur to such a person, are of course also included within the scope of the invention. The figures serve to clarify the description, and their individual components schematically illustrate width, thickness, shape, and the like in comparison to an actual embodiment. They are therefore merely exemplary and are not intended to limit the interpretation of the present invention. In the present description and the figures, elements already mentioned in another figure that fulfill an identical or similar function are provided with the same reference numerals, and a detailed description of these elements can therefore be omitted.

[0008] In the figures, an X-axis, Y-axis, and Z-axis are indicated where necessary for ease of understanding. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is a normal direction with respect to a plane containing the X-direction and the Y-direction. Viewing individual elements parallel to the Z-direction means viewing from a top view.

[0009] A display device according to the various embodiments is an organic electroluminescence display device including organic light-emitting diodes (OLEDs) as display elements, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phones, portable terminals, and the like. FIRST EMBODIMENT

[0010] Fig. 1 is a view of an exemplary embodiment of a display device DSP according to a first embodiment. The display device DSP comprises an insulating substrate 10. The substrate 10 has a display area DA for displaying images, and a surrounding area SA around the display area DA. The substrate 10 can be glass or a flexible plastic film.

[0011] In the present embodiment, the support 10 and the display area DA are rectangular in plan view. However, the shape of the support 10 and the display area DA in plan view is not limited to a rectangular shape and may also be other shapes such as a square, a circle, or an oval.

[0012] The display area DA includes a plurality of pixels PX arranged in a matrix in the X direction and the Y direction. The pixels PX include a plurality of subpixels SP that display different colors. In the present embodiment, the pixels PX include blue subpixels SP1, green subpixels SP2, and red subpixels SP3. However, the pixels PX may also include subpixels SP of a different color, such as white or the like, along with the subpixels SP1, SP2, SP3, or instead of any of the subpixels SP1, SP2, SP3.

[0013] The display device DSP comprises a connection section T arranged in the surrounding area SA. A flexible printed circuit board, for example, is connected to the connection section T, which applies a voltage or a signal for controlling the display device DSP.

[0014] The subpixels SP comprise a pixel circuit 1 and a display element DE controlled by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a control transistor 3, and a capacitor 4. The pixel switch 2 and the control transistor 3 are switching elements formed, for example, by thin-film transistors.

[0015] In the display area DA, several scanning lines G, which supply scanning signals to the pixel circuit 1 of the individual subpixels SP, several signal lines S, which supply image signals to the pixel circuit 1 of the individual subpixels SP, and several power supply lines PL are arranged. In the example of Fig. 1, the scanning lines G and the power supply lines PL extend in the X direction and the signal lines S extend in the Y direction, but this is not limited to this example.

[0016] A gate electrode of the pixel switch 2 is connected to the scanning line G. One of a source electrode and a drain electrode of the pixel switch 2 is connected to the signal line S, and the other is connected to a gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and the drain electrode is connected to the power supply line PL and the capacitor 4, and the other is connected to the display element DE.

[0017] The design of pixel circuit 1 is not limited to the example shown. For example, pixel circuit 1 may include a larger number of thin-film transistors and capacitors.

[0018] Fig. Figure 2 is a view schematically showing an example of a layout of the subpixels SP1, SP2, SP3. In the example from Fig. 2, subpixels SP2 and SP3 are each lined up next to subpixel SP1 in the X direction. Subpixel SP2 and subpixel SP3 are also lined up in the Y direction.

[0019] With such a layout of the subpixels SP1, SP2, SP3, a row in which the subpixels SP2, SP3 are arranged alternately in the Y direction and a row in which several subpixels SP1 are repeatedly arranged in the Y direction are formed in the display area DA. These rows are arranged alternately next to each other in the X direction. The layout of the subpixels SP1, SP2, SP3 is not limited to the example in Fig. 2 limited.

[0020] A rib layer 5 is arranged in the display area DA. The rib layer 5 has respective pixel openings AP51, AP52, AP53 at the subpixels SP1, SP2, SP3. In the example from Fig. 2, pixel aperture AP51 is larger than pixel aperture AP52, and pixel aperture AP52 is larger than pixel aperture AP53. That is, among subpixels SP1, SP2, and SP3, the aperture of subpixel SP1 is the largest, and the aperture of subpixel SP3 is the smallest.

[0021] Subpixel SP1 comprises a bottom electrode LE1, a top electrode UE1, and an organic layer OR1, each overlying the pixel opening AP51. Subpixel SP2 comprises a bottom electrode LE2, a top electrode UE2, and an organic layer OR2, each overlying the pixel opening AP52. Subpixel SP3 comprises a bottom electrode LE3, a top electrode UE3, and an organic layer OR3, each overlying the pixel opening AP53.

[0022] The parts of the lower electrode LE1, the upper electrode UE1, and the organic layer OR1 that overlie the pixel opening AP51 form the display element DE1 of the subpixel SP1. The parts of the lower electrode LE2, the upper electrode UE2, and the organic layer OR2 that overlie the pixel opening AP52 form the display element DE2 of the subpixel SP2. The parts of the lower electrode LE3, the upper electrode UE3, and the organic layer OR3 that overlie the pixel opening AP53 form the display element DE3 of the subpixel SP3. The display elements DE1, DE2, DE3 may further include a cover layer described below. The rib layer 5 surrounds the display elements DE1, DE2, DE3, respectively.

[0023] An electrically conductive partition 6A (first partition) is arranged on the fin layer 5. The partition 6A completely overlies the fin layer 5 and has a surface shape similar to that of the fin layer 5. The partition 6A thus has respective pixel openings AP61, AP62, AP63 at the subpixels SP1, SP2, SP3. Viewed differently, the fin layer 5 and the partition 6A, when viewed from above, are grid shapes that respectively surround the subpixels SP1, SP2, SP3. The partition 6A serves as a line for a common voltage to the upper electrodes UE1, UE2, UE3.

[0024] Fig. Figure 3 is a schematic sectional view of the display device DSP along the line III-III of Fig. 2. A circuit layer 11 is arranged on the carrier 10. The circuit layer 11 contains various circuits and conductor tracks such as the pixel circuit 1 of Fig. 1, the scanning lines G, the signal lines S, and the power supply lines PL. The circuit layer 11 is covered with an organic insulation layer 12. The organic insulation layer 12 serves as a flattening layer that smooths out unevenness caused by the circuit layer 11.

[0025] The lower electrodes LE1, LE2, LE3 are arranged on the organic insulation layer 12. The fin layer 5 is arranged on the organic insulation layer 12 and the lower electrodes LE1, LE2, LE3. End portions of the lower electrodes LE1, LE2, LE3 are covered by the fin layer 5. Although in the section of Fig. 3, the lower electrodes LE1, LE2, LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through contact holes provided in the insulation layer 12.

[0026] The partition wall 6A includes an electrically conductive lower portion 61 disposed on the fin layer 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a greater width than the lower portion 61. As a result, the two end portions of the upper portion 62 protrude from the side surfaces of the lower portion 61. Thus, the shape of the partition wall 6A can be referred to as an overhang shape.

[0027] In the example of Fig. 3, the lower section 61 has a bottom layer 63 arranged on the rib layer 5 and an axial layer 64 arranged on the bottom layer 63. The bottom layer 63 is, for example, thinner than the axial layer 64. As a result, in the example of Fig. 3 the two end sections of the bottom layer 63 on the side surfaces of the axial layer 64.

[0028] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP51. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP52. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP53. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, UE3 are in contact with a side surface of the lower portion 61 of the partition wall 6A.

[0029] The display element DE1 includes a cover layer CP1 arranged on the upper electrode UE1. The display element DE2 includes a cover layer CP2 arranged on the upper electrode UE2. The display element DE3 includes a cover layer CP3 arranged on the upper electrode UE3. The cover layers CP1, CP2, and CP3 each serve as an optical regulation layer that increases the light extraction efficiency from the individual organic layers OR1, OR2, and OR3.

[0030] In the following description, a multilayer body including the organic layer OR1, the upper electrode UE1 and the cap layer CP1 is referred to as a laminated layer FL1, a multilayer body including the organic layer OR2, the upper electrode UE2 and the cap layer CP2 is referred to as a laminated layer FL2, and a multilayer body including the organic layer OR3, the upper electrode UE3 and the cap layer CP3 is referred to as a laminated layer FL3.

[0031] A portion of the laminated layer FL1 is located on the upper portion 62. This portion is remote from the part of the laminated layer FL1 located around the partition wall 6A (the part forming the display element DE1). Likewise, a portion of the laminated layer FL2 is located on the upper portion 62, this portion being remote from the part of the laminated layer FL2 located around the partition wall 6A (the part forming the display element DE2). Also, a portion of the laminated layer FL3 is located on the upper portion 62, this portion being remote from the part of the laminated layer FL3 located around the partition wall 6A (the part forming the display element DE3).

[0032] Sealing layers SE11, SE12, and SE13 are arranged at subpixels SP1, SP2, and SP3, respectively. Sealing layer SE11 continuously covers the partition wall 6A around cover layer CP1 and subpixel SP1. Sealing layer SE12 continuously covers the partition wall 6A around cover layer CP2 and subpixel SP2. Sealing layer SE13 continuously covers the partition wall 6A around cover layer CP3 and subpixel SP3.

[0033] In the example of Fig. 3, the laminated layer FL1 and the sealing layer SE11 located on the partition wall 6A between the subpixels SP1, SP2 are separated from the laminated layer FL2 and the sealing layer SE12 on the partition wall 6A. The laminated layer FL1 and the sealing layer SE11 located on the partition wall 6A between the subpixels SP1, SP3 are separated from the laminated layer FL3 and the sealing layer SE13 on the partition wall 6A.

[0034] The sealing layers SE11, SE12, SE13 (first sealing layer) are covered by a plastic layer RS1 (first plastic layer). The plastic layer RS1 is covered by the sealing layer SE2 (second sealing layer). The sealing layer SE2 is covered by a plastic layer RS2 (second plastic layer). The plastic layers RS1, RS2 and the sealing layer SE2 are provided continuously at least throughout the entire display area DA, and a portion of them also extends to the surrounding area SA.

[0035] A cover element, such as a polarizing plate, a protective film, or a cover glass, can also be arranged over the plastic layer RS2. This cover element can be bonded to the plastic layer RS2, for example, via an adhesive layer such as OCA (optical clear adhesive).

[0036] The organic insulation layer 12 is formed from an organic insulation material such as polyimide or the like. The fin layer 5 and the sealing layers SE11, SE12, SE13, SE2 are formed, for example, from an inorganic material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or the like. The fin layer 5 is formed from silicon oxynitride in one example, and the sealing layers SE11, SE12, SE13, SE2 are formed from silicon nitride. The plastic layers RS1, RS2 are formed, for example, from a plastic material (organic plastic material) such as epoxy resin, acrylic resin, or the like.

[0037] The lower electrodes LE1, LE2, LE3 comprise, for example, a reflective layer made of silver and a pair of conductive oxidation layers covering the upper and lower surfaces of the reflective layer, respectively. The conductive oxidation layers may each be formed of a transparent electrically conductive oxide such as ITO (indium tin oxide), IZO (indium zinc oxide), IGZO (indium gallium zinc oxide), or the like.

[0038] The upper electrodes UE1, UE2, UE3 are made of a metal material such as a magnesium-silver alloy (MgAg). The lower electrodes LE1, LE2, LE3 correspond to an anode, and the upper electrodes UE1, UE2, UE3 correspond to a cathode.

[0039] The organic layers OR1, OR2, OR3 are formed by a plurality of thin films including luminescent layers. In one example, the organic layers OR1, OR2, OR3 have a structure in which a hole injection layer, a hole conduction layer, an electron blocking layer, a luminescent layer, a hole blocking layer, an electron conduction layer, and an electron injection layer are stacked sequentially in the Z direction. However, the organic layers OR1, OR2, OR3 may also have a different structure, such as a so-called tandem structure including a plurality of luminescent layers.

[0040] The cover layers CP1, CP2, and CP3, for example, have a laminated structure in which multiple transparent layers are stacked one on top of the other. These transparent layers can include layers made of an inorganic material and layers made of an organic material. The transparent layers have different refractive indices. For example, with regard to the refractive indices of the transparent layers, the refractive indices of the upper electrodes UE1, UE2, and UE3 and the refractive indices of the sealing layers SE11, SE12, and SE13 are different. At least one of the cover layers CP1, CP2, and CP3 can be omitted.

[0041] The bottom layer 63 and the axial layer 64 of the partition wall 6A are formed of a metal material. For example, molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), or a molybdenum-niobium alloy (MoNb) can be used as the metal material of the bottom layer 63. For example, aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), or an aluminum-silicon alloy (AlSi) can be used as the metal material for the axial layer 64. The axial layer 64 can also be formed of an insulating material.

[0042] The upper portion 62 of the partition wall 6A has, for example, a laminated structure of a lower layer formed of a metal material and an upper layer formed of an electrically conductive oxide. Titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy, for example, can be used as the metal material for forming the lower layer. ITO or IZO, for example, can be used as the electrically conductive oxide for forming the upper layer. The upper portion 62 may also have a single-layer structure made of a metal material. The upper portion 62 may include a layer of an insulating material.

[0043] A common voltage is applied to the partition wall 6A. The common voltage is applied to the upper electrodes UE1, UE2, UE3, respectively, which are in contact with the side surface of the lower portion 61. A pixel voltage corresponding to the image signal of the signal lines S is applied to the lower electrodes LE1, LE2, LE3 via the pixel circuit 1 of the individual subpixels SP1, SP2, SP3.

[0044] The organic layers OR1, OR2, and OR3 luminescently emit light in response to the application of voltage. Specifically, the luminescent layer of the organic layer OR1 emits light in the blue wavelength range when a potential difference exists between the lower electrode LE1 and the upper electrode UE1. When a potential difference exists between the lower electrode LE2 and the upper electrode UE2, the luminescent layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference exists between the lower electrode LE3 and the upper electrode UE3, the luminescent layer of the organic layer OR3 emits light in the red wavelength range.

[0045] As another example, the luminescent layers of the organic layers OR1, OR2, OR3 can emit light of the same color (e.g., white). In this case, the display device DSP can include a color filter that converts the light emitted by the luminescent layers into light of the color corresponding to the subpixels SP1, SP2, SP3. The display device DSP can also include a layer of electron dots that are excited by the light emitted by the luminescent layers and generate light of the color corresponding to the subpixels SP1, SP2, SP3.

[0046] Fig. Figure 4 is a schematic plan view of the display device DSP for explaining the structure of the surrounding area SA. The display device DSP further includes a partition wall 6B (second partition wall) arranged in the surrounding area SA. The partition wall 6B is formed in the same process as the partition wall shown in Figure 4. Fig. 2 and Fig. 3 and has the same structure as the partition wall 6A. In Fig. 4, the area corresponding to the partition wall 6B is provided with a dot pattern. The partition wall 6B surrounds the display area DA.

[0047] The partition wall 6B has end portions E1a, E1b, E1c, E1d (first to fourth end portions). The end portion E1a is located between the display area DA and the terminal portion T and extends parallel to the X direction. The end portion E1b is located opposite the end portion E1a with the display area DA in between and extends parallel to the X direction. The end portion E1c is connected to the left end of the end portions E1a, E1b in the figure and extends parallel to the Y direction. The end portion E1d is connected to the right end of the end portions E1a, E1b in the figure and extends parallel to the Y direction.

[0048] The display device DSP comprises a dam structure DS arranged in the surrounding area SA. In the example of Fig. 4 the dam structure DS includes rectangular dam sections DM1, DM2.

[0049] Dam section DM1 surrounds dividing wall 6B. Dam section DM2 surrounds dam section DM1.

[0050] A section of the dam sections DM1, DM2 runs between the connecting section T and the partition wall 6B.

[0051] The shape of the dam sections DM1, DM2 is not based on the example of Fig. 4. The number of dam sections of the dam structure DS can be one or three or more.

[0052] Fig. Figure 5 is a schematic sectional view of a part of the surrounding area SA on the line VV of Fig. 4. The section structure in this view can be applied to any position in the surrounding area SA.

[0053] The Fig. The circuit layer 11 shown in Figure 3 comprises the inorganic insulating layers 31, 32, 33 formed from an inorganic insulating material, the organic insulating layer 34 formed from an organic insulating material, and the metal layers 41, 42, 43. The inorganic insulating layer 31 covers the upper surface of the carrier 10. The metal layer 41 is arranged on the inorganic insulating layer 31. The inorganic insulating layer 32 covers the metal layer 41. The metal layer 42 is arranged on the inorganic insulating layer 32. The inorganic insulating layer 33 covers the metal layer 42. The organic insulating layer 34 covers the inorganic insulating layer 33. The metal layer 43 is arranged on the organic insulating layer 34 and covered by the organic insulating layer 12.

[0054] The dam sections DM1, DM2 both project above the support 10. In the example from Fig. 5, the dam section DM1 is formed by the organic insulation layers 12, 34. Likewise, the dam section DM2 is formed by the organic insulation layers 12, 34. In the present embodiment, the dam sections DM1, DM2 are formed from the same material as the organic insulation layers 12, 34 and in the same process as the organic insulation layers 12, 34.

[0055] The circuit layer 11 comprises a supply line PW to which the common voltage is applied. The supply line PW is connected to the Fig. 4 shown connection section T. In the example from Fig. 5, the feed line PW has a line W1 formed by the metal layer 42 and a second line W2 formed by the metal layer 43. The first line W1 and the second line W2 are in contact at a contact portion CN0 located between an end portion E0 of the organic insulation layer 12 and the dam portion DM1.

[0056] Also arranged in the surrounding area SA are an electrically conductive relay layer RL, which connects the partition wall 6B and the supply line PW, and the fin layer 5. The relay layer RL is formed, for example, from the same material and using the same process as the lower electrodes LE1, LE2, LE3.

[0057] The relay layer RL is located closer than the dam layer DM1 to the display area DA (on the left in the view) and covers the organic insulation layer 12. The rib layer 5 continuously covers the relay layer RL and the dam sections DM1 and DM2. One end section of the rib layer 5 is located further outward than the dam section DM2.

[0058] The partition wall 6B is arranged on the fin layer 5. The fin layer 5 is open, as viewed from above, at the contact portion CN1 overlying the organic insulation layer 12. The partition wall 6B is in contact with the relay layer RL at the contact portion CN1.

[0059] The relay layer RL is in contact with the second line W2 of the supply line PW at contact section CN2. The contact section CN2 is located between the end section E0 of the organic insulation layer 12 and the dam section DM1.

[0060] The partition wall 6B is covered by the laminated layer FL. The laminated layer FL is covered by the waterproofing layer SE1. The laminated layer FL is one of the Fig. 3 laminated layers FL1, FL2, FL3. The sealing layer SE1 is one of the Fig. 3 waterproofing layers SE11, SE12, SE13 shown.

[0061] In the example from Fig. 5, the laminated layer FL and the end section E2 of the waterproofing layer SE1 lie between the end section E1a of the partition wall 6B and the dam section DM1. The laminated layer FL is severed by the end section E1a. The waterproofing layer SE1 continuously covers the severed parts of the laminated layer FL1. By severing the laminated layer FL in this way, a path through which moisture can penetrate to the laminated layer FL can be interrupted.

[0062] Above the sealing layer SE1, the plastic layer RS1, the sealing layer SE2 and the plastic layer RS2 are made of Fig. 3. The plastic layer RS1 covers the sealing layer SE1 and the rib layer 5. The laminated layer FL and the end section E2 of the sealing layer SE1 are covered by the plastic layer RS1. The dam section DM1 serves as a containment for the not yet cured plastic layer RS1 during the manufacture of the display device DSP.

[0063] In the example from Fig. 5, the end section Er1 of the plastic layer RS1 is located above the dam section DM1. However, the position of the end section Er1 is not limited to this example.

[0064] The sealing layer SE2 covers the end section Er1 of the plastic layer RS1. The sealing layer SE2 is in contact with the ribbed layer 5 in an area further out than the end section Er1 (in the view on the right). In the example from Fig. 5 is an end section Es of the waterproofing layer SE2 located above the dam section DM2. The plastic layer RS1 is surrounded by the waterproofing layer SE1, the ribbed layer 5, and the waterproofing layer SE2. This prevents moisture from penetrating the plastic layer RS1.

[0065] The plastic layer RS2 covers the sealing layer SE2. The dam portion DM2 serves as a containment for the not yet cured plastic layer RS2 during the manufacture of the display device DSP. In the present embodiment, the end portion Er2 of the plastic layer RS2 lies between the end portion Er1 of the plastic layer RS1 and the end portion Es of the sealing layer SE2. More specifically, the end portion Er2 lies above the dam portion DM2. The position of the end portion Er2 is not limited to the example of Fig. 5 limited.

[0066] Fig. 6 is a schematic enlarged sectional view of a portion of the partition wall 6B. The partition wall 6B, like the partition wall 6A, includes the lower portion 61 and the upper portion 62. The lower portion 61 of the partition wall 6B also includes the bottom layer 63 and the axial layer 64.

[0067] In the present embodiment, the partition wall 6B comprises a plurality of openings APx. The upper portion 62 projects from the side surface of the axial layer 64 at an edge portion Ex of the openings APx. The edge portion Ex is thus, just like the Fig. 3 shown partition wall 6A overhangs. The end sections E1a, E1b, E1c, E1d of the Fig. The partition wall 6B shown in Figure 4 is overhang-like.

[0068] The laminated layer FL is severed by the edge section Ex. The sealing layer SE1 continuously covers the parts of the severed laminated layer FL.

[0069] Considering the Fig. 4 areas VII, VIII surrounded by a dashed frame are now described with regard to the shape of the surface and the arrangement of the openings APx.

[0070] Fig. Figure 7 is an enlarged plan view of area VII. Fig. 8 is an enlarged plan view of the area VIII. In these views, the partition walls 6A, 6B, the dam sections DM1, DM2, the relay layer RL and the contact section CN1 are shown, while the remaining elements have been omitted.

[0071] One in Fig. 7 and Fig. The region provided with a dot pattern in 8 corresponds to the partition walls 6A, 6B. The partition walls 6A, 6B are formed integrally. The partition wall 6A has the above-discussed plurality of pixel openings AP61, AP62, AP63. The partition wall 6B has the above-discussed plurality of openings APx.

[0072] The openings APx have an elongated shape. Specifically, the openings APx have a rectangular shape elongated in the Y direction with rounded corners. In one example, the width of the openings APx in the Y direction is 2 to 3 times the width of the openings APx in the X direction. The shape of the openings APx is not limited to this example. For example, the openings APx can have an elongated shape in the X direction.

[0073] In the example of Fig. 7 and Fig. 8, two openings APx adjacent to each other in the X direction are arranged close to each other. Such pairs of openings APx are adjacent to each other in the X direction and the Y direction. A distance between pairs of openings APx in the X direction and the Y direction is, for example, equal to the distance between the pixels PX in the X direction and the Y direction. With this configuration, the density of the openings of the partition walls 6A, 6B is uniform in the display area DA and the surrounding area SA. In this way, when manufacturing the display device DSP, when the layer forming the basis for the partition walls 6A, 6B is etched, fluctuations in the progress of erosion in the XY plane can be suppressed.

[0074] The partition wall 6B also has a plurality of slots SL1 (first slot) extending to one of the end portions E1a, E1b, E1c, E1d. These slots SL1 have, for example, a width that is less than the width of the short direction of the openings APx (in the example of Fig. 7 and Fig. 8 of the X-direction).

[0075] The slots SL1 are connected to at least one opening APx. In the following description, the openings APx connected to a slot SL1 are referred to as openings APx1 (first opening). Independent openings APx that are not connected to any slot SL1 are referred to as openings APx2 (second opening).

[0076] The slots SL1, which are located in Fig. 7 to the end section E1a, and the slots SL1, which are located in Fig. 8 to the end section E1b, for example, have a main section ST extending in the Y direction and two branch sections BR extending in the X direction, crossing the main section ST. The two end sections of the branch sections BR are each connected to the long side of the openings APx1. These slots SL1 are therefore all connected to four openings APx1.

[0077] The slots SL1, which are located in Fig. 7 to the end section E1c, and the slots SL1, which are located in Fig. 8 opening to the end section E1d extend in the X direction, and most of them are connected to the long side of four openings APx1. However, of the slots SL1 opening to the end section E1c, those slots SL located at the corner portion of the end section E1a and the end section E1c and at the end portion of the end section E1b and the end section E1d are connected to the long side of only one opening APx1.

[0078] The relationship between the slots SL1 and the openings APx1 is not limited to the one shown here as an example. For example, there may be slots SL1 connected to two openings APx1, slots SL1 connected to three openings APx1, or slots SL1 connected to five or more openings APx1.

[0079] As in Fig. 7 and Fig. 8, a first region A1 and a second region A2 of the partition wall 6B are defined. The first region A1 is a part extending along the end portions E1a, E1b, E1c, E1d of the partition wall 6B and includes the plurality of slits SL1 and the plurality of openings APx1 connected to these slits SL1. The second region A2 is a part located between the first region A1 and the display region DA and includes the plurality of openings APx2 that are not connected to the slits SL1. The second region A2 surrounds the display region DA.

[0080] For example, the boundary between the first area A1 and the second area A2 lies at a distance D from the dam section DM1. The distance D can be defined, for example, as a range of 100–300 µm. In one example, the distance D is 200 µm.

[0081] In plan view, the second area A2 overlaps the Fig. 5. The relay layer RL surrounds, for example, the display area DA. The contact section CN1 between the partition wall 6B and the relay layer RL is distributed at locations in the second area A2. In the example of Fig. 7 and Fig. 8, the contact portion CN1 is provided between the end portion E1a and the display area DA, between the end portion E1b and the display area DA, between the end portion E1c and the display area DA, and between the end portion E1d and the display area DA, respectively, at a position where it does not overlap the second openings APx2.

[0082] Next, an example of a method for manufacturing the display device DSP will be described. Fig. 9A to 9I are schematic sectional views illustrating manufacturing steps of the display device DSP. In Fig. 9A to 9I mainly show the display area DA, while the elements below the organic insulation layer 12 have been omitted.

[0083] When forming the display device DSP, the circuit layer 11 and the organic insulation layer 12 are first formed on the carrier 10. As shown in Fig. 9A, the lower electrodes LE1, LE2, LE3 are then formed on the organic insulation layer 12.

[0084] As in Fig. Next, as shown in Figure 9B, the fin layer 5 is formed, covering the organic insulation layer 12 and the lower electrodes LE1, LE2, LE3. CVD (chemical vapor deposition), for example, can be used to form the fin layer 5.

[0085] As in Fig. 9C, the partition wall 6A is also formed on the rib layer 5. Specifically, a layer is first formed that forms the basis for the bottom layer 63, the axial layer 64, and the upper portion 62, and this layer is patterned by etching. Fig. The partition wall 6B shown in Figures 4 to 8 is formed in the same step as the partition wall 6A.

[0086] After forming the partition walls 6A, 6B, the pixel openings AP51, AP52, AP53 are formed in the rib layer 5 by dry etching, as shown in Fig. 9D. In addition to this step, several dry etching processes may also be performed on the fin layer 5. For example, these dry etching processes may include dry etching for forming the contact portion CN1 in the surrounding area SA in the fin layer 5.

[0087] After forming the rib layer 5 and the partition walls 6A, 6B, the steps for forming the display elements DE1, DE2, DE3 are performed. In the present embodiment, the display element DE1 is formed first, then the display element DE2, and finally the display element DE3. However, the order of forming the display elements DE1, DE2, DE3 is not limited to this example.

[0088] When forming the display element DE1, as shown in Fig. 9E, first the laminated layer FL1 and the sealing layer SE11 are formed. The laminated layer FL1 includes, as shown in Fig. 3, the organic layer OR1 in contact with the lower electrode LE1 through the first pixel opening AP51, the upper electrode UE1 covering the organic layer OR1, and the cap layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed by vapor deposition. The sealing layer SE11 is formed by CVD.

[0089] The laminated layer FL1 and the sealing layer SE11 are formed not only in the display area DA, but also in the surrounding area SA. The laminated layer FL1 is severed into several parts by the overhang-like partition walls 6A, 6B. The sealing layer SE11 continuously covers the severed parts of the laminated layer FL1 and the partition walls 6A, 6B.

[0090] Next, the laminated layer FL1 and the sealing layer SE11 are structured. As shown in Fig. As shown in Figure 9F, during patterning, resist R is disposed on the sealing layer SE11. The resist R covers the subpixel SP1 and a portion of the partition wall 6A around it.

[0091] Then, as in Fig. 9G, using the resist R as a mask, the portion of the laminated layer FL1 and the sealing layer SE11 exposed from the resist 2 is removed by etching. In other words, the portions of the laminated layer FL1 and the sealing layer SE11 overlying the lower electrode LE1 remain, while the remaining portions are removed. In this way, the display element DE1 is formed at the subpixel SP1. The etching may include wet etching or dry etching, which are performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After etching, the resist R is removed.

[0092] The display element DE2 is formed in the same process as the display element DE1. For the display element DE2, the laminated layer FL2 and the sealing layer SE12 are formed not only in the display area DA, but also in the surrounding area SA. The laminated layer FL2 contains, as shown in Fig. 3, the organic layer OR2 in contact with the lower electrode LE2 through the first pixel opening AP52, the upper electrode UE2 covering the organic layer OR2 and the cap layer CP2 covering the upper electrode UE2.

[0093] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 are formed by vapor deposition. The sealing layer SE12 is formed by CVD. The laminated layer FL2 is severed into several parts by the overhang-like partition walls 6A, 6B. The sealing layer SE12 continuously covers the severed parts of the laminated layer FL2 and the partition walls 6A, 6B. By structuring the laminated layer FL2 and the sealing layer SE12 in this way, as shown in Fig. 9H, the display element DE2 is formed at the subpixel SP2.

[0094] The display element DE3 is formed in the same process as the display elements DE1 and DE2. For the display element DE3, the laminated layer FL3 and the sealing layer SE13 are formed not only in the display area DA, but also in the surrounding area SA. The laminated layer FL3 contains, as shown in Fig. 3, the organic layer OR3 in contact with the lower electrode LE3 through the first pixel opening AP53, the upper electrode UE3 covering the organic layer OR3 and the cap layer CP3 covering the upper electrode UE3.

[0095] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 are formed by vapor deposition. The sealing layer SE13 is formed by CVD. The laminated layer FL3 is severed into several parts by the overhang-like partition walls 6A, 6B. The sealing layer SE13 continuously covers the severed parts of the laminated layer FL3 and the partition walls 6A, 6B. By structuring the laminated layer FL3 and the sealing layer SE13 in this way, as shown in Fig. 9I, the display element DE3 is formed at the subpixel SP3.

[0096] After forming the display elements DE1, DE2, DE3, the Fig. 3 shown plastic layer RS1, the sealing layer SE2 and the plastic layer RS2 are formed.

[0097] At the Fig. 5 and Fig. For example, in the laminated layer FL shown in Figure 6, the laminated layer FL1 is the first formed laminated layer among the laminated layers FL1, FL2, and FL3. Similarly, the sealing layer SE1 is the first formed sealing layer SE11 among the sealing layers SE11, SE12, and SE13. In this way, by leaving the first formed sealing layer SE11 in the surrounding area SA, the surrounding area SA can be protected from etching when forming the display elements DE2, DE3.

[0098] As a further example, the laminated layer FL may be the most recently formed laminated layer FL3 among the laminated layers FL1, FL2, and FL3. Likewise, the waterproofing layer SE1 may be the most recently formed waterproofing layer SE13 among the waterproofing layers SE11, SE12, and SE13.

[0099] The laminated layers FL1, FL2, and FL3 formed by vapor deposition sometimes exhibit poor adhesion to the substrate. Therefore, there is a possibility that the laminated layers FL1, FL2, and FL3 and the sealing layers SE11, SE12, and SE13 covering them may detach from the substrate during the manufacture of the DSP display device.

[0100] Peeling is particularly likely to occur when the laminated layers FL1, FL2, and FL3 are formed continuously over a large area. In the display area DA, the laminated layers FL1, FL2, and FL3 are finely separated by the partition wall 6A. This prevents peeling.

[0101] In the present embodiment, the partition wall 6B is arranged around the plurality of openings APx in the surrounding area SA. Therefore, even in the surrounding area SA, the laminated layers FL1, FL2, FL3 are finely cut, preventing peeling.

[0102] With the design of Fig. 7 and Fig. 8, for example, the effects described below can also be achieved.

[0103] Fig. 10 is a schematic plan view of the surrounding area SA according to a comparative example of the present embodiment. Fig. 11 is a schematic sectional view of the surrounding area SA according to the comparative example. As shown in Fig. 10, in the comparative example, a plurality of openings APc are provided in the partition wall 6B, which are smaller than those in Fig. 7 and Fig. 8 are the openings APx. Specifically, the openings APc have a square shape with rounded corners. The width of the openings APc in the X direction is therefore equal to the width of the openings APc in the Y direction.

[0104] If these small openings APc are provided in the partition wall 6B, there is a possibility that, during the formation of the plastic layer RS1, the plastic layer RS1 may be repelled before hardening due to the unevenness in the sealing layer SE1 caused by the openings APc. Fig. 11 shows how the plastic layer RS1 was ejected in the area of ​​the opening APc located furthest to the left in the view and is cured in this state.

[0105] The plastic layer RS1 serves to level the substrate for the sealing layer SE2. When the plastic layer RS1 hardens in the repelled state, a deformation defect occurs on the overlying sealing layer SE2, which can create a pathway through which moisture can penetrate into the interior of the display device DSP.

[0106] In the present embodiment, however, the openings APx have an elongated shape in the Y direction, as shown in Fig. 7 and Fig. 8. Assuming, for example, that the width of the openings APx and APc in the X direction is equal, the width of the openings APx in the Y direction is larger. Therefore, repulsion of the plastic layer RS1 due to the opening APx does not necessarily occur.

[0107] The plastic layer RS1 is applied, for example, by an inkjet process. In this case, if the relative movement direction of a head from which the plastic layer RS1 is dispensed to the substrate (application direction) and the length direction of the openings APx are consistent, the repulsion of the plastic layer RS1 due to the openings APx can be further prevented. If the openings APx are arranged as shown in Fig. 7 and Fig. 8 have an elongated shape in the Y direction, the application direction is thus also preferably parallel to the Y direction. As a further example, the openings APx may have an elongated shape in the X direction, and the application direction may be parallel to the X direction.

[0108] Near the end sections E1a, E1b, E1c, E1d, the plastic layer RS1 is thinner, which is why repulsion can occur more easily. In contrast, in the example of Fig. 7 and Fig. 8, a plurality of slots SL1 are provided in the first region A1, which runs along the end sections E1a, E1b, E1c, E1d of the partition wall 6B, and the openings APx1 are connected to these slots SL1. With this configuration, the depressions in the sealing layer SE1, which are formed due to the openings APx, can be easily filled with the not yet cured plastic layer RS1 through the slots SL1. Therefore, the rejection can be effectively prevented.

[0109] For example, the plastic layer RS1 can be used in the area where the Fig. 7 is less than 100 µm, the distance D can be thin. If the slits SL1 are formed close to the display area DA, the resistance of the second area A2, which serves to feed the relay layer RL, may increase. For this reason, the distance D is preferably set to the range of 100-300 µm, as discussed above. SECOND EMBODIMENT

[0110] A second embodiment is described below. Configurations of the display device DSP not further mentioned in the present embodiment are identical to those of the first embodiment.

[0111] Fig. 12 and Fig. 13 are schematic enlarged sectional views of the surrounding area SA according to the present embodiment. Fig. 12 and Fig. 13 each show the same area as Fig. 7 and Fig. 8.

[0112] In the present embodiment, the partition wall 6A formed in the display area DA is divided into several segments SG by a plurality of slits SL2 (second slit). The slits SL2 extend in the Y direction. In the example of Fig. 12 and Fig. 13, the individual segments SG are formed by a row of pixels PX that are adjacent to each other in the Y direction. There is no limitation to this, and the individual segments SG can also be formed by multiple rows of pixels PX.

[0113] As in the first embodiment, a plurality of slots SL1 are provided in the partition wall 6B. Slots SL1, which are formed as in Fig. 12 extend to the end section E1a, are referred to below as slots SL1a (third slot). Slots SL1, which are shown in Fig. 13 extend to the end section E1b, are hereinafter referred to as slots SL1b (fourth slot).

[0114] As in Fig. 12, the slots SL1a are each provided in the first region A1 and are spaced apart from the slots SL2. On the other hand, a part of the plurality of slots SL1b, as shown in Fig. 13, the first area A1 and the second area A2 and is connected to the slots SL2 of the display area DA.

[0115] The interconnected slots SL1b and SL2 form continuous slots provided in the electrically conductive layer including the partition walls 6A, 6B.

[0116] In the example of Fig. 12 and Fig. 13, the relay layer RL and the contact section CN1 are provided between the display area DA and the end section E1a. However, the relay layer RL and the contact section CN1 are not provided between the display area DA and the end sections E1b, E1c, E1d.

[0117] In an electronic device in which a display device DSP is installed, a near-field communication (NFC) antenna is arranged on the back surface of the display device DSP. In this case, if a structure is used as in the first embodiment in which the lattice-shaped partition wall 6A is provided in the display area DA and is surrounded by the second partition wall portion 6B, the electrically conductive layer formed by the partition walls 6A, 6B becomes a factor that reduces the sensitivity of the wireless communication antenna.

[0118] Specifically, the magnetic field generated by the antenna creates an eddy current in the electrically conductive layer. This eddy current creates a magnetic field in a direction that cancels out the above magnetic field, which attenuates the signal strength. Therefore, if wireless communication is performed via the DSP display device, the communication sensitivity may decrease.

[0119] In contrast, in the present embodiment, the electrically conductive layer is separated from the end portion E1b by the slits SL1b, SL2. Therefore, the generation of eddy current is suppressed, so that the communication sensitivity for near-field communication can be increased. Otherwise, the DSP display device of the present embodiment can achieve the same effects as the first embodiment.

[0120] Display devices that can be obtained by a person skilled in the art with appropriate modification based on the display device described as an embodiment of the present invention also fall within the scope of the present invention as long as they contain the gist of the invention.

[0121] Within the scope of the present invention, a person skilled in the art can devise various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, in the above embodiments, a person skilled in the art can add, omit, or change the design of structural elements, or add, omit, or change the conditions of steps as needed, and all of these modifications are also within the scope of the present invention as long as they contain the gist of the invention.

[0122] Other effects resulting from the aspects discussed in the above embodiments, whether obvious from the description or achieved by consideration by the person skilled in the art, are of course also considered to be brought about by the present invention. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2024-020336

[0001]

Claims

[1] Display device (DSP) comprising: a carrier (10) having a display area (DA) in which an image is displayed and a surrounding area (SA) around the display area (DA), a plurality of display elements (DE1, DE2, DE3) arranged in the display area, each comprising a lower electrode (LE1, LE2, LE3), an upper electrode (UE1, UE2, UE3) located above the lower electrode (LE1, LE2, LE3), and an organic layer (OR1, OR2, OR3) located between the lower electrode (LE1, LE2, LE3) and the upper electrode (UE1, UE2, UE3) and illuminating in response to the application of a voltage, a first partition wall (6A) arranged in the display area (DA) and arranged between adjacent display elements (DE1, DE2, DE3), and a second partition wall (6B) arranged in the surrounding area (SA) and connected to the first partition wall (6A), wherein the first partition wall (6A) and the second partition wall (6B) include an electrically conductive lower portion (61) and an upper portion (62) having an end portion projecting from a side surface of the lower portion (61), and wherein the second partition wall (6B) has a plurality of openings (APx) of elongated shape. [2] A display device (DSP) according to claim 1, wherein the second partition wall (6B) surrounds the display area (DA). [3] The display device (DSP) according to claim 2, wherein the second partition wall (6B) has a plurality of first slits (SL1) extending to an end portion of the second partition wall (6B), the plurality of openings (APx) including a plurality of first openings (APx1) each connected to one of the plurality of first slits (SL1). [4] The display device (DSP) according to claim 3, wherein the plurality of first slits (SL1) are each connected to a long side of the plurality of first openings (APx1). [5] The display device (DSP) according to claim 3, wherein the plurality of openings (APx) include a plurality of independent second openings (APx2) that are not connected to the plurality of first slots (SL1). [6] Display device (DSP) according to claim 5, wherein the second partition wall (6B) has a first region (A1) extending along the end portion of the second partition wall (6B) and a second region (A2) located between the first region (A1) and the display region (DA), wherein the plurality of first openings (APx1) and the plurality of first slots (SL1) are provided in the first region (A1) and the plurality of second openings (APx2) are provided in the second region (A2). [7] Display device (DSP) according to claim 6, further comprising: a connection section (T) provided in the surrounding area (SA), a feed line (PW) connected to the connection section (T), and a relay layer (RL) connected to the feed line (PW) and the second partition wall (6B), wherein the relay layer (RL) is formed of the same material as the lower electrodes (LE1, LE2, LE3) and in the same layer as the lower electrodes (LE1, LE2, LE3). [8] A display device (DSP) according to claim 7, wherein the relay layer (RL) and the second partition wall (6B) are connected via a contact portion (CN1) located in the second area (A2). [9] Display device (DSP) according to claim 8, wherein the second region (A2) and the relay layer (RL) surround the display region (DA). [10] Display device (DSP) according to claim 3, wherein the first partition wall (6A) is divided into a plurality of segments (SG) by a second slit (SL2) located in the display area (DA). [11] Display device (DSP) according to claim 10, wherein the second partition wall (6B) has a first end portion (E1a) and a second end portion (E1b) opposite the first end portion (E1a) with the display area (DA) therebetween, wherein the plurality of first slots (SL1) include a third slot (SL1a) extending to the first end portion (E1a) and a fourth slot (SL1b) extending to the second end portion (E1b), wherein the second slot (SL2) is remote from the third slot (SL1a) and is connected to the fourth slot (SL1b). [12] Display device (DSP) according to one of claims 1 to 11, further comprising Dam sections (DM1, DM2) arranged in the surrounding area (SA) and surrounding the second partition wall (6B). [13] Display device (DSP) according to claim 12, further comprising a rib layer (5) formed of an inorganic material and located under the first partition wall (6A) and the second partition wall (6B), wherein the rib layer (5) covers the dam sections (DM1, DM2). [14] Display device (DSP) according to claim 13, further comprising first sealing layers (SE11, SE12, SE13) covering laminated layers (FL1, FL2, FL3) containing the organic layers (OR1, OR2, OR3) and the upper electrodes (UE1, UE2, UE3), wherein a part of the laminated layers (FL1, FL2, FL3) and the first sealing layers (SE11, SE12, SE13) is arranged in the surrounding area (SA). [15] A display device (DSP) according to claim 14, wherein the laminated layers (FL1, FL2, FL3) are severed by an edge portion of the plurality of openings (APx). [16] A display device (DSP) according to claim 14, wherein end portions of the laminated layers (FL1, FL2, FL3) and the first sealing layers (SE11, SE12, SE13) are located between an end portion of the second partition wall (6B) and the dam portions (DM1, DM2). [17] A display device (DSP) according to claim 16, wherein the laminated layers (FL1, FL2, FL3) are severed by the end portion of the second partition wall (6B). [18] A display device (DSP) according to claim 14, further comprising a first plastic layer (RS1) covering the first sealing layers (SE11, SE12, SE13). [19] Display device (DSP) according to claim 18, further comprising a second sealing layer (SE2) covering the first plastic layer (RS1), wherein the second sealing layer (SE2) is in contact with the rib layer (5) in a region further outward than an end portion of the first plastic layer (RS1). [20] A display device (DSP) according to claim 19, further comprising a second plastic layer (RS2) covering the second sealing layer (SE2).

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