ELECTRONIC DEVICE PACKAGING WITH DOUBLE-SIDED MOLDED SOLDER MASK-FREE PACKAGING SUBSTRATE FOR IMPROVED HEAT DISSIPATION AND THERMOMECHANICAL INTEGRITY

Abstract

An electronic device includes a multi-level package substrate having opposing first and second sides, a semiconductor die attached to the first side, a first molded package structure on the first side, and a second molded package structure on the second side and spaced from the first molded package structure. A method of manufacturing an electronic device includes attaching a semiconductor die to a first side of a solder mask-free multi-level package substrate, forming a first molded package structure on the first side of the multi-level package substrate, and forming a second molded package structure on an opposite second side of the multi-level package substrate and spaced from the first molded package structure.

Description

BACKGROUND

[0001] Thermal performance plays an important role in increasing device power density and / or reducing the size of electronic devices and systems. For example, improving heat dissipation or heat dissipation of flip-chip, chip-scale package (FCCSP), flip-chip ball grid array (FCBGA), and other electronic device packages is a design goal for modern electronic device applications. Ajinomoto build-up film (ABF) dielectric material, used as an insulator in FCBGA substrates, is subject to supply constraints due to the proliferation of 5G wireless communications, artificial intelligence (AI), high-performance computing (HPC), and other electronic device applications. Some applications require larger body sizes (e.g., over 50 mm body) and a higher substrate layer count for high I / O counts, with ABF being a currently popular substrate material, and smaller FCBGA form factors (e.g.,below 24 mm) are less attractive in terms of cost incentive for substrate suppliers. Transitioning select FCBGA packages that currently use ABF to substrates fabricated with prepreg dielectric materials can contribute to lower costs, such as by enlarging traditional smaller FCCSP bodies (strip-based with prepreg) to enable larger body sizes traditionally aligned with FCBGA (single-unit) form factors. However, transitioning the footprint from a smaller body FCBGA (ABF-based) to a non-traditional larger prepreg dielectric-based (e.g., FCCSP) footprint presents challenges related to package manufacturing yield and thermal performance that are not present in current FCBGA technology. In particular, larger body FCCSP designs experience greater warpage during manufacturing.In addition, conventional FCCSP solutions are not as heat dissipating as FCBGAs. SUMMARY

[0002] In one aspect, an electronic device includes a multi-level package substrate having opposing first and second sides, a semiconductor die attached to the first side, a first molded package structure on the first side, and a second molded package structure on the second side and spaced from the first molded package structure.

[0003] In another aspect, a system includes a circuit board and an electronic device attached to the circuit board, the electronic device including a multi-level package substrate having opposing first and second sides and a terminal soldered to a conductive feature of the circuit board, a semiconductor die attached to the first side, a first molded package structure on the first side, and a second molded package structure on the second side and spaced from the first molded package structure.

[0004] In another aspect, a method of manufacturing an electronic device includes attaching a semiconductor die to a first side of a solder mask-free multi-level package substrate, forming a first molded package structure having a first thermal conductivity greater than 3 W / mK on the first side of the multi-level package substrate, and forming a second molded package structure having a second thermal conductivity greater than 3 W / mK on an opposite second side of the multi-level package substrate and spaced from the first molded package structure. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a partial sectional side elevation taken along line 1-1 a of Fig. 1A of a system with an electronic device installed on a printed circuit board and having a multi-level package substrate with the top and bottom molded package structures. Fig. Figure 1A is a sectional bottom plan view of the electronic device taken along line 1-A-1A of Fig. 1. Fig. 1B is a partial cross-sectional side elevation of a system including another exemplary electronic device installed on a printed circuit board and having a multi-level package substrate with the top and bottom molded package structures and an exposed top die surface. Fig. 1C is a partial cross-sectional side elevation of a system including another exemplary electronic device installed on a printed circuit board and having a multi-level package substrate with the top and bottom molded package structures and a cap on a top die surface. Fig. 2 is a flowchart of a method for manufacturing an electronic device. Fig. 3-13 are partial side elevations of the electronic device of Fig. 1 and Fig. 1A, which are subject to manufacturing processing according to the procedure of Fig. 2 is subjected. DETAILED DESCRIPTION

[0005] Throughout the drawings, like reference numerals refer to like elements, and the various features are not necessarily drawn to scale. Additionally, the term "couple" or "couples" encompasses an indirect or direct electrical or mechanical connection, or combinations thereof. For example, when a first device couples or is coupled to a second device, this connection may be through a direct electrical connection or through an indirect electrical connection via one or more intermediate devices and connections. One or more operating characteristics of various circuits, systems, and / or components are described below in the context of functions that, in some cases, result from a configuration and / or connection of various structures when a circuit arrangement is powered and in operation.The example structures include layers or materials described as being over or on top of another layer or material, which may be a layer or material directly overlying and in contact with the other layer or material, and where other materials, such as impurities or artifacts or residual materials from manufacturing processing, may be present between the layer or material and the other layer or material. Unless otherwise noted, "about," "approximately," or "substantially" before a value means + / - 10% of the stated value. One or more structures, features, aspects, components, etc., may be referred to herein as first, second, third, etc., for example, first and second terminals, first, second, and third wells, etc., to facilitate description in conjunction with a particular drawing, but this should not be construed as a limitation on the claims. Various disclosed structures and methods of the present disclosure may be advantageously applied to the manufacture of an electronic device and / or the operation of an electronic device, such as an integrated circuit. While various improvements may be expected from such examples, no particular result is a requirement of the present disclosure unless expressly recited in a particular claim.

[0006] Fig. 1 and Fig. 1A shows an electronic device 100 having a solder mask-free multi-level package substrate 102 with a first (e.g., top) side 103 and an opposite second (e.g., bottom) side 104. The multi-level package substrate 102 does not include a solder mask on either of the opposite sides 103 and 104. The multi-level package substrate 102 is a three-level stacked structure including a top or first level L1 with dielectric layers 105 and 106 and patterned conductive metal features including first metal trace layer features M1 and first metal via layer features V1. A second level L2 includes dielectric layers 107 and 108, as well as second metal trace layer features M2 and second metal via layer features V2. A third level L3 in the illustrated example includes a third metal trace layer feature M3.In other examples, any suitable number of two or more levels of trace and / or via layer features may be used. Conductive metal terminals 109 of a semiconductor die 110 are attached by solder connections to top surfaces of corresponding first metal trace layer features M1 to provide mechanical and electrical connection of the semiconductor die 110 to the multi-level packaging substrate 102. The example electronic device 100 is a flip chip scale package (FCCSP) with solder connections between the terminals 109 and the multi-level packaging substrate 102. In other examples, other package shapes and types may be used.

[0007] How best in Fig. 1, the electronic device 100 includes a double-sided (e.g., top and bottom) molded configuration having first and second-sided molded package structures 111 and 112, respectively. The first molded package structure 111 extends at least partially on the top or first side 103 and the second molded package structure 112 extends at least partially on the bottom or second side 104 of the molded package substrate 102. The second molded package structure 112 is spaced apart (e.g., separate) from the first molded package structure 111.

[0008] The electronic device 100 is shown attached to a circuit board 116 in a system, such as a communications, AI, HPC, or other application. The double-sided molded multi-level package substrate configuration does not have a solder mask on either side 103 or 104, and this is referred to as a solder mask-free multi-level package substrate 102. The electronic device 100, in one example, includes solder balls 114 that contact a conductive metal feature M3 on the second side 104 of the multi-level package substrate 102 and provide electrical and mechanical connection of the electronic device 100 to circuitry of the host circuit board 116.

[0009] The illustrated implementation provides a ball grid array (BGA) form factor with advantages of high I / O density interconnects, as further described in Fig. 1A. In other examples, other types and shapes of connections and positioning of electrical terminals may be used, for example, dual or quad flat no-lead or leadless (e.g., DFN, QFN) devices with conductive features of a lower level of the multi-level package substrate 102 forming leads for soldering to a host circuit board, mating insertion into a socket (not shown), and / or other types of externally extending leads (e.g., gull-wing leads, "j"-type leads, etc.).

[0010] In certain examples, the molded package structures 111 and 112 may be or include any suitable molding compound or molding material, such as an epoxy-based molding compound (e.g., EMC) with a thermal conductivity greater than that of solder mask materials, to provide various advantages compared to conventional substrates with solder mask layers. For example, the dual-molded substrate 102 in the electronic device 100 provides an advanced packaging solution to address several disadvantages of standard FCCSP technology, including improved thermal performance during operation, significantly reduced substrate warpage during manufacturing, and reduced manufacturing costs.

[0011] Thermal performance can be addressed to some extent by over-molded encapsulation of a semiconductor die with a standard epoxy molding compound (EMC), but this approach is generally inadequate from a thermal conductivity perspective, and improving thermal performance by replacing higher thermal conductivity EMC materials alone is limited and expensive. Thicker semiconductor dies can be used for improved lateral heat propagation, but this involves a trade-off with increased resistance due to a longer path versus increased interface with thicker silicon and increased final device size, which may be unacceptable for certain applications.Thermal performance can benefit from an increased density of copper or another metal in the substrate, but this can also increase device size, as well as the cost and complexity of the manufacturing process. Flip-chip packages can be designed to include a cap made of copper or another metal that acts as a heat spreader to dissipate heat, but this adds cost and complexity to the assembly process and can reduce process throughput.

[0012] The double-sided molded structure of electronic device 100 improves thermal performance during operation of electronic device 100 in a host system by facilitating heat dissipation from semiconductor die 110, particularly compared to solder mask-based substrate devices. In one example implementation of electronic device 100, a 13 mm x 13 mm three-level FCCSP substrate with levels L1, L2, and L3 with implementations of first and second molded package structures 111 and 112 was tested for thermal analysis of a projected improvement in a simple circuit board surrogate model and compared to simulated results for a similarly sized three-level substrate with a solder mask along the top and bottom surfaces.The solder mask-based substrate provided a simulated junction-ambient thermal resistance of approximately 25.8°C per watt and a junction-to-board thermal resistance of approximately 5.1°C per watt. Replacing the lower thermal conductivity solder mask with a higher thermal conductivity EMC in the simulated exemplary solder mask-free double-sided molded multi-level package substrate 102 with the first and second molded package structures 111 and 112 provided a junction-to-ambient thermal resistance of approximately 25.4°C per watt and a junction-to-board thermal resistance of approximately 4.7°C per watt, representing a 1.8% and 8.4% reduction in thermal resistance, respectively, and corresponding percentage improvements in thermal conductivity.

[0013] In one example, the first molded package structure 111 provides heat dissipation from the semiconductor die 110 laterally and upwardly to the external environment, and the second molded package structure 112 contributes to dissipating heat downwardly to the host circuit board 116 (e.g., along the Z-direction in Fig. 1). In this regard, solder mask material generally has a very low thermal conductivity, such as 0.21 W / mK or less. In contrast, EMC material of the first and second molded package structures 111 and 112 has significantly higher thermal conductivity coefficients, such as greater than 3 W / mK in certain examples, thanks to solder mask material. In this or another example, the thermal conductivity coefficients of the first and second molded package structures 111 and 112 are approximately 4.3 W / mK. The molding compound material of the first and second molded package structures 111 and 112 may be the same in one example. In another example, different molding compound materials are used for the first and second molded package structures 111 and 112, each with a thermal conductivity greater than 3 W / mK.

[0014] In the example of Fig. 1, the first formed housing structure 111 also encloses the semiconductor die 110. Fig. 1B and Fig. 1C show other exemplary electronic devices 120 and 130, respectively, with similarly numbered structures and features as described above, and in which the first molded package structure 111 extends along at least a portion of the first side 103 of the multi-level package structure 102 without enclosing the semiconductor die 110. In another implementation, the first molded package structure 111 extends along at least a portion of the first side 103 of the multi-level package structure 102 and partially encloses the semiconductor die 110. The electronic device 120 in Fig. 1B has a top and bottom molded package structure 111 and 112, with an upper surface of the semiconductor die 110 exposed outside the first molded package structure 111. The electronic device 130 in Fig. 1C includes a multi-level package substrate 102 having top and bottom molded package structures 111 and 112 and a cap 132 on a top surface of the semiconductor die 110. In other implementations, one or both of the example electronic devices 120 and 130 of Fig. 1B and Fig. 1C may optionally include another separate under-molded structure (not shown), such as an epoxy molding compound, extending between a bottom side of the semiconductor die 110 and a portion of the top side 103 of the multi-level package substrate 102, with another portion of the top side 103 of the multi-level package substrate 102 at least partially covered by the first molded package structure 111.

[0015] The second molded package structure 112, in certain examples, encloses at least a portion of the third metal trace layer features M3 of the third level L3 of the multi-level package substrate 102, as shown in Fig. 1. The second molded package structure 112 extends on portions of the second level dielectric layer 108 laterally between conductive metal features M3 of the third level L3. In another implementation, the third level L3 includes a dielectric layer corresponding to the third metal trace layer features M3, and the second molded package structure 112 extends on portions of the third metal trace layer features M3 and the third level dielectric layer L3. In one implementation, the second molded package structure 112 also contacts an upper portion of the respective solder balls 114. The first and second molded package structures 111 and 112 extend to the lateral edges of the respective sides in the illustrated example, although this is not a strict requirement of all possible implementations.

[0016] Described examples also advantageously reduce substrate manufacturing costs and complexity by removing materials and process steps from the fabrication of the multi-level package substrate 102. The construction of conventional substrates with solder mask material layers on the top and bottom requires the application of solder mask, processing steps, the cost of the solder mask material, and additional time. These costs and steps can be reduced or eliminated during the fabrication of the various implementations of the exemplary solder mask-free multi-level package substrate 102. The first and second molded package structures 111 and 112 are then created during packaging processing, for example, using molding equipment and materials to create molded package structures after the semiconductor dies 110 have been attached to the solder mask-free substrate plate array (e.g.,through flip-chip die attachment and solder reflow operations).

[0017] The solder mask-free multilevel package substrate 102 also provides a process yield advantage by mitigating substrate plate warpage during manufacturing. An exemplary thermally mechanically modeled implementation of the double-sided molded solder mask-free multilevel package substrate 102 reduced warpage by approximately up to 85% from room temperature to reflow temperature. Reducing substrate warpage during manufacturing, particularly for solder mask-free multilevel package substrate plate array structures with rows and columns of simultaneously processed substrate unit areas, advantageously increases process yield and reduces scrap, thereby reducing manufacturing costs for various implementations of the electronic device 100 compared to using substrates with solder mask layers.

[0018] Also referring to Fig. 2-13 shows Fig. 2 a method 200 for manufacturing an electronic device, and Fig. 3-13 show the electronic device 100 of Fig. 1 and Fig. 1A, which is subjected to manufacturing processing according to method 200. The method 200 begins at 202 in Fig. 2 with the fabrication of a solder mask-free, double-sided molded, multi-level package substrate 102. In one implementation, the substrate 102 is fabricated in an initial or starting plate array format with rows and columns of individual unit areas that correspond to subsequently separated electronic devices to enable concurrent processing and reduced manufacturing costs.

[0019] In one example, substrate fabrication at 202 includes layer-by-layer fabrication processing steps. In one implementation, the individual layers are formed, for example, by plating a copper or other metal seed layer on a support structure (not shown), followed by patterned electroplating of a first conductive trace layer and patterned conductive metal features thereof (e.g., copper features M1 in the above Fig. 1), forming a second plating mask and selectively electroplating corresponding conductive metal via features (e.g., V1), and removing the second plating mask. Fabrication of the individual levels further includes press-molding a prepreg material or other suitable dielectric material (e.g., dielectric layers 105 and 106) to cover the metal trace and via features M1, B1, followed by grinding or other planarization to form the first level L1. Similar steps may be used to form the remaining levels L2 and L3, as in the substrate example 102 of Fig. 1. In other implementations, other suitable manufacturing processes and equipment for multi-level package substrates may be used. Importantly, the substrate fabrication at 202 does not use solder mask materials and / or processing steps, thereby saving significant manufacturing time and costs. The processing at 202 does not require the deposition of a solder mask layer or coating, exposure, development, or post-development curing, thereby saving manufacturing time and costs.

[0020] At 204 in Fig. 2, an exemplary implementation of method 200 includes copper surface roughening to enable subsequent soldering operations and / or the application of a finishing layer over the copper or other conductive metal features of the fabricated substrate. In another implementation, the processing at 204 may be omitted.

[0021] The substrate is in one example at 206 in Fig. 2 heated. Fig. 3 shows an example in which a pre-anneal process 300 for annealing the multi-level package substrate plate array 301 including levels L1-L3, as described above in connection with Fig. 1 and Fig. 1A.

[0022] The procedure 200 continues in Fig. 2 continues with die attachment processing at 208. Fig. 4 shows an example in which a flip-chip die attachment process 400 is performed in which the semiconductor die 110 is attached to the top or first side 103 of the solder-mask-free multi-level package substrate board array 301. One example includes automated placement of the semiconductor die 110 with its leads 109 engaging corresponding conductive metal features M1 in the first level L in each unit area of ​​the processed solder-mask-free multi-level package substrate board array 301, for example, using automated pick and place equipment (not shown). In one implementation, the bottom surfaces of the individual semiconductor die leads 109 may be coated with solder, such as by dipping, prior to die placement on the board array.In another example, screen printing or printing or another process is used to form a solder paste (not shown) on selected portions of the top surfaces of one or more of the conductive metal features M1, and the placement positions the semiconductor dies 110 so that their leads 109 engage the previously applied solder paste. The flip-chip die attachment process 400, in one example, also includes thermal processing or heating to reflow the solder to form solder connections between the bottom surfaces of the die leads 109 and the corresponding conductive metal features M1 of the multi-level package substrate board array 301.In another implementation, a semiconductor die may be attached to the first side 103 of the multi-level package substrate plate array 301 using an adhesive along with wire bonding or other suitable electrical interconnect processing (not shown).

[0023] In an example, the method 200 moves to 210 in Fig. 2 with flux cleaning. Fig. 5 shows an example in which a flux cleaning process 500 is performed that removes the residual flux from the multi-level package substrate plate array 301. In another implementation, the flux cleaning at 210 may be omitted, for example, if the die attach processing at 208 does not involve soldering or flux.

[0024] At 212 in Fig. 2, the method 200 continues with pre-forming annealing and pre-forming plasma cleaning. Fig. 6 shows an example in which processing 600 is performed, which may include an annealing and / or plasma cleaning step, for example, to facilitate subsequent molding operations to form the first and second molded package structures 111 and 112, as described above. In another implementation, the annealing and / or plasma cleaning operation may be omitted.

[0025] At 214 in Fig. 2, the method 200 continues by forming the first molded package structure 111 having a first thermal conductivity greater than 3 W / mK on the first side 103 of the multi-level package substrate plate array 301. Fig. 7 shows an example in which a molding process 700 is performed using a mold (not shown) having a cavity or opening that extends above the top surface 103 of the plate array 301 and also spaced from and above the top surface of the semiconductor die 110 in each unit area of ​​the plate array structure 301. The molding process 700, in one example, forms the first molded package structure 111 to enclose the semiconductor die 110 and contact a portion of the first side 103 of the multi-level package substrate 102. In the illustrated example, the molded package structure 111 extends over and contacts portions of the top surface 103 of the substrate 301, including areas laterally between the terminals 109 of the semiconductor die 110. Furthermore, in this example, the first molded package structure 111 encloses the semiconductor die 110 and its terminals 109.In other examples, other mold cavities may be used, for example, to allow a portion of the semiconductor die 110 to be exposed outside the first molded package structure 111 (e.g., the top side of the semiconductor die 110). In this or another example, the mold used in the process 700 may include features that contact portions of the top side 103 of the multi-level package substrate plate array 301, and the fabricated first molded package structure 111 may contact or cover less than the entire first or top side 103 of the first level L1 of the substrate array 301.

[0026] After forming the first molded housing structure 111, the method 200 proceeds at 216 to Fig. 2 continue with cleaning after forming. Fig. 8 illustrates an example in which a post-molding cleaning process 800 is performed, which cleans the molded package structure 111 and any exposed surfaces of the multi-level package substrate plate array 301. In another implementation, the post-molding cleaning at 216 may be omitted.

[0027] In an example, the method 200 continues at 218 in Fig. 2 with solder ball attachment processing after formation of the first molded package structure 111 at 214 and any intermediate post-molding cleaning at 216. Fig. 9 shows an example in which a solder ball attachment process 900 is performed, in which the solder balls 214 are attached to corresponding conductive metal features M3 on the second or bottom side 104 of the multi-level package substrate board array 301. Any suitable ball attachment equipment and materials may be used to implement the solder ball attachment process 900, such as those used in forming ball grid array (BGA) electronic devices. In the illustrated example, the solder ball attachment occurs at 218 prior to forming the second molded package structure 112 of Fig. 1 and Fig. 1A.

[0028] The method 200 includes, in one example, forming the second molded housing structure 112 at 220-224 in Fig. 2. The illustrated example involves forming the bottom of the substrate at 220. Fig. 10 shows an example in which a second molding process 1000 is performed, in which a second molded package structure 112 having a second thermal conductivity greater than 3 W / mK is formed on the second side 104 of the multi-level package substrate plate array 301, wherein the second molded package structure 112 is spaced from the first molded package structure 111. In the illustrated example, the second molding process 1000 forms the second molded package structure 112 to enclose the solder balls 114 attached to the bottom side 104 of the substrate plate array 301. Furthermore, the second molding process 1000 forms the second molded package structure 112 contacting a portion of the second side 104 of the multi-level package substrate 102. In the illustrated example, the molding process 1000 completely encloses the attached solder balls 114, although this is not a requirement of all possible implementations.

[0029] At 222 and 224, in one example, the method 200 further includes removing a portion of the second molded package structure 112 to expose all or a portion of the solder balls 114. The illustrated example includes grinding at 222, followed by laser ablation at 224. In other implementations, a single mold material removal process may be used, or various single- or multi-step material removal techniques and devices may be used. At 222 in Fig. 2, the exemplary method 200 includes grinding or other suitable processing to remove a first portion or part of the second molded package structure 112 to expose the solder ball 114. Fig. 11 shows an example in which a mechanical grinding process 1100 is performed in which a first portion of the second molded package structure 112 is removed to expose a lower first portion of the solder balls 114.

[0030] The method 200, in this example, continues at 224 with laser ablation according to a desired ball grid array shape based on the positions of the attached solder balls 114 along the bottom surface 104 of the multi-level package substrate board array 301. Fig. 12 shows an example in which a laser ablation process 1200 is performed, exposing a second portion of the individual solder balls 114. In one example, the laser ablation is automated, with a laser being translated relative to the multi-level package substrate board array 301 to programmatically remove the second portion of the second molded package structure 112 between the attached solder balls 114. In one implementation, the laser power and the translation speed and positioning in the process 1200 are controlled to remove a sufficient amount of the molded package structure 112 to enable subsequent user-performed soldering of the finished electronic device to a host circuit board.

[0031] The process continues at 226 in Fig. 2 with a device separation. In the illustrated example, the multi-level packaging substrate at 202-224 was fabricated and processed in the form of a plate array 301 having rows and columns of corresponding unit areas, each of which includes a future encapsulated electronic device with a corresponding semiconductor die 110 and one or more attached solder balls 114. Fig. 13 shows an example in which a device separation process 1300 is performed, separating the individual unit surfaces along lines 1302 to separate finished encapsulated electronic devices 100 from the initial plate array structure. Any suitable device separation process 1300, for example, laser cutting, sawing, chemical etching, or combinations thereof, may be used. In another implementation where no plate array structure is used, the device separation processing at 226 may be omitted.

[0032] Described examples enable improved thermal conductivity of the solder mask-free multi-level package substrate 102 and the finished encapsulated electronic device 100 beyond what is available in the industry, thereby improving the heat dissipation of the package during operation of the electronic device 100 and the system operation when installed on a printed circuit board (e.g., the printed circuit board 116 in the above Fig.1). Furthermore, the described solutions advantageously reduce substrate costs by removing solder mask processing from the manufacturing process used to fabricate the multi-level package substrate 102 in a single form or as a plate array. In addition to these advantages, the described solutions also enable significantly improved manufacturing yield during electronic device packaging by reducing substrate warpage during thermal processing. Furthermore, the processing techniques of the exemplary manufacturing method 200 can be applied using existing materials and equipment, for example, using well-developed package forming processes, grinding processes, laser ablation processes, etc.

[0033] Modifications of the described examples and other implementations are possible within the scope of the claims.

Claims

[1] Electronic device comprising: a multi-level package substrate having opposing first and second sides; a semiconductor die attached to the first side; a first molded housing structure on the first side; and a second molded housing structure on the second side and spaced from the first molded housing structure. [2] The electronic device of claim 1, wherein the first molded package structure encloses the semiconductor die. [3] The electronic device of claim 1, comprising a solder ball contacting a conductive metal feature on the second side of the multi-level package substrate. [4] The electronic device of claim 3, wherein the second molded housing structure encloses a portion of the conductive metal feature and contacts a portion of the solder ball. [5] The electronic device of claim 4, wherein the second molded housing structure has a thermal conductivity greater than 3 W / mK. [6] The electronic device of claim 1, wherein the second molded housing structure has a thermal conductivity greater than 3 W / mK. [7] The electronic device of claim 6, wherein the first molded housing structure has a thermal conductivity greater than 3 W / mK. [8] The electronic device of claim 7, wherein the thermal conductivity of the second molded housing structure is approximately 4.3 W / mK. [9] The electronic device of claim 7, wherein the first molded housing structure has a thermal conductivity that is approximately 4.3 W / mK. [10] The electronic device of claim 1, wherein the second molded housing structure has a thermal conductivity that is approximately 4.3 W / mK. [11] A system comprising a printed circuit board and an electronic device mounted on the printed circuit board, the electronic device comprising: a multi-level package substrate having opposing first and second sides and a terminal soldered to a conductive feature of the circuit board; a semiconductor die attached to the first side; a first molded housing structure on the first side; and a second molded housing structure on the second side and spaced from the first molded housing structure. [12] The system of claim 11, wherein the first molded package structure encloses the semiconductor die. [13] The system of claim 11, wherein the terminal is a solder ball contacting a conductive metal feature on the second side of the multi-level package substrate. [14] The system of claim 11, wherein the second molded housing structure has a thermal conductivity greater than 3 W / mK. [15] The system of claim 14, wherein the thermal conductivity of the second molded housing structure is approximately 4.3 W / mK. [16] A method of manufacturing an electronic device, the method comprising: Attaching a semiconductor die to a first side of a solder mask-free multi-level package substrate; Forming a first molded package structure having a first thermal conductivity greater than 3 W / mK on the first side of the multi-level package substrate; and Forming a second molded package structure having a second thermal conductivity greater than 3 W / mK on an opposite second side of the multi-level package substrate and spaced from the first molded package structure. [17] The method of claim 16, wherein forming the first molded package structure on the first side includes performing a molding process in which the first molded package structure is formed to enclose the semiconductor die and contact a portion of the first side of the multi-level package substrate. [18] The method of claim 16, further comprising, after forming the first molded package structure and before forming the second molded package structure, attaching a solder ball to a conductive metal feature on the second side of the multi-level package substrate. [19] The method of claim 18, wherein forming the second molded housing structure comprises: Performing a molding process in which the second molded package structure is formed to enclose the solder ball and contact a portion of the second side of the multi-level package substrate; and Removing a portion of the second molded package structure to expose the solder ball. [20] The method of claim 19, wherein removing a portion of the second molded housing structure comprises: Performing a grinding process in which a first portion of the second molded package structure is removed to expose a first portion of the solder ball; and Performing a laser ablation process to expose a second portion of the solder ball. [21] A method for reducing substrate warpage, comprising: Forming a solder mask-free multi-level package substrate; Forming a first molded package structure having a first thermal conductivity greater than 3 W / mK on the first side of the solder mask-free multi-level package substrate; and Forming a second molded package structure having a second thermal conductivity greater than 3 W / mK on an opposite second side of the solder mask-free multi-level package substrate and spaced from the first molded package structure.

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