Integrated inverting / non-inverting regenerative capacitive load driver with high voltage conversion ratio

Abstract

A driver circuit includes a series-parallel charge pump comprising switched capacitor cells, the series-parallel charge pump generating coarse signal steps at a first output node and a second output node; a flying capacitor connected between the first output node and the second output node; and a digital-to-analog converter (DAC) connected between the first output node and the second output node and comprising switched capacitors for generating a plurality of fine signal steps.

Description

[0001] The present invention generally relates to an integrated inverting / non-inverting recuperative capacitive load driver with a high voltage conversion ratio and a corresponding control method.

[0002] Microelectromechanical systems (MEMS) enable a high degree of miniaturization, robustness, and integration, as well as cost and manufacturing advantages, such as flow solderability. As is known in the prior art, MEMS devices are used in many applications as ultrasonic actuators and sensors. Typical MEMS equivalent circuits are generally represented by a capacitive load, which, compared to conventional inductive actuators, requires high drive voltages that significantly exceed battery voltage levels. Due to the capacitive nature of the MEMS actuator and MEMS sensor devices, a high reactive power is required for charging and discharging, which is associated with periodic excitation, actuation, or sensing. This is especially true when the MEMS devices are modulated at high operating frequencies.

[0003] Most state-of-the-art drivers lack energy recuperation capabilities and therefore dissipate all of their stored energy. This, in turn, causes excessive power consumption and battery discharge, which is unacceptable for small form factor, battery-powered applications. A 200 pF MEMS load driven at 30 Vpp (peak-to-peak) at a frequency of 1 MHz without recuperation results in a power dissipation of 180 mW, more than ten times the typical system power dissipation of, for example, wearable earbuds or true wireless earbuds (TWS). Typical capacitive MEMS devices are therefore unsuitable for wearable applications unless energy can be recuperated, given the high voltage conversion ratios and high operating frequencies, which are mutually exclusive design goals.

[0004] Applications with high dynamic range, especially audio applications, require efficient drive control at both peak and typical LSB switching amplitudes (LSB = Least Significant Bit) to achieve overall energy efficiency. Since energy recuperation decreases with decreasing amplitude for established, well-known integrated capacitive MEMS drivers, significant recuperation and sufficient efficiency during typical playback are not achievable with state-of-the-art concepts.

[0005] An example of a state-of-the-art driver circuit for controlling a MEMS load is in Fig. Figure 2 shows the driver circuit 200, which includes a differential input at nodes 210 and 212 for receiving a supply or input voltage V. inThe driver circuit 200 comprises a plurality of switching cells 202, 204, and 206, as well as an output cell 208. Switching cell 202 is coupled to a flying capacitor circuit 228, switching cell 204 is coupled to a flying capacitor circuit 230, and switching cell 206 is coupled to a flying capacitor circuit 232. Each switching cell includes three switching transistors, including transistor M. ParP , M Up and M ParN .

[0006] The transistor M is located in switching cell 202. ParP connected between nodes 210 and 214, the transistor M Up is connected between nodes 210 and 216 and the transistor M ParN It is connected between nodes 212 and 216. The capacitor circuit 228 includes capacitor C. Fly , which is connected between nodes 214 and 216. As a result of parasitic capacitances between the plates of flying capacitors and the bulk, the capacitor α occurs.τ *C Fly connected between node 214 and ground and the capacitor α B *C Fly switched between node 216 and mass, where α T denotes the fraction of the parasitic bulk capacity in relation to the flying capacity.

[0007] The transistor M is located in switching cell 202. ParP connected between nodes 210 and 214, the transistor M Up is connected between nodes 210 and 216 and the transistor M ParN is connected between nodes 212 and 216. The capacitor circuit 228 includes the capacitor CFly, which is connected between nodes 214 and 216, and parasitic capacitances αT*CFly connected between node 214 and ground and the capacitor αB*CFly connected between node 216 and ground occur.

[0008] The transistor M is located in switching cell 204. ParP connected between nodes 214 and 218, the transistor M Upis connected between nodes 214 and 220 and the transistor M ParN is connected between nodes 216 and 220. The capacitor circuit 230 includes the capacitor CFly, which is connected between nodes 218 and 220, and parasitic capacitances αT*CFly, which are connected between node 218 and ground, and the capacitor aB*CFIy, which is connected between node 220 and ground.

[0009] The transistor M is located in switching cell 206. ParP connected between nodes 218 and 222, the transistor M Up is connected between nodes 218 and 224 and the transistor M ParN It is connected between nodes 220 and 224. The capacitor circuit 232 includes capacitor C. Fly , which is connected between nodes 222 and 224, the capacitor α T *C Fly , which is connected between node 222 and ground, and the capacitor α B *C Fly , which is connected between node 224 and ground.

[0010] Finally, output cell 208 contains transistor M ParP , which is connected between node 222 and output node 226, and transistor M ParN , which is connected between node 224 and output node 226. Although the driver circuit 200 has several advantages, such as the use of low-voltage transistors, it can be difficult in some applications to significantly increase the output voltage without incurring parasitic power losses due to the number of switching cells required.

[0011] The object of the present invention is to provide driver circuits with improved properties.

[0012] This problem is solved by a driver circuit according to claim 1, claim 18 and claim 19.

[0013] According to one embodiment, a driver circuit comprises a series-parallel charge pump comprising a plurality of switched capacitor cells, wherein the series-parallel charge pump is configured to generate a plurality of coarse signal steps between a first output node and a second output node; a flying capacitor connected between the first output node and the second output node; and a digital-to-analog converter (DAC) connected between the first output node and the second output node, comprising a plurality of switched capacitors configured to generate a plurality of fine signal steps.

[0014] According to one embodiment, a driver circuit comprises a series-parallel charge pump configured to generate a plurality of coarse signal steps; a digital-to-analog converter (DAC) coupled to the series-parallel charge pump and comprising a plurality of switched capacitors; and a flying capacitor connected between the series-parallel charge pump and the DAC, wherein the DAC is configured to generate a plurality of fine signal steps and to charge the plurality of switched capacitors only when a load is coupled to the driver circuit.

[0015] According to one embodiment, a driver circuit comprises a plurality of series-connected macrocells, each macrocell comprising a plurality of booster cells for generating a plurality of coarse signal steps; and a plurality of bucker cells for generating a plurality of fine signal steps by dividing each of the coarse signal steps.

[0016] Preferred embodiments of the present invention are explained in more detail below with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of a load driver circuit according to an exemplary embodiment; Fig. 2 a schematic diagram of a state-of-the-art driver circuit; Fig. 3 is a schematic diagram of a load driver circuit according to an exemplary embodiment; Fig. 4 a timing diagram of the load driver circuit of Fig. 3 is; Fig. 5A is a schematic diagram of a fine DAC according to another embodiment; Fig. 5B is a schematic diagram of a fine DAC according to another embodiment; Fig. 5C is a schematic diagram of a fine DAC according to another embodiment; Fig. 5D is a schematic diagram of a fine DAC according to another embodiment; Fig. 5E is a schematic diagram of a fine DAC according to another embodiment; Fig. 5F is a schematic diagram of a fine DAC according to another embodiment; Fig. 6 is a schematic diagram of a system with a load driver circuit according to an exemplary embodiment; Fig. 7 is a block diagram of a load driver circuit according to another embodiment; and Fig. Figure 8 is a schematic diagram of a fine DAC according to another embodiment, which is the load driver circuit of Fig. 7 is assigned.

[0017] The manufacture and use of the preferred embodiments are explained in detail below. It should be understood, however, that the present invention provides many applicable inventive concepts that can be implemented in a wide variety of specific contexts. The specific embodiments described serve only to illustrate specific ways of manufacturing and using the invention and do not limit its scope.

[0018] The following detailed description refers to the accompanying drawings, which form part thereof and illustrate specific embodiments in which the invention can be implemented. It is understood that other embodiments may be used and structural or logical modifications may be made without departing from the scope of the present invention. For example, features illustrated or described for one embodiment may be used in or in combination with other embodiments to produce yet another embodiment. The present invention is intended to include such modifications and variations. The examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims.The drawings are not to scale and are for illustrative purposes only. For clarity, the same or similar elements have been designated by corresponding reference symbols in the various drawings, unless otherwise indicated.

[0019] According to exemplary embodiments, a highly dynamic, recuperating, integrated capacitive load driver with a high voltage conversion ratio generates periodic or arbitrary step waveforms (or signal waveforms) with dynamically configurable frequency, amplitude, phase, and waveform. According to exemplary embodiments, the load driver operates at audio, ultrasonic, or other operating frequencies and recuperates energy at both low and high amplitudes when a capacitive load is modulated. Although exemplary embodiments of the present invention are well suited for driving a capacitive load, for example, a MEMS loudspeaker, other types of loads that are not MEMS devices and are not primarily capacitive can also be driven. In some exemplary embodiments, the load can be differential and driven by two load drivers according to exemplary embodiments, as will be described in more detail later.According to exemplary embodiments, the load driver comprises a unipolar or bipolar (non-inverting and inverting) charge pump based on configurable capacitor arrays, wherein flying capacitors operate in a parallel-series configuration, while a coarse-stage boost converter (unloaded) provides either positive multiples or both positive and negative multiples of the input voltage at the output, and wherein floating supplies of integrated switches and their gate drivers are supplied by flying capacitors referenced to parallel-series charge pump levels. According to exemplary embodiments, the load driver also comprises a fine-stage converter that provides one or more intermediate voltage levels between the voltage levels at the terminations of the respective...The last flying capacitors are supplied by a capacitive tank or capacitive divider referenced to and supplied by the same flying capacitor voltage (or voltages) in the coarse converter. The intermediate voltage levels are used to traverse intermediate levels in a stepwise manner, increasing the number of steps in the stepwise charging process beyond the number of coarse-stage range levels. These and other features of the load driver according to exemplary embodiments are described in more detail below.

[0020] The load driver circuit, as described below, is counterintuitive because the fine converter adds a parasitic load to the series-parallel charge pump. The series-parallel (RP) charge pump boost functionality is extremely sensitive to loads and parasitic capacitances, and a capacitive divider network adds additional switching and parasitic capacitance losses that burden the RP charge pump. In some prior art designs, the boost functionality, voltage conversion ratio (VCR), and charge pump efficiency are affected by the additional parasitic capacitance and losses. However, in the fine converter circuits described below, the reduction of dynamic losses outweighs the additional losses.In addition, a sub-control, which is described in detail below, advantageously increases the charge pump efficiency and the VCR ratio of the RP charge pump.

[0021] Thus, in exemplary embodiments, the flying capacitor and the fine converter are configured to generate a plurality of fine signal steps and are implemented such that the majority of switched capacitors are only discharged and charged when a load is coupled to the driver circuit; otherwise, dynamic losses are minimized. This is because the flying capacitor and the fine converter act as a buffer and do not significantly load the RP charge pump when no load is present.

[0022] Fig. Figure 1 is a block diagram of a load driver circuit 100 according to an exemplary embodiment. The load driver circuit 100 comprises a bipolar series-parallel charge pump 106, which is described below with respect to a Fig. The charge pump circuit shown in Figure 3 is described in more detail below. The bipolar series-parallel charge pump 106 has outputs connected to a flying capacitor C. FlyDAC at node 108 (V P ) and node 110 (V N ) are coupled. A series capacitor (RK or SC = Series Capacitor) fine digital-to-analog converter (DAC) 112 has inputs that are coupled to nodes 108 and 110. The DAC 112 is described below with respect to the Fig. 5- Fig. The 9 DAC circuits shown are described in more detail below. A bias capacitor C BIAS is between the output of the DAC 112 (V CP ) and node 114 (V L) switched. A load 118 is coupled to node 114. As noted previously, the load 118 can be a capacitive load, but it can also be any type of load, for example, a resistive load or a sensor. The load driver circuit 100 can also include a quasi-static, high-impedance charge pump 116 connected between node 104 and the V BIAS -node is switched. The charge pump 116 advantageously provides the V BIAS -Preload independent of AC excitation (V CP ) one. Any suitable low-power charge pump can be used to implement charge pump 116, which is implemented using techniques such as reduced drive power, switching frequencies, low quiescent currents, and efficient circuit topologies known in the prior art. A bias resistor R BIAS is between the V BIAS-Node and node 114 are switched. Finally, the load driver circuit 100 can include an input DC-DC converter 102 for the initial conditioning of an input voltage signal.

[0023] Fig. Figure 3 is a schematic diagram of a load driver circuit 300 according to an exemplary embodiment. The load driver circuit 300 is advantageously designed for driving loads, and in particular capacitive loads, and comprises a bipolar series-parallel charge pump 303, which has a plurality of switched capacitor cells, comprising at least one switched capacitor cell 302 and one switched capacitor cell 304, wherein the bipolar series-parallel charge pump 303 is used to generate a plurality of coarse signal steps between a first output node V DDN and a second output node V SSN is configured. The load driver circuit 300 also features a floating capacitor C. FlyDACon, which is between the first output node V DDN and the second output node V SSN The load driver circuit 300 further comprises a fine digital-to-analog converter (DAC) 306, which is connected between the first output node VDDN and the second output node VSSN and has a plurality of switched capacitors configured to generate a plurality of fine signal steps.

[0024] The bipolar series-parallel charge pump 303 has at least one switched capacitor cell 302 and one switched capacitor cell 304, although more switched capacitor cells can be used to provide a required charge pump output voltage at the first output node V DDN and the second output node V SSNto develop. The switched capacitor cell 302 has a plurality of switches, including a first bypass switch connected between the Vin input nodes and node 305, an up switch connected between the Vin input nodes and node 307, a down switch connected between node 305 and ground, and a second bypass switch connected between node 307 and ground. The switched capacitor cell 304 has the same plurality of switches, including a first bypass switch connected between node 305 and the first output node V. DDN is switched, an UP switch located between node 305 and the second output node V SSN is switched, a DOWN switch which is switched between node 307 and the first output node VDDN, and a second BYPASS switch which is switched between node 307 and the second output node V SSNThe switched capacitor cell 304 also includes a capacitor C. Fly on, which is connected between node 305 and node 307. Additional capacitor cells, if used, also have a capacitor C. Fly up, as in Fig. 3 shown. In Fig. 3 will be the V in The device is powered by a constant battery voltage or the output voltage of a sub-regulator or power converter. The constant battery voltage has a minimum voltage of approximately one or more volts, or some other minimum voltage value determined by the semiconductor process used. Otherwise, the constant battery voltage is determined by the desired amplitude of the V. DDN - and V SSNThe voltages and the number of switched capacitor cells used are determined. The VOut output is any analog stepped waveform generated by varying the number and timing of individual coarse and fine steps, as described herein. In exemplary embodiments, the generated output signal includes or is related to analog audio, speech, or music signals to drive a MEMS device, for example, a direct-drive, paramodulated, or pumped MEMS loudspeaker. Other MEMS and non-MEMS loads can also be driven.

[0025] The output of the bipolar series-parallel charge pump 303 is coupled to a flying capacitor CFlyDAC at the first output node VDDN and the second output node VSSN. The flying capacitor CFlyDAC is part of a fine DAC or, in some embodiments, a standalone component. The fine DAC 306 is described in more detail below.

[0026] The Fein-DAC 306 also includes an optional pre-charge circuit 308 and a decoder circuit 310 for supplying the VOut output signal described below. The Fein-DAC 306 also includes a three-stage switched-capacitor voltage divider 314, which is also described below. The voltage divider 314 may have fewer or additional stages in other embodiments.

[0027] The optional pre-charge circuit 308 comprises switches S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, and S13, as well as capacitors CD1, CD2, CD3, and CD4. Capacitors CD1, CD2, CD3, and CD4 are connected in series to form a voltage divider 312. The control nodes of switches S1, S2, S3, S4, S5, and S6 are controlled by an EQLZ equalization signal. The control nodes of switches S7, S8, S9, S10, S11, S12, and S13 are controlled by an INIT initialization signal. In the example of Fig. Switch S1 is connected between node 309 and node 311, switch S2 is connected between node 309 and node 313, and switch S3 is connected between node 309 and node 315. The optional pre-charge circuit 308 also includes capacitor C. D1 and the switch S7, which are connected in series between node 311 and node 313, the capacitor C D2and the switch S8, which are connected in series between node 313 and node 315, the capacitor C D3 and the switch S9, which is connected in series between node 315 and node 309, and the capacitor C D4 , which is between node 309 and the second output node V SSN The switch S4 is switched between the second output node V. SSN and the transition between capacitor C D1 and switched to switch S7, switch S5 is between the second output node V SSN and the transition between capacitor C D2 and switched to switch S8 and switch S6 is between the second output node V SSN and the transition between capacitor C D3 and switched by switch S9. Switch S10 is located between node 311 and the first output node V. DDNSwitch S11 is switched between node 313 and node 316, switch S12 is switched between node 315 and node 318, and switch S13 is switched between node 309 and node 320.

[0028] The timing of and between the EQLZ and INIT control signals is described below. For initialization or refresh, the capacitive divider 312 can be initially or repeatedly loaded by the capacitive divider C. D1 , C D2 , C D3 , C D4 parallel to the flying supply C FlyDAC The system switches and uses periodically intervening, mutually exclusive balancing phases to equalize and balance the levels of the DAC 306. The phases of the EQLZ and INIT signals alternate as required for initialization and refresh.

[0029] The voltage divider 314 has a capacitor C S1, which is between the first output node V DDN and node 316 is connected, a capacitor C S2 , which is between the first output node V DDN and node 318 is connected, a capacitor C S3 , which is between the second output node V SSN and node 318 is connected, and a capacitor C S4 , which is connected between the second output node VSSN and node 320.

[0030] In operation, each of the capacitors C D1 , C D2 , C D 3 and C D 4. In some embodiments, the values ​​are the same. Each of the capacitors C also has the same values. S 1, Cs2, Cs3 and Cs4 have the same values ​​in some embodiments. In the example of Fig. 3. The voltage at node 316 3 / 4 of the value of (V) DDN - V SSN ), the voltage at node 318 is 1 / 2 of the value of (V DDN - V SSN) and the voltage at node 320 is 1 / 4 of the value of (V DDN - V SSN ), with all referring to the V SSN -are related to voltage.

[0031] The Fein-DAC 306 also includes a decoder 310, which includes a switch SPN connected between the first output node VDDN and the VOut output voltage node of the Fein-DAC 306, a switch FDm+1 connected between node 316 and the VOut output voltage node of the Fein-DAC 306, a switch FDm connected between node 318 and the VOut output voltage node of the Fein-DAC 306, a switch FD1 connected between node 320 and the VOut output voltage node of the Fein-DAC 306, and a switch FDN connected between the second output node VSSN and the VOut output voltage node of the Fein-DAC 306. In the Fein-DAC 306, the decoder 310, according to one embodiment, has a one-hot decoder.

[0032] During operation, one of the switches in the decoder 310 selectively transmits the V DDN -voltage, which V SSN -Voltage or the voltage divider voltages to the output of the fine-DAC under the control of a plurality of control signals (in Fig. 3 not shown), to create the desired output voltage transient to drive a capacitive load or other type of load.

[0033] Fig. Figure 4 is a timing diagram 400 of the load driver circuit from Fig. 3. In timing diagram 400, the X-axis represents time and the Y-axis represents voltage. The following voltage waveforms are shown in Fig. 4 shown: The waveform V P 402 is the "upper" voltage of capacitor C FlyDAC and corresponds to the one in Fig. 3 shown V DDN -Voltage, the waveform V N 406 is the "lower" voltage of capacitor C FlyDAC and corresponds to the one in Fig. 3 shown V SSN-Voltage and waveform V CP 404 is the output voltage of the Fig. The 3 shown fine DAC 306 corresponds to the one in Fig. 3 shown V Out -Voltage. It is in the timing diagram 400 of Fig. 4 to see that the V P - and V N -Voltage waveforms: rough representations of the input voltage V In with a discrete number of coarse voltage levels. The timing diagram 400 of Fig. 4 also shows that the V CP -Waveform provides a more accurate representation of the input voltage Vin with an additional number of fine voltage levels. In one embodiment, each coarse voltage level is divided into an equal integer number of fine voltage levels by the operation of the Fine-DAC 306. During operation, all Fine-DAC levels can be allowed or, in some embodiments, restricted and omitted. In the example of Fig. 4. Each coarse stress step is divided into three equal fine stress steps. In other embodiments, fewer or additional fine stress steps may be used for each coarse stress step. In some embodiments, the fine stress steps do not need to be exactly equal.

[0034] The control signals for the in Fig. The UP, DOWN, and BYPASS switches shown in Figure 3, and the generation of the coarse voltage with respect to the input signal, are described below. To generate the positive rising edge of the signal shown in Figure 3, the following steps are taken: Fig. In the 4th depicted triangular waveform, the BYPASS switches open sequentially while the corresponding UPWARD switches (in each of the RP charge pump stages) close, until the maximum amplitude is reached. The process is then reversed, with the UPWARD switches opening while the corresponding BYPASS switches closing, until the intermediate level is reached again, at which point all BYPASS switches are closed and all flying capacitors C Fly and C FlyDACare recharged. Then the process repeats to generate the negative half-wave, and the bypass switches are opened sequentially while the corresponding downshift switches are closed until the maximum negative amplitude is reached. The process is reversed again, and the downshift switches are opened while the corresponding bypass switches are closed until the intermediate level is reached again. Thus, with "N" stages, 2N + 1 coarse levels are generated, and the minimum stage size is calculated as the peak-to-peak amplitude divided by 2N, which is twice the number of charge pump stages.

[0035] Fig. Figure 5A is a schematic diagram of a Fein-DAC 500A according to another embodiment. The Fein-DAC 500A has an energy storage capacitor arrangement 505, which includes capacitor dividers 506 (capacitor C). P1 and capacitor C N1 ), 508 (capacitor C P2 and capacitor C N2), 510 (capacitor C P3 and capacitor C N3 ) or 512 (capacitor C) PN and C NN ) which are configured to provide a plurality of intermediate voltages 516, 518, 520 and 522 between the first output node voltage VDDN and a second output node voltage VSSN. While in the schematic diagram of Fig. While four capacitor dividers are shown in Figure 5A, additional or fewer capacitor dividers may be used in other embodiments. The Fein DAC 500A also includes a switch arrangement 514 comprising parallel switches S0, S1, S2, S3, S N-1 and S N features which are configured to selectively couple the majority of intermediate voltages 516, 518, 520 and 522 to the VOut output of the DAC. In some embodiments, “N” is an integer greater than or equal to three.

[0036] The Fein-DAC 500A optionally features a refresh and initialization circuit 501, which is coupled to the first output node VDDN and the second output node VSSN and to the energy storage capacitor arrangement 505. The refresh and initialization circuit 501 includes a capacitor divider 502, which connects capacitors C in series. D0 , C D1 , C D2 , C DN The capacitor divider 502 is in turn coupled to a switch arrangement 504, which includes switches S D0 , S D1 , SD2, SD3, S DN-1 and S DN exhibits. While four capacitors are shown in the capacitor divider 502 and six switches are shown in the switch arrangement 504, it will be obvious to those skilled in the field that additional or fewer components are used, corresponding to the number of intermediate voltages used in other embodiments.

[0037] During operation, when capacitor C Dm -pens, where C Dm the capacitors C D0 , C D1 , C D2 , C DN This corresponds to being repeatedly connected to adjacent levels between m-1 and m and between m and m+1 of the energy storage capacitor arrangement 505, thus equalizing the voltage difference between adjacent levels m-1, m and m+1. Therefore, during refresh and initialization cycles, all intermediate levels will settle to voltage levels between V DDN or V SSN are distributed.

[0038] Fig. Figure 5B is a schematic diagram of a fine DAC 500B according to another embodiment. The fine DAC 500B has a combined energy storage and capacitive divider arrangement 502B configured to provide a plurality of intermediate voltages 516B, 518B, and 520B between the first output node voltage V DDN and the second output node voltage VSSN to provide. The combined energy storage and capacitive divider arrangement 502B features a flying capacitor C. FlyDAC and a capacitor divider, which includes capacitors C D1 , C D2 , C D3 and C D4 features switches S 7B , S 8B , S 9B and S 10B are connected in series. The Fein DAC 500B also features a switch arrangement 506B configured to selectively connect the majority of intermediate voltages 516B, 518B and 520B, as well as VDDN and VSSN, to output V. Out to couple. The switch arrangement features a plurality of parallel switches S F0, S F1 , S Fm , S Fm+1 and S FMThe number of switches and the number of capacitor divider capacitors can be reduced or increased in other embodiments. The Fein-DAC 500B optionally also features a refresh and initialization circuit 504B, which is coupled to the combined energy storage and capacitive divider arrangement 502B. The refresh and initialization circuit 504B has activation switches S 1B , S 2B , S 3B , S 4B , S 5B and S 6B on, with the control node of each of the switches coupled to an EQLZ equalization control signal.

[0039] In operation, the 502B combined energy storage and capacitive divider assembly functions as an energy storage cap assembly when the activation switches are closed. The 502B combined energy storage and capacitive divider assembly establishes intermediate voltage levels between V DDN and V SSNthrough a series-connected capacitor arrangement configuration between V DDN or V SSN ready. The same arrangement also forms a capacitive divider network for refreshing and initialization, which generates intermediate voltages by dividing the V DDN -V SSN -provides differential voltage. The voltages across the capacitive divider capacitors can be balanced when the activation switches are closed. An analog multiplexer or 506B switch assembly is used to adjust the intermediate voltage levels as well as the V DDN - and V SSN -Voltages with the output node V Out to connect.

[0040] Fig. 5C is a schematic diagram of a Fein-DAC 500C according to another embodiment, which is different from the one described above with respect to Fig. The Fein-DAC 500A described in section 5A is similar, except that the refresh and initialization circuit 501 is omitted. In the relevant part, the Fein-DAC 500C has an energy storage capacitor arrangement 501C coupled to a switch arrangement 505C. The energy storage capacitor arrangement 501C includes a floating capacitor C. FlyDAC and a plurality of capacitor dividers 502C (capacitor C S1u and capacitor C S1l ), 504C (capacitor Cs mu and capacitor C Sml ) and 506C (capacitor C Smu+1u and capacitor C Sml+1l ) for generating intermediate voltages at nodes 516C, 518C, and 520C. The switch arrangement comprises a plurality of switches coupled to the energy storage capacitor arrangement 501C and includes switch S F0, S F1 , S Fm , S Fm+1 and S FMThe exact number of capacitor dividers and switches in the switch arrangement can be increased or decreased in different embodiments.

[0041] In operation, the 501C energy storage capacitor assembly provides intermediate voltage levels between VDDN and VSSN for "M" DAC cells. At least one pin of the capacitor in the 501C energy storage capacitor assembly is connected to either V DDN or V SSN coupled or in other words, in upper (C S1u , C Smu and C Smu+1u ) and lower (C S1l , C Slu and C Sml+1l ) Capacitor arrays are divided. An analog multiplexer or a 505C switch array couples the intermediate voltage levels as well as V. DDN and V SSN with the output node V Out. The refresh and initialization circuit (in Fig. 5A shown) can be used in the embodiment of Fig. 5C can be removed to minimize parasitic bulk capacitances and improve efficiency. If initial adjustment over several modulation cycles is acceptable, the Fine DAC intermediate levels will self-adjust using a periodic switching sequence for continuous DC / AC modulation. Adjustment can be further reduced by adjusting the ratio of the upper and lower capacitors of the 501C energy storage capacitor array to form capacitive dividers that reflect the set values ​​when the Fine DAC 500C's power supply is powered up. For example, for three levels, the ratio of C S1u / C S1l 1 / 3, the ratio of C S2u / C S2l can be one and the ratio for C S3u / C S3l can be three, which represent levels of 1 / 4, 1 / 2 and 3 / 4 of the V DDN -V SSN -results in a voltage difference.

[0042] Fig. Figure 5D is a schematic diagram of a Fein-DAC 500D according to another embodiment. The Fein-DAC 500D has a plurality of series-connected unit cells 502D, 504D, and 506D configured to implement a binary-weighted sum of shifted input voltage components, each unit cell having a pair of series-connected capacitors and two pairs of switches coupled to the pair of series-connected capacitors. Unit cell 502D has capacitors C D1U and C D1L , a first pair of switches, including switch S D1U and S D1L , and a second pair of switches S D1U' and S D1L' The 504D unit cell has capacitors C DmU and C DmL , a first pair of switches, including switch S DmU and S DmL , and a second pair of switches S DmU' and S DmL'The Fein DAC 500D also features a multiplexer coupled with the 506D unit cell, which includes switches S. F0, S F1 , SF2, SF3 and S F4 The Fein-DAC 500D optionally also features a compensating capacitor C. E on, which is coupled to the unit cell 506D. Specifically, the capacitor CE is between node 525D (transition between switches S). DMU and S DML ) and node 527D (transition between switches S DMU' and S DML ,) switched.

[0043] In operation, the Fein-DAC 500D is a fine DAC based on a binary adder, featuring "M" stages of unit cells that implement a binary-weighted sum of shifted input voltage components. In the example of Fig. In 5D, "M" is an integer equal to three. However, "M" can take on other integer values. As described previously, each unit cell contains two capacitors C. DmU and CDmL on, forming a binary capacitive voltage divider. The capacitor voltage dividers are used to halve the input voltage. Two pairs of switches (S FMU and S FML , and S FMU' and S FML ) couple a subsequent unit cell “(m+1)” input to the outputs of the “m” preceding unit cell. Each unit cell outputs the upper half of the input voltage when switch S is closed. DmU and S DmU' are activated, and outputs the lower half of the input voltage when switch S is activated. DmL and S DmL' are activated. The last stage “M” is coupled to a multiplexer, which at least activates switch S. F1 , S F2 and S F3 features to connect the upper, middle, or lower output of the last capacitive divider to the load at the V Out -To connect nodes. The compensating capacitor C Eis coupled to the output of the last "M" unit cell to determine the voltages across each of the capacitors C DMU and C DML to compensate. With each additional unit cell, the number of intermediate voltage levels more than doubles: "2M-1" unit cells provide => F = 1, 3, 7, 15, ... intermediate levels. In the Fig. In the embodiment shown in Figure 5D, the capacitor voltages of the unit cells are self-balancing up to "M-1" and generally do not require an additional balancing capacitor. The switches S F0 and S F4 are used optionally to bypass the Fein-DAC 500D.

[0044] Fig. Figure 5E is a schematic diagram of a Fein-DAC 500E according to another embodiment. The Fein-DAC 500E has a plurality of unit cells 502E, 504E, 506E, 508E, each unit cell having a plurality of series-connected capacitor banks, each capacitor bank having one or more capacitors; and a pair of switches coupled to each capacitor in the DAC, a first capacitor bank “M” having series-connected capacitors, where “M” is an integer greater than one, and a last capacitor bank having a single capacitor.

[0045] A capacitor bank in the 502E unit cell has four C D1 -capacitors connected in series between V DDN and V SSN are switched and intermediate nodes 516E, 518E and 520E are located between the C D1-capacitors. The capacitor chain of the unit cell 502E also has a first set of series-connected switches S. D1U and S D1L about a first C D1 -capacitor switched, a second set of switches connected in series S D1U and S D1L is via a second C D1 -capacitor switched, a third set of switches connected in series S D1U and SD 1L is about a third C D1 -capacitor switched and a fourth set of switches connected in series S D1U and S D1L is about a fourth C D1 -Capacitor switched.

[0046] A capacitor bank of the unit cell 504E has three C D2 -capacitors connected in series between nodes 528E and 522E and intermediate nodes 524E and 526E between the C D2-capacitors. The capacitor chain of the unit cell 504E also has a first set of series-connected switches S. D2U and S D2L about a first C D2 -capacitor switched and a second set of switches connected in series S D2U and S D2L is via a second C D2 -capacitor switched, a third set of switches connected in series S D2U and S D2L is about a third C D2 -Capacitor switched.

[0047] A capacitor bank of the unit cell 506E has two C Dm -capacitors connected in series between nodes 530E and 534E and intermediate node 532E between the C Dm -capacitors. The capacitor chain of the unit cell 506E also has a first set of series-connected switches S. DmU and S DmL about a first C D2-capacitor switched and a second set of switches connected in series S DmU and S DmL is via a second C D2 -capacitor connected. A capacitor chain of unit cell 508E has a single C DM -Capacitor connected between nodes 538E and 536E. A set of series-connected switches S DMU and S DML is over the C DM -capacitor switched. The transition between the S DMU - and S DML -switches is the V Out -node. The number of capacitors in each successive unit cell between the first capacitor string in unit cell 502E and the last capacitor string of unit cell 508E decreases by one capacitor. In the embodiment of Fig. Therefore, in 5E, the series-connected capacitor banks in each unit cell decrease from four capacitors to three capacitors, to two capacitors, and then to a single capacitor. In other embodiments, different numbers of unit cells can be used to represent different numbers of microvoltage levels at the V. Out -provide an output node.

[0048] It is in operation when switch S DmU is activated, switch S DmL deactivated and vice versa, and the successive stage is coupled to the upper or lower capacitors of the previous capacitor chain. With each additional chain of capacitors and switch pairs (unit cell), the number of voltage levels increases by one (F = M-1). In the Fein-DAC 500E from Fig. 5E: The capacitor voltages are self-balancing. All capacitors have the same voltage = (V DDN -V SSN) / M, where "M" = the number of unit cells. Each unit cell (except the last unit cell) can shift the successive unit cells up or down by one voltage level, and by adjusting the shift of each unit cell, the output voltage VOut takes on one of the "N" voltage levels between V DDN and V SSN to.

[0049] Fig. Figure 5F is a schematic diagram of a Fein-DAC 500F according to another embodiment. The Fein-DAC 500F has a plurality of unit cells 502F, 504F, 506F, and 508F. In one embodiment, each of the unit cells has a capacitor and a half-switch coupled to the capacitor, the half-switch being configured to selectively couple one unit cell to the next unit cell of the plurality of unit cells.

[0050] Thus, the 502F unit cell has a capacitor C. FlyDACon, which is coupled with a half-bridge, the switches S D1U (upper switch) and switch S D1L (lower switch). The 504F unit cell has a capacitor C. D1 on, which is coupled with a half-bridge, the switches S D2U and switch S D2L The 506F unit cell has a capacitor C. Dm on, which is coupled with a half-bridge, the switches S DmU and switch S DmL The 508F unit cell has a capacitor C. DM on, which is coupled to a half-bridge switch, the switch S DMU and switch S DML exhibits. The transition between the switches in the 508F unit cell is linked to the output voltage node V. Out coupled. While in Fig. Since Figure 5F shows four unit cells, it will be obvious to those skilled in the field that a different number of unit cells can be used in different embodiments. Fig. 5F is the CFlyDAC flying capacitor shown as part of a Fein-DAC 500F and not specifically shown as separate from the Fein-DAC, as is the case, for example, in Fig. 1 and in Fig. 3 is shown.

[0051] In operation, the Fein-DAC 500F implements a Fein-DAC 500F based on a flying capacitor multilevel inverter (FCMLI) or a capacitor-clamped multilevel inverter. The Fein-DAC 500F is a chain of switch pairs with capacitors between the pairs, where "M" stages of unit cells implement a weighted sum of a stage-size scaled input voltage difference. Each unit cell is defined by the half-bridge in each unit cell, which connects the two switches S DmU and S DmL exhibits, on a proportion of the input voltage m*(V DDN -V SSN ) / M charged. The half-bridge couples either the upper or lower capacitor pin and the potential to the next successive unit cell. By setting the circuit pattern, different capacitors are configured to be floating or in series, thus diverting the capacitor voltages from the V DDN- or V SSN Voltage can be ignored, added, or subtracted. For each additional switch pair and capacitor (unit cell), the number of fine-tuning DAC voltage levels increases by one (= M-1). In some embodiments, capacitor voltages are actively balanced by switching between redundant switch configurations, thus charging and discharging the capacitors.

[0052] The scope of application of the load driver circuit described here can be extended by additional system aspects, as shown in an exemplary embodiment. Fig. Figure 6 is a schematic diagram of a System 600 with a load driver circuit, such as the one in Fig. 3 shown load driver circuit 300, as well as additional system circuits, which are described in more detail below.

[0053] The relevant part of the system 600 comprises a load driver circuit of the type described above, which includes a series-parallel charge pump, capacitor and switching cells 608 and 610, a flying capacitor CN, a pre-charge circuit 620, and a capacitor and switch assembly 622, which are shown within the LV cell, C-fine DAC, and sensing circuit block 624. The system 600 also shows a capacitive load 626, which includes a MEMS device C. MEMS System 600 can exhibit a load that is controlled by the load driver circuit. System 602 also shows a voltage input source 602. Other types of loads can also be included in the system shown. Fig. The 600 system shown can be used.

[0054] The system 600 optionally includes a subregulator circuit 606 for subregulating the input voltage provided by the voltage input source 602. In some embodiments, the subregulator circuit 606 comprises a "gearbox" charge pump (which includes a so-called "gearbox" that combines two or more different converter topologies in conjunction with a topology switching scheme), an inductive buck-boost converter, a low-dropout (LDO) voltage converter, a DC-DC converter, or any other suitable voltage converter. Subregulating the input voltage with the subregulator circuit 606 advantageously allows the use of low-voltage components in the load driver circuit with a lower drain-to-source "on" resistance (RDS(on)). DSon ) and a lower switching power (P SWThe sub-regulator circuit 606 also allows the use of more series-parallel charge pump stages, resulting in lower current consumption due to smaller coarse stages and therefore more stages to achieve the same output voltage, and reduced appropriate supply variation. In some embodiments, the supply current can be indirectly measured by measuring the current supplied by the series-parallel charge pump (SP-CP or RP-CP).

[0055] The System 600 optionally includes a cross-circuit consisting of a low-power charging pump 604, a resistance divider R3 and R4, and a switch S. PW / Rup as well as a bias capacitor C biasThe crossover circuit provides independent adjustment of the quasi-static MEMS actuator bias and the activation of the AC excitation. It exhibits low quiescent current consumption because only a static high voltage needs to be supplied to the voltage divider R3 and R4, and the low-power charge pump 604 can have a high output resistance. The crossover enables power-efficient AC modulation of the series-parallel charge pump around the battery level. Advantageously, the crossover circuit regulates the MEMS bias for maximum sensitivity, for example, during playback with a lower Isb (least significant bit) level, resulting in higher MEMS sensitivity (~+5 dB) compared to omitting the crossover circuit.

[0056] In some embodiments, System 600 also includes an optional sensing circuit. Potential-free supplies power an integrated low-voltage sensing circuit in parallel with the RK fine DAC (shown in block 624) for the direct acquisition of small signals without a high-voltage switch, using a low-voltage circuit of flying capacitors referenced to parallel-series charge pump levels. The output voltage (at node V) SENS The signal is acquired by an amplifier 616 and an ADC 612, and by an amplifier 618 and an ADC 614. The acquisition branch, which includes the amplifier 618 and the ADC 614, can have an optional switch S. SENSE The detected driver output voltage and / or current is used to control the driver operation. The output voltage is further measured by an amplifier 628 and an ADC 630 through a capacitive (C1 and C2) and a resistive (R1 and R2) divider.

[0057] Fig. Figure 7 is a block diagram of a load driver circuit 700 according to another embodiment. The driver circuit has a plurality of series-connected macrocells (706A / 712A, 706B / 712B), each macrocell having a plurality of boost converter cells (implemented in the RP charge pump 706A or the RP charge pump 706B) for generating a plurality of coarse signal steps; and a plurality of buck converter cells (implemented in the fine DAC 712A or the fine DAC 712B) for generating a plurality of fine signal steps by dividing each of the coarse signal steps. Each macrocell also has a flying capacitor C. FlyDACa capacitor, CFlyDAC, is connected between the RP charge pump and the fine DAC. A first flying capacitor CFlyDAC is connected between node 708A and node 710A (VP and VN). A second flying capacitor CFlyDAC is connected between node 708B and node 710B (VP'' and VN''). The term "step-up" is used because the V In -Input voltage is "stepped up" to a maximum voltage that is greater than the V In -Voltage at the V P - and V N -node. The term "downward conversion" is used because the tension at the V DDN - and V SSN -node voltage is "stepped down" to an output voltage that is smaller than the differential voltage across the V P - and V N -node is.

[0058] The load driver circuit 700 also includes an optional DC / DC converter 702, which is connected to node 704, a C Bias-capacitor connected between the VCP node and the VL node (node ​​714), a quasi-static charge pump 716 connected between node 704 and the V Bias -node is switched, and a bias resistor R Bias , which is between the V Bias -Node and node 714 are connected. A load 718 is coupled to the VL node (node ​​714). The load 718 can be a MEMS component such as a loudspeaker, an actuator, a sensor, a capacitive load, or any other suitable load. These additional components were described previously.

[0059] Both RP charge pumps 706A and 707B have two inputs and two outputs and have been described previously. The Fein-DAC 712B has two inputs and only one output, which has also been described previously. However, the Fein-DAC 712A has two inputs and two outputs, which has not been described previously. While the Fein-DAC 712A is similar to a previously described Fein-DAC, it has a different output switch topology, which is shown below in relation to the schematic diagram of Fig. 8 is described. If more than two macrocells are used, all fine DAC circuits, except for the fine DAC in a last macrocell, have the circuit as described in Fig. 8 is shown.

[0060] Fig. Figure 8 is a schematic diagram of a Fein-DAC 800 according to another embodiment, in particular with two inputs (V DDN - and V SSN-node) and two outputs (VP'' and VN'' nodes). The Fein-DAC 800 thus has capacitors C D1U and C D1L and switch S D1U , SD1L, S D2U and S D2L up, which between the V DDN - and V SSN -Node and nodes 802 and 804 are connected. The Fein-DAC 800 has capacitors C DmU and C DmL and switch S DmU , S DmL , S DmU' and S DmL' on, which are connected between nodes 802 and 804 and nodes 806 and 808. The Fein-DAC 800 also has capacitors C DMU , C DML and C E and switch S DMU , S DML , S DMU' , and S DML on, which are connected between nodes 806 and 810. These components were all described below with reference to the in Fig. The Fein-DAC 500D shown in Figure 5D is described. However, the Fein-DAC 800 has additional switches S. F0, S F1 , S F2 , SF3 , and S F4 to connect the VSSN node, node 810, node 808, node 806, or VDDN node to node VP''. The Fein-DAC 800 has additional switches S F5 , S F6 , S F7 , S F8 , and S F9 up to the V SSN -node, node 810, node 808, node 806 or V DDN -node with node V N '' to connect.

[0061] In some embodiments, the timing and DAC stages of the load driver circuit and the timing control are controlled directly or indirectly by a delta-sigma modulator or a register setting. The control signals of the switches described above can also be controlled by an external or integrated controller.

[0062] In some embodiments, the load may be a capacitive MEMS load, for example a mobile phone speaker, or a MEMS may be used to generate a static pressure, gas flow or pressure modulation as sound waves, infrared or ultrasonic waves.

[0063] Exemplary embodiments of the present invention are summarized here. Other exemplary embodiments can also be understood from the entirety of the description and the claims filed herein.

[0064] Example 1. According to one embodiment, a driver circuit comprises a series-parallel charge pump having a plurality of switched capacitor cells, wherein the series-parallel charge pump is configured to generate a plurality of coarse signal steps at a first output node and a second output node; a flying capacitor, capacitor array, or storage element connected between the first output node and the second output node; and a digital-to-analog converter (DAC) connected between the first output node and the second output node, comprising a plurality of switched capacitors configured to generate a plurality of fine signal steps.

[0065] Example 2. The driver circuit according to Example 1, wherein the series-parallel charge pump is a bipolar series-parallel charge pump.

[0066] Example 3. The driver circuit according to one of the above examples, further comprising a bias capacitor coupled to an output of the DAC and a load coupled to the bias capacitor.

[0067] Example 4. The driver circuit according to one of the above examples, further comprising a quasi-static bias charge pump with an input coupled to an input of the series-parallel charge pump; and a bias resistor connected between an output of the quasi-static bias charge pump and a junction between the bias capacitor and the load.

[0068] Example 5. The driver circuit according to one of the above examples, which further includes a DC-DC converter coupled to an input of the series-parallel charge pump.

[0069] Example 6. The driver circuit according to one of the above examples, wherein the DAC has a first capacitor connected between the first output node and a first intermediate node; a second capacitor connected between the second output node and a second intermediate node; and a decoder coupled to the first output node, the second output node, the first intermediate node, and the second intermediate node.

[0070] Example 7. The driver circuit according to one of the above examples, wherein the decoder has a one-hot decoder.

[0071] Example 8. The driver circuit according to one of the above examples, wherein the DAC has an energy storage capacitor arrangement configured to provide a plurality of intermediate voltages between a first output node voltage and a second output node voltage; and a switching arrangement configured to selectively couple the plurality of intermediate voltages to an output of the DAC.

[0072] Example 9. The driver circuit according to one of the above examples, further comprising a refresh and initialization circuit coupled to the first output node and the second output node, and coupled to the energy storage capacitor arrangement.

[0073] Example 10. The driver circuit according to one of the above examples, wherein the DAC has a combined energy storage and capacitive divider arrangement configured to provide a plurality of intermediate voltages between a first output node voltage and a second output node voltage; and a switching arrangement configured to selectively couple the plurality of intermediate voltages to an output of the DAC.

[0074] Example 11. The driver circuit according to one of the above examples, further comprising a refresh and initialization circuit coupled to the combined energy storage and capacitive divider arrangement.

[0075] Example 12. The driver circuit according to one of the above examples, wherein the DAC comprises a plurality of unit cells connected in series, configured to implement a binary weighted sum of shifted input voltage components, each unit cell having a pair of capacitors connected in series and two pairs of switches coupled to the pair of capacitors connected in series; and a multiplexer coupled to at least one of the unit cells.

[0076] Example 13. The driver circuit according to one of the above examples, further comprising an additional capacitor coupled to a final unit cell in the plurality of unit cells connected in series.

[0077] Example 14. The driver circuit according to one of the examples above, wherein the DAC has a plurality of unit cells, each unit cell having a plurality of series-connected capacitor banks, each capacitor bank having one or more capacitors; and a pair of switches coupled to each capacitor in the DAC, wherein a first capacitor bank 'M' has series-connected capacitors, where 'M' is an integer greater than one, and a last capacitor bank has a single capacitor.

[0078] Example 15. The driver circuit according to one of the above examples, wherein the number of capacitors in each successive unit cell between the first capacitor chain and the last capacitor chain decreases by one capacitor.

[0079] Example 16. The driver circuit according to one of the above examples, wherein the DAC has a plurality of unit cells, and wherein at least one of the plurality of unit cells has a capacitor; and has a half-bridge switch coupled to the capacitor, wherein the half-bridge switch is configured to selectively couple the at least one of the plurality of unit cells to a nearest unit cell of the plurality of unit cells.

[0080] Example 17. The driver circuit according to one of the above examples, further comprising an additional half-bridge switch connected between the flying capacitor and a first unit cell of the plurality of unit cells.

[0081] Example 18. According to one embodiment, a driver circuit comprises a series-parallel charge pump configured to generate a plurality of coarse signal steps; a digital-to-analog converter (DAC) coupled to the series-parallel charge pump and comprising a plurality of switched capacitors; and a flying capacitor connected between the series-parallel charge pump and the DAC, wherein the DAC is configured to generate a plurality of fine signal steps and to charge the plurality of switched capacitors only when a load is coupled to the driver circuit.

[0082] Example 19. According to one embodiment, a driver circuit comprises a plurality of series-connected macrocells, each macrocell having a plurality of boost cells for generating a plurality of coarse signal steps; and a plurality of buck cells for generating a plurality of fine signal steps by dividing each of the coarse signal steps.

[0083] Example 20. The driver circuit of Example 19, further comprising a load coupled to the plurality of buck converter cells, wherein the load comprises a MEMS device, an actuator, a sensor or a capacitive load.

[0084] Although this invention has been described with reference to illustrative embodiments, this description is not intended to be restrictive. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be obvious to those skilled in the art with reference to the description. It is therefore intended that the appended claims include such modifications or embodiments.

Claims

[1] Driver circuit which has the following features: a series-parallel charge pump comprising a plurality of switched capacitor cells, wherein the series-parallel charge pump is configured to generate a plurality of coarse signal steps at a first output node and a second output node; a flying capacitor, a capacitor array, or a storage element connected between the first output node and the second output node; and a digital-to-analog converter (DAC) that is connected between the first output node and the second output node and has a plurality of switched capacitors configured to generate a plurality of fine signal steps. [2] Driver circuit according to claim 1, wherein the series-parallel charge pump comprises a bipolar series-parallel charge pump. [3] Driver circuit according to claim 1 or 2, further comprising a bias capacitor coupled to an output of the DAC and a load coupled to the bias capacitor. [4] Driver circuit according to claim 3, further comprising: a quasi-static bias charge pump with an input coupled to an input of the series-parallel charge pump; and a bias resistor that is connected between an output of the static bias charge pump and a junction between the bias capacitor and the load. [5] Driver circuit according to one of claims 1 to 4, which further comprises a DC-DC converter coupled to an input of the series-parallel charge pump. [6] Driver circuit according to any one of claims 1 to 5, wherein the DAC comprises: a capacitor connected between the first output node and a first intermediate node; a decoder that is coupled to the first output node and the first intermediate node. [7] Driver circuit according to claim 6, wherein the decoder comprises a one-hot decoder. [8] Driver circuit according to any one of claims 1 to 7, wherein the DAC comprises: an energy storage capacitor arrangement configured to provide a plurality of intermediate voltages between a first output node voltage and a second output node voltage; and a switch arrangement configured to selectively couple the majority of intermediate voltages to one output of the DAC. [9] Driver circuit according to claim 8, further comprising a refresh and initialization circuit coupled to the first output node and the second output node and coupled to the energy storage capacitor arrangement. [10] Driver circuit according to any one of claims 1 to 7, wherein the DAC comprises: a combined energy storage and capacitive divider arrangement configured to provide a plurality of intermediate voltages between a first output node voltage and a second output node voltage; and a switch arrangement configured to selectively couple the majority of intermediate voltages to one output of the DAC. [11] Driver circuit according to claim 10, further comprising a refresh and initialization circuit coupled to the combined energy storage and capacitive divider arrangement. [12] Driver circuit according to any one of claims 1 to 11, wherein the DAC comprises: a plurality of unit cells connected in series, configured to implement a binary weighted sum of shifted input voltage components, each unit cell comprising a pair of series-connected capacitors and two pairs of switches coupled to the pair of series-connected capacitors; and a multiplexer that is coupled to at least one of the unit cells. [13] Driver circuit according to claim 12, further comprising an additional capacitor coupled to a last unit cell in the plurality of unit cells connected in series. [14] Driver circuit according to any one of claims 1 to 13, wherein the DAC has a plurality of unit cells, each unit cell having: a plurality of capacitor strings connected in series, each capacitor string comprising one or more capacitors; and a pair of switches coupled to each capacitor in the DAC, wherein a first capacitor chain “M” has capacitors connected in series, where “M” is an integer greater than one, and a final capacitor chain has a single capacitor. [15] Driver circuit according to claim 14, wherein the number of capacitors in each successive unit cell between the first capacitor chain and the last capacitor chain decreases by one capacitor. [16] Driver circuit according to any one of claims 1 to 15, wherein the DAC has a plurality of unit cells, and wherein at least one of the plurality of unit cells has the following: a capacitor; and a half-bridge switch coupled to the capacitor, wherein the half-bridge switch is configured to selectively couple at least one of the plurality of unit cells with a next unit cell of the plurality of unit cells. [17] Driver circuit according to claim 16, further comprising an additional half-bridge switch connected between the flying capacitor and a first unit cell of the plurality of unit cells. [18] Driver circuit which has the following features: a series-parallel charge pump configured to generate a plurality of coarse signal steps; a digital-to-analog converter (DAC) coupled to the series-parallel charge pump and comprising a plurality of switched capacitors; and a flying capacitor connected between the series-parallel charging pump and the DAC, where the DAC is configured to generate a plurality of fine signal steps and to charge the plurality of switched capacitors only when a load is coupled to the driver circuit. [19] Driver circuit which has the following features: a plurality of macrocells connected in series, each macrocell having the following features: a plurality of upconverter cells to generate a plurality of coarse signal steps; and a plurality of step-down converter cells to generate a plurality of fine signal steps by dividing each of the coarse signal steps. [20] Driver circuit according to claim 19, further comprising a load coupled to the plurality of step-down converter cells, wherein the load comprises a MEMS device, an actuator, a sensor or a capacitive load.

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