Semiconductor device and method for manufacturing a semiconductor device

Abstract

A semiconductor device has a plurality of trenches (51, 52) formed on a first main surface of a semiconductor substrate, and insulating layers (11b, 12b, 21b, 72b) and electrodes (11a, 12a, 21a, 72a) formed in the plurality of trenches (51, 52). The plurality of trenches (51, 52) has a first trench (51) and a second trench (52), which is deeper and wider than the first trench (51). A bottom layer (60) of a second conductivity type, which is in contact with a bottom of the second trench (52) but not in contact with the first trench (51), is arranged below the second trench (52).

Description

Background Technical field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. Description of the state of the art

[0002] A trench-gate semiconductor device is known which has a structure in which a gate electrode is embedded in a trench. For example, Japanese patent application no. 2016-225566 discloses below a configuration in which a bottom layer (also referred to as a "BP layer"), which is a p-type semiconductor layer, is applied to the bottom of a trench of a gate electrode in a trench-gate IGBT. The BP layer has an effect on relaxing the electric field at the bottom of the trench to prevent semiconductor avalanche formation, in particular a transient avalanche formation phenomenon at the time of interruption after energization, which is called dynamic avalanche formation.

[0003] Increasing the depth (thickness) of the bonding layer (BP) enhances the electric field relaxation effect, thus allowing the BP layer to be built to a certain depth. However, the BP layer also widens laterally as it becomes deeper, and if the BP layer becomes too deep, it will block the gap between adjacent trenches, rendering the semiconductor device inoperable. Therefore, it is necessary to design the BP layer depth within a range where the gap between adjacent trenches is not blocked by the BP layer, and ensuring sufficient BP layer depth can sometimes be challenging. Summary

[0004] It is an object of the present disclosure to provide a semiconductor device which is capable of forming a deep soil layer while preventing the soil layer from blocking a gap between adjacent trenches.

[0005] A semiconductor device according to the present disclosure comprises: a semiconductor substrate with a drift layer of a first conductivity type between a first principal surface and a second principal surface opposite the first principal surface; a plurality of trenches formed on the first principal surface of the semiconductor substrate; an insulating layer formed on an inner surface of the plurality of trenches; and an electrode embedded in each of the plurality of trenches by the insulating layer. The plurality of trenches includes a first trench and a second trench, which is deeper and wider than the first trench. A bottom layer of a second conductivity type, which is in contact with the bottom of the second trench but not with the first trench, is formed below the second trench.

[0006] According to the semiconductor device of the present disclosure, it is possible to form the soil layer deep while preventing the soil layer from blocking the gap between adjacent trenches.

[0007] These and other tasks, features, aspects and advantages of the present revelation will become clearer based on the following detailed description of the present revelation in conjunction with the accompanying figures. Brief description of the characters Fig. Figure 1 is a top view illustrating a configuration example of a chip of a semiconductor device according to a first preferred embodiment; Fig. Figure 2 is a top view illustrating a configuration example of the chip of the semiconductor device according to the first preferred embodiment; Fig. Figure 3 is a top view illustrating a configuration example of the chip of the semiconductor device according to the first preferred embodiment; Fig. Figure 4 is a top view illustrating an example of the structure of an IGBT region; Fig. Figure 5 is a cross-sectional view illustrating an example of the structure of the IGBT region; Fig. Figure 6 is a cross-sectional view illustrating an example of the structure of the IGBT region; Fig. Figure 7 is a top view illustrating the structure of the IGBT region of the semiconductor device according to the first preferred embodiment; Fig. Figure 8 is a cross-sectional view illustrating the structure of the IGBT region of the semiconductor device according to the first preferred embodiment; Fig. Figure 9 is a cross-sectional view illustrating the structure of the IGBT region of the semiconductor device according to the first preferred embodiment; Fig. Figure 10 is a top view illustrating an example of the structure of a diode region; Fig. Figure 11 is a cross-sectional view illustrating an example of the structure of the diode region; Fig. Figure 12 is a cross-sectional view illustrating an example of the structure of the diode region; Fig. Figure 13 is a top view illustrating the structure of the diode region of the semiconductor device according to the first preferred embodiment; Fig. Figure 14 is a cross-sectional view illustrating the structure of the diode region of the semiconductor device according to the first preferred embodiment; Fig. Figure 15 is a cross-sectional view illustrating the structure of the diode region of the semiconductor device according to the first preferred embodiment; Fig. Figure 16 is a cross-sectional view illustrating an example of the structure of a boundary between the IGBT region and the diode region; Fig. Figure 17 is a cross-sectional view illustrating an example of the structure of a termination region; Fig. Figure 18 is a cross-sectional view illustrating an example of the structure of the termination region; Fig. Figure 19 is a cross-sectional view illustrating an example of the structure of the termination region; Fig. Figure 20 is a cross-sectional view illustrating an example of the structure of the termination region; Fig. Figure 21 is a cross-sectional view illustrating the structure of the termination region of the semiconductor device according to the first preferred embodiment; Fig. Figure 22 is a cross-sectional view illustrating the structure of the termination region of the semiconductor device according to the first preferred embodiment; Fig. Figure 23 is a view illustrating an example of a process for manufacturing an RC-IGBT; Fig. Figure 24 is a view illustrating an example of the process for manufacturing an RC-IGBT; Fig. Figure 25 is a view illustrating an example of the process for manufacturing an RC-IGBT; Fig. Figure 26 is a view illustrating an example of the process for manufacturing an RC-IGBT; Fig. Figure 27 is a view illustrating an example of the process for manufacturing an RC-IGBT; Fig. Figure 28 is a view illustrating an example of the process for manufacturing an RC-IGBT; Fig. Figure 29 is a view illustrating an example of the process for manufacturing an RC-IGBT; Fig. Figure 30 is a view illustrating an example of the process for manufacturing an RC-IGBT; Fig. Figure 31 is a view illustrating an example of the process for manufacturing an RC-IGBT; Fig. Figure 32 is a view illustrating an example of the process for manufacturing an RC-IGBT; Fig. Figure 33 is a view illustrating an example of the process for manufacturing an RC-IGBT; Fig. Figure 34 is a view illustrating an example of the process for manufacturing an RC-IGBT; Fig. 35 is a view illustrating a method for manufacturing the semiconductor device according to the first preferred embodiment; and Fig. Figure 36 is a view illustrating the method for manufacturing the semiconductor device according to the first preferred embodiment. Description of preferred embodiments

[0008] In the following description, an n-type and a p-type represent a conductivity type of a semiconductor, and in the present disclosure, a first conductivity type is described as the n-type and a second conductivity type is described as the p-type. However, the first conductivity type may be the p-type and the second conductivity type may be the n-type. Furthermore, n denotes - , that a defect concentration is lower than n, and n +This indicates that the impurity concentration is higher than n. Similarly, p indicates that... - , that the impurity concentration is lower than p, and p + indicates that the impurity concentration is higher than p.

[0009] Furthermore, the level of the defect concentration in each region is defined by a peak concentration. That is, a region with a high (or low) defect concentration corresponds to a region with a high (or low) peak defect concentration. <Erste bevorzugte Ausführungsform>

[0010] A configuration of a semiconductor device according to a first preferred embodiment is described below. The semiconductor element included in the semiconductor device is assumed to be a trench-gate type semiconductor element, for example a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), a reverse-conducting IGBT (RC-IGBT), or the like.

[0011] The semiconductor element material can be silicon (Si) or a wide-bandgap semiconductor such as silicon carbide (SiC). Semiconductor devices constructed using wide-bandgap semiconductors exhibit superior performance at high voltage, high current, and high temperature compared to semiconductor devices using silicon. Examples of wide-bandgap semiconductors include gallium nitride (Gan)-based materials and diamond, in addition to silicon carbide.

[0012] The Fig. 1, Fig. 2 to Fig. Figure 3 are views illustrating examples of a chip of a planar structure of the semiconductor device according to the first preferred embodiment. Fig. Figure 1 is a top view illustrating a semiconductor device that is an IGBT. Fig. Figure 2 is a top view illustrating a semiconductor device that is an RC-IGBT. Fig. Figure 3 is a top view illustrating a semiconductor device that is an RC-IGBT with a different configuration.

[0013] A provided RC-IGBT, which has a Fig. The semiconductor device 100 illustrated in Figure 2 has an IGBT region 10 and a diode region 20, which are provided side by side in a strip form, and it can also simply be referred to as a "strip type". An RC-IGBT, which includes the Fig. The semiconductor device 100 illustrated in Figure 3 has a plurality of diode regions 20 which are provided in the longitudinal and lateral directions, and the IGBT region 10 is provided around the diode regions 20, and it can also simply be referred to as an "island type". (1) General planar structure of the IGBT

[0014] In Fig. Figure 1 shows that the semiconductor device 100 has an IGBT region 10. A pad region 40 is also provided adjacent to the lower side of the IGBT region 10. The pad region 40 contains a control pad 41, which controls the semiconductor device 100. The IGBT region 10 is also referred to as the cell region. A termination region 30 is provided around a combined region of the cell region and the pad region 40 to maintain a voltage hold-up of the semiconductor device 100. A known voltage hold-up structure can be selected appropriately and provided in the termination region 30.For example, the voltage withstand structure can be designed by providing a field limiting ring (FLR) surrounding a combined region of the cell region and the pad region 40 by means of a p-type termination well layer of a p-type semiconductor, or by providing a variation of lateral doping (VLD) surrounding a combined region of the cell region and the pad region 40 by means of a p-type termination well layer in which a concentration gradient is provided on one side of a first principal surface, which is one side of a front surface of the semiconductor device 100, and the number of annular p-type termination well layers used for the FLR and a concentration distribution used for the VLD can be selected appropriately in accordance with the voltage withstand design of the semiconductor device 100.Furthermore, the p-type termination tray layer can be provided over essentially the entire pad region 40, and an IGBT cell can be provided in pad region 40.

[0015] For example, the control pad 41 can be a current-sensing pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, and temperature-sensing diode pads 41d, 41e. The current-sensing pad 41a is the control pad for detecting the current flowing through the cell region of the semiconductor device 100, and it is the control pad that is electrically connected to IGBT cells or diode cells in a part of the cell region such that when the current flows through the cell region of the semiconductor device 100, some fractions up to some ten-thousandths of the current flowing through the entire cell region are detected.

[0016] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate driver voltage is applied to activate and deactivate the semiconductor device 100. The Kelvin emitter pad 41b is electrically connected to the p-type base layer and an n + The Kelvin emitter pad 41b of the IGBT cell is connected to the Kelvin emitter layer, and the gate pad 41c is electrically connected to the gate-trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer can be electrically connected by a p-type electrode. + -type contact layer connected. The temperature sensing diode pads 41d, 41e are control pads which are electrically connected to an anode and a cathode of a temperature sensing diode provided in the semiconductor device 100. The voltage between the anode and the cathode of the temperature sensing diode (not illustrated), which is provided in the cell region, is measured to measure the temperature of the semiconductor device 100. (2) General planar structure of strip-type RC-IGBT

[0017] In Fig. Figure 2 describes the semiconductor device 100 as comprising the IGBT region 10 and the diode region 20. The IGBT region 10 and the diode region 20 extend from one end face to the other end face of the semiconductor device 100 and are provided alternately in a stripe form in a direction orthogonal to an extension direction of the IGBT region 10 and the diode region 20. Fig. Figure 2 illustrates three IGBT regions 10 and two diode regions 20, with all diode regions 20 enclosed between the IGBT regions 10. However, the number of IGBT regions 10 and the number of diode regions 20 are not limited here, and the number of IGBT regions 10 can be equal to or greater than three and equal to or less than three, and the number of diode regions 20 can be equal to or greater than two or equal to or less than two. Furthermore, locations of the IGBT region 10 and the diode region 20 can be in Fig. The IGBT regions 10 and diode regions 20 can be swapped, or all of them can be enclosed between the diode regions 20. Furthermore, the IGBT region 10 and the diode region 20 can be arranged adjacent to each other, one after the other.

[0018] As in Fig. As illustrated in Figure 2, pad region 40 is provided adjacent to the lower side of the IGBT region 10. Pad region 40 is a region in which a control pad 41 is provided, which controls the semiconductor device 100. The IGBT region 10 and the diode region 20 are also collectively referred to as the cell region. A termination region 30 is provided around a combined region of the cell region and pad region 40 to maintain a standby voltage of the semiconductor device 100. A known standby voltage retention structure can be selected appropriately and provided in the termination region 30.For example, the voltage withstand structure can be designed by providing a field limiting ring (FLR) surrounding a combined region of the cell region and the pad region 40 by means of a p-type termination well layer of a p-type semiconductor, or by providing a variation of lateral doping (VLD) surrounding a combined region of the cell region and the pad region 40 by means of a p-type termination well layer in which a concentration gradient is provided on one side of a first principal surface, which is one side of a front surface of the semiconductor device 100, and the number of annular p-type termination well layers used for the FLR and a concentration distribution used for the VLD can be selected appropriately in accordance with the voltage withstand design of the semiconductor device 100.In addition, the p-type termination tray layer can be provided over essentially the entire pad region 40, and an IGBT cell and a diode cell can be provided in pad region 40.

[0019] For example, the control pad 41 can be the current sensing pad 41a, the Kelvin emitter pad 41b, the gate pad 41c, and the temperature sensing diode pads 41d, 41e. The current sensing pad 41a is the control pad for detecting the current flowing through the cell region of the semiconductor device 100, and it is the control pad that is electrically connected to IGBT cells or diode cells in a part of the cell region such that when the current flows through the cell region of the semiconductor device 100, some fractions up to some ten-thousandths of the current flowing through the entire cell region are detected.

[0020] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate driver voltage is applied to activate and deactivate the semiconductor device 100. The Kelvin emitter pad 41b is electrically connected to the p-type base layer and an n + The Kelvin emitter pad 41b of the IGBT cell is connected to the Kelvin emitter layer, and the gate pad 41c is electrically connected to the gate-trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer can be electrically connected by a p-type electrode. + -type contact layer connected. The temperature sensing diode pads 41d, 41e are control pads which are electrically connected to an anode and a cathode of a temperature sensing diode provided in the semiconductor device 100. The voltage between the anode and the cathode of the temperature sensing diode (not illustrated), which is provided in the cell region, is measured to measure the temperature of the semiconductor device 100. (3) General planar structure of the island type

[0021] In Fig. Figure 3 shows that the semiconductor device 100 comprises the IGBT region 10 and the diode region 20 within a semiconductor device. A plurality of diode regions 20 are arranged side-by-side in the longitudinal and lateral directions within the semiconductor device, and the diode region 20 is surrounded by the IGBT region 10. That is, the plurality of diode regions 20 are arranged in an island configuration within the IGBT region 10. Fig. In Figure 3, the diode regions 20 are provided in a matrix of four columns in a horizontal direction and two rows in the direction of an upper boundary in the drawing. However, the number and arrangement of the diode regions 20 are not limited to this, and one or a multitude of diode regions 20 can be provided in the IGBT region 10 in a mixed manner, and each of the diode regions 20 can be surrounded by the IGBT region 10.

[0022] As in Fig. As illustrated in Figure 3, pad region 40 is provided adjacent to the lower side of the IGBT region 10. Pad region 40 is a region in which a control pad 41 is provided, which controls the semiconductor device 100. The IGBT region 10 and the diode region 20 are also collectively referred to as the cell region. A termination region 30 is provided around a combined region of the cell region and pad region 40 to maintain a standby voltage of the semiconductor device 100. A known standby voltage retention structure can be selected appropriately and provided in the termination region 30.For example, the voltage withstand structure can be designed by providing a field limiting ring (FLR) surrounding a combined region of the cell region and the pad region 40 by means of a p-type termination well layer of a p-type semiconductor, or by providing a variation of lateral doping (VLD) surrounding a combined region of the cell region and the pad region 40 by means of a p-type termination well layer in which a concentration gradient is provided on one side of a first principal surface, which is one side of a front surface of the semiconductor device 100, and the number of annular p-type termination well layers used for the FLR and a concentration distribution used for the VLD can be selected appropriately in accordance with the voltage withstand design of the semiconductor device 100.In addition, the p-type termination tray layer can be provided over essentially the entire pad region 40, and an IGBT cell and a diode cell can be provided in pad region 40.

[0023] For example, the control pad 41 can be the current sensing pad 41a, the Kelvin emitter pad 41b, the gate pad 41c, and the temperature sensing diode pads 41d, 41e. The current sensing pad 41a is the control pad for detecting the current flowing through the cell region of the semiconductor device 100, and it is the control pad that is electrically connected to IGBT cells or diode cells in a part of the cell region such that when the current flows through the cell region of the semiconductor device 100, some fractions up to some ten-thousandths of the current flowing through the entire cell region are detected.

[0024] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate driver voltage is applied to activate and deactivate the semiconductor device 100. The Kelvin emitter pad 41b is electrically connected to the p-type base layer and an n + The Kelvin emitter pad 41b of the IGBT cell is connected to the Kelvin emitter layer, and the gate pad 41c is electrically connected to the gate-trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer can be electrically connected by a p-type electrode. + -type contact layer connected. The temperature sensing diode pads 41d, 41e are control pads which are electrically connected to an anode and a cathode of a temperature sensing diode provided in the semiconductor device 100. The voltage between the anode and the cathode of the temperature sensing diode (not illustrated), which is provided in the cell region, is measured to measure the temperature of the semiconductor device 100. (4) Example of the structure of IGBT region 10

[0025] Fig. Figure 4 is a partially enlarged top view illustrating the configuration of an IGBT region in a semiconductor device, which is an RC-IGBT. Fig. 5 and Fig. Figure 6 shows cross-sectional views illustrating a configuration of the IGBT region of the semiconductor device, which is the RC-IGBT. Fig. Figure 4 is an enlarged view illustrating a region defined by a dashed line 82 in the Fig. 2 illustrated semiconductor device 100 or the one in Fig. 3 illustrated semiconductor device 100 is surrounded. Fig. 5 is a cross-sectional view, which is drawn along a dashed line AA of the in Fig. 4 illustrated semiconductor device 100 is taken from, and Fig. 6 is a cross-sectional view, which is drawn along a dashed line BB of the in Fig. 4 illustrated semiconductor device 100 is taken from.

[0026] As in Fig. As illustrated in Figure 4, an active trench gate 11 and a dummy trench gate 12 are provided in a strip shape in the IGBT region 10. In the strip-type RC-IGBT, the active trench gate 11 and the dummy trench gate 12 extend in a longitudinal direction of the IGBT region 10, and the longitudinal direction of the IGBT region 10 is a longitudinal direction of the active trench gate 11 and the dummy trench gate 12. In contrast, in the island-type RC-IGBT, there is no specific distinction between the longitudinal direction and a lateral direction in the IGBT region 10, but the lateral direction in the drawing can be the longitudinal direction of the active trench gate 11 and the dummy trench gate 12, and a vertical direction in the drawing can be the longitudinal direction of the active trench gate 11 and the dummy trench gate 12.

[0027] The active trench gate 11 is configured such that a gate trench electrode 11a is provided in a trench which is formed in the semiconductor substrate by a gate trench insulating layer 11b. The dummy trench gate 12 is configured such that a dummy trench electrode 12a is provided in the trench in the semiconductor substrate by a dummy trench insulating layer 12b. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode which is provided on a first main surface of the semiconductor device 100.

[0028] A + -Type emitter layer 13 is provided on both sides in a latitudinal direction of the active trench gate 11 such that it is in contact with the gate-trench insulating layer 11b. The n +-Type emitter layer 13 is a semiconductor layer which contains, for example, arsenic or phosphorus as an n-type defect, and the concentration of the n-type defect corresponds to 1.0E+17 / cm². 3 up to 1.0E+20 / cm 3 . The n + -Type emitter layer 13 and a p + -Type contact layer 14 are provided alternately along the extension direction of the active trench gate 11. The p + A type contact layer 14 is also provided between two adjacent dummy trench gates 12. The p + -Type contact layer 14 is a semiconductor layer which contains, for example, boron or aluminum as a p-type defect, and the concentration of the p-type defect corresponds to 1.0E+15 / cm². 3 up to 1.0E+20 / cm 3 .

[0029] As in Fig. As illustrated in Figure 4, in the IGBT region 10 of the semiconductor device 100, three dummy trench gates 12 are arranged next to three active trench gates 11, and three active trench gates 11 are arranged next to three dummy trench gates 12. The IGBT region 10 has a configuration in which one set of active trench gates 11 and one set of dummy trench gates 12 are arranged differently than described above. Fig. 4 is the number of active trench gates 11 contained in a set of active trench gates 11; three, but it can be equal to or greater than one. Furthermore, the number of dummy trench gates 12 contained in a set of dummy trench gates 12 can be equal to or greater than one, and the number of dummy trench gates 12 can be zero. That is, all trenches provided in IGBT region 10 can be used as the active trench gates 11.

[0030] Fig. Figure 5 is a cross-sectional view of the semiconductor device 100, which extends along the dashed line AA from Fig. Figure 4 is taken from the diagram, and it is a cross-sectional view of the IGBT region 10. The semiconductor device 100 has an n - -Type drift layer 1, which is formed from a semiconductor substrate. The n - -Type drift layer 1 is a semiconductor layer which, for example, contains arsenic or phosphorus as the n-type defect, and the concentration of the n-type defect corresponds to 1.0E+12 / cm². 3 up to 1.0E+15 / cm 3 In Fig. 5 the semiconductor substrate lies in an area of ​​the n + -Type emitter layer 13 and the p + -Type contact layer 14 up to a p-type collector layer 16. In Fig. 5 become the upper ends of the n + -Type emitter layer 13 and the p +The p-type contact layer 14 in the drawing is designated as a first principal surface of the semiconductor substrate, and a lower end of the p-type collector layer 16 in the drawing is designated as a second principal surface of the semiconductor substrate. The first principal surface of the semiconductor substrate is a principal surface on one side of a front face of the semiconductor device 100, and the second principal surface of the semiconductor substrate is a principal surface on a rear face of the semiconductor device 100. The semiconductor device 100 has the n - -Type drift layer 1 between the first main surface and the second main surface, which is opposite the first main surface, in the IGBT region 10, which is the cell region.

[0031] As in Fig. Figure 5 illustrates an n-type charge carrier storage layer 2 in IGBT region 10 with a higher n-type defect concentration than the n --Type Drift layer 1 on the side of the first main surface of the n - -Type drift layer 1 is provided. The n-type charge carrier storage layer 2 is a semiconductor layer which contains, for example, arsenic or phosphorus as the n-type defect, and the concentration of the n-type defect corresponds to 1.0 E+13 / cm². 3 up to 1.0E+17 / cm 3 It should be noted that the semiconductor device 100 may have a configuration in which the n-type charge carrier storage layer 2 is not provided and the n - -Type drift layer 1 is also provided in a region of the n-type charge carrier storage layer 2, which is located in Fig. Figure 5 illustrates this. Providing the n-type charge carrier storage layer 2 can reduce current loss when current flows in the IGBT region 10. The n-type charge carrier storage layer 2 and the n - -Type Drift Layer 1 can be collectively referred to as one Drift Layer.

[0032] The n-type charge carrier storage layer 2 is formed by ion implantation of the p-type dopant into the semiconductor substrate, which contains the n - -Type drift layer 1 is formed and subsequently diffused by the implanted dopant through a heat treatment of the semiconductor substrate, which the n - -Type Drift Layer 1 is.

[0033] A p-type base layer 15 is provided on the side of the first main surface of the n-type charge carrier storage layer 2. The p-type base layer 15 is a semiconductor layer which, for example, contains boron or aluminum as a p-type defect, and the concentration of the p-type defect corresponds to 1.0 E+12 / cm². 3 up to 1.0E+19 / cm 3 The p-type base layer 15 is in contact with the gate-trench insulation layer 11b of the active trench gate 11. On the side of the first main surface of the p-type base layer 15, the n +-Type emitter layer 13 provided, which is in contact with the gate-trench insulation layer 11b of the active trench gate 11, and the p + -Type contact layer 14 is provided in the remaining region. The n + -Type emitter layer 13 and the p + The -type contact layer 14 forms the first main surface of the semiconductor substrate. The p + -Type contact layer 14 is a region which has a higher concentration of defects than the p-type soil layer 15, and if it is necessary to remove the p + To distinguish between the -type contact layer 14 and the p-type base layer 15, they can be referred to individually, and the p + The -type contact layer 14 and the p-type base layer 15 can be referred to together as a p-type base layer.

[0034] In the semiconductor device 100, an n-type buffer layer 3 has a higher impurity concentration than the n --Type Drift layer 1 on the side of the second main surface of the n - The n-type drift layer 1 is provided. The n-type buffer layer 3 is provided to prevent the propagation of a depletion layer extending from the p-type base layer 15 to the side of the second main surface when the semiconductor device 100 is in an off state. The n-type buffer layer 3 can be provided, for example, by implanting the phosphorus (P) or the proton (H). + ) are formed, or by implanting both phosphorus (P) and proton (H). + The concentration of the n-type defect in the n-type buffer layer 3 corresponds to 1.0 E+12 / cm². 3 up to 1.0E+18 / cm 3 .

[0035] It should be noted that the semiconductor device 100 may have a configuration in which the n-type buffer layer 3 is not provided and the n --Type drift layer 1 is also provided in a region of the n-type buffer layer 3, which is in Fig. Figure 5 illustrates the n-type buffer layer 3 and the n - -Type Drift Layer 1 can be collectively referred to as one Drift Layer.

[0036] In the semiconductor device 100, the p-type collector layer 16 is provided on the side of the second main surface of the n-type buffer layer 3. That is, the p-type collector layer 16 is located between the n - The p-type drift layer 1 and the second main surface are provided. The p-type collector layer 16 is a semiconductor layer which, for example, contains boron or aluminum as the p-type defect, and the concentration of the p-type defect corresponds to 1.0 E+16 / cm². 3 up to 1.0E+20 / cm 3The p-type collector layer 16 forms the second main area of ​​the semiconductor substrate. The p-type collector layer 16 is provided not only in the IGBT region 10 but also in the termination region 30, and a portion of the p-type collector layer 16 is provided in the termination region 30, forming a p-type termination collector layer 16a. Furthermore, the p-type collector layer 16 can be provided such that it partially extends from the IGBT region 10 to the diode region 20.

[0037] As in Fig. Figure 5 illustrates trenches that penetrate the p-type base layer 15 starting from the first main surface of the semiconductor substrate and the n - -Type drift layer 1 is formed in the semiconductor device 100. The gate-trough electrode 11a is provided in the trench by the gate-trough insulating layer 11b to form the active trench gate 11. The gate-trough electrode 11a lies at the n- -Type drift layer 1 through the gate-trough insulating layer 11b opposite. The dummy-trough electrode 12a is provided in the trench through the dummy-trough insulating layer 12b to form the dummy-trough gate 12. The dummy-trough electrode 12a lies opposite the n - -Type drift layer 1 is opposite the dummy trench insulation layer 12b. The gate trench insulation layer 11b of the active trench gate 11 is in contact with the p-type base layer 15 and the n + -Type emitter layer 13. When the gate driver voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15, which is in contact with the gate trench insulating layer 11b of the active trench gate 11.

[0038] As in Fig. Figure 5 illustrates an interlayer insulating layer 4 provided on the gate-trench electrode 11a of the active trench gate 11. A barrier metal 5 is formed on the region of the first main surface of the semiconductor substrate where the interlayer insulating layer 4 is not provided and on the interlayer insulating layer 4. For example, the barrier metal 5 can be a conductor containing titanium (Ti), and it can be titanium nitride or TiSi, which is obtained by alloying titanium and silicon (Si). As shown in Fig. As illustrated in Figure 5, the barrier metal 5 is in ohmic contact with the n + -Type emitter layer 13, the p + -Type contact layer 14, and the dummy trench electrode 12a, and is electrically connected to the n + -Type emitter layer 13, the p +-Type contact layer 14, and the dummy trench electrode 12a are connected. An emitter electrode 6 is provided on the barrier metal 5. For example, the emitter electrode 6 can be formed from an aluminum alloy such as an aluminum-silicon alloy (Al-Si-based alloy), or it can be an electrode having multiple layers of metal, with a plating layer formed on an electrode made of an aluminum alloy by electroless plating or electrolytic plating. For example, the plating layer formed by electroless plating or electrolytic plating can be a nickel (Ni) plating layer.Furthermore, in the case of a thin region between adjacent intermediate insulating layers 4 or the like and a region in which preferential embedding in the emitter electrode 6 cannot be achieved, tungsten, which has better embedding properties than the emitter electrode 6, can be arranged in the thin region, and the emitter electrode 6 can be provided on the tungsten. The emitter electrode 6 can be placed on the n. + -Type emitter layer 13, the p + -type contact layer 14, and the dummy trench electrode 12a, without being provided on the barrier metal 5. Alternatively, the barrier metal 5 can be provided only on the n-type semiconductor layer such as the n + -Type emitter layer 13 is provided. The barrier metal 5 and the emitter electrode 6 can be referred to collectively as an emitter electrode. Although Fig. Figure 5 illustrates a view in which the interlayer insulating layer 4 is not provided on the dummy trench electrode 12a of the dummy trench gate 12. If the interlayer insulating layer 4 is provided on the dummy trench electrode 12a of the dummy trench gate 12, the emitter electrode 6 and the dummy trench electrode 12a can be electrically connected in another section.

[0039] A collector electrode 7 is provided on the side of the second main surface of the p-type collector layer 16. Similar to the emitter electrode 6, the collector electrode 7 can be made of an aluminum alloy or of an aluminum alloy and a plating layer. The collector electrode 7 can have a configuration that differs from that of the emitter electrode 6. The collector electrode 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to it.

[0040] Fig. Figure 6 is a cross-sectional view of the semiconductor device 100, which is shown along the dashed line BB from Fig. 4 is taken from this, and it is a cross-sectional view of IGBT region 10. A difference from the cross-sectional view shown along the in Fig. The point illustrated by the dashed line in point 5 is that the n +-Type emitter layer 13, which is provided on the side of the first main surface of the semiconductor substrate in contact with the active trench gate 11, is not seen in the cross-sectional view, which is along the dashed line BB in Fig. 6 is taken from this. That is, as in Fig. As illustrated in section 4, the n + -Type emitter layer 13 is selectively provided on the side of the first main surface of a p-type base layer. The p-type base layer referred to here is a p-type base layer in which the p-type base layer 15 and the p + -Type contact layer 14 are collectively referred to. (5) Structure of IGBT region 10 according to the present preferred embodiment

[0041] The Fig. 7, Fig. 8 to Fig. Figure 9 are views which each illustrate a structure of the IGBT region 10 of the semiconductor device 100 according to the first preferred embodiment. Fig. Figure 7 is an enlarged top view of part of IGBT region 10. Fig. 8 and Fig. Figure 9 are cross-sectional views, each illustrating a configuration of an IGBT located in IGBT region 10. Fig. Figure 7 is an enlarged view illustrating a region enclosed by the dashed line 82 in the semiconductor device 100, which is located in the Fig. 1, Fig. 2, or 3 is illustrated. Fig. 8 is a cross-sectional view, which is taken along a line in Fig. 7 illustrated dashed line A1-A1 is taken from, and Fig. 9 is a cross-sectional view, which is taken along a line in Fig. 7 illustrated dashed line B1-B1 is taken from this.

[0042] As in the Fig. 7, Fig. 8 to Fig. As illustrated in Figure 9, first trenches 51 and second trenches 52, which have different widths, are arranged in the IGBT region 10 of the semiconductor device 100 according to the first preferred embodiment. The width of the second trenches 52 is wider than the width of the first trenches 51. The active trench gate 11, which comprises the gate-trough electrode 11a and the gate-trough insulating layer 11b, is formed in the first trenches 51, and the dummy trench gate 12, which comprises the dummy trench electrode 12a and the dummy trench insulating layer 12b, is formed in the second trenches 52 (as shown in the figures). Fig. 8 and Fig. 9 removable, the dummy trench electrode 12a in each of the second trenches 52 is connected to the emitter electrode 6 through the barrier metal 5 and does not function as the gate electrode of the IGBT. Although the entire upper surface of the dummy trench electrode 12a is connected to the emitter electrode 6 through the barrier metal 5 in the Fig. 8 and Fig. 9 is connected, the upper surface of the dummy trench electrode 12a may be partially covered by the intermediate insulating layer 4.

[0043] Here is a direction from the first main surface (surface at the top of the drawing) into the Fig. 8 and Fig. 9) of the semiconductor substrate in the direction of the second main surface (surface on the bottom side of the drawing in the Fig. 8 and Fig. 9), that is, a depth direction originating from the first principal surface of the semiconductor substrate is defined as a “first direction”. Furthermore, a direction perpendicular to the first direction and perpendicular to a longitudinal direction of the first trench 51 and the second trench 52, that is, a lateral direction of the first trench 51 and the second trench 52, is defined as a “second direction”. That is, the first direction is a downward direction in the drawing in the Fig. 8 and Fig. 9, and the second direction is a lateral direction in the drawing of the Fig. 8 and Fig. 9.

[0044] As in the Fig. 8 and Fig. As illustrated in Figure 9, the depth of the second trench 52 is deeper than the depth of the first trench 51 in the first direction, and the width of the second trench 52 is wider than the width of the first trench 51 in the second direction. Furthermore, a p-type soil layer 60 is provided at the bottom of the second trench 52 such that it is in contact with the second trench 52. The p-type soil layer 60 is not formed at the bottom of the first trench 51.

[0045] Since the second trenches 52 are deeper than the first trenches 51, the distance between the bottoms of the second trenches 52, in which the p-type soil layers 60 are provided, is considerable. This prevents the adjacent p-type soil layers 60 from connecting and prevents the p-type soil layers 60 from forming a gap between the trenches. Therefore, the p-type soil layers 60 can be formed at a greater depth. Furthermore, since the widths of the second trenches 52 are wide, the regions occupied by the p-type soil layers 60 can be enlarged, and the effect of the p-type soil layers 60 on the electrical field relaxation can be increased.

[0046] In the present preferred embodiment, the n-type charge carrier storage layer 2 is arranged between the p-type base layer 15 and the p-type bottom layer 60, and the p-type bottom layer 60 is in contact with the n-type charge carrier storage layer 2. By means of this arrangement, the p-type bottom layer 60 is further prevented from spreading in the lateral direction, and an effect to prevent the p-type bottom layer 60 from shielding the gap between trenches is improved.

[0047] Furthermore, the bottom of the n-type charge carrier storage layer 2 is deeper than the bottom of the first trench 51. This configuration further prevents the lateral spread of the p-type soil layer 60. However, the electric field generated in the n-type charge carrier storage layer 2 increases if its bottom is deeper than the bottom of the p-type soil layer 60; therefore, the bottom of the n-type charge carrier storage layer 2 is preferably shallower than the bottom of the p-type soil layer 60.

[0048] Here, the example described is in which the active trench gate 11 is formed in the first trench 51 and the dummy trench gate 12 is formed in the second trench 52, but conversely, the dummy trench gate 12 can be formed in the first trench 51, and the dummy trench gate 12 can be formed in the second trench 52.

[0049] Although the first trenches 51 and the second trenches 52 alternate side by side in Fig. 7, the IGBT region 10 can include a region in which the plurality of first trenches 51 are arranged continuously adjacent to one another and a region in which the plurality of second trenches 52 are arranged continuously adjacent to one another. That is, it is not necessary for all first trenches 51 to be adjacent to the second trenches 52, and it is sufficient for at least some of the first trenches 51 to be adjacent to the second trenches 52. Similarly, it is not necessary for all second trenches 52 to be adjacent to the first trenches 51, and it is sufficient for at least some of the second trenches 52 to be adjacent to the first trenches 51. In a case in which the dummy trench gates 12 are each formed in the second trenches 52, the p-type soil layers 60 at the bottoms of the adjacent second trenches 52 can be connected to one another in a different region in which the second trenches 52 are arranged continuously adjacent to one another. (6) Example of the structure of diode region 20

[0050] Fig. Figure 10 is a partially enlarged top view illustrating the configuration of a diode region in a semiconductor device that is an RC-IGBT. Fig. 11 and Fig. Figure 12 are cross-sectional views, each illustrating a configuration of the diode region of the semiconductor device, which is the RC-IGBT. Fig. Figure 10 is an enlarged view illustrating a region surrounded by a dashed line 83 in the semiconductor device 100, which is in Fig. 2 is illustrated. Fig. Figure 11 is a cross-sectional view taken along a dashed line CC of the semiconductor device 100, which is shown in Fig. 10 is illustrated. Fig. Figure 12 is a cross-sectional view taken along a dashed line DD of the semiconductor device 100, which is shown in Fig. 10 is illustrated.

[0051] A diode trench gate 21 extends along the first main surface of the semiconductor device 100 from one end face of the diode region 20, which is the cell region, towards the opposite end face. The diode trench gate 21 is formed by a diode trench electrode 21a in the trench formed in the semiconductor substrate of the diode region 20 by a diode trench insulating layer 21b. The diode trench electrode 21a lies at the n - -Type drift layer 1 through the diode trench insulating layer 21b opposite. A p + A -type contact layer 24 and a p-type anode layer 25 are provided between two adjacent diode trench gates 21. The p + -Type contact layer 24 is a semiconductor layer which, for example, contains boron or aluminum as a p-type defect, and the concentration of the p-type defect corresponds to 1.0E+15 / cm². 3 up to 1.0E+20 / cm 3The p-type anode layer 25 is a semiconductor layer which, for example, contains boron or aluminum as the p-type defect, and the concentration of the p-type defect corresponds to 1.0E+12 / cm². 3 up to 1.0E+19 / cm 3 . The p + The -type contact layer 24 and the p-type anode layer 25 are provided alternately in the longitudinal direction of the diode trench gate 21.

[0052] Fig. Figure 11 is the cross-sectional view of the semiconductor device 100, which is located along the dashed line CC of Fig. Figure 10 is taken from the diagram and is a cross-sectional view of the diode region 20. The semiconductor device 100 also has the n - -Type drift layer 1, which comprises a semiconductor substrate in the diode region 20 as in the IGBT region 10. The n - -Type drift layer 1 of diode region 20 and the n -The drift-type layer 1 of IGBT region 10 is continuous and integral, and it is formed from the same semiconductor substrate. Fig. 11 the semiconductor substrate extends from the p + -Type contact layer 24 up to a n + -Type cathode layer 26. In Fig. 11 will be an upper end of the p + -Type contact layer 24 in the drawing is designated as a first main surface of the semiconductor substrate, and a lower end of the n + The cathode layer 26 in the drawing is designated as a second principal area of ​​the semiconductor substrate. The first principal area of ​​diode region 20 and the first principal area of ​​IGBT region 10 are flush with each other, and the second principal area of ​​diode region 20 and the second principal area of ​​IGBT region 10 are flush with each other.

[0053] As in Fig. As illustrated in Figure 11, the n-type charge carrier storage layer 2 is also located on the side of the first main surface of the n in the diode region 20. - -Type drift layer 1 is provided, and the n-type buffer layer 3 is on the side of the second main surface of the n --Type drift layer 1 as provided in IGBT region 10. The n-type charge carrier storage layer 2 and the n-type buffer layer 3 provided in diode region 20 have the same configuration as the n-type charge carrier storage layer 2 and the n-type buffer layer 3 provided in IGBT region 10. The n-type charge carrier storage layer 2 is not necessarily provided in IGBT region 10 and diode region 20, and it is possible that the n-type charge carrier storage layer 2 is not provided in diode region 20 even if the n-type charge carrier storage layer 2 is provided in IGBT region 10. Similar to IGBT region 10, the n - The -type drift layer 1, the n-type charge carrier storage layer 2, and the n-type buffer layer 3 are collectively referred to as a drift layer.

[0054] The p-type anode layer 25 is provided on the side of the first main surface of the n-type charge carrier storage layer 2. The p-type anode layer 25 is located between the n - The p-type drift layer 1 and the first main surface are provided. In the p-type anode layer 25, the p-type anode layer 25 and the p-type base layer 15 can be formed simultaneously by making the concentration of the p-type defect identical to that of the p-type base layer 15 of the IGBT region 10. Furthermore, the concentration of the p-type defect in the p-type anode layer 25 can be lower than the concentration of the p-type defect in the p-type base layer 15 of the IGBT region 10, in order to reduce the number of implanted holes that are implanted into the diode region 20 during diode operation. Recovery loss during diode operation can be reduced by decreasing the number of implanted holes during diode operation.

[0055] The p + The p-type contact layer 24 is provided on the side of the first main surface of the p-type anode layer 25. The concentration of the p-type defect of the p + The concentration of the p-type contact layer 24 can be the same or different from the concentration of the p-type defect. + -Type contact layer 14 of IGBT region 10. The p + The -type contact layer 24 forms the first main surface of the semiconductor substrate. If the p + -Type contact layer 24 is a region which has a higher concentration of the p-type defect than the p-type anode layer 25, and if it is required that the p + The -type contact layer 24 and the p-type anode layer 25 can be distinguished from each other; they can be designated individually, and the p + The -type contact layer 24 and the p-type anode layer 25 can be referred to together as a p-type anode layer.

[0056] In diode region 20, the n +-Type cathode layer 26 is provided on the side of the second main surface of the n-type buffer layer 3. The n + -Type cathode layer 26 is located between the n - -Type drift layer 1 and the second main surface provided. The n + -Type cathode layer 26 is a semiconductor layer which, for example, contains arsenic or phosphorus as the n-type defect, and the concentration of the n-type defect corresponds to 1.0E+16 / cm². 3 up to 1.0E+21 / cm 3 As illustrated in Fig. 3, the n + -Type cathode layer 26 provided in part or in all of the diode region 20. The n + The p-type cathode layer 26 forms the second main surface of the semiconductor substrate. Although not illustrated, the p-type defect can also be selectively implanted in the region where the n described above is located. +-type cathode layer 26 is formed, and the p-type cathode layer can be provided using a part of the region in which the n + -Type cathode layer 26 is formed as the p-type semiconductor.

[0057] As in Fig. Figure 11 illustrates trenches that penetrate the p-type anode layer 25 starting from the first main surface of the semiconductor substrate and the n - -Type drift layer 1 is formed in the diode region 20 of the semiconductor device 100. The diode trench electrode 21a is provided in the trench of the diode region 20 by the diode trench insulating layer 21b to form the diode trench gate 21. The diode trench electrode 21a lies to the n - -Type drift layer 1 opposite the diode trench insulating layer 21b.

[0058] As in Fig. Figure 11 illustrates the barrier metal 5 on the diode trench electrode 21a and the p +-Type contact layer 24 is provided. The barrier metal 5 is in ohmic contact with the diode trench electrode 21a and the p + -Type contact layer 24, and it is electrically connected to the diode trench electrode and the p + -Type contact layer 24 connected. The barrier metal 5 can have the same configuration as the barrier metal 5 in the IGBT region 10. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6, which is provided in the diode region 20, is continuous with the emitter electrode 6, which is provided in the IGBT region 10. Similar to the IGBT region 10, the diode trench electrode 21a and the p + -Type contact layer 24 is brought into ohmic contact with the emitter electrode 6 without providing the barrier metal 5. Although Fig. Figure 11 illustrates a view in which the interlayer insulating layer 4 is not provided on the diode trench electrode 21a of the diode trench gate 21. If the interlayer insulating layer 4 is formed on the diode trench electrode 21a of the diode trench gate 21, the emitter electrode 6 and the diode trench electrode 21a may be electrically connected in another section.

[0059] The collector electrode 7 is located on the side of the second main surface of the n + -Type cathode layer 26 is provided. Similar to the emitter electrode 6, the collector electrode 7 of the diode region 20 is formed continuously with the collector electrode 7, which is provided in the IGBT region 10. The collector electrode 7 is in ohmic contact with the n + -Type cathode layer 26 and is electrically connected to the n+ -Type cathode layer 26 connected.

[0060] Fig. Figure 12 is a cross-sectional view of the semiconductor device 100, which is shown along the dashed line DD from Fig. taken from 10, and it is a cross-sectional view of the diode region 20. Differences to the cross-sectional view which is shown along the in Fig. The dotted line CC, illustrated in point 11, indicates that the p + -Type contact layer 24 is not provided between the p-type anode layer 25 and the barrier metal 5, and that the p-type anode layer 25 forms the first major surface of the semiconductor substrate. That is, the p + -Type contact layer 24 in Fig. 11 is selectively provided on the side of the first main surface of the p-type anode layer 25. (7) Structure of the diode region 20 according to the present preferred embodiment

[0061] The Fig. 13, Fig. 14 to Fig. Figure 15 are views illustrating a structure of the diode region 20 of the semiconductor device 100 according to the first preferred embodiment. Fig. Figure 13 is an enlarged view of part of the diode region 20. Fig. 14 and Fig. Figure 15 are cross-sectional views, each illustrating a configuration of a diode located in the diode region 20. Fig. Figure 13 is an enlarged view illustrating a region defined by the dashed line 83 in the Fig. 2 or Fig. 3 illustrated semiconductor device 100 is surrounded. Fig. 14 is a cross-sectional view, which is taken along a line in Fig. 13 illustrated dashed line C1-C1 is taken from, and Fig. 15 is a cross-sectional view, which is taken along a line in Fig. 13 illustrated dashed line D1-D1 is taken from.

[0062] As in the Fig. 13, Fig. 14 to Fig. As illustrated in Figure 15, in the semiconductor device 100 according to the first preferred embodiment, the first trenches 51 and the second trenches 52, which have different widths, are also arranged in the diode region 20. The width of the second trenches 52 is wider than the width of the first trenches 51. The diode trench gate 21, which has the diode trench electrode 21a and the diode trench insulating layer 21b, is formed in both the first trench 51 and the second trench 52.

[0063] As in the Fig. 14 and Fig. As illustrated in Figure 15, the depth of the second trench 52 is greater than the depth of the first trench 51 in a first direction (downward in the drawing), and the width of the second trench 52 is greater than the width of the first trench 51 in a second direction (lateral in the drawing). Furthermore, a p-type soil layer 60 is provided at the bottom of the second trench 52 such that it is in contact with the second trench 52. The p-type soil layer 60 also exhibits the effect of electric field relaxation in the diode region 20. The p-type soil layer 60 is not formed at the bottom of the first trench 51. Furthermore, the p-type soil layer 60 is formed at the bottom of the second trench 52 such that it is not in contact with the first trench 51.

[0064] Since the second trenches 52 are deeper than the first trenches 51, the distance between the bottoms of the second trenches 52, in which the p-type soil layers 60 are provided, is considerable. This prevents the adjacent p-type soil layers 60 from connecting and prevents the p-type soil layers 60 from forming a gap between the trenches. Therefore, the p-type soil layers 60 can be formed at a greater depth. Furthermore, since the widths of the second trenches 52 are wide, the regions occupied by the p-type soil layers 60 can be enlarged, and the effect of the p-type soil layers 60 on the electrical field relaxation can be increased.

[0065] Although the first trenches 51 and the second trenches 52 alternate side by side in Fig. If the diode region 20 is arranged in a pattern of 13, it can include a region in which the plurality of first trenches 51 are arranged continuously adjacent to each other and a region in which the plurality of second trenches 52 are arranged continuously adjacent to each other. That is, it is not necessary for all first trenches 51 to be adjacent to the second trenches 52, and it is sufficient for at least some of the first trenches 51 to be adjacent to the second trenches 52. Similarly, it is not necessary for all second trenches 52 to be adjacent to the first trenches 51, and it is sufficient for at least some of the second trenches 52 to be adjacent to the first trenches 51.

[0066] The ratio of the regions in which the p-type soil layers 60 are located in the diode region 20 and the ratio of the regions in which the p-type soil layers 60 are located in the IGBT region 10 may differ.

[0067] Although the Fig. 14 and Fig. 15 To illustrate an example in which the n-type charge carrier storage layer 2 is formed in the diode region 20, the n-type charge carrier storage layer 2 is not necessarily provided in the diode region 20. (8) Border region between IGBT region 10 and diode region 20

[0068] Fig. Figure 16 is a cross-sectional view illustrating a configuration of a boundary between an IGBT region and a diode region of a semiconductor device, which is an RC-IGBT. Fig. Figure 16 is a cross-sectional view taken along a dashed line GG in the semiconductor device 100, which is located in Fig. 2 is illustrated.

[0069] As in Fig. As illustrated in Figure 16, the p-type collector layer 16, which is provided on the side of the second main surface of the IGBT region 10, is provided such that it projects from the boundary between the IGBT region 10 and the diode region 20 towards the side of the diode region 20 by a distance U1. If, as described above, the p-type collector layer 16 is provided such that it projects towards the diode region 20, a distance between the n + -Type cathode layer 26 of the diode region 20 and the active trench gate 11 are increased, and even if the gate driver voltage is applied to the gate trench electrode 11a during freewheeling diode operation, it can be prevented that the current which originates from a channel which is formed next to the active trench gate 11 of the IGBT region 10, flows to the n +-Type cathode layer 26 flows. For example, the distance U1 can be 100 µm. It should be noted that the distance U1 can be zero or a distance less than 100 µm, depending on the application of the semiconductor device 100, which is the RC-IGBT. (9) Example of a structure of the termination region 30

[0070] The Fig. 17 and Fig. Figure 18 are cross-sectional views, each illustrating a configuration of a termination region of a semiconductor device that is an RC-IGBT. Fig. 17 is a cross-sectional view, which is drawn along a dashed line EE from Fig. 2 or Fig. 3 is taken from, and it is a cross-sectional view from IGBT region 10 to termination region 30. Fig. Figure 18 is a cross-sectional view, drawn along a dashed line FF from Fig. 2 is taken from, and it is a cross-sectional view from the diode region 20 to the termination region 30.

[0071] As in the Fig. 17 and Fig. Figure 18 illustrates that the termination region 30 of the semiconductor device 100 has the n - -Type drift layer 1 between the first major surface and the second major surface of the semiconductor substrate. The first major surface and the second major surface of the termination region 30 are each flush with the first major surfaces and the second major surfaces of the IGBT region 10 and the diode region 20. The n - -Type Drift layer 1 of termination region 30 has the same configuration as the n - -Type drift layer 1 of the IGBT region 10 and the diode region 20, and it is continuous and integrally formed.

[0072] A p-type termination trough layer 31 is located on the side of the first main surface of the n --Type drift layer 1 provided, namely between the first main surface of the semiconductor substrate and the n - -Type drift layer 1. The p-type termination tray layer 31 is a semiconductor layer which contains, for example, boron or aluminum as the p-type defect, and the concentration of the p-type defect corresponds to 1.0E+14 / cm². 3 up to 1.0E+19 / cm 3 The p-type termination collector layer 31 is provided such that it surrounds the cell region encompassing the IGBT region 10 and the diode region 20. A plurality of the p-type termination well layers 31 are provided in a ring configuration, and the number of p-type termination well layers 31 provided is appropriately selected in accordance with the withstand voltage design of the semiconductor device 100. Furthermore, an n +-Type channel stopper layer 32 is provided on one side of a more outward edge of the p-type termination collector layer 31, and the n + The -type channel stopper layer 32 surrounds the p-type termination collector layer 31.

[0073] The p-type termination collector layer 16a is located between the n - -type drift layer 1 and the second main surface of the semiconductor substrate are provided. The p-type termination collector layer 16 is integral and continuous with the p-type collector layer 16, which is provided in the cell region. Accordingly, the p-type termination collector layer 16a can be referred to as the p-type collector layer 16. In the configuration in which the diode region 20 is adjacent to the termination region 30 as in the Fig. In the semiconductor device 100 illustrated in Figure 2, the p-type termination collector layer 16a is provided such that an end part of the side of the diode region 20 protrudes from the diode region 20 by a distance U2, as shown in Figure 2. Fig. Figure 18 illustrates this. If, as described above, the p-type termination collector layer 16a is provided such that it protrudes towards the diode region 20, the distance between the n + The distance between the p-type cathode layer 26 of the diode region 20 and the termination well layer 31 can be increased, and it can be prevented that the p-type termination well layer 31 acts as an anode of the diode. For example, the distance U2 can be 100 µm.

[0074] The collector electrode 7 is located on the second main surface of the semiconductor substrate. The collector electrode 7 extends integrally from the cell region, which contains the IGBT region 10 and the diode region 20, to the termination region 30. On the other hand, the emitter electrode 6, which extends continuously from the cell region, and a termination electrode 6a, which is separate from the emitter electrode 6, are located on the first main surface of the semiconductor substrate in the termination region 30.

[0075] The emitter electrode 6 and the termination electrode 6a are electrically connected by a semi-insulating layer 33. For example, the semi-insulating layer 33 can be a semi-insulating silicon nitride (sinSiN) layer. The termination electrode 6a, the p-type termination well layer 31, and the n +The channel stopper layer 32 is electrically connected to each other via the contact hole formed in the intermediate insulating layer 4, which is provided on the first main surface of the termination region 30. Furthermore, a termination protection layer 34 is provided in the termination region 30 such that it covers the emitter electrode 6, the termination electrode 6a, and the semi-insulating layer 33. For example, the termination protection layer 34 can be made of polyimide.

[0076] Fig. Figure 19 is a cross-sectional view illustrating another example of the configuration of the termination region of the semiconductor device, which is the RC-IGBT. It shows a cross-section across the diode region 20, the IGBT region 10, and the termination region 30. A wiring region 70 is provided in a portion on the inner peripheral side of the termination region 30. Although wiring region 70 is contained within termination region 30 here, wiring region 70 and termination region 30 can be defined as separate regions.

[0077] In wiring region 70, for example, a wiring electrode 6b is arranged like a gate wiring. The termination electrode 6a in termination region 30 and the wiring electrode 6b in wiring region 70 are covered by a protective insulating layer 35.

[0078] In the semiconductor substrate of the termination region 30, the p-type termination well layer 31 is located on the side of the first main surface of the n - -Type drift layer 1 formed. In the example of Fig. 19 The p-type termination trough layer 31 has a VLD structure.

[0079] A multitude of trenches are provided in wiring region 70, which is the portion on the inner peripheral side of termination region 30, as in IGBT region 10 and diode region 20. Here, a trench on the outermost side of the trenches provided in termination region 30 is defined as the "outermost trench." An outermost trench gate 71, which has the same configuration as active trench gate 11 and dummy trench gate 12, is formed in the outermost trench. That is, the outermost trench gate 71 has an insulating layer (outermost trench insulating layer 71b) formed on an inner surface of the outermost trench and an electrode (outermost trench electrode 71a) formed on the insulating layer.

[0080] In the trench-gate semiconductor device, an electric field tends to concentrate near the bottom of the outermost trench gate 71, and it is a task to relax the electric field in such a part. In the example of Fig. 19 is a depth of the p-type termination trough layer 31 deeper than a depth of the trench, and the bottom of the outermost trench gate 71 is covered by the p-type termination trough layer 31. As a result, an electric field is relaxed near the bottom of the outermost trench gate 71.

[0081] In Fig. 20 The p-type termination trough layer 31 is less deep than trenches compared to the configuration in Fig. 19. In this case, the bottom of the outermost trench gate 71 is not covered by the p-type termination trough layer 31, and therefore an electric field near the bottom of the outermost trench gate 71 tends to increase. (10) Structure of the termination region 30 of the present preferred embodiment

[0082] Fig. Figure 21 is a cross-sectional view illustrating the structure of the termination region 30 of the semiconductor device according to the present preferred embodiment. As shown in Fig. As illustrated in Figure 21, in the present preferred embodiment, the first trenches 51 and the second trenches 52 are provided in the wiring region 70, which is part of the inner peripheral side of the termination region 30 (boundary between the cell region and the termination region 30), as in the IGBT region 10 and the diode region 20. The outermost trench gate 71 is located in the second trench 52. The p-type bottom layer 60, which is in contact with the bottom of the second trench 52, is provided below the second trench 52 in which the outermost trench gate 71 is located.

[0083] In the present preferred embodiment, the bottom of the p-type termination trough layer 31 is less deep than the bottom of the second trench 52, in which the outermost trench gate 71 is located. Therefore, the bottom of the outermost trench gate 71 is not covered by the p-type termination trough layer 31.

[0084] According to the configuration of Fig. 21 The p-type soil layer 60 beneath the outermost trench can relax the electric field near the bottom of the outermost trench gate 71. Therefore, even if the soil of the p-type termination trough layer 31 is less deep than the bottom of the outermost trench, it prevents the electric field from increasing near the bottom of the outermost trench gate 71.

[0085] Although the outermost end of the n-type charge carrier storage layer 2 is located on the outer side (right side in the drawing) of the outermost trench gate 71 in Fig. 21, the outermost end of the n-type charge carrier storage layer 2 can be located on the inner side (left side in the drawing) of the outermost trench gate 71 as shown in Fig. 22 are located.

[0086] Furthermore, a plurality of the outermost trench gates 71, each featuring the p-type soil layer 60 at the bottom, can be arranged continuously. That is, of the trenches provided in termination region 30, a plurality of trenches located at the outermost side can be defined as "outermost trenches," and the outermost trench gate 71 and the p-type soil layer 60 can be provided in each of these plurality of outermost trenches. If the spacing between the plurality of outermost trench gates 71 gradually increases towards the outer side, the effect on relaxing the electric field is further enhanced. It is possible that the plurality of outermost trench gates 71 is provided only in some trenches in termination region 30 or in all trenches of termination region 30. (11) Example of the process for manufacturing the IGBT and the RC-IGBT

[0087] The Fig. 23, Fig. 24, Fig. 25, Fig. 26, Fig. 27, Fig. 28, Fig. 29, Fig. 30, Fig. 31, Fig. 32, Fig. 33 to Fig. Figure 34 are views illustrating a method for fabricating a semiconductor device that is an RC-IGBT. A method for fabricating an IGBT is obtained by extracting a process for fabricating an IGBT region from the method for fabricating an RC-IGBT. That is, since the method for fabricating an IGBT is essentially contained within the method for fabricating an RC-IGBT, the method for fabricating an RC-IGBT is described here.

[0088] The Fig. 23, Fig. 24, Fig. 25, Fig. 26, Fig. 27, Fig. 28, Fig. 29 to Fig. Figure 30 shows views illustrating a process for forming one side of a front surface of the semiconductor device 100, and the Fig. 31, Fig. 32, Fig. 33 to Fig. Figure 34 are views illustrating a process for forming one side of a rear surface of the semiconductor device 100.

[0089] First, as in Fig. Figure 23 illustrates a semiconductor substrate which the n -The semiconductor substrate is prepared to form a -type drift layer 1. The semiconductor substrate can be, for example, a so-called floating-zone (FZ) wafer produced by an FZ process, a so-called magnetic field-applied Czochralski (MCZ) wafer produced by an MCZ process, or an n-type wafer containing an n-type defect. The concentration of the n-type defect in the semiconductor substrate is selected appropriately depending on the withstand voltage of the semiconductor device to be manufactured. For example, in the semiconductor device with a withstand voltage of 1200 V, the concentration of the n-type defect is adjusted such that the resistivity of the n - The -type drift layer 1, which forms the semiconductor substrate, has a resistance of approximately 40 Ω·cm to approximately 120 Ω·cm. As in Fig. As illustrated in 23, the entire semiconductor substrate is the n --Type drift layer 1 in the process for preparing the semiconductor substrate, and a p-type or n-type dopant ion is implanted from one side of a first face or one side of a second main face of the semiconductor substrate, and subsequently diffused into the semiconductor substrate by heat treatment or the like, thereby forming a p-type or an n-type semiconductor layer to fabricate the semiconductor device 100.

[0090] As in Fig. 23 illustrates the semiconductor substrate which the n -The drift layer 1 of type 1 forms a region which becomes IGBT region 10 and diode region 20. Although not illustrated, a region which becomes termination region 30 is provided around the region which becomes IGBT region 10 and diode region 20. Although mainly a method for fabricating configurations of IGBT region 10 and diode region 20 of semiconductor device 100 is described below, termination region 30 of semiconductor device 100 can be fabricated by a known fabrication method.For example, if the FLR, which has the p-type termination tray layer 31 as the stress-holding structure, is formed in the termination region 30, the FLR can be formed by implanting the p-type dopant ion before the IGBT region 10 and the diode region 20 of the semiconductor device 100 have been processed, or it can be formed by simultaneously implanting the p-type dopant ions during the implantation of the p-type defect in the IGBT region 10 or the diode region 20 of the semiconductor device 100.

[0091] Next, as in Fig. Figure 24 illustrates the implantation of an n-type impurity, such as phosphorus (P), from the side of the first major face of the semiconductor substrate to form the n-type charge carrier storage layer 2. Furthermore, a p-type impurity, such as boron (B), is implanted from the side of the first major face of the semiconductor substrate to form the p-type base layer 15 and the p-type anode layer 25. The n-type charge carrier storage layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed by implanting the dopant ions into the semiconductor substrate and subsequently diffusing them through a heat treatment.The n-type and p-type dopant are ion-implanted after mask processing on the first major face of the semiconductor substrate, so that the n-type and p-type defects are selectively formed on the side of the first major face of the semiconductor substrate. The n-type charge carrier storage layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed in the IGBT region 10 and the diode region 20, and are connected to the p-type termination well layer 31 in the termination region 30.Mask processing refers to a process for applying a resist to the semiconductor substrate, for forming an opening in a predefined region of the resist using a photolithography technique, and for forming a mask on the semiconductor substrate in order to perform ion implantation or etching with respect to the predefined region of the semiconductor substrate through the opening.

[0092] The p-type base layer 15 and the p-type anode layer 25 can be formed by simultaneously implanting the p-type dopant. In this case, the depths or p-type defect concentrations of the p-type base layer 15 and the p-type anode layer 25 are identical, and they exhibit the same configuration. Alternatively, the depths of the p-type defect concentrations of the p-type base layer 15 and the p-type anode layer 25 can be formed differently by separately ion-implanting the p-type dopant into the p-type base layer 15 and the p-type anode layer 25 via mask processing.

[0093] The p-type termination well layer 31, formed in a separate section, can be formed by ion implantation of the p-type dopant simultaneously with the p-type anode layer 25. In this case, the depths of the p-type defect concentrations in the p-type termination well layer 31 and the p-type anode layer 25 are identical, and they can have the same configuration. Furthermore, the p-type termination well layer 31 and the p-type anode layer 25 can be implanted by simultaneous ion implantation of the p-type defect, and the p-type defect concentrations in the p-type termination well layer 31 and the p-type anode layer 25 can be set to different concentrations. In this case, one or both of the masks can be used as a grid-like mask to modify an opening ratio.

[0094] Furthermore, the depths of the p-type defect concentrations in the p-type termination well layer 31 and the p-type anode layer 25 can be configured differently by separately implanting the p-type dopant into the p-type termination well layer 31 and the p-type anode layer 25 via mask processing. The p-type termination well layer 31, the p-type base layer 15, and the p-type anode layer 25 can be formed by simultaneous ion implantation of the p-type dopant.

[0095] Next, as in Fig. Figure 25 illustrates the selective implantation of the n-type dopant into the side of the first major surface of the p-type basal layer 15 of the IGBT region 10 by mask processing to create the n +-type emitter layer 13. For example, the implanted n-type dopant can be arsenic (As) or phosphorus (P). Furthermore, the p-type dopant is selectively implanted by mask processing into the side of the first major surface of the p-type base layer 15 of the IGBT region 10 to form the p + -type contact layer 14 is formed, and the p-type dopant is selectively implanted into the side of the first main surface of the p-type anode layer 25 of the diode region 20 to form the p + -type contact layer 24 is formed. For example, the implanted p-type defect is boron (B) or aluminum (Al).

[0096] Next, as in Fig. Figure 26 illustrates that trenches 8 are formed, each penetrating the p-type base layer 15 and p-type anode layer 25 starting from the side of the first main surface of the semiconductor substrate and the n --Type drift layer 1 is reached. In IGBT region 10, a side wall of trench 8 forms, which the n + -Type emitter layer 13 penetrates, a part of the n + -Type emitter layer 13. After an oxide layer such as SiO2 has been applied to the semiconductor substrate, the opening in the oxide layer is formed in a portion where the trench 8 is formed by mask processing, and the semiconductor substrate is formed using the oxide layer, which has the opening as a mask, thereby allowing the trench 8 to be formed. Although the trenches 8, which have the same spacing, are in Fig. Since the grooves 8 are formed in the IGBT region 10 and the diode region 20, they can be formed at different distances between the IGBT 10 and the diode region 20. The distance between the grooves 8 can be appropriately changed depending on the mask structure of the mask processing in a top view.

[0097] It should be noted that the process for forming the trenches 8 precedes the process for forming the n + -Type emitter layer 13 and the p + -Type contact layer 14 can be implemented.

[0098] Next, as in Fig. Figure 27 illustrates that the semiconductor substrate is heated in an oxygen-containing atmosphere to form an oxide layer 9 on the inner walls of the trenches 8 and the first major surface of the semiconductor substrate. Within the oxide layer 9 formed on the inner wall of the trench 8, the oxide layer 9 formed in the trench 8 of the IGBT region 10 is the gate-trough insulating layer 11b of the active trench gate 11 and the dummy-trough insulating layer 12b of the dummy-trough gate 12. The oxide layer 9 formed in the trench 8 of the diode region 20 is the diode-trough insulating layer 21b. The oxide layer 9 formed on the first major surface of the semiconductor substrate is removed in a subsequent process.

[0099] Next, as in Fig. Figure 28 illustrates polysilicon doped with an n-type or p-type dopant, deposited by chemical vapor deposition (CVD) or the like in the trench 8 in which the oxide layer 9 is formed on the inner wall, thereby forming the gate trench electrode 11a, the dummy trench electrode 12a, and the diode trench electrode 21a.

[0100] Next, as in Fig. Figure 29 illustrates that after the interlayer insulating layer 4 has formed on the gate-trough electrode 11a of the active trench gate 11 of the IGBT region 10, the oxide layer 9 on the first main surface of the semiconductor substrate is removed. For example, the interlayer insulating layer 4 can be SiO2. Subsequently, the contact hole is formed in the interlayer insulating layer 4, which was applied by mask processing. The contact holes are located on the n + -Type emitter layer 13, the p +-Type contact layer 14, the p + -Type contact layer 24, the dummy trench electrode 12a, and the diode trench electrode 21a are formed.

[0101] Next, as in Fig. Figure 30 illustrates that the barrier metal 5 is formed on the first main surface of the semiconductor substrate and the interlayer insulating layer as a single layer of the interlayer insulating layer 4, which has a multilayer structure including the insulating layer, and the emitter electrode 6 is furthermore formed on the barrier metal 5. The barrier metal 5 can be omitted and formed by depositing titanium nitride by physical vapor deposition (PVD) or CVD.

[0102] For example, the emitter electrode 6 can be formed by depositing an aluminum-silicon alloy (Al-Si-based alloy) onto the barrier metal 5 by PVD processes such as sputtering or vapor deposition. A nickel alloy (Ni alloy) can then be formed onto the aluminum-silicon alloy by electroless or electrolytic plating to form the emitter electrode 6. When the emitter electrode 6 is formed by plating, a thick metal layer can be easily created as the emitter electrode 6, thus increasing its heat capacity and improving its thermal resistance.Furthermore, if the nickel alloy is formed by plating after the emitter electrode 6 has been formed, which was formed from the aluminium-silicon alloy by PVD, the plating treatment can be carried out to form the nickel alloy after the side of the second main surface of the semiconductor substrate has been processed.

[0103] Next, as in Fig. Figure 31 illustrates how the side of the second main surface of the semiconductor substrate is ground to reduce the semiconductor substrate to a specified, predefined thickness. For example, the thickness of the ground semiconductor substrate can be between 80 µm and 200 µm.

[0104] Next, as in Fig. Figure 32 illustrates the implantation of an n-type dopant from the side of the second major face of the semiconductor substrate to form the n-type buffer layer 3. Additionally, the p-type defect is implanted from the side of the second major face of the semiconductor substrate to form the p-type collector layer 16. The n-type buffer layer 3 can be formed in the IGBT region 10, the diode region 20, and the termination region 30, or it can be formed only in the IGBT region 10 or the diode region 20.

[0105] For example, the n-type buffer layer 3 can be formed by implanting a phosphorus (P) ion. Furthermore, the n-type buffer layer 3 can be formed by implanting a proton (H). +) can be formed. Furthermore, both the proton and the phosphorus can be implanted. The proton can be injected from the second main surface of the semiconductor substrate to a considerable depth with a relatively low acceleration energy. Moreover, the depth to which the proton is injected can be changed relatively easily by altering the acceleration energy. For this reason, when the n-type buffer layer 3 is formed by the proton, if the implantation is performed several times while varying the acceleration energy, the n-type buffer layer 3 can be formed wider in the thickness direction of the semiconductor substrate than the one formed from the phosphorus.

[0106] Furthermore, the phosphorus can increase the activation rate of the n-type defect compared to the proton, thus more reliably preventing the depletion layer from penetrating the semiconductor substrate itself, which is made thinner by forming the n-type buffer layer 3 with the phosphorus. To further reduce the thickness of the semiconductor substrate, the n-type buffer layer 3 is preferably formed by injecting both the proton and the phosphorus, and in this case, the proton is injected at a position that is deeper than the phosphorus, relative to the second main surface.

[0107] For example, the p-type collector layer 16 is formed by implanting boron (B). The p-type collector layer 16 is also formed in the termination region 30, and the p-type collector layer 16 of termination region 30 becomes the p-type termination collector layer 16a. After ion implantation from the side of the second major surface of the semiconductor substrate, the second major surface is irradiated with a laser to perform laser heat treatment, activating the implanted boron to form the p-type collector layer 16. At the same time, the phosphorus for the n-type buffer layer 3, which was injected at a relatively shallow position from the second major surface of the semiconductor substrate, is also activated.On the other hand, the proton is activated at a relatively low heat treatment temperature of 350°C to 500°C, so care must be taken to ensure that the temperature of the entire semiconductor substrate does not exceed 350°C to 500°C, except during the proton activation process after injection. Laser heat treatment can raise the temperature only near the second major surface of the semiconductor substrate, so laser heat treatment can be used to activate the n-type or p-type defect even after the proton has been implanted.

[0108] Next, as in Fig. 33 illustrates the n + -Type cathode layer 26 is formed in the diode region 20. For example, the n + -Type cathode layer 26 is formed by implantation of phosphorus (P). As in Fig. Figure 33 illustrates that phosphorus is implanted so selectively from the side of the second main surface by a mask processing that a boundary is formed between the p-type collector layer 16 and the n + -Type cathode layer 26 is located at a position approximately U1 from the boundary between IGBT region 10 and diode region 20 towards the side of diode region 20. An implantation amount of the n-type dopant, which the n + The amount of p-type dopant that forms the p-type cathode layer 26 is greater than the amount of p-type dopant that forms the p-type collector layer 16. Fig. 33 are depths of the p-type collector layer 16 and the n + -Type cathode layer 26 starting from the second main surface identical, but the depth of the n + The depth of the p-type cathode layer 26 is equal to or greater than the depth of the p-type collector layer 16. In the region where the n +For the -type cathode layer 26 to be formed, it is necessary that the n-type semiconductor substrate be formed by implanting the n-type dopant in the region into which the p-type dopant is implanted, so that the concentration of the implanted p-type dopant is made higher than the concentration of the n-type dopant in the entire region in which the n + -Type cathode layer 26 is formed.

[0109] Next, as in Fig. Figure 34 illustrates the formation of the collector electrode 7 on the second major surface of the semiconductor substrate. The collector electrode 7 is formed over the entire areas of the IGBT region 10, the diode region 20, and the termination region 30 on the second major surface. The collector electrode 7 can be formed over the entire second major surface of the n-type wafer, which is the semiconductor substrate. The collector electrode 7 can be formed by depositing an aluminum-silicon alloy (Al-Si-based alloy), titanium (Ti), or the like by PVD such as sputtering or vapor deposition, or the collector electrode 7 can be formed by laminating a variety of metals such as an aluminum-silicon alloy, titanium, nickel, or gold.Furthermore, a metal layer can be formed on the metal layer formed by PVD by electroless plating or electrolytic plating to form the collector electrode 7.

[0110] The semiconductor device 100 is manufactured by the processes described above. A multitude of semiconductor devices 100 are formed in a matrix on an n-type wafer, so that the semiconductor devices 100 are completed by cutting the wafer into the individual semiconductor devices 100 by laser singulation or blade singulation. (12) Method for manufacturing a semiconductor device according to the present preferred embodiment

[0111] The semiconductor device according to the present preferred embodiment can be formed by forming the first trench 51 and the second trench 52 as the trenches 8 and by further forming the p-type bottom layer 60 by ion implantation of a p-type defect into the bottom of the second trench 52 in the fabrication process described above. In a process for forming the p-type bottom layer 60, the p-type dopant can be implanted into the entire bottom surface of the second trench 52, but it is preferably ion-implanted only into the central part of the second trench 52 in order to reduce the lateral widening of the p-type bottom layer 60.

[0112] A method for manufacturing the semiconductor device according to the present preferred embodiment is described with reference to a flowchart of Fig. 35 described in more detail. Since the semiconductor device according to the present preferred embodiment can be formed by a method similar to the example of the manufacturing process described above, differences from the example of the manufacturing process described above are described here. Fig. Figure 35 illustrates a representative manufacturing process in a case where the first trench 51 and the second trench 52 are formed in the IGBT region 10. This process is similar to the one described in Fig. 35 can be used in a case where the first trench 51 and the second trench 52 are formed in the diode region 20 or the termination region 30.

[0113] In the process for producing the semiconductor substrate according to the present preferred embodiment, the first trench 51 and the second trench 52 are formed in the process for forming the trenches 8 on the first main surface of the semiconductor substrate (step S1). In this process, it is necessary for the second trench 52 to be formed deeper than the first trench 51. Since a wider trench is generally formed deeper, the second trench 52 will be deeper than the first trench 51 if the first trench 51 and the second trench 52 are formed under the same etching conditions. Therefore, the first trench 51 and the second trench 52 can be formed at the same time, and it is not necessary to consider any coordination between the first trench 51 and the second trench 52.

[0114] Subsequently, the oxide layer 9, which becomes the gate-trough insulating layer 11b and the dummy-trough insulating layer 12b, is formed on inner surfaces of the first trench 51 and the second trench 52 (step S2). Then, polysilicon doped with an n-type or p-type defect is applied to form the gate-trough electrode 11a and the dummy-trough electrode 12a in the first trench 51 and the second trench 52, respectively (step S3).

[0115] Next, a resist mask 80, which has an opening in the middle part of the second trench 52, is formed on a first main surface of the semiconductor substrate using a photolithographic technique, and a middle part of the dummy trench electrode 12a in the second trench 52 is removed by etching using the resist mask 80 as a mask (step S4). In addition, the p-type bottom layer 60 is formed on a part where the dummy trench electrode 12a was removed, that is, a bottom of the middle part of the second trench 52 by ion implantation of a p-type dopant using the resist mask 80 as a mask (step S5).

[0116] Subsequently, polysilicon doped with an n-type or p-type dopant is reapplied to re-form the dummy trench electrode 12a in the area where the dummy trench electrode 12a was removed in step S4 (step S6). Furthermore, a heat treatment is performed to activate the defect in the p-type soil layer 60. In step S6, the portion of the dummy trench electrode 12a removed in step S4 can be embedded with a metal layer such as aluminum or tungsten, or it can be embedded with an insulating layer such as a polysilicon thermal oxide layer or a CVD oxide layer.

[0117] According to this method, since the p-type dopant can only be ion-implanted in the middle part of the second trench 52, the widening of the p-type soil layer 60 in the lateral direction can be prevented.

[0118] Fig. Figure 36 illustrates a further example of the method for manufacturing the semiconductor device according to the present preferred embodiment. In the manufacturing process of Fig. 36 A process for forming the first trench 51 and the second trench 52 (step S1) is carried out on a semiconductor substrate on which the p-type base layer 15 is not formed.

[0119] After the first trench 51 and the second trench 52 have been formed, the oxide layer 9, which becomes the gate-trough insulating layer 11b and the dummy-trough insulating layer 12b, is formed on their inner surfaces (step S2). Subsequently, polysilicon doped with an n-type or p-type defect is applied to form the gate-trough electrode 11a and the dummy-trough electrode 12a in the first trench 51 and the second trench 52, respectively (step S3). At this point, the thickness of the applied polysilicon is adjusted such that the entire first trench 51 is filled with the gate-trough electrode 11a, and the dummy-trough electrode 12a is formed on a side wall and bottom of the second trench 52.

[0120] Next, as the polysilicon is etched back, a central portion of the dummy trench electrode 12a in the second trench 52 is removed, while the gate trench electrode 11a in the first trench 51 and the dummy trench electrode 12a, which forms on the side wall of the second trench 52, are retained (step S4). In this state, a p-type dopant is implanted into a first major surface of the semiconductor substrate to form the p-type bottom layer 60 in the area where the dummy trench electrode 12a was removed, that is, the bottom of a central portion of the second trench 52 (step S5). At the same time, the p-type base layer 15 is formed near the first major surface of the semiconductor substrate.

[0121] Subsequently, polysilicon doped with an n-type or p-type dopant is reapplied to re-form the dummy trench electrode 12a in the area where the dummy trench electrode 12a was removed in step S4 (step S6). Furthermore, a heat treatment is performed to activate the defect in the p-type soil layer 60.

[0122] Since the p-type dopant can only be implanted in the middle part of the second groove 52, the manufacturing process of Fig. 36. Furthermore, the widening of the p-type soil layer 60 in the lateral direction is prevented.

[0123] In particular, it is used in the manufacturing process of Fig. 36. It is not necessary to add a photolithography process, since the central part of the dummy trench electrode 12a can be selectively removed without using the resist mask 80. Furthermore, alignment of the p-type bottom layer 60 with respect to the second trenches 52 can be achieved by self-alignment. In addition, there is also the advantage that defect implantation processes can be reduced, since the p-type bottom layer 60 and the p-type base layer 15 can be formed simultaneously. Therefore, the manufacturing process of Fig. 36 contribute significantly to simplifying the manufacturing process and reducing manufacturing costs.

[0124] In the above description of the preferred embodiment, an RC-IGBT with an IGBT region and a diode region is mainly described as an example of the semiconductor device, but the semiconductor device can be a single IGBT, which does not have any of the features described above. Fig. Figure 1 illustrates a diode region. Furthermore, the semiconductor device can be a semiconductor device with a MOSFET region, which is obtained by replacing the p-type collector layer 16 of the IGBT region with the n + -Type cathode layer 26 is replaced, or it can be a single MOSFET which has no diode region. In any semiconductor device, the same effects as those of the preferred embodiment of the RC-IGBT can be achieved.

[0125] It should be noted that the preferred embodiment described above may be modified or omitted as appropriate. <appendizes>

[0126] The following sections describe various aspects of the present revelation together as appendices. (Appendix 1)

[0127] comprising a semiconductor device: a semiconductor substrate which has a drift layer of a first conductivity type between a first main surface and a second main surface opposite the first main surface; a multitude of trenches formed on the first main surface of the semiconductor substrate; an insulating layer formed on an inner surface of the multitude of trenches; and an electrode which is embedded in each of the multitude of trenches through the insulating layer, which features a large number of trenches: a first trench; and a second ditch, which is deeper and wider than the first ditch, and wherein a soil layer of a second conductivity type, which is in contact with a soil of the second trench and not in contact with the first trench, is formed under the second trench. (Appendix 2)

[0128] Semiconductor device further comprising according to Appendix 1: a base layer of the second conductivity type, formed on a side facing the first main surface of the drift layer in the semiconductor substrate; and a charge carrier storage layer of the first conductivity type, which is formed between the base layer and the drift layer, where the bottom layer is in contact with the charge carrier storage layer. (Appendix 3)

[0129] Semiconductor device according to Appendix 2, wherein a bottom of the charge carrier storage layer is deeper than a bottom of the first trench and less deep than a bottom of the bottom layer. (Appendix 4)

[0130] Semiconductor device according to one of Appendices 1 to 3, wherein the semiconductor substrate has a termination region in an outer peripheral part, the semiconductor substrate in the termination region has a termination trough layer of the second conductivity type, which is formed on the side facing the first main surface of the drift layer, an outermost trench, which is the trench that is located on an outermost side in the termination region, the second trench is, the soil layer is formed under the outermost ditch, and The bottom of the termination basin layer is less deep than the bottom of the outermost trench. (Appendix 5)

[0131] Semiconductor device according to one of Appendices 1 to 3, wherein the semiconductor substrate has a cathode layer of the first conductivity type which is in contact with the second main surface on a side which faces the second main surface of the drift layer. (Appendix 6)

[0132] Semiconductor device according to one of Appendices 1 to 3, wherein the semiconductor substrate has a collector layer of the second conductivity type which is in contact with the second main surface on a side which faces the second main surface of the drift layer. (Appendix 7)

[0133] Semiconductor device according to any one of Appendices 1 to 6, wherein the semiconductor substrate exhibits: an IGBT region in which an IGBT is formed, which has the electrode that is configured as a gate electrode in the first or second trench; and a diode region in which an anode layer of the second conductivity type is arranged in contact with the first main surface on a side facing the first main surface of the drift layer, and a cathode layer of the first conductivity type is arranged in contact with the second main surface on a side facing the second main surface of the drift layer. (Appendix 8)

[0134] Semiconductor device according to Appendix 7, wherein the first trench, the second trench, and the bottom layer are also arranged in the diode region. (Appendix 9)

[0135] A method for manufacturing a semiconductor device, wherein the method comprises: (a) Preparing a semiconductor substrate having a first conductivity type drift layer between a first principal surface and a second principal surface opposite the first principal surface; (b) Forming a first trench and a second trench, which is wider than the first trench, on the first principal surface of the semiconductor substrate; (c) Forming an insulating layer on one inner surface of the first trench and the second trench; (d) Forming an electrode in the first trench and the second trench after forming the insulating layer; (e) Removal of a central part of the electrode in the second trench; (f) Forming a soil layer by ion implantation of a fault of a second conductivity type into soil of the second trench in a part from which the electrode has been removed; (g) Re-formation of the electrode in the part from which the electrode was removed, after the formation of the soil layer; and (h) Performing a heat treatment to activate the soil layer. (Appendix 10)

[0136] Method for manufacturing a semiconductor device according to Appendix 9, wherein the step (e) is carried out by etching back the electrode, and a base layer of the second conductivity type is formed on one side which faces the first main surface of the drift layer, together with the bottom layer by ion implantation in step (f).

[0137] While the revelation has been shown and described in detail, the preceding revelation is illustrative in all aspects and not limiting. It is therefore understood that numerous modifications and variations can be conceived. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2016-225566

[0002] < / appendizes>

Claims

[1] comprising a semiconductor device (100): • a semiconductor substrate comprising a drift layer (1) of a first conductivity type between a first principal surface and a second principal surface opposite the first principal surface; • a multitude of trenches (51, 52) which are formed on the first main surface of the semiconductor substrate; • an insulating layer (11b, 12b, 21b, 72b) formed on an inner surface of each of the plurality of trenches (51, 52); and • an electrode (11a, 12a, 21a, 72a) which is embedded in each of the plurality of trenches (51, 52) through the insulating layer (11b, 12b, 21b, 72b), wherein • exhibits a large number of ditches (51, 52): ◯ a first trench (51); and ◯ a second trench (52), which is deeper than the first trench (51) and wider than the first trench (51), and • a soil layer (60) of a second conductivity type, which is in contact with a soil of the second trench (52) and which is not in contact with the first trench (51), is formed under the second trench (52). [2] Semiconductor device (100) according to claim 1 further comprising: • a base layer (15) of the second conductivity type, which is formed on one of the main surfaces of the drift layer (1) in the semiconductor substrate; and • a charge carrier storage layer (2) of the first conductivity type, which is formed between the base layer (15) and the drift layer (1), wherein • the bottom layer (60) is in contact with the charge carrier storage layer (2). [3] Semiconductor device (100) according to claim 2, wherein a bottom of the charge carrier storage layer (2) is deeper than a bottom of the first trench (51) and less deep than a bottom of the bottom layer (60). [4] Semiconductor device (100) according to any one of claims 1 to 3, wherein • the semiconductor substrate has a termination region (30) in an outer peripheral part, • the semiconductor substrate in the termination region (30) has a termination trough layer (31) of the second conductivity type, which is formed on the side facing the first main surface of the drift layer (1), • an outermost trench, which is the trench located on an outermost side in the termination region (30), the second trench (52), • the soil layer (60) is formed under the outermost trench, and • the bottom of the termination basin layer (31) is less deep than the outermost trench. [5] Semiconductor device (100) according to one of claims 1 to 3, wherein the semiconductor substrate has a cathode layer (16) of the first conductivity type which is in contact on one side with the second main surface which faces the second main surface of the drift layer (1). [6] Semiconductor device (100) according to one of claims 1 to 3, wherein the semiconductor substrate has a collector layer (6) of the second conductivity type, which is in contact with the second main surface on a side which faces the second main surface of the drift layer (1). [7] Semiconductor device (100) according to any one of claims 1 to 6, wherein the semiconductor substrate comprises: • an IGBT region (10) in which an IGBT is formed which has the electrode embedded in the first trench (51) or the second trench (52) as the gate electrode (11a); and • a diode region (20) in which an anode layer of the second conductivity type, which is in contact with the first main surface, is arranged on a side which faces the first main surface of the drift layer (1), and a cathode layer (16) of the first conductivity type, which is in contact with the second main surface, is arranged on a side which faces the second main surface of the drift layer (1). [8] Semiconductor device (100) according to claim 7, wherein the first trench (51), the second trench (52), and the bottom layer (60) are also arranged in the diode region (20). [9] A method for manufacturing a semiconductor device (100) comprising the steps for: (a) Preparing a semiconductor substrate having a drift layer (1) of a first conductivity type between a first principal surface and a second principal surface opposite the first principal surface; (b) Forming a first trench (51) and a second trench (52), which is wider than the first trench (51), on the first principal surface of the semiconductor substrate; (c) Forming an insulating layer (11b, 12b, 21b, 72b) on an inner surface of the first trench (51) and the second trench (52); (d) Forming an electrode (11a, 12a, 21a, 72a) in the first trench (51) and the second trench (52) respectively after forming the insulating layer (11b, 12b, 21b, 72b); (e) Removal of a central part of the electrode (11a, 12a, 21a, 72a) in the second trench (52); (f) Forming a soil layer (60) by ion implantation of a dopant of a second conductivity type into a soil of the second trench (52) in a part from which the electrode (11a, 12a, 21a, 72a) has been removed; (g) Re-formation of the electrode (11a, 12a, 21a, 72a) in the part from which the electrode (11a, 12a, 21a, 72a) was removed, after the formation of the soil layer (60); and (h) Performing a heat treatment to activate the soil layer (60). [10] Method for manufacturing a semiconductor device (100) according to claim 9, wherein • the step (e) is carried out by back-etching the electrode (11a, 12a, 21a, 72a), and • a base layer (15) of the second conductivity type on one side which faces the first main surface of the drift layer (1), together with the bottom layer (60) is formed by ion implantation in step (f).

Images