Semiconductor device

Abstract

A semiconductor device comprises an emitter electrode, a temperature sensor unit located adjacent to the emitter electrode, sensor wiring, and a first wire-bond section located adjacent to a connection section between the emitter electrode and the sensor wiring. The sensor wiring comprises a first sensor wiring section, a second sensor wiring section, and a bent section. The distance from the connection section to the first wire-bond section is shorter than the distance from the bent section to the connection section.

Description

Background Technical field

[0001] The present disclosure relates to a semiconductor device. Description of the state of the art

[0002] A configuration has been proposed in which wiring leading from either the anode or cathode of a temperature sensor unit mounted on a semiconductor chip is connected to a main current electrode, such as the emitter electrode of a semiconductor device (for example, PCT International Publication No. 2015 / 029159). According to this configuration, since part of the main current electrode can be used as an electrode contact point for the temperature sensor unit, the area required for the electrode contact point of the temperature sensor unit can be reduced.

[0003] In the configuration described above, the distance between the connection section (the wiring leading from the temperature sensor unit to the main current electrode) and the wire-bonding section (the wire used to read the temperature sensor unit's potential at the main current electrode) can become considerable. When this distance is large, the temperature sensor unit's potential, read through the wire, is significantly affected by the main current flowing through the electrode, resulting in an inaccurate measurement (unreading) of the temperature sensor unit's potential. Summary

[0004] The present disclosure has been developed in view of the above problem, and one objective of the present disclosure is to provide a technique suitable for accurately measuring the potential of a temperature sensor unit.

[0005] A semiconductor device according to the present disclosure comprises a semiconductor substrate having a first main surface, an emitter electrode selectively provided on the first main surface, a temperature sensor unit provided on the first main surface and adjacent to the emitter electrode further on the inner side than a terminal end of the semiconductor substrate in a top view, sensor wiring having one end connected to the temperature sensor unit and another end connected to the emitter electrode at the terminal end of the semiconductor substrate, the sensor wiring being provided along the emitter electrode, and a first wire-bond sub-region provided on the emitter electrode and adjacent to a connection sub-region between the emitter electrode and the sensor wiring, the sensor wiring comprising a first sensor wiring sub-region,which, in a top view, extends in a first direction from the inner side of the semiconductor substrate to the terminal end, a second sensor wiring section which extends at the terminal end from the first sensor wiring section to the bonding section along a second direction that differs from the first direction of the first sensor wiring section, and has a curved section between the first sensor wiring section and the second sensor wiring section, and a distance from the bonding section to the first wire bonding section is shorter than a distance from the curved section to the bonding section.

[0006] It is possible to correctly measure the potential of the temperature sensor unit.

[0007] These and other tasks, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description of the present disclosure when considered in conjunction with the accompanying drawings. Brief description of the drawings Fig. Figure 1 is a top view showing a configuration of a semiconductor device according to a first preferred embodiment; Fig. 2 is a top view showing another configuration of the semiconductor device according to the first preferred embodiment; Fig. Figure 3 is a partially enlarged top view showing a configuration of an IGBT area of ​​the semiconductor device according to the first preferred embodiment; Fig. 4 and Fig. Figure 5 are cross-sectional views, each representing a configuration of the IGBT area of ​​the semiconductor device according to the first preferred embodiment; Fig. Figure 6 is a partially enlarged top view showing a configuration of a diode area of ​​the semiconductor device according to the first preferred embodiment; Fig. 7 and Fig. Figure 8 are cross-sectional views, each representing a configuration of the diode area of ​​the semiconductor device according to the first preferred embodiment; Fig. Figure 9 is a cross-sectional view showing a configuration of a boundary region between the IGBT region and the diode region of the semiconductor device according to the first preferred embodiment; Fig. 10 and Fig. Figure 11 are cross-sectional views, each representing a configuration of a termination area of ​​the semiconductor device according to the first preferred embodiment; Fig. Figures 12A to 17B are cross-sectional views, each representing a method of manufacturing the semiconductor device according to the first preferred embodiment; Fig. Figure 18 is a cross-sectional view showing a configuration of the semiconductor device according to the first preferred embodiment; Fig. 19 is a top view schematically representing a configuration of the semiconductor device according to the first preferred embodiment; Fig. Figure 20 is a top view schematically representing a configuration of a related device; Fig. 21 is a top view schematically representing a configuration of the semiconductor device according to the first preferred embodiment; Fig. 22 is a top view schematically representing a configuration of the semiconductor device according to a second preferred embodiment; Fig. 23 is an enlarged top view schematically representing a configuration of the semiconductor device according to a third preferred embodiment; Fig. 24 is an enlarged top view schematically representing a configuration of the semiconductor device according to a fourth preferred embodiment; Fig. 25 is an enlarged top view schematically representing a configuration of the semiconductor device according to a fifth preferred embodiment; Fig. Figure 26 is a top view schematically representing a configuration of the semiconductor device according to a sixth preferred embodiment; Fig. 27 is a top view schematically representing a configuration of the semiconductor device according to a seventh preferred embodiment; Fig. 28 is a top view schematically representing a configuration of the semiconductor device according to an eighth preferred embodiment; and Fig. Figure 29 is a top view schematically representing a configuration of the semiconductor device according to a ninth preferred embodiment. Description of preferred embodiments<Erste bevorzugte Ausführungsform>

[0008] In the following description, n and p represent a conductivity type of a semiconductor, and in the present disclosure, a first conductivity type is described as an n-type, and a second conductivity type is described as a p-type, but the first conductivity type can be described as an n-type, and the second conductivity type can be described as an n-type. Furthermore, n shows - that one impurity concentration is lower than that of n, and n + indicates that a contaminant concentration is higher than that of n. Similarly, p indicates - that one impurity concentration is lower than that of p, and p + indicates that a contaminant concentration is higher than that of p.

[0009] Fig. Figure 1 is a top view showing a semiconductor device that incorporates a reverse-conducting IGBT (RC-IGBT). Furthermore, Fig. 2 A top view showing another configuration of the semiconductor device comprising an RC-IGBT according to a first preferred embodiment. A Fig. The semiconductor device 100 shown in Figure 1 is provided with an IGBT region 10 and a diode region 20 arranged in a strip shape and can simply be referred to as a "strip type". The Fig. 2 The semiconductor device 100 shown is provided with a plurality of diode regions 20 in a longitudinal direction and a lateral direction, and the IGBT region 10 is provided around the diode region 20 and can simply be referred to as an “island type”. <Gesamtebenenstruktur des Streifentyps>

[0010] In Fig. Figure 1 of the semiconductor device 100 comprises the IGBT region 10 and the diode region 20. The IGBT region 10 and the diode region 20 extend from one end face to the other end face of the semiconductor device 100 and are arranged alternately in a strip shape in a direction orthogonal to a direction of extension of the IGBT region 10 and the diode region 20. Fig. Figure 1 represents a configuration in which three of the IGBT regions 10 and two of the diode regions 20 are shown, and all of the diode regions 20 are embedded between the IGBT regions 10. However, the number of IGBT regions 10 and diode regions 20 is not limited to these, and the number of IGBT regions 10 can be three or more or three or fewer, and the number of diode regions 20 can be two or more or two or fewer.

[0011] Furthermore, the configuration can be such that only the IGBT section 10 is provided, without including the diode section 20 at all. Alternatively, a metal-oxide-semiconductor field-effect transistor (MOSFET) can be provided instead of an IGBT, in which a section that functions as a collector of the IGBT section 10 is eliminated. Furthermore, a diode of the diode section 20 can be a freewheeling diode (FWD), a Schottky blocking diode (SBD), or a PN junction diode (PND). Furthermore, the configuration can be such that the IGBT section 10 and the diode section 20 are in Fig. The IGBT areas 10 are swapped in one position, or all IGBT areas 10 are embedded between the diode areas 20. Furthermore, the configuration can be such that the IGBT area 10 and the diode area 20 are individually adjacent to each other.

[0012] As in Fig. As shown in Figure 1, a contact area 40 is provided adjacent to the IGBT area 10 on the lower side of the diagram. Contact area 40 is an area where an electrode contact point 41 is provided for controlling the semiconductor device 100. In the following description, the IGBT area 10 and the diode area 20 can be referred to together as a cell area. A termination area 30 is provided around an area that combines the cell area and the contact area 40 to maintain the dielectric strength of the semiconductor device 100. A known dielectric strength retention structure can be suitably provided in the termination area 30.In the dielectric strength support structure, for example, a field limiting ring (FLR) surrounding a cell region with a p-type termination well layer of a p-type semiconductor, or a variation of lateral doping (VLD) surrounding a cell region with a p-type well layer exhibiting a concentration gradient, may be provided on the side of the first main surface, which is the side of the front surfaces of the semiconductor device 100. It should be noted that the number of annular p-type termination well layers used for an FLR and the concentration distribution used for a VLD must be appropriately selected according to a dielectric strength design of the semiconductor device 100.Furthermore, a p-type termination tray layer can be provided essentially over the entire contact point area 40, and an IGBT cell or a diode cell can be provided in the contact point area 40.

[0013] The electrode contact point 41, for example, has at least one current sensor contact point 41a, one Kelvin emitter contact point 41b, one gate contact point 41c, and temperature sensor diode contact points 41d and 41e. It should be noted that in the present description, for example, at least one of A, B, C, ... and Z means one of all combinations obtained by extracting one or more types from groups of A, B, C, ... and Z.

[0014] The current sensor junction 41a is an electrode junction for detecting a current flowing through a cell region of the semiconductor device 100. When a current flows through a cell region of the semiconductor device 100, the current sensor junction 41a is electrically connected to a portion of the cell region, such that a current of a fraction ranging from several tenths to several ten-thousandths of the current flowing through the entire cell region flows through an IGBT cell or a diode cell in a portion of the cell region.

[0015] The Kelvin emitter junction 41b and the gate junction 41c are electrode junctions to which a gate control voltage is applied for switching the semiconductor device 100 on and off. The Kelvin emitter junction 41b is electrically connected to a p-type base layer of an IGBT cell. The gate junction 41c is electrically connected to a gate trench electrode of an IGBT cell. The Kelvin emitter junction 41b and a p-type base layer can also be connected via a p +The temperature sensor diode contact points 41d and 41e are electrode contact points electrically connected to an anode and a cathode of a temperature sensor diode, which is a temperature sensor unit 50 provided in the semiconductor device 100. A voltage between an anode and a cathode of a temperature sensor diode (not shown), provided in a cell area, is measured by means of the temperature sensor diode contact points 41d and 41e, and the temperature of the semiconductor device 100 is measured based on the voltage. <Gesamtebenenstruktur des Inseltyps>

[0016] In Fig. Figure 2 of the semiconductor device 100 comprises the IGBT region 10 and the diode region 20 within a single semiconductor device. A plurality of diode regions 20 are arranged side by side in a longitudinal and a lateral direction within the semiconductor device 100, and the diode regions 20 are surrounded by the IGBT region 10. That is, a plurality of diode regions 20 are arranged in an island configuration within the IGBT region 10. Fig. Figure 2 represents a configuration in which the diode regions 20 are arranged in a matrix of four columns in a horizontal direction and two rows in a vertical direction in the diagram. However, the number and arrangement of the diode regions 20 are not limited to this configuration, and the configuration need only be one in which one or more of the diode regions 20 are embedded within the IGBT region 10, and the periphery of each of the diode regions 20 is surrounded by the IGBT region 10.

[0017] As in Fig. As shown in Figure 2, the contact area 40 is located adjacent to the lower side of the IGBT area 10 in the diagram. Contact area 40 is an area where an electrode contact point 41 is provided for controlling the semiconductor device 100. In this description, the IGBT area 10 and the diode area 20 are collectively referred to as a cell area. A termination area 30 is provided around this area, which combines the cell area and the contact area 40 to maintain the dielectric strength of the semiconductor device 100. A known dielectric strength retention structure can be suitably provided in the termination area 30.In the dielectric strength support structure, for example, on the side of the first main surface, which is the front surface of the semiconductor device 100, an FLR can be provided that surrounds an area combining the cell area and the contact area 40 with a p-type termination well layer of a p-type semiconductor, or a VLD can be provided that surrounds a cell area with a p-type well layer with a concentration gradient. It should be noted that the number of annular p-type termination well layers used for an FLR and the concentration distribution used for a VLD must be appropriately selected according to a dielectric strength design of the semiconductor device 100.Furthermore, a p-type termination tray layer can be provided over substantially the entire contact point area 40, and an IGBT cell or a diode cell can be provided in the contact point area 40.

[0018] The electrode contact point 41, for example, has at least one current sensor contact point 41a, one Kelvin emitter contact point 41b, one gate contact point 41c and temperature sensor diode contact points 41d and 41e.

[0019] The current sensor junction 41a is an electrode junction for detecting a current flowing through a cell region of the semiconductor device 100. When a current flows through a cell region of the semiconductor device 100, the current sensor junction 41a is electrically connected to a portion of the cell region, such that a current of a fraction ranging from several tenths to several ten-thousandths of the current flowing through the entire cell region flows through an IGBT cell or a diode cell in a portion of the cell region.

[0020] The Kelvin emitter junction 41b and the gate junction 41c are electrode junctions to which a gate control voltage is applied for switching the semiconductor device 100 on and off. The Kelvin emitter junction 41b is electrically connected to a p-type base layer and an n +The Kelvin emitter junction 41b and a p-type base layer are connected to the source layer of an IGBT cell. The gate junction 41c is electrically connected to a gate trench electrode of an IGBT cell. The Kelvin emitter junction 41b and a p-type base layer can also be connected via a p-type base layer. + The temperature sensor diode contact points 41d and 41e are electrode contact points electrically connected to an anode and a cathode of a temperature sensor diode, which is a temperature sensor unit 50 provided in the semiconductor device 100. A voltage between an anode and a cathode of a temperature sensor diode (not shown), provided in a cell area, is measured by means of the temperature sensor diode contact points 41d and 41e, and the temperature of the semiconductor device 100 is measured based on the voltage. <IGBT-Bereich 10>

[0021] Fig. Figure 3 is a partially enlarged top view showing a configuration of the IGBT area 10 of a semiconductor device, which is an RC-IGBT. In particular, Fig. 3 an enlarged view of an area defined by a dashed line 82 in the Fig. 1 and Fig. 2 depicted semiconductor device 100 is surrounded.

[0022] Furthermore, Fig. 4 and Fig. Five cross-sectional views showing a configuration of the IGBT area 10 of a semiconductor device, which is an RC-IGBT. In particular, Fig. 4 a cross-sectional view, drawn along a dashed line AA of the in Fig. 3 depicted semiconductor device 100 is included, and Fig. 5 is a cross-sectional view drawn along a dashed line BB of the Fig. 3 shown semiconductor device 100 is included.

[0023] As in Fig. Figure 3 shows an active trench gate 11 and a dummy trench gate 12 arranged in a strip configuration within the IGBT area 10. In the semiconductor device 100 of Fig. 1. The active trench gate 11 and the dummy trench gate 12 extend in a longitudinal direction of the IGBT region 10, and the longitudinal direction of the IGBT region 10 corresponds to a longitudinal direction of the active trench gate 11 and the dummy trench gate 12. In contrast, in the semiconductor device 100 of Fig. 2 a longitudinal direction and a lateral direction in the IGBT area 10 are not particularly distinguished, and a direction from left to right in the diagram may correspond to a longitudinal direction of the active trench gate 11 and the dummy trench gate 12, and a vertical direction in the diagram may correspond to a longitudinal direction of the active trench gate 11 and the dummy trench gate 12.

[0024] The active trench gate 11 is configured such that a gate trench electrode 11a is provided in a trench of a semiconductor substrate, with a gate trench insulation layer 11b inserted between them. The dummy trench gate 12 is configured such that a dummy trench electrode 12a is provided in a trench of a semiconductor substrate, with a dummy trench insulation layer 12b inserted between them. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate contact 41c of Fig. 1 and Fig. 2 connected. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode provided on the first main surface of the semiconductor device 100.

[0025] As in Fig. As shown in 3, there is an n +-Type source layer 13 is provided in contact with the gate trench insulation layer 11b on both sides in a lateral direction of the active trench gate 11. The n + The -type source layer 13 is also a type of semiconductor device, depending on the semiconductor device. + called a -type emitter layer. The n + -Type source layer 13 is a semiconductor layer that contains, for example, arsenic or phosphorus as an n-type impurity, and a concentration of the n-type impurity is 1.0E+17 / cm². 3 up to 1.0E+20 / cm 3 Furthermore, the n + -Type-Source layer 13 alternating with a p + A type contact layer 14 is provided along one extension direction of the active trench gate 11. Furthermore, the p + The type contact layer 14 is positioned between two adjacent dummy trench gates 12 in such a way that it is in contact with the dummy trench insulation layer 12b. The p +-Type contact layer 14 is a semiconductor layer that contains, for example, boron or aluminum as a p-type impurity, and a concentration of the p-type impurity is, for example, 1.0E+15 / cm². 3 up to 1.0E+20 / cm 3 .

[0026] As in Fig. As shown in Figure 3, in the IGBT region 10 of the semiconductor device 100, three of the dummy trench gates 12 are arranged next to an arrangement of three of the active trench gates 11. Then, three of the active trench gates 11, which differ from those described above, are arranged next to the three dummy trench gates 12 described above. The IGBT region 10 has a configuration in which a group of active trench gates 11 and a group of dummy trench gates 12 are arranged alternately, as described above. Fig. 3 is the number of active trench gates 11 contained in a group of active trench gates 11, but it can be any number, one or more. Furthermore, the number of dummy trench gates 12 contained in a group of dummy trench gates 12 can be one or more, and the number of dummy trench gates 12 can be zero. That is, all trench gates provided in the IGBT area 10 can be active trench gates 11.

[0027] Fig. Figure 4 is a cross-sectional view of the semiconductor device 100, taken along the dashed line AA in Fig. 3, and is a cross-sectional view of the IGBT area 10. The semiconductor device 100 has an n - -Type drift layer 1, which comprises a semiconductor substrate. The n --Type drift layer 1 is a semiconductor layer that contains, for example, arsenic or phosphorus as an n-type impurity, and a concentration of the n-type impurity is, for example, 1.0E+12 / cm². ® up to 1.0E+15 / cm 3 It should be noted that a concentration of the n-type impurity in the n described above + -Type source layer 13 is higher than a concentration of the n-type impurity in the n - -Type-Drift layer 1.

[0028] In Fig. 4 is a region of the semiconductor substrate, a region of the n + -Type-Source layer 13 and the p + -type contact layer 14 to a p-type collector layer 16. The p-type collector layer 16 is also called a p-type drain layer, depending on the semiconductor device. In Fig. 4 will be the upper end in the diagram of n + -Type-Source layer 13 and the p +The p-type contact layer 14 is designated as a first major surface of the semiconductor substrate, and a lower end in the diagram of the p-type collector layer 16 is designated as a second major surface of the semiconductor substrate. The first major surface of the semiconductor substrate is a major surface on the side of the front surface of the semiconductor device 100, and the second major surface of the semiconductor substrate is a major surface on the side of the back surface of the semiconductor device 100. The semiconductor device 100 has the n -A type drift layer 1 is located between the first main surface and the second main surface on the opposite side to the first main surface in the IGBT region 10, which is a cell region. It should be noted that the semiconductor substrate can, for example, have at least one wafer and one epitaxial growth layer. Furthermore, the semiconductor substrate can have a wide-bandgap semiconductor (silicon carbide (SiC), gallium nitride (GaN), and diamond), which enables stable operation at high temperatures.

[0029] As in Fig. As shown in Figure 4, in the IGBT area 10 there is an n-type charge carrier storage layer 2 which has a higher concentration of an n-type impurity than the n - -Type drift layer 1, on the first main surface side of the n -An n-type drift layer 1 is provided. The n-type charge carrier storage layer 2 is a semiconductor layer that contains, for example, arsenic or phosphorus as an n-type impurity, and a concentration of the n-type impurity is, for example, 1.0 E+13 / cm². 3 up to 1.0E+17 / cm 3 It should be noted that the semiconductor device 100 may have a configuration in which the n-type charge carrier storage layer 2 is not provided and the n - -Type drift layer 1 also in an area of ​​the in Fig. The n-type charge carrier storage layer 2 shown in Figure 4 is provided. By providing the n-type charge carrier storage layer 2, excitation loss when a current flows in the IGBT region 10 can be reduced. The n-type charge carrier storage layer 2 and the n - Type 1 drift layers can be referred to together as one drift layer.

[0030] The n-type charge carrier storage layer 2 is created by ion implantation of an n-type impurity into a semiconductor substrate, which contains the n - -Type drift layer 1 is formed, and then the implanted n-type impurity diffuses into the semiconductor substrate as the n - -Type drift layer 1 formed by annealing.

[0031] A p-type base layer 15 is provided on the side of the first main surface of the n-type charge carrier storage layer 2. The p-type base layer 15 is a semiconductor layer that contains, for example, boron or aluminum as a p-type impurity, and a concentration of the p-type impurity is, for example, 1.0 E+12 / cm². 3 up to 1.0E+19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulation layer 11b of the active trench gate 11. In the example of Fig. 4 the p-type base layer 15 is also in contact with the dummy trench insulation layer 12b of the dummy trench gate 12.

[0032] The n + -Type source layer 13 in contact with the gate trench insulation layer 11b of the active trench gate 11 is provided in a sub-area on the side of the first main surface of the p-type base layer 15, and the p + The -type contact layer 14 is selectively provided in the remaining area on the side of the first main surface of the p-type base layer 15. The n + -Type-Source layer 13 and the p + -Type contact layer 14 forms the first main surface of the semiconductor substrate. It should be noted that the p + -type contact layer 14 is an area that has a higher p-type impurity concentration than the p-type base layer 15. In a case where the p + Since the -type contact layer 14 and the p-type base layer 15 must be distinguished from each other, they can be designated individually, or in a case where the p +Since the -type contact layer 14 and the p-type base layer 15 do not need to be distinguished from each other, they can be referred to together as a p-type base layer.

[0033] Furthermore, on the side of the second main surface of the n - -Type drift layer 1 of the semiconductor device 100 provides an n-type buffer layer 3 which has a higher concentration of an n-type impurity than the n - -Type drift layer 1. The n-type buffer layer 3 is provided to prevent breakdown of a depletion layer extending from the p-type base layer 15 to the side of the second main surface when the semiconductor device 100 is in an off state. The n-type buffer layer 3 can be provided, for example, by introducing phosphorus (P) or a proton (H). + ) can be formed, or can be formed by introducing both phosphorus (P) and a proton (H). +) are formed. For example, a concentration of an n-type impurity in the n-type buffer layer 3 is 1.0 E+12 / cm². 3 up to 1.0E+18 / cm 3 It should be noted that the semiconductor device 100 may have a configuration in which the n-type buffer layer 3 is not provided, and the n - -Type drift layer 1 also in an area of ​​the in Fig. The n-type buffer layer 3 shown in section 4 is provided. The n-type buffer layer 3 and the n - Type 1 drift layers can be referred to together as one drift layer.

[0034] On the side of the second main surface of the n-type buffer layer 3 of the semiconductor device 100, the p-type collector layer 16 is provided. That is, the p-type collector layer 16 is located between the n -The p-type drift layer 1 and the second main surface are provided. The p-type collector layer 16 is a semiconductor layer that contains, for example, boron or aluminum as a p-type impurity, and a concentration of the p-type impurity is, for example, 1.0 E+16 / cm². 3 up to 1.0E+20 / cm 3 The p-type collector layer 16 forms the second main surface of the semiconductor substrate. The p-type collector layer 16 can be configured as a p-type termination collector layer 16a, which is described below, and can be located not only in the IGBT region 10 but also in the termination region 30. Furthermore, the p-type collector layer 16 can be configured to partially extend from the IGBT region 10 into the diode region 20.

[0035] As in Fig. Figure 4 shows a trench that penetrates the p-type base layer 15 from the first main surface of the semiconductor substrate and the n --Type drift layer 1 is reached in the IGBT area 10 of the semiconductor device 100. The gate trench electrode 11a is inserted into some trenches with the gate trench insulation layer 11b between them to form the active trench gate 11. The gate trench electrode 11a lies to the n - -type drift layer opposite, with the gate trench insulation layer 11b inserted between them. Furthermore, the dummy trench electrode 12a is provided in some trenches with the dummy trench insulation layer 12b inserted between them to form the dummy trench gate 12. The dummy trench electrode 12a lies opposite the n - -Type drift layer 1 opposite, with the dummy trench insulation layer 12b inserted between them.

[0036] The gate trench insulation layer 11b of the active trench gate 11 is in contact with the p-type base layer 15 and the n +-Type source layer 13. When a gate control voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate trench insulation layer 11b of the active trench gate 11.

[0037] As in Fig. As shown in Figure 4, an interlayer insulating layer 4 is provided on the gate-trench electrode 11a of the active-trench gate 11. A barrier metal 5 is formed on the interlayer insulating layer 4 in an area where it is not located on the first main surface of the semiconductor substrate. The barrier metal 5 can, for example, be a conductor containing titanium (Ti), and in particular can be titanium nitride or TiSi obtained by alloying titanium and silicon (Si). As shown in Fig. As shown in Figure 4, the barrier metal 5 is in ohmic contact with the n + -Type-Source layer 13, the p +-Type contact layer 14 and the dummy trench electrode 12a and is electrically connected to the n + -Type-Source layer 13, the p + -Type contact layer 14 and the dummy trench electrode 12a are connected. In contrast, the barrier metal 5 is electrically isolated from the gate trench electrode 11a by the interlayer insulating layer 4.

[0038] An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 can, for example, be made of an aluminum alloy, such as an aluminum-silicon alloy (Al-Si-based alloy), or it can be an electrode comprising multiple layers of metal foils, with a coating foil being formed on an electrode made of an aluminum alloy by electroless or electrolytic coating. The coating foil formed by electroless or electrolytic coating can, for example, be a nickel (Ni) coating foil.In a case where there is a fine region between adjacent intermediate insulation layers 4 or the like, wherein the region is one where favorable embedding cannot be obtained by the emitter electrode 6, a tungsten layer exhibiting better embedding properties than the emitter electrode 6 can be arranged in the fine region, and the emitter electrode 6 can be provided on the tungsten layer. It should be noted that the emitter electrode 6 is located on the n. + -Type-Source layer 13, the p + -type contact layer 14 and the dummy trench electrode 12a can be provided without the barrier metal 5. Furthermore, the barrier metal 5 may only be present on an n-type semiconductor layer, such as an n + -Type source layer 13 is provided. The barrier metal 5 and the emitter electrode 6 can together be referred to as an emitter electrode.

[0039] It should be noted that, although Fig. 4 represents a configuration in which the intermediate insulation layer 4 is not provided on the dummy trench electrode 12a of the dummy trench gate 12, the intermediate insulation layer 4 in a cross-sectional area of Fig. 4 may be provided on the dummy trench electrode 12a of the dummy trench gate 12. In a case where the intermediate insulation layer 4 is located in the cross-sectional area of Fig. 4 on the dummy trench electrode 12a of the dummy trench gate 12, the emitter electrode 6 and the dummy trench electrode 12a can be electrically connected in a different cross-sectional area.

[0040] A collector electrode 7 is provided on the side of the second main surface of the p-type collector layer 16. Similar to the emitter electrode 6, the collector electrode 7 can comprise an aluminum alloy or multiple layers of an aluminum alloy and a coating foil. The collector electrode 7 can have a configuration different from that of the emitter electrode 6. The collector electrode 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to it. It should be noted that a MOSFET can be provided instead of an IGBT without the p-type collector layer 16.

[0041] Fig. Figure 5 is a cross-sectional view of the semiconductor device 100, taken along the dashed line BB in Fig. 3, and is a cross-sectional view of the IGBT area 10. Unlike the cross-sectional part area, which is located along the in Fig. The section shown in section 4, indicated by the dashed line AA, is recorded in a cross-sectional area that runs along the line shown in Fig. 5 shown as dashed line BB is included, none of the n + -Type source layer 13, which is in contact with the active trench gate 11 and is located on the first side of the main surface of the semiconductor substrate. That is, the one in Fig. 3 shown n + The p-type source layer 13 is selectively located on the side of the first main surface of a p-type base layer. It should be noted that the p-type base layer referred to here is p-type base layer 15 and the p + -Type contact layer 14 may include. <Diodenbereich 20>

[0042] Fig. Figure 6 is a partially enlarged top view showing a configuration of the diode area 20 of the semiconductor device, which is an RC-IGBT. In particular, Fig. 6 an enlarged view of an area defined by a dashed line 83 in the Fig. 1 and Fig. 2 depicted semiconductor device 100 is surrounded.

[0043] Furthermore, Fig. 7 and Fig. Eight cross-sectional views showing a configuration of the diode area 20 of the semiconductor device, which is an RC-IGBT. In particular, Fig. 7 a cross-sectional view, drawn along a dashed line CC of the in Fig. 6 shown semiconductor device 100 is included, and Fig. 8 is a cross-sectional view drawn along a dashed line DD of the Fig. The semiconductor device 100 shown in section 6 is included.

[0044] A diode trench gate 21 extends along the first main surface of the semiconductor device 100 from one end face of the diode region 20 of a cell region in a direction opposite another end face. The diode trench gate 21 is formed by providing a diode trench electrode 21a inserted into a trench of the diode region 20 with a diode trench insulation layer 21b between them. The diode trench electrode 21a lies opposite the n - -Type drift layer 1 opposite, with the diode trench insulation layer 21b inserted between them.

[0045] A p + -type contact layer 24 and a p-type anode layer 25, which has a p-type impurity concentration that is lower than that of the p + -Type contact layer 24, are provided between two adjacent diode trench gates 21. The p +-Type contact layer 24 is a semiconductor layer that contains, for example, boron or aluminum as a p-type impurity, and a concentration of the p-type impurity is, for example, 1.E+15 / cm². 3 up to 1.0E+20 / cm 3 The p-type anode layer 25 is a semiconductor layer that contains, for example, boron or aluminum as a p-type impurity, and a concentration of the p-type impurity is, for example, 1.0 E+12 / cm². 3 up to 1.0E+19 / cm 3 . The p + The p-type contact layer 24 and the p-type anode layer 25 are arranged alternately in a longitudinal direction of the diode trench gate 21.

[0046] Fig. Figure 7 is a cross-sectional view of the semiconductor device 100, taken along the dashed line CC in Fig. 6, and is a cross-sectional view of the diode area 20. The semiconductor device 100 has the n --Type drift layer 1, which has a semiconductor substrate as in the IGBT region 10 and also in the diode region 20. The n - -Type drift layer 1 of the diode region 20 and the n - -Type drift layer 1 of the IGBT area 10 are continuous and formed in one piece and are formed from the same semiconductor substrate.

[0047] In Fig. 7 is an area of ​​the semiconductor substrate, an area of ​​the p + -Type contact layer 24 to a n + -Type cathode layer 26. In Fig. 7 will be an upper end in the diagram of the p + -Type contact layer 24 is designated as a first main surface of the semiconductor substrate, and a lower end in the diagram of the n +The -type cathode layer 26 is referred to as a second principal surface of the semiconductor substrate. The first principal surface of the diode region 20 and the first principal surface of the IGBT region 10 are contained in the same plane, and the second principal surface of the diode region 20 and the second principal surface of the IGBT region 10 are contained in the same plane.

[0048] As in Fig. As shown in Figure 7, the n-type charge carrier storage layer 2 is also located in the diode region 20, similar to the IGBT region 10, on the side of the first main surface of the n - -Type drift layer 1 is provided, and the n-type buffer layer 3 is on the side of the second main surface of the n -The n-type drift layer 1 is provided. The n-type charge carrier storage layer 2 and the n-type buffer layer 3 provided in diode area 20 can have the same configuration as the n-type charge carrier storage layer 2 and the n-type buffer layer 3 provided in IGBT area 10. It should be noted that the n-type charge carrier storage layer 2 is not necessarily provided in both IGBT area 10 and diode area 20, and, for example, the configuration can be such that the n-type charge carrier storage layer 2 is provided in IGBT area 10 but not in diode area 20. Furthermore, similar to IGBT area 10, the n - The -type drift layer 1, the n-type charge carrier storage layer 2 and the n-type buffer layer 3 together are referred to as a drift layer.

[0049] The p-type anode layer 25 is provided on the side of the first main surface of the n-type charge carrier storage layer 2. The p-type anode layer 25 is located between the n -The p-type drift layer 1 and the first main surface are provided. The concentration of a p-type impurity in the p-type anode layer 25 can be set to be the same as the concentration of a p-type impurity in the p-type base layer 15 of the IGBT area 10, and the p-type anode layer 25 and the p-type base layer 15 can be formed simultaneously. Furthermore, the concentration of a p-type impurity in the p-type anode layer 25 can be set to be lower than the concentration of a p-type impurity in the p-type base layer 15 of the IGBT area 10, in order to reduce the number of holes introduced into the diode area 20 during diode operation. By reducing the number of holes introduced during diode operation, recovery losses during diode operation can be reduced.

[0050] The p +The p-type contact layer 24 is provided on the side of the first main surface of the p-type anode layer 25. A concentration of a p-type impurity of the p + The concentration of a p-type impurity in the p-type contact layer 24 can be the same or different from that of a p-type impurity. + -Type contact layer 14 of the IGBT area 10. The p + The -type contact layer 24 forms the first main surface of the semiconductor substrate. It should be noted that the p + -type contact layer 24 is an area that has a higher concentration of a p-type impurity than the p-type anode layer 25, and in a case where it is necessary to remove the p + To distinguish between the -type contact layer 24 and the p-type anode layer 25, the p + -type contact layer 24 and the p-type anode layer 25 can be designated individually, and in a case where it is not necessary to designate the p +To distinguish between the -type contact layer 24 and the p-type anode layer 25, the p + The -type contact layer 24 and the p-type anode layer 25 together are referred to as a p-type anode layer.

[0051] The n + The -type cathode layer 26 is provided on the side of the second main surface of the n-type buffer layer 3 of the semiconductor device 100. That is, the n + -Type cathode layer 26 is located between the n - -Type drift layer 1 and the second main surface are provided. The n + -Type cathode layer 26 is a semiconductor layer that contains, for example, arsenic or phosphorus as an n-type impurity, and a concentration of the n-type impurity is, for example, 1.0E+16 / cm². 3 up to 1.0E+21 / cm 3 . The n + The -type cathode layer 26 is provided in part or all of the diode region 20. The n +The -type cathode layer 26 forms the second main surface of the semiconductor substrate. It should be noted that, although not shown, a p-type cathode layer, which is a p-type semiconductor layer, can be provided by further selective implantation of a p-type impurity into a portion of a region where the n + -Type cathode layer 26 is formed.

[0052] As in Fig. Figure 7 shows a trench that penetrates the p-type anode layer 25 from the first main surface of the semiconductor substrate and the n - -Type drift layer 1 is reached in the diode region 20 of the semiconductor device 100. The diode trench electrode 21a is provided in a trench of the diode region 20, with the diode trench insulation layer 21b inserted between them, so that the diode trench gate 21 is formed. The diode trench electrode 21a lies against the n --Type drift layer 1 opposite, with the diode trench insulation layer 21b inserted between them.

[0053] As in Fig. As shown in Figure 7, the barrier metal 5 is located on the diode trench electrode 21a and the p + A type contact layer 24 is provided. The barrier metal 5 is in ohmic contact with the diode trench electrode 21a and the p + -Type contact layer 24 and is electrically connected to the diode trench electrode 21a and the p + -Type contact layer 24 connected. The barrier metal 5 can have the same configuration as the barrier metal 5 in the IGBT area 10.

[0054] An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 provided in the diode region 20 is fully connected to the emitter electrode 6 provided in the IGBT region 10. It should be noted that, as in the case of the IGBT region 10, the diode trench electrode 21a and the p +-Type contact layer 24 can be brought into ohmic contact with the emitter electrode 6 without the provision of the barrier metal 5.

[0055] It should be noted that, although Fig. 7 represents the configuration in which the intermediate insulation layer 4 is as in Fig. 4 is not provided on the diode trench electrode 21a of the diode trench gate 21, the intermediate insulation layer 4 in a cross-sectional area of Fig. 7 may be provided on the diode trench electrode 21a. In the cross-sectional area of Fig. 7 In a case where the intermediate insulation layer 4 is provided on the diode trench electrode 21a of the diode trench gate 21, the emitter electrode 6 and the diode trench electrode 21a only need to be electrically connected in a different cross-sectional area.

[0056] The collector electrode 7 is located on the side of the second main surface of the n +A type cathode layer 26 is provided. Similar to the emitter electrode 6, the collector electrode 7 of the diode region 20 is formed continuously with the collector electrode 7 provided in the IGBT region 10. The collector electrode 7 is in ohmic contact with the n + -Type cathode layer 26 and is electrically connected to the n + -Type cathode layer 26 connected.

[0057] Fig. Figure 8 is a cross-sectional view of the semiconductor device 100, taken along the dashed line DD in Fig. 6, and is a cross-sectional view of the diode area 20. Unlike the cross-sectional part area, which is shown along the in Fig. The area shown in section 7, dashed line CC, is in a cross-sectional area that extends along the dashed line DD. Fig. 8 is recorded, the p +-Type contact layer 24 is not provided between the p-type anode layer 25 and the barrier metal 5, and the p-type anode layer 25 is the first major surface of the semiconductor substrate. That is, the one in Fig. 7 shown p + -Type contact layer 24 is selectively provided on the side of the first main surface of the p-type anode layer 25. <Konfiguration eines Grenzbereichs zwischen dem IGBT-Bereich 10 und dem Diodenbereich 20>

[0058] Fig. Figure 9 is a cross-sectional view showing a configuration of a boundary region between the IGBT region 10 and the diode region 20 of the semiconductor device, which is an RC-IGBT. In particular, Fig. 9 a cross-sectional view, drawn along a dashed line EE in the Fig. 1 and Fig. 2 shown semiconductor device 100 is included.

[0059] As in Fig. Figure 9 shows the p-type collector layer 16, which is provided on the side of the second main surface of the IGBT area 10, and the n + The p-type cathode layer 26, which is provided on the side of the second main surface of the diode region 20, is adjacent to each other in one direction in one plane of the semiconductor substrate. Then the p-type collector layer 16 is provided such that it projects by a distance U1 from a boundary between the IGBT region 10 and the diode region 20 in the direction of the side of the diode region 20.

[0060] As described above, by providing the p-type collector layer 16 such that it protrudes towards the diode region 20, a distance between the n +-type cathode layer 26 of the diode region 20 and the active trench gate 11 are enlarged. For this reason, even in a case where a gate control voltage is applied to the gate trench electrode 11a during freewheeling diode operation, it can be prevented that a current from a channel that is adjacent to the active trench gate 11 of the IGBT region 10 flows to the n + -Type cathode layer 26 flows. The distance U1 can be, for example, 100 µm. It should be noted that the distance U1 can be zero or less than 100 µm depending on the application of the semiconductor device 100, which is an RC-IGBT. <Terminierungsbereich 30>

[0061] Fig. 10 and Fig. Figure 11 shows cross-sectional views of a configuration of the termination area 30 of the semiconductor device 100, which is an RC-IGBT. In particular, Fig. 10 a cross-sectional view, which is along a Fig. 1 and Fig. The dashed line FF shown in section 2 is a cross-sectional view from IGBT area 10 to termination area 30. Furthermore, Fig. 11 a cross-sectional view, which is drawn along a Fig. GG is shown in the dashed line 1, and is a cross-sectional view from the diode area 20 to the termination area 30.

[0062] As in Fig. 10 and Fig. As shown in Figure 11, the termination area 30 of the semiconductor device 100 has the n - -Type drift layer 1 between the first main surface and the second main surface of the semiconductor substrate. The first main surface and the second main surface of the termination region 30 are each contained in the same plane as the first main surface and the second main surface of the IGBT region 10 and the diode region 20. Furthermore, the n --Type drift layer 1 of termination area 30 has the same configuration as the n - -Type drift layer 1 of each of the IGBT area 10 and the diode area 20 and is formed continuously and in one piece.

[0063] A p-type termination trough layer 31 is selectively located on the side of the first main surface of the n - -Type drift layer 1, that is, between the first main surface of the semiconductor substrate and the n - A p-type drift layer 1 is provided. The p-type termination well layer 31 is a semiconductor layer that contains, for example, boron or aluminum as a p-type impurity, and a concentration of the p-type impurity is, for example, 1.0 E+14 / cm². 3 up to 1.0E+19 / cm 3The p-type termination well layer 31 is designed to surround a cell region comprising the IGBT region 10 and the diode region 20. The p-type termination well layer 31 is provided in a plurality of ring shapes, and the number of termination well layers 31 to be provided is suitably selected according to a dielectric strength design of the semiconductor device 100. Furthermore, an n + -Type channel stopper layer 32 further provided on the side of the outer edge of the p-type termination trough layer 31, and the n + -Type channel stopper layer 32 surrounds the p-type termination trough layer 31 in a top view.

[0064] The p-type termination collector layer 16a is located between the n -The p-type drift layer 1 of the termination region 30 and the second main surface of the semiconductor substrate is provided. The p-type termination collector layer 16a is formed continuously and in one piece with the p-type collector layer 16, which is provided in the IGBT region 10 of a cell region. Therefore, the p-type collector layer 16, which includes the p-type termination collector layer 16a, can be referred to as a p-type collector layer.

[0065] In the configuration in which the diode area 20 is adjacent to the termination area 30, as in the Fig. In the semiconductor device 100 shown in Figure 1, the p-type termination collector layer 16a is as shown in Figure 1. Fig. Figure 11 is shown such that it has an end section on the side of the diode section 20, which projects from the diode section 20 by a distance U2. According to such a configuration, since there is a distance between the n +The distance between the p-type cathode layer 26 of the diode region 20 and the p-type termination well layer 31 can be increased, thus preventing the p-type termination well layer 31 from acting as an anode of a diode. The distance U2 can be, for example, 100 µm.

[0066] The collector electrode 7 is located on the second main surface of the semiconductor substrate. The collector electrode 7 extends in one continuous piece from a cell region, comprising the IGBT region 10 and the diode region 20, to the termination region 30.

[0067] In contrast, the emitter electrode 6 is provided on the first main surface of the semiconductor substrate of the termination region 30, and a terminal electrode 6a is structurally separated from the emitter electrode 6. The emitter electrode 6 and the terminal electrode 6a are electrically connected via a semi-insulating layer 33. The semi-insulating layer 33 can, for example, be semi-insulating silicon nitride (sinSiN). The terminal electrode 6a is electrically connected via a contact hole in the interlayer insulating layer 4, which is provided on the first main surface of the termination region 30, to each of the p-type termination well layers 31 and the n +The termination area 30 is connected to a type channel stopper layer 32. Furthermore, the termination area 30 is provided with a termination protection layer 34, which covers the emitter electrode 6, the terminal electrode 6a, and the semi-insulating layer 33. The termination protection layer 34 is, for example, polyimide. <Verfahren einer Fertigung eines RC-IGBTs>

[0068] Fig. Figures 12A to 17B are cross-sectional views illustrating a manufacturing process for a semiconductor device which is an RC-IGBT. Fig. 12A to 15B are diagrams that show a step in the main formation of the side of the front surface of the boundary region of Fig. 9 of the semiconductor device 100 represent, and Fig. Figures 16A to 17B are diagrams that show a step in the main formation of the side of the back surface of the boundary region of Fig. 9 of the semiconductor device 100.

[0069] First, as in Fig. 12A shows a semiconductor substrate prepared which the n - -type drift layer 1 is formed. The semiconductor substrate can be, for example, an FZ wafer produced by a floating-zone (FZ) process, an MCZ wafer produced by an applied magnetic field CZochralski (MCZ) process, or an n-type wafer containing an n-type impurity. The concentration of an n-type impurity contained in the semiconductor substrate is selected according to the voltage rating of the semiconductor device to be manufactured. For example, in a semiconductor device with a voltage rating of 1200 V, the concentration of an n-type impurity is adjusted so that the specific resistance of the n - The -type drift layer 1, which forms the semiconductor substrate, has a thickness of approximately 40 to 120 Ω·cm. As shown in Fig. As shown in Figure 12A, in the step of preparing the semiconductor substrate, the entire semiconductor substrate is the n - -Type drift layer 1. By implanting p-type or n-type impurity ions from the side of the first main surface or the side of the second main surface of such a semiconductor substrate and then diffusing the same into the semiconductor substrate by heat treatment or the like, a p-type or n-type semiconductor layer is suitably formed, and the semiconductor device 100 is produced.

[0070] As in Fig. As shown in 12A, the semiconductor substrate which supports the n -The -type drift layer 1 forms a region that is intended to be the IGBT region 10 and the diode region 20. Furthermore, although not shown, a region intended to be the termination region 30 and the like is provided around the region that is intended to be the IGBT region 10 and the diode region 20. The following mainly describes a method for manufacturing a configuration of the IGBT region 10 and the diode region 20 of the semiconductor device 100, but the termination region 30 and the like of the semiconductor device 100 can be manufactured by a known manufacturing method.For example, in a case where an FLR having the p-type termination well layer 31 as a dielectric strength support structure is formed in the termination region 30, the FLR can be formed by implanting p-type impurity ions before the IGBT region 10 and the diode region 20 of the semiconductor device 100 are processed. Alternatively, when a p-type impurity is ion-implanted into the IGBT region 10 or the diode region 20 of the semiconductor device 100, p-type impurity ions can be implanted simultaneously to form an FLR.

[0071] Next, as in Fig. Figure 12B shows an n-type impurity such as phosphorus (P) being implanted from the first major surface of the semiconductor substrate to form the n-type charge carrier storage layer 2. Furthermore, a p-type impurity such as boron (B) is implanted from the first major surface of the semiconductor substrate to form the p-type base layer 15 and the p-type anode layer 25. The n-type charge carrier storage layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed by implanting impurity ions into a semiconductor substrate and then diffusing the impurity ions through heat treatment. Since the ion implantation of an n-type impurity and a p-type impurity is performed after mask processing is carried out on the first main surface of the semiconductor substrate, different layers are selectively formed on the side of the front surface of the semiconductor substrate.The n-type charge carrier storage layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed in the IGBT region 10 and the diode region 20 and are connected to the p-type termination well layer 31 in the termination region 30. Mask processing is the application of a cover material to a semiconductor substrate, the creation of an opening in a predetermined area of ​​the cover material using photolithography, and the formation of a mask on the semiconductor substrate to perform ion implantation or etching on the predetermined area of ​​the semiconductor substrate through the opening. Through the mask processing and ion implantation described above, the n-type charge carrier storage layer 2, the p-type base layer 15 and the p-type anode layer 25 are selectively formed on the side of the first main surface of the IGBT area 10 and the diode area 20.Similarly, the p-type termination trough layer 31 is selectively formed in the termination area 30.

[0072] The p-type impurities of the p-type base layer 15 and the p-type anode layer 25 can be implanted simultaneously. In this case, the depths and p-type impurity concentrations of the p-type base layer 15 and the p-type anode layer 25 are the same. Alternatively, the p-type impurities of the p-type base layer 15 and the p-type anode layer 25 can be ion-implanted separately using mask processing to achieve different depths and p-type impurity concentrations for the p-type base layer 15 and the p-type anode layer 25.

[0073] The p-type impurities of the p-type termination trough layer 31 and the p-type anode layer 25 of the termination area 30, which is not in Fig. As shown in Figure 12B, ions can be implanted simultaneously. In this case, the depths and p-type impurity concentrations of the p-type termination well layer 31 and the p-type anode layer 25 are the same. Alternatively, the p-type impurities of the p-type termination well layer 31 and the p-type anode layer 25 can be ion-implanted separately by mask processing to ensure that the depths and p-type impurity concentrations of the p-type termination well layer 31 and the p-type anode layer 25 differ. Alternatively, the p-type impurities of the p-type termination well layer 31 and the p-type anode layer 25 are simultaneously ion-implanted using masks that have different opening ratios, so that p-type impurity concentrations of the p-type termination well layer 31 and the p-type anode layer 25 can be designed differently from each other.In this case, the open-cell ratios of the masks need only differ by using one or both of the masks as a mesh-like mask. Similarly, the p-type impurities of the p-type termination well layer 31, the p-type base layer 15, and the p-type anode layer 25 can be ion-implanted simultaneously using masks with different open-cell ratios, so that the p-type impurity concentrations of the p-type termination well layer 31, the p-type base layer 15, and the p-type anode layer 25 can be designed differently from one another. The p-type termination well layer 31, the p-type base layer 15, and the p-type anode layer 25 can be formed by ion implantation of the p-type impurities at the same time.

[0074] Next, as in Fig. 13A shown, the n +The p-type source layer 13 on the side of the first main surface of the p-type base layer 15 in the IGBT region 10 is selectively formed by mask processing and n-type impurity implantation. The n-type impurity to be implanted can be, for example, arsenic (As) or phosphorus (P). Furthermore, the p-type source layer 13 is selectively formed by mask processing and p-type impurity implantation. + -Type contact layer 14 selectively formed on the side of the first main surface of the p-type base layer 15 of the IGBT region 10, and the p + The p-type contact layer 24 is selectively formed on the side of the first main surface of the p-type anode layer 25 of the diode region 20. The p-type impurity to be implanted can be, for example, boron (B) or aluminum (Al).

[0075] Next, as in Fig. Figure 13B shows a trench 8 which penetrates the p-type base layer 15 and the p-type anode layer 25 from the side of the first main surface of the semiconductor substrate and the n - -Type drift layer 1 is reached and formed. In the IGBT area 10, a side wall of the trench 8, which comprises the n + -Type-Source layer 13 penetrates a part of the n + -Type-Source layer 13. In the IGBT area 10, a side wall of the trench 8, which contains the p + -Type contact layer 14 penetrates a part of the p + -Type contact layer 14. In the diode region 20, a side wall of the trench 8, which comprises the p + -Type contact layer 24 penetrates a part of the p + -Type contact layer 24.

[0076] The trench 8 is formed, for example, by applying an oxide layer of SiO2 or the like to a semiconductor substrate, forming an opening in the oxide layer in a sub-area where the trench 8 is to be formed by mask processing, and etching the semiconductor substrate using the oxide layer in which the opening is formed as a mask. Fig. In 13B, the trenches 8 are formed at the same distance between the IGBT area 10 and the diode area 20, but the spacing of the trenches 8 can be designed differently between the IGBT area 10 and the diode area 20. The spacing and pattern of the trenches 8 in a top view can be suitably modified according to a mask pattern of a mask edit.

[0077] Next, as in Fig. Figure 14A shows the semiconductor substrate being heated in an oxygen-containing atmosphere to form an oxide layer 9 on an inner wall of the trench 8 and on the first main surface of the semiconductor substrate. The oxide layer 9 formed on the trench 8 of the IGBT region 10 is the gate trench insulation layer 11b of the active trench gate 11 and the dummy trench insulation layer 12b of the dummy trench gate 12. Furthermore, the oxide layer 9 formed on the trench 8 of the diode region 20 is the diode trench insulation layer 21b. The oxide layer 9 formed on the first main surface of the semiconductor substrate is subsequently removed, except for a portion formed on the trench 8.

[0078] Next, as in Fig. Figure 14B shows polysilicon doped with n-type or p-type impurities applied to the oxide layer 9 in the trench 8 by chemical vapor deposition (CVD) or the like to form the gate trench electrode 11a, the dummy trench electrode 12a and the diode trench electrode 21a.

[0079] Next, as in Fig. Figure 15A shows the interlayer insulation layer 4 formed on the gate-trench electrode 11a of the active-trench gate 11 of the IGBT region 10. The interlayer insulation layer 4 can, for example, be SiO2. By forming a contact hole in the applied insulation layer, which is to be the interlayer insulation layer 4, and removing the oxide layer 9, which is formed on the first main surface of the semiconductor substrate by masking, the interlayer insulation layer 4 and the like are formed in Fig. 15A is formed. The contact hole of the intermediate insulation layer 4 is located on the n + -Type-Source layer 13, the p + -Type contact layer 14, the p + -Type contact layer 24, the dummy trench electrode 12a and the diode trench electrode 21a are formed.

[0080] Next, as in Fig. Figure 15B shows the barrier metal 5 formed on the first main surface of the semiconductor substrate and on the interlayer insulating layer 4, and the emitter electrode 6 is further formed on the barrier metal 5. The barrier metal 5 is formed by forming a layer of titanium nitride by physical vapor deposition (PVD) or CVD.

[0081] The emitter electrode 6 can be formed, for example, by depositing an aluminum-silicon alloy (Al-Si-based alloy) onto the barrier metal 5 using PVD processes such as sputtering or vapor deposition. Furthermore, a nickel alloy (Ni alloy) can be applied to the aluminum-silicon alloy by electroless or electrolytic coating to form the emitter electrode 6. When the emitter electrode 6 is formed by coating, a thick metal layer can be used to create the emitter electrode 6, thereby increasing its heat absorption capacity and improving its heat resistance.It should be noted that if a nickel alloy is further formed by a coating operation on the emitter electrode 6 after the emitter electrode 6, which is made of an aluminum-silicon alloy, has been formed by PVD, the coating operation to form the nickel alloy can be carried out after the side of the second main surface of the semiconductor substrate has been machined.

[0082] Next, as in Fig. Figure 16A shows the side of the second main surface of the semiconductor substrate ground to thin the semiconductor substrate to a designed, predetermined thickness. The thickness of the semiconductor substrate after grinding can be, for example, 80 µm to 200 µm.

[0083] Next, as in Fig. Figure 16B shows an n-type impurity being implanted from the side of the second main surface of the semiconductor substrate to form the n-type buffer layer 3. A p-type impurity is also implanted from the side of the second main surface of the semiconductor substrate to form the p-type collector layer 16. The n-type buffer layer 3 can be formed in the IGBT region 10, the diode region 20, the termination region 30, and so on, or it may be formed only in the IGBT region 10 or the diode region 20. The n-type buffer layer 3 can be formed, for example, by implanting phosphorus (P-) ions, protons (H+), or both protons and phosphorus. Protons can be introduced from the second main surface of the semiconductor substrate to a deep position with a relatively low acceleration energy.Furthermore, the depth to which protons are introduced can be relatively easily changed by altering the acceleration energy. Therefore, if the n-type buffer layer 3 is formed from protons, and implantation is performed multiple times by changing the acceleration energy, the n-type buffer layer 3 can be formed thicker in one thickness direction of the semiconductor substrate than the phosphorus layer.

[0084] Furthermore, since phosphorus can increase the activation rate as an n-type impurity compared to protons, if the n-type buffer layer 3 is formed from phosphorus, breakdown of a depletion layer can be prevented even in a dilute semiconductor substrate. To make the semiconductor substrate even thinner, it is preferable to form the n-type buffer layer 3 by introducing both protons and phosphorus, and in this case, protons are introduced to a deeper position from the second main surface than phosphorus.

[0085] The p-type collector layer 16 can be formed, for example, by the introduction of boron (B). The p-type collector layer 16 is also formed in the termination region 30, and the p-type collector layer 16 in the termination region 30 becomes the p-type termination collector layer 16a. After ion implantation from the side of the second primary surface of the semiconductor substrate, the second primary surface is irradiated with a laser for laser annealing, so that the implanted boron is activated to form the p-type collector layer 16. At the same time, phosphorus, which is introduced at a relatively shallow position from the second primary surface of the semiconductor substrate, is also activated.Since, on the other hand, protons are activated at a relatively low annealing temperature, such as 350°C to 500°C, it is necessary to be careful that the temperature of the entire semiconductor substrate does not exceed 350°C to 500°C, except for the proton activation step after the protons have been introduced. Because laser annealing can raise the temperature only near the second main surface of the semiconductor substrate, it can be used to activate both n-type and p-type impurities, even after protons have been implanted.

[0086] Next, as in Fig. 17A shown, the n + -Type cathode layer 26 is formed on the side of the second main surface of the diode region 20. The n + -Type cathode layer 26 can be formed, for example, by introducing arsenic (As), phosphorus (P), or the like. As in Fig. As shown in Figure 17A, an n-type impurity is selectively implanted from the side of the second main surface by a masking process, so that a boundary between the p-type collector layer 16 and the n + The -type cathode layer 26 is arranged at a position at a distance U1 from a boundary between the IGBT region 10 and the diode region 20 in the direction of the side of the diode region 20. An implantation quantity of an n-type impurity to form the n + The -type cathode layer 26 is larger than the implantation quantity of a p-type impurity to form the p-type collector layer 16. In Fig. 17A are depths of the p-type collector layer 16 and the n + -Type cathode layer 26 from the second main surface shown so that they are the same, but with a depth of n + The -type cathode layer 26 is equal to or greater than one depth of the p-type collector layer 16. In a region where the n +Since it is necessary to introduce an n-type impurity into an area where a p-type impurity is implanted in order to finally make the area an n-type, the concentration of the n-type impurity must be higher than the concentration of the p-type impurity implanted in the entire area where the n + -Type cathode layer 26 is formed.

[0087] Next, as in Fig. Figure 17B shows the collector electrode 7 formed on the second primary surface of the semiconductor substrate. The collector electrode 7 is formed over the entire surface of the second primary surface, such as the IGBT region 10, the diode region 20, and the termination region 30. Furthermore, the collector electrode 7 can be formed over the entire surface of the second primary surface of an n-type wafer as a semiconductor substrate. The collector electrode 7 can be formed by depositing an aluminum-silicon alloy (Al-Si-based alloy), titanium (Ti), or the like by PVD such as sputtering or vapor deposition, or it can be formed by laminating multiple pieces of metal, such as an aluminum-silicon alloy, titanium, nickel, or gold.Furthermore, the collector electrode 7 can be formed by further forming a metal layer by electroless coating or electrolytic coating on the metal layer formed by PVD.

[0088] The semiconductor device 100 is manufactured by the preceding steps. A majority of the semiconductor devices 100 are manufactured in a state where they are integrated in a matrix on a semiconductor substrate, such as an n-type wafer. For this reason, the semiconductor device 100 is individually cut by laser cutting or blade cutting. <Temperatursensoreinheit 50>

[0089] Fig. Figure 18 is a cross-sectional view showing a configuration of the semiconductor device according to the first preferred embodiment. The semiconductor device according to the first preferred embodiment includes not only the RC-IGBT described above but also the components shown in Fig. 2, Fig. 3 and Fig. 18 The temperature sensor unit 50 shown is a polysilicon element.

[0090] As in Fig. As shown in Figure 18, the semiconductor device according to the first preferred embodiment comprises the temperature sensor unit 50, a semiconductor substrate 51, a lower insulating layer 52, an upper insulating layer 54, a cathode electrode 55 and an anode electrode 56.

[0091] The semiconductor substrate 51 is the semiconductor substrate described above and has a front surface 51a, which is the first main surface. The temperature sensor unit 50 is provided on a different area than a main current-carrying area, such as the IGBT area 10, on the front surface 51a of the semiconductor substrate 51 by means of the lower insulating layer 52. The temperature sensor unit 50 has an n + -Type cathode area 53a, a p + -Type anode area 53b and a p- -Type drift range 53c on. The n + -Type cathode area 53a, the p + -Type anode area 53b and the p - Type drift area 53c is provided on the lower insulation layer 52.

[0092] A contamination of the n + -Type cathode area 53a can be the same as a contamination of the n + -Type-Source layer 13 of Fig. 9. Furthermore, contamination of the p + -Type anode area 53b be the same as an impurity of the p + -Type contact layer 14 of Fig. 9. The p - -Type drift range 53c is between the n + -Type cathode area 53a and the p + -Type anode area 53b is provided, and an impurity concentration of p - -Type drift range 53c is lower than a contamination concentration of the p + -Type anode range 53b.

[0093] The upper insulation layer 54 covers an upper part area and a side part area of ​​the temperature sensor unit 50 and has a contact hole for exposing the n + -Type cathode area 53a and a contact hole for exposing the p + -Type anode area 53b. It should be noted that the lower insulating layer 52 and the upper insulating layer 54 may be thermal oxide layers.

[0094] The cathode electrode 55 is electrically connected to the n + -Type cathode area 53a connected in a contact hole that the n + -Type cathode region 53a is exposed. The anode electrode 56 is electrically connected to the p + -Type anode area 53b connected in a contact hole that the p + -Type anode area 53b is exposed. The temperature sensor unit 50, as described above, functions as a temperature sensor diode.

[0095] It should be noted that in Fig. 18 a width of the n+ -type cathode region 53a in a cross-sectional view, that is, a length in a plane direction with reference to an upward direction, which is a direction from a rear surface of the semiconductor substrate 51 towards the front surface 51a, but the present invention is not limited thereto. Furthermore, in the example of Fig. 18 a width of the n + -Type cathode region 53a in a cross-sectional view with respect to the upward direction is continuously monotonically increasing, but can change stepwise with respect to the upward direction. In the configuration in which a width of n + By changing the type of cathode region 53a in a cross-sectional view with reference to a direction from a rear surface of the semiconductor substrate 51 towards the front surface 51a, a transition area of ​​a pn junction can be enlarged. <Verdrahtung der Temperatursensoreinheit>

[0096] Fig. Figure 19 is a top view (top view) which schematically represents a configuration of the semiconductor device according to the first preferred embodiment. Fig. 19 is a diagram that schematically illustrates the configuration, particularly in Fig. 2 and Fig. 3 is shown, represents, and the configuration of Fig. 19 is slightly different from the configuration of Fig. 2 and Fig. 3. It should be noted that a dotted area in Fig. 19 indicates an effective area, such as a cell range.

[0097] As in Fig. The figures shown in 19 are those in Fig. 4. The emitter electrode 6 and the like are selectively provided on a front surface of the semiconductor substrate 51. In the first preferred embodiment, one emitter electrode 6 is generally provided on each of the left and right sides of the semiconductor substrate 51. It should be noted that, although in Fig. Figure 19 (not shown) shows a plurality of second wire-bond sub-areas connected to a plurality of wires through which an emitter current (that is, a main current flowing through a channel of an IGBT and the emitter electrode 6) flows on the emitter electrode 6. In such a configuration, the area of ​​a path through which the emitter current flows can be designed to be large.

[0098] The temperature sensor unit 50 is provided on a front surface of the semiconductor substrate 51 and adjacent to the emitter electrode 6. In the first preferred embodiment, the temperature sensor unit 50 is provided on the inner side as a terminal end of the semiconductor substrate 51 in a top view and between the emitter electrodes 6 to the left and right.

[0099] One form of the emitter electrode 6 comprises a projecting sub-region 61b which, in a top view from a main body sub-region 61a of the emitter electrode 6, projects towards the outside of the emitter electrode 6. In the first preferred embodiment, the projecting sub-region 61b is provided in a top view at a terminal end (i.e., the termination region 30) of the semiconductor substrate 51 and projects in one direction (first direction) opposite to a Y-direction.

[0100] A cathode wiring 62, which is a sensor wiring, is provided along the emitter electrode 6. One end of the cathode wiring 62 is connected to the temperature sensor unit 50, and another end of the cathode wiring 62 is connected to the emitter electrode 6 (the aforementioned sub-section 61b). According to such a configuration, since a part of the emitter electrode 6 can be used as a cathode contact point, which is a type of electrode contact point 41 in Fig. 2 and Fig. 3. Not only is an area needed only for a cathode contact point removed, but a reduction of an ineffective area and an improvement in composability can also be expected.

[0101] In the first preferred embodiment, the cathode wiring 62 comprises a first sensor wiring section 62a, a second sensor wiring section 62b, and a curved section 62c. The first sensor wiring section 62a extends in a direction (first direction) opposite to the Y-direction from the inner side to a terminal end of the semiconductor substrate 51 between the emitter electrodes 6 on the left and right in a top view. The second sensor wiring section 62b extends from the first sensor wiring section 62a to the connection section 63 between the emitter electrode 6 and the cathode wiring 62 along an X-direction (second direction) that differs from the extension direction (first direction) of the first sensor wiring section 62a at a terminal end of the semiconductor substrate 51.The curved section 62c is a section between the first sensor wiring section 62a and the second sensor wiring section 62b.

[0102] An anode wiring 64 is provided adjacent to the emitter electrode 6, similar to the cathode wiring 62. One end of the anode wiring 64 is connected to the temperature sensor unit 50, and another end of the anode wiring 64 is connected to an anode contact point 65, which is a type of electrode contact point 41 in Fig. 2 and Fig. 3. A wire-bonded sub-area 66, which is connected to a wire (not shown), for reading an anode potential of the temperature sensor unit 50 is provided at the anode contact point 65.

[0103] It should be noted that in the first preferred embodiment, in a region between the emitter electrodes 6 on the left and right, where the first sensor wiring section 62a is provided, the anode wiring 64, which is a type of wiring having a potential different from that of the cathode wiring 62, is provided, but the present invention is not limited thereto. In this region, for example, gate wiring or the like, as a wiring with a different potential, can also be provided, which is a wiring having a potential different from that of the cathode wiring 62.Furthermore, in an area from the first sensor wiring section 62a to the connection section 63, where the second sensor wiring section 62b is provided, for example a gate wiring or the like may also be provided as a wiring of a different potential, which is a wiring that has a potential that is different from that of the cathode wiring 62.

[0104] A first wire-bonded section 67, connected to a wire (not shown), for reading a cathode potential of the temperature sensor unit 50, is provided on the emitter electrode 6 and adjacent to the connecting section 63 between the emitter electrode 6 (the foregoing section 61b) and the cathode wiring 62. In the first preferred embodiment, the distance from the connecting section 63 to the first wire-bonded section 67 is shorter than the distance from the bent section 62c to the connecting section 63.

[0105] Gate contact point 41c in Fig. 2 and Fig. 3, which is separate from the emitter electrode 6, is provided on the side opposite the cathode wiring 62 with reference to the connection section 63. A wire-bond section 69, to which a wire (not shown) for supplying a gate control voltage to the gate trench electrode 11a is connected, is provided at the gate contact point 41c. It should be noted that the electrode contact point in Fig. 2 and Fig. 3 a different electrode contact point than the emitter electrode 6 used as a cathode contact point, the anode contact point 65 and the gate contact point 41c may be provided.

[0106] Fig. Figure 20 is a top view schematically representing a configuration of a related device related to the semiconductor device according to the first preferred embodiment, and is a top view relating to Fig. 19 corresponds. In the related device of Fig. 20 The emitter electrode 6 is not provided with the foreground sub-section 61b. For this reason, a gap exists between the first wire-bond sub-section 67 and the connecting part 70 between the cathode wiring 62 and the emitter electrode 6. Fig. 20 longer than a distance between the connecting part area 63 and the first wire bond part area 67 in Fig. 19. In such a configuration, since a cathode potential of the temperature sensor unit 50, which is read by a wire of the first wire-bond sub-area 67, is strongly influenced by an emitter current flowing through the emitter electrode 6, the cathode potential of the temperature sensor unit 50 cannot be measured correctly.

[0107] On the other hand, in the first preferred embodiment, the distance from the connecting part section 63 to the first wire-bond section 67 is shorter than the distance from the bent section 62c to the connecting part section 63. According to such a configuration, since the influence that the cathode potential of the temperature sensor unit 50, which is read from a wire of the first wire-bond section 67, receives from the emitter current flowing through the emitter electrode 6 can be reduced, the cathode potential of the temperature sensor unit 50 can be measured correctly.

[0108] Furthermore, in the first preferred embodiment, the gate contact point 41c, which is separated from the emitter electrode 6, is located on the side opposite the cathode wiring 62 with respect to the connection section 63. According to this configuration, it is possible to prevent an emitter current flowing through the emitter electrode 6 from flowing in a region on the side opposite the cathode wiring 62 with respect to the connection section 63. This further reduces the influence that the cathode potential of the temperature sensor unit 50, which is read by a wire of the first wire-bond section 67, receives from the emitter current flowing through the emitter electrode 6, thus ensuring that the cathode potential of the temperature sensor unit 50 can be measured correctly.

[0109] It should be noted that, although the emitter electrode 6 has the aforementioned sub-section 61b in the preceding description, the emitter electrode 6 does not necessarily have to have the aforementioned sub-section 61b, as described in Fig. 21. This applies similarly to the second and subsequent preferred embodiments. <Zweite bevorzugte Ausführungsform>

[0110] Fig. 22 is a top view schematically representing a configuration of the semiconductor device according to the second preferred embodiment, and is a top view that is related to Fig. 19 corresponds.

[0111] In the first preferred embodiment, the projecting sub-section 61b extends in one direction (first direction) opposite to the Y-direction. In contrast, in the second preferred embodiment, the projecting sub-section 61b extends in the X-direction (second direction).

[0112] Furthermore, in the first preferred embodiment, the cathode wiring 62 extends in one direction (first direction) opposite to the Y-direction and, by being bent in the middle, extends in the X-direction (second direction). In contrast, in the second preferred embodiment, the cathode wiring 62 is not bent in the middle and, in a top view, extends in one direction (first direction) opposite to the Y-direction from the inner side of the semiconductor substrate 51 to the projecting section 61b at the terminal end. Furthermore, in the second preferred embodiment, the distance from the connection section 63 to the first wire-bond section 67 is shorter than the distance from the temperature sensor unit 50 to the connection section 63.According to the present second preferred embodiment, as described above, a cathode potential of the temperature sensor unit 50 can be measured accurately, similar to the first preferred embodiment.

[0113] It should be noted that in the second preferred embodiment, the anode wiring 64, which is a type of wiring having a potential different from that of the cathode wiring 62, is provided in a region between the emitter electrodes 6 on the left and right, where the cathode wiring 62 is provided, but the present invention is not limited thereto. In this region, for example, gate wiring or the like, as a wiring of a different potential, may also be provided, which is a wiring having a potential different from that of the cathode wiring 62. Furthermore, the cathode wiring 62 may be slightly bent, provided that, in a top view, the cathode wiring 62 extends in one direction (first direction) opposite to the Y-direction from the inner side of the semiconductor substrate 51 to the emitter electrode 6 at a terminal end. <Dritte bevorzugte Ausführungsform>

[0114] Fig. Figure 23 is an enlarged top view schematically representing a configuration of the semiconductor device according to a third preferred embodiment, and is an enlarged top view of a periphery of the interconnection part area 63 in Fig. 19. It should be noted that Fig. Figure 23 represents a plurality of second wire-bond sub-regions 73 connected by a wire (not shown) through which an emitter current flows. A plurality of second wire-bond sub-regions 73 are provided on the emitter electrode 6 on the side opposite the connecting sub-region 63 with respect to the first wire-bond sub-region.

[0115] In the third preferred embodiment, as indicated by a dashed line in Fig. Figure 23 shows the cathode wiring 62, the connection section 63, and the emitter electrode 6 forming a U-shape in a top view. An insulating component is provided in a slot-shaped section 72 within a U-shape, and various electrodes, such as a gate electrode, are not present. According to this configuration, the area of ​​the emitter electrode 6 can be maximized. This effect can be further enhanced by making the slot-shaped section 72 as thin as possible. It should be noted that, although the third preferred embodiment is based on the configuration of the first preferred embodiment in Fig. 19, the third preferred embodiment is applied to the configuration of the second preferred embodiment in Fig. 22 can be applied. <Vierte bevorzugte Ausführungsform>

[0116] Fig. 24 is an enlarged top view schematically representing a configuration of the semiconductor device according to a fourth preferred embodiment, and is an enlarged top view that is shown to Fig. 23 corresponds.

[0117] In the fourth preferred embodiment, an active cell is provided on the semiconductor substrate 51 in a square, as indicated by a dashed line in Fig. Displayed as 24, with a line segment 75 between the connection sub-area 63 and the first wire-bond sub-area 67 as a diagonal line. The active cell corresponds, for example, to a part of the IGBT area 10.

[0118] An emitter current flowing through the active cell flows towards a plurality of wires (a plurality of main emitter wirings) (not shown) which are connected to the emitter electrode 6 by a plurality of second wire-bond sub-areas 73. At this time, in a square provided with the active cell, a cathode potential of the temperature sensor unit 50, which is read from a wire of the first wire-bond sub-area 67, is strongly influenced by an emitter current flowing through the emitter electrode 6.

[0119] In light of the foregoing, in the fourth preferred embodiment, since the distance between the connection section 63 and the first wire-bond section 67 is shortened such that ΔV = Is × ρ × L < 0.7 × N is satisfied, the aforementioned influence can be reduced. In the above equation, L is the length of the line segment 75, which is a diagonal line, Is is a current density in a cross-sectional direction flowing between the connection section 63 and the first wire-bond section 67, p is a specific resistance of the emitter electrode 6, N is the number of series of diodes included in the temperature sensor unit 50, and ΔV is a voltage between the connection section 63 and the first wire-bond section 67.

[0120] In the preceding equation, 0.7 is a value of a predetermined silicon potential. The temperature of the temperature sensor unit 50 is measured based on the difference between predetermined potentials before and after a change in the temperature of the temperature sensor unit 50. To enable such a measurement, in the fourth preferred embodiment, the voltage ΔV is set by the preceding equation such that it is a value within a range of predetermined potentials. In a case where the number of diodes contained in the temperature sensor unit 50 is N, the voltage ΔV in the fourth preferred embodiment is set by the preceding equation such that it is a value within a range of predetermined potentials corresponding to the number of diodes.In the fourth preferred embodiment, since the setting described above is achieved by the equation above, the temperature of the temperature sensor unit 50 can be suitably measured.

[0121] It should be noted that in the fourth preferred embodiment, the metal of the emitter electrode 6 is aluminum and the resistivity ρ of the emitter electrode 6 is the resistivity of aluminum, but the resistivity ρ can be changed depending on the metal used for the emitter electrode 6. <Fünfte bevorzugte Ausführungsform>

[0122] Fig. 25 is an enlarged top view schematically representing a configuration of the semiconductor device according to a fifth preferred embodiment, and is an enlarged top view that is shown to Fig. 22 corresponds.

[0123] Fig. Figure 25 represents a line segment 76 extending from the first wire-bond segment 67 to one end of the emitter electrode 6 in a straight line, which extends from the second wire-bond segment 73 through the first wire-bond segment 67 to the end of the emitter electrode 6. In the fifth preferred embodiment, an active cell is provided on a semiconductor substrate in a substantially triangular region surrounded by the line segment 76 and one end of the emitter electrode 6. In a quadrilateral provided with the active cell as described above, a cathode potential of the temperature sensor unit 50, which is read by a wire of the first wire-bond segment 67, is strongly influenced by the emitter current flowing through the emitter electrode 6, similar to the fourth preferred embodiment.

[0124] In light of the foregoing, in the fifth preferred embodiment, since the distance between the connecting part section 63 and the first wire-bond section 67 is shortened such that ΔV = Is × ρ × L < 0.7 × N is satisfied, the aforementioned influence can be reduced. It should be noted that in the above equation, L is a length of the line section 76. Other values ​​of Is, ρ, N, and ΔV are similar to those in the fourth preferred embodiment. According to such a configuration, since the voltage ΔV is set to be a value within a set of predetermined potentials corresponding to the number of diodes contained in the temperature sensor unit 50, the temperature of the temperature sensor unit 50 can be suitably measured. <Variation der vierten und fünften bevorzugten Ausführungsformen>

[0125] The voltage ΔV can be 50% or less of a range between the lower and upper limits of a standard voltage for the temperature sensor unit 50. For example, if the lower and upper limits of a standard voltage for the temperature sensor unit 50 are 1.8 V and 2.2 V, respectively, the voltage ΔV can be 0.2 V (= 0.4 V × 50%). In such a configuration, the temperature measurement accuracy of the temperature sensor unit 50 can be improved compared to a configuration where the voltage ΔV exceeds 50% of the aforementioned range. Furthermore, in a configuration where the voltage ΔV is 30% or less of the aforementioned range, the temperature measurement accuracy of the temperature sensor unit 50 can be improved compared to a configuration where the voltage ΔV exceeds 30% of the aforementioned range.Furthermore, in a configuration where the voltage ΔV is 10% or less of the aforementioned range of the temperature sensor unit 50, the temperature measurement accuracy of the temperature sensor unit 50 can be improved compared to a configuration where the voltage ΔV exceeds 10% of the aforementioned range of the temperature sensor unit 50. Furthermore, in a configuration where the voltage ΔV is 1% or less of the aforementioned range of the temperature sensor unit 50, the temperature measurement accuracy of the temperature sensor unit 50 can be improved compared to a configuration where the voltage ΔV exceeds 1% of the aforementioned range of the temperature sensor unit 50. <Sechste bevorzugte Ausführungsform>

[0126] Fig. 26 is a top view schematically representing a configuration of the semiconductor device according to a sixth preferred embodiment, and is a top view that is shown to Fig. 19 corresponds.

[0127] In the sixth preferred embodiment, an insulating layer 78 is provided, which covers the emitter electrode 6 and the front surface 51a of the semiconductor substrate 51. It should be noted that in Fig. 26 the emitter electrode 6 covered with the insulating layer 78 is indicated by a dashed line.

[0128] The insulating layer 78 has openings 78a, 78b, 78c and 78d. Opening 78a exposes the second wire-bond sub-area 73 in Fig. 23 and Fig. 24. Opening 78b exposes the first wire-bond sub-area 67. Opening 78c exposes the wire-bond sub-area 66 of the anode contact point 65. Opening 78d exposes the wire-bond sub-area 69 of the gate contact point 41c. According to such a configuration, the influence of an external factor can be reduced by the insulating layer 78.

[0129] It should be noted that the insulating layer 78 can cover the emitter electrode 6 and the front surface 51a in at least one sub-region other than the area between the first wire-bond sub-region 67 and an end (i.e., a terminal end) of the semiconductor substrate 51, while exposing the first wire-bond sub-region 67. According to such a configuration, the first wire-bond sub-region 67 can be located further away from the second wire-bond sub-region 73 by the amount provided by the insulating layer 78. For this reason, it is possible to reduce the influence of the emitter current flowing through the emitter electrode 6 on the cathode potential of the temperature sensor unit 50, which is read from a wire of the first wire-bond sub-region 67. <Siebte bevorzugte Ausführungsform>

[0130] Fig. 27 is a top view schematically representing a configuration of the semiconductor device according to a seventh preferred embodiment, and is a top view that is shown to Fig. 19 corresponds. It should be noted that in Fig. 27 the insulating layer 78 described in the sixth preferred embodiment is provided, but this is not essential in the seventh preferred embodiment.

[0131] In the seventh preferred embodiment, an area where the first wire-bond sub-area 67 is provided in the semiconductor substrate 51 is not dotted and is an ineffective area of ​​the p-type termination tray layer 31 and the like. According to such a configuration, it is possible to reduce the influence of an emitter current flowing through the emitter electrode 6 on the cathode potential of the temperature sensor unit 50, which is read from a wire of the first wire-bond sub-area 67. <Achte bevorzugte Ausführungsform>

[0132] Fig. 28 is a top view schematically representing a configuration of the semiconductor device according to an eighth preferred embodiment, and is a top view that is to Fig. 19 corresponds. It should be noted that in Fig. 28 the insulating layer 78 described in the sixth preferred embodiment is provided, but this is not essential in the eighth preferred embodiment. Furthermore, in Fig. 28 similar to the seventh preferred embodiment, a region where the first wire-bond sub-region 67 is provided in the semiconductor substrate 51, an ineffective region, but this is not essential in the eighth preferred embodiment.

[0133] In the eighth preferred embodiment, the anode wiring 64 overlaps, as a wiring in a top view, at least a portion of the cathode wiring 62. For example, in an overlapping partial area 79 of Fig. 28 on one of the cathode wiring 62 and the anode wiring 64, the other is provided with an insulating layer inserted between them, and the cathode wiring 62 and the anode wiring 64 overlap in a Z-direction of Fig. 28 in a state that they are isolated from each other. According to such a configuration, since the areas of the cathode wiring 62 and the anode wiring 64 can be reduced in a top view, for example an area of ​​an active cell or the like can be enlarged. <Neunte bevorzugte Ausführungsform>

[0134] Fig. 29 is a top view schematically representing a configuration of the semiconductor device according to a ninth preferred embodiment, and is a top view that is shown to Fig. 19 corresponds. It should be noted that in Fig. 29 the insulating layer 78 described in the sixth preferred embodiment is provided, but this is not essential in the ninth preferred embodiment.

[0135] In the ninth preferred embodiment, the semiconductor substrate 51 has a rectangular shape in a top view, with a long side 80a extending along the X-direction and a short side 80b extending along the Y-direction. The first wire-bond section 67 is then located on the side of the long side 80a of the semiconductor substrate 51. According to such a configuration, since the lengths of the cathode wiring 62 and the anode wiring 64 can be shortened compared to a configuration in which the first wire-bond section 67 is located on the side of the short side 80b of the semiconductor substrate 51, for example, the area of ​​an active cell and the like can be enlarged.

[0136] It should be noted that in the present revelation, "a" and "an" mean one or more in English. For this reason, "a", "an", "one or more" and "at least one" can be used interchangeably.

[0137] It should be noted that the preferred embodiments and variations can be freely combined, and the preferred embodiments and variations can be suitably modified or omitted.

[0138] The following section describes various aspects of the present revelation together as an appendix. (Appendix 1)

[0139] Semiconductor device comprising: a semiconductor substrate that has a first main surface; an emitter electrode that is selectively provided on the first main surface; a temperature sensor unit which is provided on the first main surface and adjacent to the emitter electrode further on an inner side as a terminal end of the semiconductor substrate in a top view; a sensor wiring system comprising one end connected to the temperature sensor unit and another end connected to the emitter electrode at the terminal end of the semiconductor substrate, wherein the sensor wiring is provided along the emitter electrode; and a first wire-bond sub-area provided on the emitter electrode and adjacent to a connection sub-area between the emitter electrode and the sensor wiring, wherein the sensor wiring has: a first sensor wiring section that extends in a top view in a first direction from the inner side of the semiconductor substrate to the terminal end; a second sensor wiring section that extends from the first sensor wiring section to the connection section at the terminal end along a second direction that differs from the first direction of the first sensor wiring section; and a curved section between the first sensor wiring section and the second sensor wiring section, and a distance from the connecting part area to the first wire-bonded part area is shorter than a distance from the bent part area to the connecting part area. (Appendix 2)

[0140] Semiconductor device comprising: a semiconductor substrate that has a first main surface; an emitter electrode that is selectively provided on the first main surface; a temperature sensor unit which is provided on the first main surface and adjacent to the emitter electrode further on an inner side as a terminal end of the semiconductor substrate in a top view; a sensor wiring system comprising one end connected to the temperature sensor unit and another end connected to the emitter electrode at the terminal end of the semiconductor substrate, wherein the sensor wiring is provided along the emitter electrode; and a first wire-bond sub-area provided on the emitter electrode and adjacent to a connection sub-area between the emitter electrode and the sensor wiring, wherein the sensor wiring extends in a top view in a first direction from the inner side of the semiconductor substrate to the terminal end, and The distance from the connection section to the first wire-bond section is shorter than the distance from the temperature sensor unit to the connection section. (Appendix 3)

[0141] Semiconductor device comprising: a semiconductor substrate that has a first main surface; an emitter electrode that is selectively provided on the first main surface; a temperature sensor unit provided on the first main surface and adjacent to the emitter electrode; a sensor wiring system having one end connected to the temperature sensor unit and another end connected to the emitter electrode, wherein the sensor wiring is provided along the emitter electrode; and a first wire-bond sub-area provided on the emitter electrode and adjacent to a connection sub-area between the emitter electrode and the sensor wiring, wherein the sensor wiring, the connection section and the emitter electrode as a whole have a U-shape in a top view, and An electrode is missing in a section of the U-shape. (Appendix 4)

[0142] Semiconductor device comprising: a semiconductor substrate that has a first main surface; an emitter electrode that is selectively provided on the first main surface; a temperature sensor unit provided on the first main surface; a sensor wiring system having one end connected to the temperature sensor unit and another end connected to the emitter electrode; and a first wire-bond sub-area provided on the emitter electrode and adjacent to a connection sub-area between the emitter electrode and the sensor wiring, wherein an active cell is provided on the semiconductor substrate in a square which has a line segment between the connection part area and the first wire-bond part area as a diagonal line, and If L is the length of the diagonal line, Is is the current density in a cross-sectional direction flowing between the connection part area and the first wire-bond part area, ρ is the specific resistance of the emitter electrode, N is the number of series of diodes included in the temperature sensor unit, and ΔV is the voltage between the connection part area and the first wire-bond part area, then ΔV = Is × ρ × L < 0.7 × N applies. (Appendix 5)

[0143] Semiconductor device comprising: a semiconductor substrate that has a first main surface; an emitter electrode that is selectively provided on the first main surface; a temperature sensor unit provided on the first main surface; a sensor wiring system that has one end connected to the temperature sensor unit and another end connected to the emitter electrode; a first wire-bond sub-area provided on the emitter electrode and adjacent to a connection sub-area between the emitter electrode and the sensor wiring; and a second wire-bond sub-area provided on the emitter electrode on one side opposite the connection sub-area with reference to the first wire-bond sub-area, wherein an active cell is provided on the semiconductor substrate in an area surrounded by one end of the emitter electrode and a line section extending from the first wire-bond section to the end of the emitter electrode in a straight line extending from the second wire-bond section to the end of the emitter electrode through the first wire-bond section, and If the length of the line section is L, the current density in a cross-sectional direction flowing between the connection section and the first wire-bond section is Is, the specific resistance of the emitter electrode is p, the number of series of diodes included in the temperature sensor unit is N, and the voltage between the connection section and the first wire-bond section is ΔV, then ΔV = Is × ρ × L < 0.7 × N applies. (Appendix 6)

[0144] Semiconductor device according to Appendix 4 or 5, wherein The ΔV is 50% or less of a range between the upper and lower limits of a standard voltage of the temperature sensor unit. (Appendix 7)

[0145] Semiconductor device according to Appendix 4 or 5, wherein The ΔV is 30% or less of a range between the upper and lower limits of a standard voltage of the temperature sensor unit. (Appendix 8)

[0146] Semiconductor device according to Appendix 4 or 5, wherein The ΔV is 10% or less of a range between the upper and lower limits of a standard voltage of the temperature sensor unit. (Appendix 9)

[0147] Semiconductor device according to Appendix 4 or 5, wherein The ΔV is 1% or less of a range between the upper and lower limits of a standard voltage of the temperature sensor unit.

[0148] (Appendix 10)

[0149] Semiconductor device according to any one of Appendices 1 to 9, further comprising: an electrode contact point which is provided on one side opposite the sensor wiring with reference to the connection part area and separate from the emitter electrode. (Appendix 11)

[0150] Semiconductor device according to any one of Appendices 1 to 10, further comprising: an insulating layer covering the emitter electrode and the first main surface, and having an opening through which the first wire-bond sub-area is exposed. (Appendix 12)

[0151] Semiconductor device according to any of Appendices 1 to 10, further comprising an insulating layer covering the emitter electrode and the first main surface in at least one sub-region other than a region between the first wire-bond sub-region and an end of the semiconductor substrate, while exposing the first wire-bond sub-region. (Appendix 13)

[0152] Semiconductor device according to any one of Appendices 1 to 12, wherein an area where the first wire-bond sub-area is provided in the semiconductor substrate is an ineffective area. (Appendix 14)

[0153] Semiconductor device according to any of Appendices 1 to 13, further comprising wiring connected to the temperature sensor unit and overlapping in a top view with at least part of the sensor wiring. (Appendix 15)

[0154] Semiconductor device according to any one of Appendices 1 to 14, wherein the semiconductor substrate has a rectangular shape in a top view, and the first wire bond sub-area is provided on one side of a long side of the semiconductor substrate.

[0155] Although the revelation has been shown and described in detail, the foregoing description is descriptive in all aspects and not limiting. It is therefore understood that numerous modifications and variations can be devised. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] WO 2015 / 029159

[0002]

Claims

[1] Semiconductor device comprising: a semiconductor substrate (51) having a first main surface (51a); an emitter electrode (6) which is selectively provided on the first main surface (51a); a temperature sensor unit (50) which is provided on the first main surface (51a) and adjacent to the emitter electrode (6) further on an inner side as a terminal end of the semiconductor substrate (51) in a top view; a sensor wiring (62) having one end connected to the temperature sensor unit (50) and another end connected to the emitter electrode (6) at the terminal end of the semiconductor substrate (51), wherein the sensor wiring (62) is provided along the emitter electrode (6); and a first wire-bond sub-area (67) which is provided on the emitter electrode (6) and adjacent to a connection sub-area (63) between the emitter electrode (6) and the sensor wiring (62), wherein the sensor wiring (62) has: a first sensor wiring section (62a) which extends in a top view in a first direction from the inner side of the semiconductor substrate (51) to the terminal end; a second sensor wiring section (62b) extending from the first sensor wiring section (62a) to the connection section (63) at the terminal end along a second direction that differs from the first direction of the first sensor wiring section (62a); and a curved section (62c) between the first sensor wiring section (62a) and the second sensor wiring section (62b), and a distance from the connecting part area (63) to the first wire bonding part area (67) is shorter than a distance from the bent part area (62c) to the connecting part area (63). [2] Semiconductor device comprising: a semiconductor substrate 51), which has a first main surface (51a); an emitter electrode (6) which is selectively provided on the first main surface (51a); a temperature sensor unit (50) which is provided on the first main surface (51a) and adjacent to the emitter electrode (6) further on an inner side as a terminal end of the semiconductor substrate (51) in a top view; a sensor wiring (62) having one end connected to the temperature sensor unit (50) and another end connected to the emitter electrode (6) at the terminal end of the semiconductor substrate (51), wherein the sensor wiring (62) is provided along the emitter electrode (6); and a first wire-bond sub-area (67) which is provided on the emitter electrode (6) and adjacent to a connection sub-area (63) between the emitter electrode (6) and the sensor wiring (62), wherein the sensor wiring (62) extends in a top view in a first direction from the inner side of the semiconductor substrate (51) to the terminal end, and a distance from the connection part area (63) to the first wire bond part area (67) is shorter than a distance from the temperature sensor unit (50) to the connection part area (63). [3] Semiconductor device comprising: a semiconductor substrate (51) having a first main surface (51a); an emitter electrode (6) which is selectively provided on the first main surface (51a); a temperature sensor unit (50) which is provided on the first main surface (51a) and adjacent to the emitter electrode (6); a sensor wiring (62) having one end connected to the temperature sensor unit (50) and another end connected to the emitter electrode (6), wherein the sensor wiring (62) is provided along the emitter electrode (6); and a first wire-bond sub-area (67) which is provided on the emitter electrode (6) and adjacent to a connection sub-area (63) between the emitter electrode (6) and the sensor wiring (62), wherein the sensor wiring (62), the connection part area (63) and the emitter electrode (6) together have a U-shape in a top view, and An electrode is missing in a section of the U-shape. [4] Semiconductor device comprising: a semiconductor substrate (51) having a first main surface (51a); an emitter electrode (6) which is selectively provided on the first main surface (51a); a temperature sensor unit (50) provided on the first main surface (51a); a sensor wiring (62) having one end connected to the temperature sensor unit (50) and another end connected to the emitter electrode (6); and a first wire-bond sub-area (67) which is provided on the emitter electrode (6) and adjacent to a connection sub-area (63) between the emitter electrode (6) and the sensor wiring (62), wherein an active cell is provided on the semiconductor substrate (51) in a square which has a line segment (75) between the connection part area (63) and the first wire bond part area (67) as a diagonal line, and if L is the length of the diagonal line, Is is the current density in a cross-sectional direction flowing between the connection part area (63) and the first wire-bond part area (67), ρ is the specific resistance of the emitter electrode (6), N is the number of series of diodes included in the temperature sensor unit (50), and ΔV is the voltage between the connection part area (63) and the first wire-bond part area (67), ΔV = Is × ρ × L < 0.7 × N applies. [5] Semiconductor device comprising: a semiconductor substrate (51) having a first main surface (51a); an emitter electrode (6) which is selectively provided on the first main surface (51a); a temperature sensor unit (50) provided on the first main surface (51a); a sensor wiring (62) which has one end connected to the temperature sensor unit (50) and another end connected to the emitter electrode (6); a first wire-bond sub-area (67) provided on the emitter electrode (6) and adjacent to a connection sub-area (63) between the emitter electrode (6) and the sensor wiring (62); and a second wire-bond sub-area (73) which is provided on the emitter electrode (6) on one side opposite the connection sub-area (63) with reference to the first wire-bond sub-area (67), wherein an active cell is provided on the semiconductor substrate (51) in an area surrounded by an end of the emitter electrode (6) and a line section (76) from the first wire-bond section (67) to the end of the emitter electrode (6) in a straight line extending from the second wire-bond section (73) to the end of the emitter electrode (6) through the first wire-bond section (67), and if the length of the line section (76) is L, the current density in a cross-sectional direction flowing between the connection section (63) and the first wire-bond section (67) is Is, the specific resistance of the emitter electrode (6) is ρ, the number of series of diodes included in the temperature sensor unit (50) is N, and the voltage between the connection section (63) and the first wire-bond section (67) is ΔV, then ΔV = Is × ρ × L < 0.7 × N applies. [6] Semiconductor device according to claim 4 or 5, wherein the ΔV is 50% or less of a range between upper and lower limits of a standard voltage of the temperature sensor unit (50). [7] Semiconductor device according to claim 4 or 5, wherein the ΔV is 30% or less of a range between upper and lower limits of a standard voltage of the temperature sensor unit (50). [8] Semiconductor device according to claim 4 or 5, wherein the ΔV is 10% or less of a range between upper and lower limits of a standard voltage of the temperature sensor unit (50). [9] Semiconductor device according to claim 4 or 5, wherein the ΔV is 1% or less of a range between upper and lower limits of a standard voltage of the temperature sensor unit (50). [10] Semiconductor device according to one of claims 1 to 9, further comprising an electrode contact point (41c) which is provided on one side opposite the sensor wiring (62) with reference to the connecting part area (63) and separate from the emitter electrode (6). [11] Semiconductor device according to any one of claims 1 to 10, further comprising an insulating layer (78) covering the emitter electrode (6) and the first main surface (51a) and having an opening through which the first wire-bond sub-area (67) is exposed. [12] Semiconductor device according to any one of claims 1 to 10, further comprising an insulating layer (78) which covers the emitter electrode (6) and the first main surface (51a) in at least one sub-area other than an area between the first wire-bond sub-area (67) and an end of the semiconductor substrate (51), while exposing the first wire-bond sub-area (67). [13] Semiconductor device according to any one of claims 1 to 12, wherein a region where the first wire-bond sub-region (67) is provided in the semiconductor substrate (51) is an ineffective region. [14] Semiconductor device according to any one of claims 1 to 13, further comprising a wiring (64) which is connected to the temperature sensor unit (50) and overlaps in a top view with at least a part of the sensor wiring (62). [15] Semiconductor device according to any one of claims 1 to 14, wherein the semiconductor substrate (51) has a rectangular shape in a top view, and the first wire bond sub-area (67) is provided on one side of a long side (80a) of the semiconductor substrate (51).

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