MULTI-PHASE POWER CONVERTER CONTROL

Abstract

In the described examples, a device includes a first and second inductor, a first and second phase-shifting circuit, a proportional-integral (PI) compensator, and a controller. The first and second phase-shifting circuits are coupled to the first and second inductors, respectively. The controller is coupled to the first and second phase-shifting circuits and the PI compensator. The controller performs the following actions: It generates a phase error signal in response to a phase difference between a first and second control signal corresponding to the first and second phase-shifting circuits, respectively, a switching period, and a target phase delay between the first and second control signals. It supplies the phase error signal to the PI compensator. And it controls the first and second phase-shifting circuits in a first phase and a second phase in response to the first and second control signals, respectively.second control signal and a PI compensator output signal.

Description

TECHNICAL FIELDThis application relates generally to pulse width modulation (PWM) control of power converters, and more particularly to PWM control of polyphase power converters.BACKGROUNDIn some examples, a PWM signal is used to control a switched device, such as a power converter. One power converter example is a Zero Voltage Switching (ZVS-QSW) converter that enables efficient (low-loss) supply of power. Some example ZVS QSW converters are boost converters. A boost converter increases a voltage from its input to its output while reducing a current. Exemplary applications for power converters include server, telecommunication, automobile, industrial, and other power supply applications.Some applications, such as certain high power applications, utilize polyphase interleaved converters. In some examples, polyphase converters use multiple circuits of different phases coupled to respective primary energy storage devices such as inductors. Control signals of the circuits of different phases are out of phase with respect to each other. In some example interleaved converters, there is a fixed phase relationship between the various phases below the operating frequency (or frequencies). Deviation from the intended or specified fixed phase relationship, particularly if persistent, may cause converter inefficiency or instability.SUMMARYIn described examples, an apparatus includes first and second inductors, first and second phase switching circuits, a proportional-integral (PI) compensator, and a controller. The first and second phase switching circuits are coupled to the first and second inductors, respectively. The controller is coupled to the first and second phase switching circuits and the PI compensator. The controller performs the following actions. It generates a phase error signal responsive to a phase difference between first and second control signals corresponding to the first and second phase switching circuits, respectively, a switching period, and a target phase delay between the first and second control signals. It supplies the phase error signal to the PI compensator. And it controls the first and second phase switching circuits in a first phase and a second phase responsive to the first and second control signals, respectively, and a PI compensator output signal.In described examples, an apparatus includes first and second inductors, first and second phase switching circuits, and a controller. A first terminal of the first phase switching circuit is coupled to a first terminal of the first inductor. A first terminal of the second phase switching circuit is coupled to a first terminal of the second inductor. The controller includes a proportional-integral (PI) compensator. First and second outputs of the controller are coupled to control terminals of the first and second phase switching circuits, respectively. The third output of the controller is coupled to the first input of the PI compensator. The controller performs the following actions. It generates a phase error signal responsive to a switching period, a target phase delay of the second control signal with respect to the first control signal, and a phase difference between a first control signal corresponding to the first phase switching circuit and a second control signal corresponding to the second phase switching circuit. It supplies the phase error signal to the first input of the PI compensator. And it controls the first phase switching circuit in a first phase and the second phase switching circuit in a second phase responsive to the first and second control signals and an output signal of the PI compensator.In the described examples, a device includes a sensor, a first phase switching circuit, a second phase switching circuit, a gate driver, and a controller. The first and second outputs of the gate driver are coupled to the control terminals of the first and second phase switching circuits, respectively. The controller includes a PI compensator. An input of the controller is coupled to an output of the sensor. A first output of the controller is coupled to the input of the gate driver. A second output of the controller is coupled to a first input of the PI compensator. The controller performs the following actions. It generates a phase error signal responsive to a phase difference between a switching period, a target phase delay of the second control signal with respect to the first control signal, and a first control signal corresponding to the first phase switching circuit, and a second control signal corresponding to the second phase switching circuit. It supplies the phase error signal to the first input of the PI compensator. And it controls the first phase switching circuit in a first phase and the second phase switching circuit in a second phase responsive to the first and second control signals and an output signal of the PI compensator.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1A is a functional block diagram and circuit diagram of an example power conversion system. FIG. 1B is a functional block diagram and circuit diagram of a second example power conversion system. FIG. 1C is a functional block diagram and circuit diagram of a third example power conversion system. FIG. 2A is a first set of graphs of example signals corresponding to PWM control of the first phase circuit of the power converter system of FIG. 1A. FIG. 2B is a second set of graphs of example signals corresponding to PWM control of the first phase circuit of the power converter system of FIG. 1A. FIG. 3A is a state plane diagram of example signals of the power converter system of FIG. 1A responsive to PWM control as described with reference to FIGS. 2A and 2B. FIG. 3B is a set of tables showing equations described with reference to FIG. 3A, enabling example control of the boost converter system 100 of FIG. 1A. FIG. 4 is a functional block diagram of an example of the phase timing adjustment (PTA) module of FIG. 1A. FIG. 5 is a process flow diagram of an example process for generating a phase delay timing adjustment value using the PTA module of FIGS. 1 and 4. FIG. 6 is a graph of exemplary inductor current versus time for the power converter system of FIG. 1A responsive to phase timing adjustment as described with reference to FIGS. 4 and 5. FIG. 7 is a graph of example signals of the power converter system of FIG. 1A responsive to a delay between an input voltage measurement by the signal sensor and processing of the input voltage measurement. FIG. 8 is a functional block diagram of a compensation module for correcting a measured input voltage for measurement and / or signal path delay. FIG. 9 is a process flow diagram of an example process for correcting a measured input voltage value responsive to measurement and signal path delay as described with reference to FIG. 8. FIG. 10 is a graph of total harmonic distortion in an output signal versus load in the power conversion system of FIG. 1A.DETAILED DESCRIPTIONPolyphase boost converters are useful in a variety of applications, such as industrial and automotive applications. Polyphase boost converters include a first phase circuit connected to and transferring power across a first inductor and a second phase circuit connected to and transferring power across a second inductor. Switches of the first phase circuit control application of energy to the first inductor to store or discharge magnetic energy. Similarly, switches of the second phase circuit control application of energy to the second inductor to store or discharge magnetic energy.The second phase switches are controlled to open and close with a phase delay with respect to control of the first phase switches. This phase delay may be provided using a delay circuit that provides second phase control signals having a delay time responsive to a set of input, feedback, and control information along with certain physical characteristics of the power converter. For example, for two phase circuits, a phase delay of 180 degrees (x radians) is used, and for a Pth (P is a number) phase circuit of a number of N phase circuits in a power converter, a phase delay of (P-1)*(360 degrees) / N or (P-1)*(2π radians) / N is used. In some examples, various counters are used to determine on (enable) and off (disable) timings and to determine a phase delay duration. In one example, a phase delay counter is reset responsive to a first phase circuit off event, such as the one falling edge of a corresponding PWM control signal, and a turn-on of the second phase circuit is responsive to the counter exceeding a threshold corresponding to a particular phase delay. In some examples, other counter reset triggers or other types of comparison are used to determine a phase delay end.Some ZVS QSW power converters are used in power factor correction (PFC) applications. In some examples, power obtained from an alternating current (AC) power supply line in which current and voltage are not in phase causes or is correlated with generation of harmonics in the power signal. In an AC power signal, phase-shifted current(s) and voltage and / or harmonics may result in wasted power. In one example, a PFC power converter shapes power drawn from an AC power supply line such that a waveform of a current drawn is a sine wave having a same shape as and in phase with a corresponding voltage waveform, so that harmonics are reduced, enabling reduced power loss.In some examples, a ZVS QSW PFC power converter uses a triangular current mode (TCM) controller with multiple interleaved phases with precisely timed switch control to reduce input ripple current and improve system efficiency. Zero current detection (ZCD) control may be used to improve cycle-by-cycle control of a synchronous rectifier in a ZVS QSW power converter. In one example, a ZCD controller corresponds to switch-off timing responsive to detecting a zero current through the switch. In some examples, an effective switching period of a power converter system using ZCD control changes from cycle to cycle responsive to variations in signal levels corresponding to voltage and temperature fluctuations. In such examples, counter values or thresholds of a target designed phase delay may not track fast enough or accurate enough to meet design requirements.An example ZVS QSW boost converter system 100 is further described below with reference to FIG. 1A. Precise deterministic control of the boost converter system 100 of FIG. 1A is further described with reference to FIGS. 2A, 2B, 3A, and 3B. Described systems and processes enable more accurate determination of switch timing and other control parameters to improve stability and efficiency of an interleaved polyphase ZVS QSW power converter.Two example approaches to improving switch control of an interleaved polyphase ZVS QSW power converter are described herein. The first approach relates to deviations of phase delay and / or current balance between different phases of a polyphase converter from designed values. In some examples, such deviations are caused by event detection delay or process variation. A phase delay offset may be measured after manufacture, such as during a device test, to determine proportional and integral compensation factors. These compensation factors may be provided to a proportional integral (PI) compensator along with a measured phase delay error to generate an adjustment factor. This adjustment factor may be applied in various ways to improve power converter performance, for example, to reduce phase delay error and to improve current balance.Compensating for a detection delay and signal propagation delay responsive to ZCDby a control switch and / or a rectifier switch is further described below with reference to FIGS. 4 and 5. This corresponds to the first approach to improving power converter performance described above. In some examples, such compensation enables improved determination of on / off timing. Improved (such as more accurate) determination of on / off timing in interleaved polyphase converters allows for some or all of the various advantages, such as higher efficiency, reduced harmonics, improved signal shaping, improved system stability, improved current balance between phases, and improved phase delay compliance over system design.The second approach relates to a delay between a measurement of an input voltage and a receipt of a responsive control signal by a switch. This delay may cause delivered power signals to deviate from the design. A measured AC input voltage used for determining a switching timing is not the same as at the time of a measurement as at the time of a switch control signal reception. A compensation factor may be determined after manufacture and used to correct the delay from measurement to control.Compensating for measurement and signal propagation delay responsive to an input voltage level is further described below with reference to FIGS. 7, 8, and 9. This corresponds to the second approach to improving power converter performance described above. Improved (such as more precise) determination of phase delay in interleaved polyphase converters allows for some or all of the various advantages, such as higher efficiency, reduced harmonics, improved signal shaping, improved system stability, improved current balance between phases, and improved compliance with phase delay over system design.Here, some structures or signals that are distinct but associated have reference numerals that use a [Zahl][Bindestrich][Zahl] format, such as a first PTA circuit 402- 1 and a second PTA circuit 402- 2. In some examples, these structures or signals are generally referred to in the singular or as a group using the [number] and without [hyphen][letter], such as PTA circuitry 402.For convenience, metal oxide semiconductor field effect transistors (MOSFETs) are numbered as M[channel type][number] in this document, with the number increasing for each different transistor of a same channel type. Channel types include n-channel MOSFETs (NMOSs) and p-channel MOSFETs (PMOSs). The channel type for each transistor is just one example, and other examples may replace any illustrated transistor with another transistor of a different type. In addition, the same reference numerals or other reference numerals are used in the drawings to designate features that are structurally and / or functionally related.FIG. 1A is a functional block diagram and circuit diagram of an example boost converter system 100. In one example, the boost converter system 100 receives alternating current (AC) power and outputs direct current (DC) power. Accordingly, the boost converter system 100 is an AC-DC converter. The boost converter system 100 includes a biphasic boost converter 102, a load 104, a control block 105 including a signal sensor 106, an integrated circuit (IC) 108 and a gate driver circuit 110, and an AC voltage source 112. In some examples, systems and processes described herein apply to polyphase ZVS QSW power converters other than boost converters, such as a buck, buck-boost or flyback converter.The boost converter system 100 illustrated in FIG. 1A corresponds to one-half of a period of a voltage signal provided by the AC voltage source 112. A boost converter 146 corresponding to the entire period of the voltage signal provided by the AC voltage source 112 is described with reference to FIG. 1B. A biphasic boost converter system 162 corresponding to the entire period of the voltage signal provided by the AC voltage source 112 is described with reference to FIG. 1C.The biphasic boost converter 102 includes a first phase circuit 114, a second phase circuit 116, and a capacitor 118. The first phase circuit 114 includes a first energy storage device (e.g., a first inductor 120), a first NMOS (MN1) 122, and a second NMOS (MN2) 124. The second phase circuit 116 includes a second energy storage device (e.g., a second inductor 126), a third NMOS (MN3) 128, and a fourth NMOS (MN4) 130. MN1 122, MN2 124, MN3 128, and MN4 130 are collectively referred to as the switches.The control IC 108 includes a PWM module 132, a processor 134, a memory 136, and a clock circuit 138. The PWM module 132 includes a delay circuit 140 and a phase timing adjustment (PTA) module 141. In some examples, the PWM module 132 controls the switches 122, 124, 128, and 130 via the gate driver 110 responsive to hardware, software, or a combination thereof. In some examples, the processor 134 is a central processing unit (CPU), a digital signal processor (DSP), or a microcontroller unit (MCU). In some examples, the processor 134 provides signals to the PWM module 132, such as control signals or sensed sensor information, responsive to hardware, software, or a combination thereof.The memory 136 includes memory circuitry that stores instructions for performing an interrupt service routine (ISR) or other background process (or process) for controlling the PWM module 132. In some examples, a PWM control process is stored in a flash memory bank of memory 136. In some examples, signals responsive to voltage and / or current measurements by the signal sensor 106 are sensed by circuitry of the control IC 108, such as the circuitry of the processor 134. Samples are processed by the processor 134 and / or stored by the memory 136.In some examples, an ISR update rate (execution frequency) is between 50 and 100 kilohertz. Accordingly, a switching frequency of MN1 122, MN2 124, MN3 128, and MN4 130 may be between 70 kilohertz and 1.2 megahertz. A typical grid frequency of an input voltage signal corresponding to a power signal provided by a power line corresponding to the voltage source 112 is 50 to 60 Hertz. Accordingly, the ISR update rate is similar or slower than the switching frequency and faster than the grid frequency.A first terminal of the voltage source 112 is connected to a first terminal of the first inductor 120, a first terminal of the second inductor 126, and a first input of the signal sensor 106. A second terminal of the first inductor 120 is connected to a source of MN 1 122, a drain of MN 2 124, and a second input of the signal sensor 106. A node A 145 is located between the source of MN1 122 and the drain of MN2 124. A second terminal of the second inductor 126 is connected to a source of MN 3 128, a drain of MN 4 130, and a third input of the signal sensor 106. Gates of MN1 122, MN2 124, MN3 128, and MN4 130 are connected to an output(s) of gate driver circuit 110. In some examples, gates of MN 1 122 and MN 2 124 are connected to a first set of complementary outputs of gate driver circuit 110, and gates of MN 3 128 and MN 4 130 are connected to a second set of complementary outputs of gate driver circuit 110.Drains of MN 1 122 and MN 3 128 are connected to a first terminal of capacitor 118, a first output terminal 142, and a fourth input of signal sensor 106. A second terminal of the voltage source 112 is connected to sources of MN2 124 and MN4 130, a second terminal of the capacitor 118, a second output terminal 144, and a fifth input of the signal sensor 106. The first output terminal 142 is connected to a first terminal of the load 104. The second output terminal 144 is connected to a second terminal of the load 104. In one example, the first, second, third, fourth, and fifth inputs of the signal sensor 106 correspond to first, second, third, fourth, and fifth inputs of the control block 105, respectively.MN1 122, MN2 124, MN3 128 and MN4 130 serve as a switching function for boost converter 102. MN 1 122 and MN 2 124 control a current flow through first inductor 120, and MN 3 128 and MN 4 130 control a current flow through second inductor 126. Accordingly, MN1 122, MN2 124, MN3 128, and MN4 130 control transfer of energy from voltage source 112 to load 104. A voltage between the first output terminal 142 and the second output terminal 144 corresponds to an output voltage V AUS of the boost converter 102, corresponding to a voltage across the load 104.An output of the signal sensor 106 is connected to an input of the control IC 108. The processor 134 is bidirectionally coupled for communicating with the memory 136. An output of the processor 134 is connected to an input of the PWM module 132. An output of the control IC 108 is connected to an input of the gate driver circuit 110. In some examples, a plurality of outputs of the control IC 108 corresponding to the plurality of phase circuits of the boost converter 102 are connected to corresponding inputs of the gate driver circuit 110.The processor 134 controls the PWM module 132 responsive to instructions in the memory 136 (such as the ISR described above) and responsive to feedback signals provided by the signal sensor 106. The PWM module 132 controls the gate driver 110. The gate driver 110 controls MN1 122, MN2 124, MN3 128, and MN4 130 to turn on and off. MN 1 122 and MN 2 124 are controlled to enable energy transfer across first inductor 120. MN 3 128 and MN 4 130 are controlled to enable energy transfer across the second inductor 126.In some examples, the signal sensor 106 provides signals indicative of voltage and / or current signals of the boost converter 102 to the control IC 108, and the control IC 108 samples the signals to determine voltage and / or current values and / or related information. In some examples, the signal sensor 106 senses and / or samples the signals of the boost converter 102 to determine voltage and / or current values and / or associated information. In some examples, certain voltage and / or current values and / or related information includes a maximum voltage of an AC signal (such as a power signal corresponding to an input voltage provided by voltage source 112), an output voltage, a current I L through first inductor 120, an indicator of zero current (ZCD) detection by MN 1 122 (e.g., a high side switch), or an indicator of ZCD by MN 2 124 (e.g., a low side switch).FIG. 1B is a functional block diagram and circuit diagram of a second example power converter system 146. In one example, the power converter system 146 of FIG. 1B corresponds to a phase (e.g., the first phase circuit 114 or the second phase circuit 116) of the boost converter 102 of FIG. 1A. The power conversion system 146 includes an AC voltage source 148, an inductor 150, a first NMOS (S 1) 152, a second NMOS (S 2) 154, a third NMOS (S 3) 156, a fourth NMOS (S 4) 158, and an output capacitor 160. S 1 152 and S 2 154 correspond to MN 1 122 and MN 2 124, respectively, in one example. In one example, S 3 154 and S 4 156 are enhancement mode FETs.A first terminal of the AC voltage source 148 is connected to a first terminal of the inductor 150. A second terminal of inductor 150 is connected to sources of S 1 152 and S 3 156 and drains of S 2 154 and S 4. Drains of S 1 152 and S 3 156 are connected to a first terminal of the output capacitor 160 and sources of S 2 154 and S 4 158 are connected to a second terminal of the output capacitor 160.Returning to FIG. 1A, the operation of each phase circuit of boost converter 102 is generally controlled by the closed or open state of a respective control switch and a so-called rectifier switch, as now described. In some examples where the voltage source 112 provides an AC signal, as in the power conversion system 146 of FIG. 1B, MN 1 122 and MN 3 128 function as a rectifier switch for one half (a positive voltage half or a negative voltage half) of the period of the AC signal and as a control switch for one half (a negative voltage half or a positive voltage half) of the period of the AC signal. Similarly, MN2 124 and MN4 130 function as a control switch for one half (a positive half voltage or a negative half voltage) of the period of the AC signal and as a rectifier switch for one half (a negative half voltage or a positive half voltage) of the period of the AC signal. Here, for convenience, one half of the period of the AC signal is described: MN1 122 and MN3 128 are described as rectifier switches and MN2 124 and MN4 130 are described as control switches. Functionality described herein also applies to the other half of the AC signal period.During a dead time (also referred to as a dead band), both the control switch and the rectifier switch are opened to prevent shoot-through. Except during dead times, within a phase circuit 114 or 116, one of the control switch and the rectifier switch is closed and the other is open. A dead time is between changing which of the control switch and the rectifier switch is opened and closed."Phase", without the word "circuit", is used herein to refer to a control duration of a switching period of a phase circuit 114 or 116. Accordingly, each phase circuit 114 or 116 is controlled to have two phases and two dead times within a switching period. In a first phase, also referred to herein as an energy storage phase, MN 1 122 or MN 3 128 is open and (or) MN 2 124 or MN 4 130 is closed. During the energy storage phase, a current across inductor 120 or 126 is increased. In addition, the inductor 120 or 126 stores energy by generating a magnetic field while current from the voltage source 112 flows through the inductor 120 or 126 and MN2 124 or MN4 130. In addition, capacitor 118 discharges through load 104. A body diode of MN1 122 or MN3 128 prevents discharge of capacitor 118 via MN1 122 or (or) MN3 128.In a second phase, also referred to herein as a discharge phase, MN1 122 or MN3 128 is closed and (or) MN2 124 or MN4 130 is open. Energy stored in inductor 120 or 126 is discharged as current through load 104 and charges capacitor 118.The clock circuit 138 generates a clock signal. The control IC 108 receives voltage and / or current information sensed and processed by the processor 134 from the signal sensor 106. The PWM module 132 generates a PWM control signal for the first phase switching circuit 114 responsive to the clock signal and the processed signal information. The delay circuit 140 generates a PWM control signal for the second phase circuit 116 responsive to the first phase circuit PWM control signal, with a phase delay that shifts the second phase circuit PWM control signal at a later time. In some examples, the second phase-switching PWM control signal for the second phase-switching circuit 116 is equal to the first phase-switching PWM control signal, but with the added phase delay.In some examples, the delay provided by the delay circuit 140 is determined such that the second phase PWM control signal has a phase delay with respect to the first phase PWM control signal equal to 180° (π radians). In some examples, a designed phase delay is responsive to circuit conditions other than 180° (π radians). In some examples, a designed phase delay is for or is responsive to a Pth phase (integer P) of an integer N of phases (P-1)*(360 degrees) / N or (P-1)*(2π radians) / N.In some examples, various factors may introduce an error in a particular phase delay time or in a second phase current. In some examples, a delay error or current imbalance may arise due to a delay between a signal event, such as a zero current through a switch 122, 124, 128, or 130, and generation of a signal responsive to a measurement of that signal event. A delay error or current imbalance may also be caused by variations in device parameters introduced during manufacture (e.g., process variation). The delay circuit 140 adjusts the phase delay for the second phase circuit PWM control signal responsive to the PTA module 141 to correct phase delay and / or current imbalance errors. A function of the PTA module 141 is further described with reference to FIGS. 4 and 5.FIG. 1C is a functional block diagram and circuit diagram of a third example boost converter system 162. In addition to the structures of the boost converter system 100 of FIG. 1A, the boost converter system 162 of FIG. 1C includes a fifth n-channel MOSFET (MN 5) 164 and a sixth n-channel MOSFET (MN 6) 166. In one example, MN5 164 and MN6 166 are enhancement mode FETs.The second terminal of the voltage source 112 is connected to a source of MN 5 164, a drain of MN 6 166, and a sixth input of the control block 105 (corresponding to a sixth input of the signal sensor 106). Drains of MN1 122, MN3 128, and MN5 164 are connected to the first terminal of capacitor 118, the fourth input of control block 105, and the first output terminal 142. Sources of MN2 124, MN4 130, and MN6 166 are connected to the fifth input of control block 105, the second terminal of capacitor 118, and the second output terminal 144. The output of control block 105 is connected to the gates of MN1 122, MN2 124, MN3 128, MN4 130, MN5 164, and MN6 166.In a first half of a period of the voltage signal provided by the voltage source 112, MN 6 166 is closed and MN 5 164 is open. This corresponds to connectivity described with reference to the boost converter 102 of FIG. 1A. Accordingly, operation of the boost converter system 162 under this condition corresponds to operation of the boost converter system 100 as described with reference to FIG. 1A.In a second half of a period of the voltage signal provided by the voltage source 112, MN 5 164 is closed and MN 6 166 is open. Operation of the biphasic boost converter system 162 under this condition is similar to operation of the biphasic boost converter system 100, except that MN 1 122 and MN 3 128 function as control switches and MN 2 124 and MN 4 130 function as rectifier switches. Accordingly, the control and response behavior with respect to MN1 122 is interchanged with the control and response behavior with respect to MN2 124. Similarly, the control and response behavior with respect to MN3 128 is interchanged with the control and response behavior with respect to MN4 130.FIG. 2A is a first set of graphs 200 of example signals corresponding to PWM control of the first phase circuit 114 of the power conversion system of FIG. 1A over signals of the gate driver 110 as further described in FIG. 2B. The graphs 200 include a first graph 202 and a second graph 204. A horizontal axis of each of the graphs 202 and 204 indicates a time. A vertical axis of the first graph 202 indicates a current. A vertical axis of the second graph 204 indicates a voltage. The first graph 202 includes an inductor current (I L)- curve 206 representing a current through the first inductor 120. The second graph 204 includes a voltage curve (V MN2-DS) 208 of MN2 A drain-source voltage (V DS) of MN2 124.A switching period of the first phase circuit 114 includes four durations, namely t 1 210, t 2 212, t 3 214, and t 4 216, which correspond to a switching state of MN 1 122 and MN 2 124, respectively. At the beginning of t 1 210, there is a zero voltage across MN 2 124, allowing MN 2 124 to turn on with reduced (or minimal) loss, which corresponds to ZVS. Accordingly, MN1 122 remains off and turns MN2 124 on. Turning on (closing) MN2 124 provides a low resistance conductive path through which the voltage is very low or zero, such that I L206 increases linearly. Accordingly, t 1 210 corresponds to the energy storage phase of the first phase circuit 114.At the beginning of t2 212, MN1 122 remains off and turns MN2 124 off, such that t2 212 corresponds to a first dead time. During t2 212, I L206 increases slightly and then begins to decrease because I L206 discharges the parasitic capacitance of MN1 122 and charges the parasitic capacitance of MN2 124. Charging the parasitic capacitance of MN2 124 causes voltage curve 208 of MN2 to increase from zero to the line voltage provided by voltage source 112.At the beginning of t 3 214, it passes a zero voltage across MN 1 122, allowing MN 1 122 to turn on with reduced (or minimal) loss, which corresponds to ZVS. Accordingly, MN1 122 turns on and MN2 124 remains off. Initially, conduction through MN1 122 may correspond to a third quadrant conduction feature of MN1 122 or activation of a body diode of MN1 122. During t 3 214, a current through the first inductor 120 is provided to the load 104 and charges the capacitor 118 such that a current through the first inductor 120 decreases. Accordingly, t 3 214 corresponds to the discharge phase of the first phase circuit 114.At the beginning of t4 216, MN1 122 turns off and MN2 124 remains turned off, such that t4 216 corresponds to a second dead time. During t4 216, I L206 decreases slightly and then begins to increase because I L206 charges the parasitic capacitance of MN1 122 and discharges the parasitic capacitance of MN2 124. Discharging the parasitic capacitance of MN2 124 causes voltage curve 208 of MN2 to decrease from V DC to zero.FIG. 2B is a second set of graphs 218 of example signals corresponding to PWM control of the first phase circuit 114 of the power conversion system of FIG. 1A. The graphs 218 include a first graph 220, a second graph 222, a third graph 224, and a fourth graph 226. A horizontal axis of each of the graphs 220, 222, 224, and 226 indicates a time. A vertical axis of each of the graphs 220, 222, 224, and 226 indicates a voltage.The first graph 220 includes a PWM control signal 228 from MN 1 122 (or high side switch). The second graph 222 includes a PWM control signal 230 from MN 2 124 (or low side switch). The third graph 224 includes a high-side ZCD signal 232 indicating a time when a current through the high-side switch (such as MN 1 122) is equal to zero. The fourth graph 226 includes a low-side ZCD signal 234 indicating a time when a current through the low-side switch (such as MN 2 124) is equal to zero. In some examples, the high-side and low-side ZCD signals 232 and 234 are provided by the signal sensor 106 or by a signal sensor structure within MN 1 122, MN 2 124, MN 3 128, and / or MN 4 130.In the high-side and low-side PWM control signals 228 and 230, a high voltage corresponds to controlling the respective switch to turn on. A low voltage corresponds to the switching of the respective switch to switch off. In high-side and low-side ZCD signals 232 and 234, a low voltage indicates that no ZCD event is occurring by MN1 122 or (or) MN2 124, and indicates a high voltage that a ZCD event is detected by MN1 122 or (or) MN2 124.There is a high side ZCD event at a first time 236, and a low side ZCD event at a second time 238. In some examples, a turn-off time for MN 1 122 responds to first time 236, and a turn-off time for MN 2 124 responds to second time 238. In some examples, the off time for MN 1 122 is responsive to the first time 236 while MN 1 122 is the rectifier switch (such as while MN 5 164 is closed and MN 6 166 is open), and not while MN 1 122 is the control switch (such as while MN 5 164 is open and MN 6 166 is closed). In some examples, the off time of MN 2 124 responds to the second time 238 while MN 2 124 is the rectifier switch (such as while MN 5 164 is open and MN 6 166 is closed), and not while MN 2 124 is the control switch (such as while MN 5 164 is closed and MN 6 166 is open).It is noted that ZCD detection is not instantaneous and a signal path from a ZCD event to a responsive switch (such as MN1 122 or MN2 124) controller is also not instantaneous. A controller responsive to a ZCD event, including correction of ZCD detection and other associated delay along a signal path responsive to switch control, is further described with reference to FIGS. 3A, 3B, 4, and 5.FIG. 3A is a state plane diagram 300 of example signals of the boost converter system 100 of FIG. 1A responsive to PWM control as described with reference to FIGS. 2A and 2B. State plane diagram 300 maps time domain waveforms I L( t) 206 and v(t) 208 (FIG. 2A ) to normalized voltage domain current signal 302.A vertical axis indicates a normalized current J L( or J L( t)), which is described by Equation 9 below. A horizontal axis indicates a normalized voltage m (or mc(t)) described by Equation 8. A midpoint of the state plane diagram 300 is at (M, 0), where M is a normalized value of the instantaneous (e.g., measured) input voltage V EIN provided by the voltage source 112. M is further described with reference to Equation 7 below.The normalized voltage domain current signal 302 has four corners, as shown in FIG. 3A. A normalized current at a first corner 306 is J L1, a normalized current at a second corner 308 is J L2, a normalized current at a third corner 310 is J L3 and a normalized current at a fourth corner 312 is J L4. J L1, J L2, J L3 and J L4 are normalized currents at the beginning of durations t1 210, t2 212, t3 214, and t4 216, respectively. J L1 and J L4 correspond to a normalized voltage of zero and are respectively an amount M on the left side of the midpoint of the state plane diagram 300. J L2 and J L3 correspond to a normalized voltage of one and are respectively an amount one minus M on the right side of the midpoint of the state plane diagram 300.C is the sum of the capacitances at node A 145, corresponding to the source-drain capacitances of M 1 122 and M 2 124, and the corresponding conductive line(s). θ 1, θ 2, θ 3 and θ 4 are normalized angles summed up at a switching period of the first phase circuit 114. Normalized angles θ 1, θ 2, θ 3 and θ 4 are traversed by the voltage domain current signal J L( v) in durations t 1 210, t 2 212, t 3 214, and t 4 216, respectively.Some or all of the previously described values (and / or other values, such as other characteristics of boost converter 102 or its operation) may be derived precisely and in real-time to provide some or all of various advantages including: higher efficiency, reduced harmonics, improved signal shaping, improved system stability, improved current balance between phases, and improved compliance with phase delay over system design. This deviation and the use of these values to control boost converter 102 will be further described below.Here, L is the inductance value of the first inductor 120. R 0, a characteristic impedance of the first phase circuit 114 is shown in Equation 1. The resonant frequency ω 0 of the boost converter 102 is shown in Equation 2.Equations 3 and 4 respectively described a normalization factor for a voltage V Basis and a normalization factor for a current I Basis. V Basis corresponds to an output voltage, and I Basis corresponds to an output current.An angle θ (theta) in the state plane diagram 300 is given in Equation 5 (θ may exceed 2π radians). A normalized frequency F is shown in Equation 6, where f SW is the switching frequency of the boost converter 102.A normalized input voltage M is shown in Equation 7, where V EIN is the input voltage at a time. A normalized voltage at node A 145 (e.g., across MN2 124) mc(t) is shown in Equation 8.The current I L( t) through the first inductor 120 at a time t is shown in Equation 9.During a switching period of the first phase circuit 114, the state plane diagram 300 traverses a normalized angle corresponding to a full circle, which is described by Equation 10. θ 1, θ 2, θ 3 and θ 4 may be determined trigonometrically, as shown in Equations 11, 12, 13 and 14, respectively.The arcs between J L1 and J L2, and between J L3 and J L4 are circular, such that J L1 and J L2 are equal radii of a first circle and J L3 and J L4 are equal radii of a second circle. Normalized currents J L1, J L2, J L3 and J L4 may be determined trigonometrically as shown in equations 15 and 16. J L is determined as shown in equation 17 by forming the integral of the current (I L) through the first inductor 120 over a switching cycle and normalizing the result.Equations 10 through 17 provide eight equations with eleven variables: J L1, J L2, J L3, J L4, θ 1, θ 2, θ 3, θ 4, M, F, and J L. Solving for these eleven variables enables deterministic, enhanced (or optimized) control of the first phase circuit 114 and responsive thereto the second phase circuit 116. For example, θ 1, θ 2, θ 3 and θ 4 may be used to determine on-off timing for MN 1 122 and MN 2 124. In some examples, the equations described above for the second phase circuit 116 may be solved using corresponding signal measurements provided by the signal sensor 106.Three of the variables may be fixed or treated as inputs. In some examples, input variables are determined and / or measured according to design rules, or are enabled to be determined by signals provided by the signal sensor 106, and / or are determined by the control IC 108 responsive to a measurement.J LR is a compensation parameter generated from measurements and used to maintain V AUS at the regulated voltage level within designed tolerances. J LR may also be described as a normalized current reference for a power factor control loop. In one example, J LR is determined as a current reference divided by I Basis. In another example, J LR is determined as an output of a voltage loop compensator multiplied by a measured value of V EIN and divided by the square of a root-mean-squared (RMS) value of V EIN( V EIN_RMS2). The voltage loop compensator is a proportional-integral (PI) compensator that monitors V AUS. Responsive to J LR the control IC 108 determines a target amount of power to deliver which the converter is to be controlled to maintain V AUS at the regulated value. Note that J LR is used in Equation 19 below.Example input variables or values that enable determination of input variables include: average value of inductor current I L or normalized inductor current J L, peak current I L1 prior to turning off the control switch (such as MN 1 122), normalized frequency F, one or more of the values used to determine normalization values (equations 1-9), or J LR. Accordingly, the system of control equations corresponding to equations 10 to 17 can be solved. In some examples, J L1, J L2, J L3, J L4, M, F, and J L are intermediate values used to determine θ 1, θ 2, θ 3, θ 4 corresponding to on / off control operations.In some examples, equations 10 through 17 are a transcented set of equations. In some examples, solving the control equations uses an iterative numerical method that is computationally intensive. In some examples, using the numerical method to achieve designed control accuracy prevents real-time converter control. Equations 19-26 allow simplification of the set of control equations to promote and / or allow more precise (or precise) real-time solution and corresponding control of boost converter 102 or other ZVS QSW converter.Equations 15 and 17 are rewritten as shown in equations 19 and 20. For example, Equation 19 is determined by using Equations 11, 13, 15, 16, and 25 (described below) to make a series of substitutions in Equation 17. It is noted that solving equation 19 to determine J L1 enables solving equation 20 to determine J L2.Equation 21 provides a trigonometric identity that allows Equation 14 to be simplified:In some examples, π / 2 is an appropriate mapping of a portion of the switching period of the first phase circuit 114 to t 4 216, because during t 4 216, a negative current I L is relatively low. Accordingly, it takes a relatively long time for the current through the first inductor 120 to discharge parasitic capacitances of MN 1 122. As previously described, θ 4 t4corresponds to 216. Accordingly, in consideration of Equations 14 and 21, θ 4 can be set as shown in Equation 22.Further, a J L3- term in Equation 17 may be described as x in Equation 21, and a J L4- term in Equation 17 may be described as 1 / x in Equation 21. Similarly, J L3 and J L4 are related as shown in equation 23.Given Equation 23, J L3 and J L4 may be chosen as described by Equations 24 and 25. As shown in equations 24 and 25, J L3 and J L4 depend on the ratio M between input and output voltages and are independent of a switching timing or an average value of the inductor current.A normalized angle θ 3,ext corresponds to the portion of t3 214 after J L drops below zero (an "extra" duration in t3). Accordingly, θ 3,ext begins responsive to ZCD 236 by MN1 122, and specifies when MN1 122 should be turned off, so that t4 216 begins. In some examples, using θ 3,ext instead of θ 3 simplifies the set of control equations and improves their utility by making a switch timing more explicit responsive to a measurement by the signal sensor 106. θ 3,ext is given by equation 26:Responsive to some or all of Equations 1 through 9, Equations 11, 12, 19, 20, 22, 24, 25, and 26 may be processed sequentially (such as in a sequence responsive to the variables selected as fixed or input variables) to determine values that enable control of boost converter 102. As described above, such values include, for example, J L1, J L2, J L3, J L4, θ 1, θ 2, θ 3, θ 4, M, F, and J L. This may be done in real-time to enable more precise (or precise) real-time control of boost converter 102. In some examples, different variables and / or different equations and / or different combinations of the equations described above may be used to enable such precise real-time control.A measurement delay may introduce an error in the determination of control parameters for the boost converter 102 according to the equations described above. One or more process stages, such as measurement, signal processing, or control signal generation, may introduce delay from a measured event or value until a responsive control signal reaches controlled components, such as switches. Setup and / or process approaches for correcting such errors responsive to ZCD events are described with reference to FIGS. 4 and 5. Setup and / or process approaches for correcting such errors responsive to an input voltage measurement are described with reference to FIGS. 7, 8, and 9.In some examples, a set of determined values of θ 1, θ 2, θ 3 and θ 4 is applied to a determination of on / off timing for all phase circuits in a power converter. In some examples, certain adjustment factors, such as those described with reference to FIGS. 4 and 5, are independently applied with respect to each phase circuit to determine corresponding on / off timings.FIG. 3B is a set of tables 314 showing equations described with reference to FIG. 3A, enabling example control of the boost converter system 100 of FIG. 1A. Tables 314 include a first table 316 showing equations 1 through 9 and a second table 318 showing equations 11, 12, 19, 20, 22, 24, 25 and 26.FIG. 4 is a functional block diagram of an example of the PTA (Phase Timing Adjustment) module 141 of FIG. 1A. For a power converter including a number of N phase circuits, the PTA module 141 includes N minus one PTA circuit 402. A first PTA circuit 402- 1 provides a first phase delay timing adjustment value for adjusting a phase delay of second phase circuit PWM control signals with respect to first phase circuit PWM control signals. A second PTA circuit 402- 2 provides a second phase delay timing adjustment value for adjusting a phase delay of third phase circuit PWM control signals with respect to the first phase circuit PWM control signals. And so on, such that an (N-1)th PTA circuit 402-(N-1) provides an (N-1)th phase delay timing adjustment value for adjusting a phase delay of Nth phase circuit PWM control signals with respect to the first phase circuit PWM control signals. Accordingly, an S-th (S is a number) phase circuit (such as the second phase circuit 116) corresponds to an (S-1)-th PTA circuit 402-(S-1) (such as the first PTA circuit 402-1).The PTA circuits 402 each include a division block 404, an addition block 406, a PI compensator 408, a first multiplier 410, and a second multiplier 412. A first input of the division block 404 receives a phase delay measurement and a second input of the division block receives a period measurement, referred to as T. The phase delay measurement is referred to as φs, where S is the number of the corresponding phase circuit. In some examples, φ M and T are binary values representing a corresponding duration as fractional seconds.Division block 404 provides φ S / T to an inverting input of addition block 406. φ S / T represents a fraction of a switching control period corresponding to the measured phase delay and may be described as a normalized phase delay. A noninverting input of the addition block 406 receives S / N representing a designed portion of the switching control period corresponding to the measured phase delay. S / N may be described as the reference for the PI compensator 408. The addition block 406 provides S / N - φ S / T to a first input of the PI compensator 408. S / N - φ S / T can be described as a phase delay error.K P,N is a normalized proportional PI compensator gain. K I,N is a normalized integral PI compensator gain. In some examples, K P,N and K I,N are determined at the design level, such as by calculation or simulation, or responsive to testing of a sample device.A first input of the first multiplier 410 receives K P,N. A second input of the first multiplier 410 receives T. The first multiplier 410 scales K P,N by multiplying it by T and provides K P,N × T = K P to a second input of the PI compensator 408. K P is a proportional compensator gain. A first input of the second multiplier 412 receives K L,N. A second input of the second multiplier 412 receives T. The second multiplier 412 scales K L,N by multiplying it by T and provides K I,N × T = K I to a third input of the PI compensator 408. K I is an integral PI compensator gain. Each PI compensator 408 outputs a phase delay timing adjustment value tφ,S(a duration responsive to φ S applicable to the Sthphase circuit) for use by the PWM module 132 to determine a phase delay and corresponding switch control signal timings. Generation of tφ,Sand use of tφ,Sto determine switch control signal timings is further described with reference to FIG. 5.In one example, the addition block 406 may be described as an error amplifier along with the PI compensator 408. In some examples, this error amplifier may be implemented using an operational amplifier (op-amp).FIG. 5 is a process flow diagram of an example process 500 for generating a phase delay timing adjustment value using the PTA module 141 of FIGS. 1 and 4.In step 502, a phase delay tφ,Sand a period T for an Sthphase circuit (such as the second phase circuit 116) are measured with respect to the first phase circuit (such as the first phase circuit 114). In one example, step 502 may be performed by detecting a digital or analog measure of a delay duration between a falling (or rising) edge of a first phase-switching PWM control signal (or other controller-responsive first phase-switching signal) and a rising (or falling) edge of an S-th phase-switching PWM control signal (or other controller-responsive S-th phase-switching signal that matches the measured first phase-switching signal). Measured PWM control signals may correspond to signals provided by the PWM module 132 or by the gate driver 110, for example.It should be noted that for a total of N phase circuits, PWM control signals for an Sth phase circuit should be phase delayed by (S-1)*(360 degrees) / N of PWM control signals for a first phase circuit. Accordingly, in one example, PWM control signals for MN 3 128 and MN 4 130 should be phase delayed by 180 degrees from PWM control signals for MN 1 122 and MN 2 124.In step 504, a normalized phase delay tφ,S / Tis determined. In step 506, proportional and integral compensator gains K P,N and K I,N are scaled (e.g., multiplied) by the period T to generate K P and K I. In step 508, determining the phase delay timing adjustment value tφ,Sfor the Sthphase circuit is responsive to a difference between a designed phase delay (S / N) and the normalized phase delay and responsive to the compensator gains K P and K I. In step 510, one or more switch timing parameters are adjusted responsive to tφ,S, and the power converter (such as boost converter 102) is controlled using the adjusted timing parameters. For example, timing parameters corresponding to θ 1, θ 2, θ 3, θ 4, and / or t1, t2, t3, or t4, and / or other switch timing parameters described below (e.g., t cf and / or t sr,ext).In some examples, adjusting a duration (t cf, corresponding to θ 1 ) in a switch control period during which a control switch (such as MN 2 124 or MN 4 130) is turned on may be used to correct a phase delay error. The phase delay error is equal to S / N- φ S / T. In some examples, adjusting a synchronous rectifier on duration after ZCD(t sr,ext, corresponding to θ 3,ext ) may be used to compensate for the adjusted t cf- on time. In some examples, adjusting t sr,ext with t cf adjusts an average current through an inductor 120 and / or 126 to enable accurate interleaving and current balance.In some examples, the variables determined in equations 1-9 are assumed to be the same across the set of phase circuits in the polyphase power converter. Here, t cf and t sr,ext are common durations determined using these values (such as R 0, V Basis, I Basis, F, M, and ω 0). Example phase delay correction options are provided according to a two-phase power converter. Similar approaches may be used for a more than two-phase power converter.A first example corrects a phase delay by setting a first phase circuit control switch on-state duration (t cf,1) and a second phase circuit control switch on-duration (t cf,2) as shown in equations 27 and 28.A second example corrects a phase delay by setting t cf,1 and t cf,2 as shown in equations 29 and 30.A third example corrects phase delay and current balance responsive to tφ,S<0. Values of t cf,1, t cf,2, a first phase-circuit synchronous rectifier on-state duration after ZCD(t sr,ext,1) and a second phase-circuit synchronous rectifier on-state duration after ZCD(t sr,ext,2) are determined as shown in equations 31, 32, 33, and 34. Values of t cf,1, t cf,2, t sr,ext,1 and t sr,ext,2 are adjusted responsive to tφ,S<0 to increase an average current in the first phase circuit to equal an average current in the second phase circuit. In some examples, the tφ,S factor may be described as an adjustment for an increase (or decrease) in current through an S-th phase inductance due to a longer (or shorter) t cf by decreasing (or increasing) current through the S-th phase inductance by the same amount. Equations 31, 32, 33, and 34 follow:A fourth example corrects phase delay and current balance responsive to tφ,S>0. Values of t cf,1, t cf,2, t sr,ext,1 and t sr,ext,2 are determined responsive to tφ,S>0 to reduce an average current in the second phase circuit to equal an average current in the first phase circuit. Values of t cf,1, t ef2, t sr,ext,1 and t sr,ext,2 are determined as shown in equations 35, 36, 37 and 38.A fourth example corrects phase delay and current balance responsive to tφ,S<0. A current portion adjustment term for an Sthphase circuit α S( alpha index-S) is used to correct relatively larger errors in current sharing than are addressed by adjusting a control FET on-state duration using tφ,S. The α S- term may be used to reduce an average current in a phase circuit that leads to an excessive current, or to increase an average current in a phase circuit that leads to too little current.In some examples, the value of α S is determined using a PI compensator. A first input of the PI compensator receives a difference between a current through a first phase inductance (such as the first inductance 120) and a current through an Sth phase inductance (such as the second inductance 126). The current through the first phase inductance can be described as a reference for the PI compensator. A second input of the PI compensator receives a proportional gain (similar to K P) and a third input of the PI compensator receives an integral gain (similar to K I). The proportional and input gain value are determined at the design level, such as by calculation or simulation, or responsive to testing of a sample device. The output of the PI compensator is α S.Values of t cf,1, t cf,2, t sr,ext,1 and t sr,ext,2 are determined responsive to tφ,S<0 to increase an average current in the first phase circuit to equal an average current in the second phase circuit. Values of t cf,1, t cf,2, t sr,ext,1 and t sr,ext,2 are determined as shown in equations 39, 40, 41 and 42.A fifth example corrects phase delay and current balance responsive to tφ,S>0. Values of t cf,1, t cf,2, t sr,ext,1 and t sr,ext,2 are determined responsive to tφ,S>0 to reduce an average current in the second phase circuit to match an average current in the first phase circuit. Values of t cf,1, t cf,2, t sr,ext,1 and t sr,ext,2 are determined as shown in equations 43, 44, 45 and 46.A sixth example corrects for phase delay by adjusting the phase time constant, such as by adjusting the value of L used in calculations relating to one or more of the phase switching circuits. For example, decreasing L will increase a frequency of a corresponding phase circuit and increasing L will decrease the frequency of the corresponding phase circuit. In one example, L is adjusted at the ISR update rate. In some examples, adjusting L reduces current imbalance with respect to an L / C discrepancy.FIG. 6 is a graph 600 of exemplary inductor current versus time for the boost converter system 100 of FIG. 1A responsive to phase timing adjustment as described with reference to FIGS. 4 and 5. A horizontal axis of the graph 600 indicates a time. A vertical axis of the graph 600 indicates a current. The graph 600 includes a first inductor current curve 602 and a second inductor current curve 604. Following application of phase time adjustment, as described with reference to FIGS. 4 and 5, the first and second inductor current curves 602 and 604 are phase shifted from each other by approximately 180 degrees (π radians). In addition, sequentially successive first and second peak and average inductor currents 602 and 604 are approximately equal. These characteristics enable advantages including system stability, improved efficiency, and / or reduced harmonics.FIG. 7 is a graph 700 of example signals of the boost converter system 100 of FIG. 1A responsive to a delay corresponding to a signal path from an input voltage measurement by the signal sensor 106 to a use of control signals responsive to the input voltage measurement. A horizontal axis of the graph 700 indicates a time. A vertical axis of the graph 700 indicates a voltage. Graph 700 includes an actual V EIN- curve 702, a measured V EIN- curve 704, a correction signal curve 706, and a compensated V EIN- curve 708.The actual V EIN- curve 702 corresponds to a value of V EIN at a time t MESS, when a process of measuring V EIN, such as a signal controlling a measurement component for detecting an instant V EIN occurs according to control. Accordingly, t MESS is a time designed to correspond to the measured value of V EIN and other parameters used to determine on / off timing may be determined versus the same t MESS. However, different delay durations of t MESS are introduced for processing ("observation") by the measured value of V EIN processor 134 to generate responsive switch control signals to control terminals of responsive controlled switches (such as gates of MN1 122, MN2 124, MN3 128, or MN4 130). Accordingly, a certain time is required (delay) to perform the measurement, a delay is introduced by sampling (or filtering) the measurement signal, and an additional delay is contributed in processing the sampled measurement signal to generate switch control signals. This delay may also result as a delay from the input on the power lines to the "observed" input.As discussed above with reference to FIGS. 3A and 3B, V EIN is used to determine (for example) a normalized input voltage M (equation 7) that is used throughout the system of control equations. A measurement and signal path delay affecting V EIN corresponds to a delay of the V EIN- waveform. The delayed V EIN- waveform corresponds to the measured V EIN- curve 704. In one example, at time t 710, the actual V EIN- curve 702 has a first voltage value 712 and the measured V EIN- curve 704 has a second voltage value 714. A correction signal 706 may be applied to the measured V EIN- curve 704, as further described with reference to FIGS. 8 and 9, to determine the compensated V EIN- curve 708. The compensated V EIN- curve 708 is almost equal to the actual V EIN- curve 702.FIG. 8 is a functional block diagram of a compensation module 800 for correcting a measured input voltage for measurement and / or signal path delay. In some examples, the compensation module 800 is located in the signal sensor 106, or is included in the processor 134, or is otherwise a part of the control IC 108. The compensation module 800 includes a first analog-to-digital converter (ADC) 802, a second ADC 804, a first adder 806, a V RMS- block 808, a timing block 810, a correction signal block 812, a correction factor block 814, a first multiplier 816, a second multiplier 818, and a second adder 820.The first ADC 802 receives and samples a line voltage signal V L of an AC voltage source. The second ADC 804 receives and samples a neutral voltage signal V N, such as a zero or ground voltage, of the AC voltage source. The voltage signal VIN_tats of the AC voltage source may be described as shown in equation 47, where V RMS is a square-average voltage of the AC voltage source, t is a time at which V EIN is measured, and ω is the angular frequency of the line voltage. In some examples, ω is 50 to 60 hertz. In some examples, an accurate value of ω is superfluous due to the relatively small amplitude of the compensation signal.A non-inverting input of the first adder 806 receives the digitized sampled V L and an inverting input of the first adder 806 receives the digitized sampled V N. An error factor φ fil represents the phase shift introduced by measuring / sampling (filtering) the V EIN- signal, such as by processing the V L- and V N- signals using the first and second ADCs 802 and 804. The first adder 806 generates a measured V ElN- value V EIN_gemessen as a difference between V L and V N, which may be described as shown in equation 48.The first adder 806 provides the measured V EIN- value to the V RMS- block 808 and the timing block 810 and to a first input of the first multiplier 816. The V RMS- block 808 determines V RMS responsive to the measured V EIN- value, such as using an infinite impulse response (IIR) filter or on a duty cycle basis. In one example, a duty cycle basis corresponds to determining when a period of the source voltage waveform begins and ends, and determining an RMS average of the source voltage over a period. The V RMS- block 808 provides V RMS to a first input of the correction signal block 812 and a second input of the first multiplier 816.Timing block 810 maintains a timer, such as a counter, that tracks a time t. The timer is reset responsive to a zero crossing of the measured V EIN. In some examples, the timer is reset at a positive zero crossing of the measured V EIN( transition from a negative V EIN to a positive V EIN). In some examples, the timer is set to a value corresponding to one-half switching cycle (switching period T) responsive to a negative zero crossing of the measured V EIN( transition from a positive V EIN to a negative V EIN). Responsive to an iterative execution of the switch control ISR, the timer is incremented by a step corresponding to a duration of execution of the switch control ISR. Timing block 810 supplies t to correction signal block 812. The time t is used to determine an angular position (tω) of the measured V EIN within the V EIN- signal.The correction signal block 812 generates a signal VIN_correction that is used to correct the measured V EIN. This signal is shown in equation 49, where ω is the AC line frequency of the V EIN- waveform. In some examples, ω is provided or is determined responsive to a measurement or control signal that adjusts ω.The correction signal block 812 provides V EIN_ correction to a first input of the second multiplier 818. A correction factor φ is determined at the design level, such as by calculation or simulation, or responsive to testing of a sample device. The correction factor φ is equal to (or represents) a phase correction that will shift the observed input signal (the measured V EIN- value) to align with the actual V EIN- input signal. The correction factor φ is used to compensate for the delay sources that cause errors with respect to a V EIN- measurement, as described above. An additional error term φ err represents the measured V EIN- signal that is not accounted for by φ fil. The correction factor block 814 provides cos(φ) to a third input of the first multiplier 816 and provides sin(φ) to a second input of the second multiplier 818. The first multiplier 816 outputs to a first input of the second adder 820 and the second multiplier 818 outputs to a second input of the second adder 820. Accordingly, the second adder 820 outputs a corrected measured V EIN- signal V EIN_ compensated, which is described in equation 50.VIN_compensated is used in the equations described with reference to FIG. 3A to more accurately determine θ 1, θ 2, θ 3, θ 4, and responsive thereto, more accurately determine an on / off control timing for switches 122, 124, 128, and / or 130. In some examples, VIN_compensated to determine the current reference J LR( described above with reference to Equation 19) and used in a 90 degree zero voltage detection (ZCD / ZVD) control process. 90 degrees refers to setting θ 4 equal to π / 2 (equation 22). Accordingly, the control process described above with reference to Equations 1 to 26 is an example of a 90-degree ZCD / ZVD control process. In some examples, J LR is determined as shown in equation 51, where P cmd is a designed / determined power level for delivery responsive to V AUS to adjust V AUS to the regulated voltage:Accordingly, correction of a measured V EIN, as described above, allows for some or all of the various advantages, including higher efficiency, reduced harmonics, improved signal shaping, and improved system stability.FIG. 9 is a process flow diagram of an example process 900 for correcting a measured input voltage value responsive to measurement and signal path delay as described with reference to FIG. 8. In step 902, an AC grid voltage is measured with respect to a neutral voltage of the AC grid using one or more ADCs. In step 904, the AC voltage measurement is used to determine V RMS of the input voltage, an angular position in the V EIN- waveform is determined, the AC line voltage signal frequency is determined, and responsive thereto, V EIN_ correction is determined (equation 49). In step 906, the total phase error φ introduced by a measurement of V EIN and a subsequent signal path by controlling the converter control switches (e.g., switches 122, 124, 128, and / or 130) using control signals responsive to a measured V EIN is characterized.In step 908, an ideal 90 degree out-of-phase version of the measured V EIN- signal is determined. In step 910, correction factors cos(φ) and sin(φ) are determined for the measured V EIN and for V EIN_ correction. In step 912, VIN_compensated responsive to cos(φ), sin(φ) and VIN_correction(equation 50) are determined. In step 914, a current reference responsive to VIN_compensated (equation 51) is determined and the current reference is compared to a detected inductor current (such as a total current through the first and second inductors 120 and 126) using a PI compensator (or other digital compensator) to generate a compensated error signal. A compensated error represented by the compensated error signal is added to a control switch on time (t cf) to generate a compensated control switch on time. The control switch (e.g., MN1 122 or MN3 128, depending on which half period the V EIN- signal is located) is controlled responsive to the compensated control switch on time. In step 916, determining PWM timing parameters responsive to the compensated error signal and a 90 degree ZCD / ZVD control process and controlling the power converter using the PWM timing parameters occurs.FIG. 10 is a graph 1000 of total harmonic distortion (iTHD) in an output signal versus load in the boost converter system 100 of FIG. 1A. A horizontal axis of the graph 1000 indicates a load (a power level) of the power converter. A vertical axis of the graph 1000 indicates total harmonic distortion. The graph includes a curve 1002 of total harmonic distortion without V EIN- phase compensation and a curve 1004 of total harmonic distortion with V EIN- phase compensation. There is greater overall harmonic distortion in curve 1002 with no phase compensation across all load levels than in curve 1004 with phase compensation.Modifications are possible in the examples described and other examples are possible within the scope of the claims.In some examples, system design aspects and processes described herein may be used with or adapted to ZVS QSW converters other than AD-DC converters, such as AC-AC converters or DC-DC converters.In some examples, the control circuitry and processes described herein may be used to control polyphase PWM controlled devices having more than one phase, corresponding to two or more phases.In some examples, determinations described herein as being performed during device design may be performed during device testing or at a later stage.In some examples, the signal sensor 106 also detects a temperature of the biphasic boost converter 102.In some examples, an inductance may also be described as a winding.In some examples, one or more of MN1 122, MN2 124, MN3 128, or MN4 130 include structures described herein as corresponding to signal sensor 106.In some examples, a ZVS QSW power converter is controlled using a control process other than a 90 degree ZCD / ZVD control process.The term "couple" is used throughout the specification. The term may cover connections, communications, or signal paths that enable a functional relationship in accordance with this description. For example, if device A provides a signal for controlling device B to perform an action, in a first example, device A is coupled to device B, or in a second example, device A is coupled to device B via an intervening component C if the intervening component C does not substantially alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal provided by device A.In this specification, the term "and / or" (when used in a form such as A, B, and / or C) refers to any combination or subset of A, B, C, such as: (a) A alone; (b) B alone; (c) C alone; (d) A with B; (e) A with C; (f) B with C; and (g) A with B and with C. Additionally, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to implementations including any of: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.A device "configured" to perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function at a time of manufacture by a manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuring may be through firmware and / or software programming of the device, through a construction and / or layout of hardware components and interconnections of the device, or a combination thereof.As used herein, the terms "terminal", "node", "interconnect", "pin", "ball", and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are used generally to mean an interconnection between an endpoint of a device element, a circuit element, an integrated circuit, a device, or another electronic or semiconductor component.A circuit or device described herein as including certain components may instead be configured to be coupled to these components to form the described circuit arrangement device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package) and may be configured to be coupled to at least some of the passive elements and / or the sources to form the described structure either at the time of manufacture or after a time of manufacture, for example, by an end user and / or a third party.Although the use of certain transistors is described herein, other transistors (or equivalent devices) may instead be used with little or no change to the rest of the circuitry. For example, a MOSFET (such as an n-channel MOSFET, nMOSFET, or a p-channel MOSFET, pMOSFET), a gallium nitride field effect transistor (GaN-FET, such as an n-channel GaN-FET or a p-channel GaN-FET), a bipolar transistor (BJT, e.g., NPN or PNP), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistor (JFET) may be used in place of or in conjunction with the devices disclosed herein. The transistors may be depletion mode devices, extended drain devices, enhancement mode devices, natural transistors, or transistors with another type of device structures. Further, the devices may be implemented in / over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).Circuits described herein are reconfigurable to include the replacement components to provide functionality that is at least partially similar to functionality available prior to component replacement. Components shown as resistors, unless otherwise indicated, generally represent any one or more elements coupled in series and / or in parallel to provide an amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.Although certain elements of the described examples may be included in an integrated circuit and other elements are external to the integrated circuit, additional or fewer features may be incorporated into the integrated circuit in other embodiments. Additionally, some or all of the features illustrated as external to the integrated circuit may be included in the integrated circuit and / or some features illustrated as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) embedded in / over a semiconductor substrate; (ii) embedded in a single semiconductor package; (iii) embedded in the same module; and / or (iv) embedded in / on the same circuit board.Uses of the phrase "mass" in the foregoing description include a package ground, a ground ground ground, a floating ground, a virtual ground, a digital ground, a common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this description. Unless otherwise indicated, "about," "approximately," or "substantially" means prior to a + / - 10% value of the indicated value, or, if the value is zero, an appropriate range of values around zero.

Claims

An apparatus comprising: a first inductor; a second inductor; a first phase switching circuit coupled to the first inductor; a second phase switching circuit coupled to the second inductor; and a controller coupled to the first and second phase switching circuits and the PI compensator, the controller including a proportional-integral (PI) compensator having a first input and an output, the controller configured to: generate a phase error signal responsive to a switching period, a target phase delay of the second control signal with respect to the first control signal, and a phase difference between a first control signal corresponding to the first phase switching circuit and a second control signal corresponding to the second phase switching circuit; provide the phase error signal to the first input of the PI compensator; and controlling the first phase switching circuit in a first phase and the second phase switching circuit in a second phase responsive to the first and second control signals and an output signal of the PI compensator.The apparatus of claim 1, wherein the target phase delay is determined responsive to a number of phases and a phase number of the second phase switching circuit.The apparatus of claim 1, wherein the PI compensator has second and third inputs, and the controller is configured to: provide the second input of the PI compensator with a proportional compensator gain value; and provide the third input of the PI compensator with an integral compensator gain value.The apparatus of claim 3, wherein the controller is configured to: determine the proportional compensator gain value responsive to a normalized proportional compensator gain value and the switching period; and determine the integral compensator gain value responsive to a normalized integral compensator gain value and the switching period.The apparatus of claim 1, wherein the first control signal corresponds to switching times of the first phase switching circuit and the second control signal corresponds to switching times of the second phase switching circuit; and wherein the controller is configured to: compare an average current through the first phase switching circuit with an average current through the second phase switching circuit; adjust the switching times of the first phase switching circuit or the second phase switching circuit responsive to the comparing action to provide adjusted switching times; and control the first and second phase switching circuits responsive to the adjusted switching times.The apparatus of claim 5, wherein the controller is configured to perform the adjusting action responsive to a source voltage of the apparatus and an output voltage of the apparatus.The apparatus of claim 1, wherein the apparatus is a quasi-square wave power converter for voltageless switching.The apparatus of claim 1, further comprising a sensor having first and second inputs and an output, the output of the sensor being coupled to the controller; wherein the first and second inductors each have a terminal, the first input of the sensor being coupled to the terminal of the first inductor and the second input of the sensor being coupled to the terminal of the second inductor.An apparatus comprising: a first inductor having a first terminal; a second inductor having a first terminal; a first phase switching circuit having a first terminal and a control terminal, wherein the first terminal of the first phase switching circuit is coupled to the first terminal of the first inductor; a second phase switching circuit having a first terminal and a control terminal, wherein the first terminal of the second phase switching circuit is coupled to the first terminal of the second inductor; and a controller having first, second, and third outputs, the controller including a proportional integral (PI) compensator having a first input and an output, the first and second outputs of the controller being coupled to the control terminals of the first and second phase switching circuits, respectively, and the third output of the controller being coupled to the first input of the PI compensator, the controller configured to: generate a phase error signal responsive to a switching period, a target phase delay of the second control signal with respect to the first control signal, and a phase difference between a first control signal corresponding to the first phase switching circuit and a second control signal corresponding to the second phase switching circuit; provide the phase error signal to the first input of the PI compensator; and controlling the first phase switching circuit in a first phase and the second phase switching circuit in a second phase responsive to the first and second control signals and an output signal of the PI compensator.The apparatus of claim 9, wherein the PI compensator has second and third inputs, the controller has fourth and fifth outputs coupled to the second and third inputs, respectively, of the PI compensator, and the controller is configured to: provide the second input of the PI compensator with a proportional compensator gain value; and provide the third input of the PI compensator with an integral compensator gain value.The apparatus of claim 10, wherein the controller is configured to: determine the proportional compensator gain value responsive to a normalized proportional compensator gain value and the switching period; and determine the integral compensator gain value responsive to a normalized integral compensator gain value and the switching period.The apparatus of claim 9, wherein the first control signal corresponds to switching times of the first phase switching circuit and the second control signal corresponds to switching times of the second phase switching circuit; and wherein the controller is configured to: compare an average current through the first phase switching circuit with an average current through the second phase switching circuit; adjust the switching times of the first phase switching circuit or the second phase switching circuit responsive to the comparing action to provide adjusted switching times; and control the first and second phase switching circuits responsive to the adjusted switching times.The apparatus of claim 12, wherein the controller is configured to perform the adjusting action responsive to a source voltage of the apparatus and an output voltage of the apparatus.The apparatus of claim 9, further comprising a sensor having first and second inputs and an output, the output of the sensor being coupled to the controller; wherein the first and second inductors each have a second terminal, the first input of the sensor being coupled to the second terminal of the first inductor, and the second input of the sensor being coupled to the second terminal of the second inductor.An apparatus comprising: a sensor having an output; a first phase switching circuit having a control terminal; a second phase switching circuit having a control terminal; a gate driver having an input and first and second outputs, the first and second outputs of the gate driver being coupled to the control terminals of the first and second phase switching circuits, respectively; and a controller having an input and a first and second output, the controller including a proportional integral (PI) compensator having a first input and an output, the input of the controller being coupled to the output of the sensor, the first output of the controller being coupled to the input of the gate driver, and the second output of the controller being coupled to the first input of the PI compensator, the controller configured to: generate a phase error signal responsive to a phase difference between a switching period, a target phase delay of the second control signal with respect to the first control signal, and a first control signal corresponding to the first phase switching circuit, and a second control signal corresponding to the second phase switching circuit; providing the phase error signal to the first input of the PI compensator; and controlling the first phase switching circuit in a first phase and the second phase switching circuit in a second phase responsive to the first and second control signals and an output signal of the PI compensator.The apparatus of claim 15, wherein the sensor has first and second inputs, the first and second phase switching circuits each have a respective current path, the first input of the sensor is coupled to the current path of the first phase switching circuit, and the second input of the sensor is coupled to the current path of the second phase switching circuit.The apparatus of claim 15, wherein the controller has third and fourth outputs coupled to the second and third inputs, respectively, of the PI compensator, and the controller is configured to: provide the second input of the PI compensator with a proportional compensator gain value; and provide the third input of the PI compensator with an integral compensator gain value.The apparatus of claim 17, wherein the controller is configured to: determine the proportional compensator gain value responsive to a normalized proportional compensator gain value and the switching period; and determine the integral compensator gain value responsive to a normalized integral compensator gain value and the switching period.The apparatus of claim 15, wherein the first control signal corresponds to switching times of the first phase switching circuit and the second control signal corresponds to switching times of the second phase switching circuit; and wherein the controller is configured to: compare an average current through the first phase switching circuit with an average current through the second phase switching circuit; adjust the switching times of the first phase switching circuit or the second phase switching circuit responsive to the comparing action to provide adjusted switching times; and control the first and second phase switching circuits responsive to the adjusted switching times.The apparatus of claim 19, wherein the controller is configured to perform the adjusting action responsive to a source voltage of the apparatus and an output voltage of the apparatus.

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