Semiconductor component and method for manufacturing a semiconductor component

Abstract

A method for fabricating a semiconductor device is provided, comprising: forming an insulating film on a semiconductor substrate; selectively removing the insulating film; forming a metal film on the semiconductor substrate by leaving a damage layer on the surface of the semiconductor substrate, the damage layer being generated when the insulating film is selectively removed; forming an electrode by selectively removing the metal film; and forming polyimide on the electrode. The damage layer on the surface of the semiconductor substrate, generated when the insulating film is selectively removed, can be selectively removed.

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS

[0001] The present application claims priority over Japanese patent application No. 2024-145046, filed on August 27, 2024, the contents of which are hereby incorporated into this application by reference. BACKGROUND

[0002] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0003] There is a disclosed technique listed below.

[0004] [Patent Document 1] JP 2024-054039 A

[0005] Patent document 1 discloses a method for manufacturing a semiconductor device, wherein the method comprises wet etching to reduce damage to a surface of a semiconductor substrate caused by dry etching in a contact step for joining the semiconductor substrate and one or more metal wires. SUMMARY

[0006] However, if etching is performed to reduce damage to the surface of the semiconductor substrate, the problem arises that silicon pits are generated in a subsequent step or steps. Therefore, one purpose of the present disclosure is to provide a manufacturing process and the like for a semiconductor device, wherein the process forms a metal film by leaving a damage layer on the surface of the semiconductor substrate to suppress the generation of silicon pits.

[0007] Further problems and new features will become apparent from the present description and the accompanying drawings.

[0008] According to one embodiment, a method for manufacturing a semiconductor device forms a metal layer on a semiconductor substrate by leaving a damage layer on a surface of the semiconductor substrate, wherein the damage layer is generated when an intermediate insulating film is selectively removed.

[0009] According to the embodiment, the method for manufacturing the semiconductor device can be provided, wherein the method forms the metal film by leaving the damage layer on the surface of the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 shows a top view of a first semiconductor device according to the present disclosure. Fig. Figure 2 shows a cross-sectional view along the VIB-VIB line of the semiconductor device. Fig. 1. Fig. Figure 3 shows a first cross-sectional view of a semiconductor device, which explains a manufacturing process of the related semiconductor device. Fig. Figure 4 shows a second cross-sectional view of a semiconductor device, illustrating a manufacturing process of the related semiconductor device. Fig. Figure 5 shows a third cross-sectional view of a semiconductor device, illustrating a manufacturing process of the related semiconductor device. Fig. Figure 6 shows a fourth cross-sectional view of a semiconductor device, which explains a manufacturing process of the related semiconductor device. Fig. Figure 7 shows a fifth cross-sectional view of a semiconductor device, illustrating a manufacturing process of the related semiconductor device. Fig. Figure 8 shows VI characteristics when silicon pits of the semiconductor device are created, and VI characteristics when the silicon pits of the semiconductor device are not created. Fig. Figure 9 shows a schematic representation of the silicon pits formed in the semiconductor device. Fig. Figure 10 shows a flowchart of a manufacturing process for a related semiconductor device. Fig. Figure 11 shows a cross-sectional view of a manufacturing process for a related semiconductor device. Fig. Figure 12 shows a representation that illustrates a relationship between a light etching time and VF characteristics. Fig. Figure 13 shows a flowchart of a manufacturing process for a semiconductor device according to the present disclosure. Fig. Figure 14 shows a cross-sectional view of a first manufacturing step of the semiconductor device according to the present disclosure. Fig. Figure 15 shows a cross-sectional view of a second manufacturing step of the semiconductor device according to the present disclosure. Fig. Figure 16 shows a cross-sectional view illustrating a generation principle of the silicon pits. Fig. Figure 17 shows a representation illustrating the relationship between the width and depth of the silicon pit. Fig. Figure 18 shows a representation that depicts a current path when a probe is applied to a position where the silicon pits are created. Fig. Figure 19 shows a representation that depicts a current path when a bond wire is applied at the position where the silicon pits are created. Fig. Figure 20 shows a representation illustrating a consideration regarding the spacing of the silicon pits. Fig. Figure 21 shows a representation that displays a simulation result of a relationship between the distance of the silicon pits and VR characteristics. Fig. Figure 22 shows a top view of a second semiconductor device according to the present disclosure. Fig. Figure 23 shows a cross-sectional view along line XXI-XXI of the semiconductor device. Fig. 22. DETAILED DESCRIPTION FORM

[0010] Embodiments of the present invention are explained below with reference to the drawings. However, the invention according to the scope of the claims is not limited to the embodiments mentioned below. Furthermore, not all configurations described in the embodiments are necessarily essential for solving the problems. For the sake of clarity, the following descriptions and drawings are omitted and simplified where necessary. The same reference numerals are used for the same components in each of the drawings, and repeated explanations are omitted where necessary. EXPLANATION OF THE SEMICONDUCTOR ELEMENT OF THE PRESENT DISCLOSURE

[0011] Fig. Figure 1 is a top view of a first semiconductor device according to the present disclosure. Fig. 2 is a cross-sectional view along the VIB-VIB line of the semiconductor device made of Fig. 1. A first semiconductor device according to the present disclosure is described with reference to Fig. 1 and Fig. 2 explained.

[0012] As in Fig. As shown in Figure 1, the semiconductor device according to the present disclosure is configured in a rectangular shape when viewed from the top surface of a semiconductor substrate. In this example, although configured in a rectangular shape, the semiconductor device may be configured in a rectangular shape without corners, a circular shape, an oval shape, or a similar shape to occupy a specific area of ​​the semiconductor substrate. A semiconductor device 100, viewed from the top surface, has an anode pad 101 in the center and a polyimide 102 surrounding the anode pad.

[0013] As in Fig. As shown in 2, the semiconductor device according to the present disclosure has, in the order from bottom to top, a cathode electrode 24, an N + -conducting semiconductor area 201, an N -The semiconductor device according to the present disclosure is a diode comprising a PN junction of a P-type semiconductor. + -conducting semiconductor area and the N - -conducting drift region forms. The semiconductor device cannot form an N + -conducting semiconductor area 201. EXPLANATION OF THE MANUFACTURING PROCESS OF A RELATED SEMICONDUCTOR COMPONENT

[0014] Fig. Figure 3 is a first cross-sectional view of a semiconductor device, illustrating a manufacturing process of the related semiconductor device. Fig. Figure 4 is a second cross-sectional view of a semiconductor device, illustrating a manufacturing process of the related semiconductor device. Fig. Figure 5 is a third cross-sectional view of a semiconductor device, illustrating a manufacturing process of the related semiconductor device. Fig. Figure 6 is a fourth cross-sectional view of a semiconductor device, illustrating a manufacturing process of the related semiconductor device. Fig. Figure 7 is a fifth cross-sectional view of a semiconductor device, illustrating a manufacturing process of the related semiconductor device. A manufacturing process of a related semiconductor device according to the present disclosure is described with reference to Fig. 3 to Fig. 7 explained. Fig. 3 to Fig. Figure 7 shows cross-sectional views illustrating the manufacturing steps of the product. Fig. 2 represent the semiconductor device shown.

[0015] First, as in Fig. Figure 3 shows a prepared semiconductor wafer configured from a monocrystalline silicon semiconductor substrate 1a into which N-conducting impurities such as phosphorus are introduced. The semiconductor wafer has a top surface 1a and a back surface 1b opposite the top surface 1a.

[0016] The concentration of N-conducting defects in the semiconductor wafer can, for example, be approximately 2 × 10 14 cm -3 The thickness of the semiconductor wafer can be adjusted. For example, it can be set to approximately 450 micrometers to 1000 micrometers.

[0017] Next, a silicon nitride (Si3N4) film is formed on the top surface of the semiconductor wafer, and an Si3N4 film mask is formed by structuring the Si3N4 film. An elemental isolation region 12 is formed by oxidizing the top surface of the semiconductor wafer in a region other than a Si3N4 film mask region under an oxidizing atmosphere.

[0018] Next, by an ion implantation process using a resist pattern as a mask, p-conducting defects are introduced into a semiconductor substrate 1s on one side of the top surface 1a of the semiconductor wafer, thereby forming a p-conducting field region 13. As an ion implantation condition at this stage, the ion implantation condition, where, for example, an ion type such as boron (B) is selected, can deliver a dose of approximately 3.5 × 10 13 cm -2The setting of an ion implantation energy of approximately 75 keV can be cited as an example of a suitable condition.

[0019] Next, after removing the resist, annealing is carried out at, for example, about 1200 degrees Celsius for about 30 minutes under an atmosphere of nitrogen gas (N2) as an inert gas, and repair and expansion diffusion of crystal defects with respect to the P-conducting field area 13 are carried out.

[0020] Next, as in Fig. 4 shown, by the ion implantation procedure using the resist pattern as a mask the P-conducting defects are introduced into necessary sections of a cell area 2a and a scratch area 3, thereby forming a P-conducting body area 14.

[0021] In particular, this P-conducting body region 14 is located on the P-conducting field region 13 and on the N --conducting drift region 11 (1s) is formed, which are formed in cell region 2a. Additionally, the P-conducting body region 14 is formed on the N - -Drift area 11 (1s) formed in the scoring area 3.

[0022] As an ion implantation condition at this time, the ion implantation condition, in which, for example, the ion type is set to B, can be the dose as approximately 1 × 10 13 cm -2 The setting of the implantation energy to approximately 75 keV can be cited as a suitable condition, for example. After removal of the resist, annealing is carried out at, for example, approximately 1000 degrees Celsius for about 100 minutes under an atmosphere of nitrogen gas.

[0023] Next, as in Fig. 5 shown, by the ion implantation method using the resist pattern as a mask the N --conducting defects on the N- -conducting drift area 11(1s) in a peripheral area 2b and on the P-conducting body area 14 in the scribe area 3, thereby introducing an N + -conducting semiconductor region 15 is formed.

[0024] As an ion implantation condition at this time, the ion implantation condition, in which, for example, the ion type is set to arsenic (As), can be the dose as approximately 5 × 10 15 cm -2 The setting of the implantation energy to approximately 80 keV is cited as a suitable condition, for example. After removal of the resist, annealing is carried out at, for example, approximately 1000 degrees Celsius for about 100 minutes under an atmosphere of nitrogen gas.

[0025] Next, as in Fig. Figure 6 shows an interlayer insulating film 21, which consists, for example, of a phosphosilicate glass (PSG) film, formed on the upper surface 1a of the semiconductor wafer, for example, by a CVD process or the like. The interlayer insulating film 21 is formed such that it, for example, - -conducting drift area 11(1s), the P-conducting field area 13, the P-conducting body area 14 and the N + -conductive semiconductor area 15 is covered. The thickness of the interlayer insulating film 21 is, for example, approximately 0.6 micrometers. Examples of suitable materials for this interlayer insulating film 21 include a boron-phosphorus silicate glass (BPSG) film, an undoped silicate glass (NSG) film, a spin-oh glass (SOG) film, a silicon oxide (SiO2) film, a composite film of these, or the like.

[0026] Next, a contact hole (opening) 22 is formed in the interlayer insulating film 21 by an anisotropic dry etching process using the resist pattern as a mask. A mixed gas or the like, consisting, for example, of argon (Ar) gas, trifluoromethane (CHF3) gas, and tetrafluoromethane (CF4) gas, can be cited as a suitable gas for this anisotropic dry etching.

[0027] Subsequently, to reduce damage to the upper surface of the semiconductor substrate caused by dry etching, the contact hole 22 and the semiconductor substrate 1s are etched using a wet SEZ etching process with the interlayer insulating film 21 as a mask after resist removal. For example, nitric acid (HNO3) : hydrogen fluoride (HF) = 200 : 1 can be considered a suitable etching fluid for the dry SEZ etching process. Alternatively, the contact hole 22 and the semiconductor substrate 1s can be etched using the dry etching process instead of the wet SEZ etching process. For example, a mixture of oxygen (O2) and tetrafluoromethane (CF4) gas can be considered a suitable gas for this dry etching process.

[0028] Next, as in Fig. Figure 7 shows a metal layer 23, such as the anode electrode AE, being formed. In particular, the following procedure is carried out, for example. First, an aluminum-based metal film (for example, a few percent is silicon additive, the remainder is aluminum) is formed on the entire upper surface 1a of the semiconductor wafer, for example by a sputtering process, to fill the contact hole 22. The thickness of the aluminum-based metal film is, for example, about 5 micrometers.

[0029] Next, a metal layer 23 is formed from the aluminum-based metal film using the resist pattern as a mask via a dry etching process. Chlorine gas (Cl2) / boron trichloride gas (BCl3) or similar gases could be used as examples of suitable gases for this dry etching process.

[0030] Consequently, in cell area 2a, the anode electrode AE ​​is formed in the contact hole 22 and on the intermediate insulating film 21. In the scribed area 3, electrode pads 42, 43 are formed in the contact hole 22 and on the intermediate insulating film 21. Here, the metal layer 23 in the contact hole 22 is referred to as the contact section.

[0031] The anode electrode AE ​​is electrically connected to the P-conducting body region 14 formed in cell region 2a. The electrode pad 42 is electrically connected to the P-conducting body region 14 formed in scribble region 3, and the electrode pad 43 is electrically connected to the N-conducting body region 14 formed in scribble region 3. + -conductive semiconductor area 15 connected.

[0032] Next, an insulating film, consisting of an organic film containing polyimide as its main component, is formed on the anode electrode as a passivation film. The thickness of this insulating film is approximately 2.5 to 10 micrometers.

[0033] Next, the insulating film is structured using the resist pattern as a mask via a dry etching process, creating an opening that penetrates the insulating film and reaches the anode electrode AE. An anode pad is then formed by the anode electrode AE ​​in the section exposed by the opening.

[0034] Next, a back-side grinding process is performed on the back side 1b of the semiconductor wafer, reducing the thickness from approximately 800 micrometers to approximately 30 to 200 micrometers, if necessary. For example, if the breakdown voltage is approximately 600 V, the final thickness will be approximately 70 micrometers. Additionally, chemical etching and similar processes are performed, if required, to remove damage to the back side 1b.

[0035] Next, for example, a cathode electrode 24, which is electrically connected to the N, is produced by the sputtering process. - The conductive drift region 11(1s) is connected to the back side 11b of the semiconductor wafer. Then, by dicing and the like, the semiconductor substrate 1s is subdivided into one or more semiconductor chip regions 2, and by sealing in a package, if necessary, a semiconductor chip is almost completed as a semiconductor device. FOR THE FORMATION OF SILICON PITS OF THE SEMICONDUCTOR ELEMENT

[0036] Fig. Figure 8 shows VI characteristics when silicon pits of the semiconductor device are created, and VI characteristics when the silicon pits of the semiconductor device are not created. Fig. Figure 9 is a schematic representation of the silicon pits formed on the semiconductor device. Fig. Figure 10 is a flowchart of a manufacturing process for a related semiconductor device. Fig. Figure 11 is a cross-sectional view of a manufacturing process of a related semiconductor device.

[0037] As in Fig. As shown in Figure 8, in the related semiconductor device, when measuring V1 characteristic curves, a diode was produced as a good product, in which a current rises sharply at a specific voltage, as in C, and a diode as a defective product, in which a current leaks and rises gradually, as in A and B. In the defective diode, silicon pits, which are holes in silicon, were formed. Accordingly, A and B, in which the silicon pits are generated, are the defective products, and C is the good product.

[0038] As in Fig. As shown in Figure 9, silicon pits were also formed in the good product, but the silicon pit did not reach a depletion layer. For example, if the depletion layer is 0.5 micrometers thick, the silicon pit of the good product has a depth of approximately 0.5 micrometers or less, as in the middle or right, while the silicon pit of the defective product exceeds 0.5 micrometers and reaches 1 micrometer.

[0039] As in Fig. 10 and Fig. As shown in Figure 11, it is conceivable that the silicon pits are created as follows. First, an anode contact is opened by dry etching (step S1001). The opening is formed by selectively removing the insulating film, such as the interlayer insulating film, on the semiconductor substrate. This results in, as shown in the figure above in Fig. Figure 11 shows a damage layer 1101 formed on the p-conducting body region 14 in the opening. The damage layer 1101 is an unterminated layer such as a silicon suboxide.

[0040] Next, the damaged layer is removed by light etching (step S1002). As shown in the second figure in Fig. As shown in Figure 11, the damaged layer 1101 is removed. Next, an AISi electrode is formed (step S1003). As shown in the third figure in Fig. As shown in Figure 11, the anode electrode AE ​​is formed by the AISi. At this point, a trench 1102, which reaches silicon, can be formed.

[0041] Finally, after the anode is formed, the silicon pit is created by introducing alkaline liquid into trench 1102 through a polyimide formation step. Chemical liquid introduced in a subsequent heating processing step is evaporated. Additionally, an electrode is melted and embedded in a silicon pit section (step S1004). As shown in the last figure in Fig. As shown in 11, the silicon pit reaches the N - -conducting drift area 11 and is formed.

[0042] It is conceivable that such a case is a factor causing the occurrence of a leakage current. Therefore, the manufacturing process and similar aspects of the semiconductor device, in which the formation of silicon pits is suppressed, are necessary. EXPLANATION OF THE FIRST MANUFACTURING PROCESS OF THE SEMICONDUCTOR ELEMENT OF THE PRESENT DISCLOSURE

[0043] Fig. Figure 12 is a representation showing a relationship between a light etching time and VF characteristics. Fig. Figure 13 is a flowchart of a manufacturing process for a semiconductor device according to the present disclosure. Fig. Figure 14 is a cross-sectional view of a first manufacturing step of the semiconductor device according to the present disclosure. A first manufacturing process of a semiconductor device according to the present disclosure is described with reference to Fig. 13 and Fig. 14 explained.

[0044] The inventor discovered that when the damage layer is removed by step S1002 in the manufacturing process of the related semiconductor device, silicon pits are created. Additionally, the inventor discovered that, as in Fig. Figure 12 shows, for example, that by performing light etching for 10 seconds to 20 seconds the VF characteristics can decrease as resistance, whereas if the light etching is not performed, the VF characteristics decrease further.

[0045] Therefore, as in Fig. Figure 13 shows the first manufacturing process of the semiconductor device according to the present disclosure, creating an anode contact by dry etching (step S01301). As shown in the figure above in Fig. As shown in Figure 14, the damage layer 1101 is formed by the anode opening. Next, the light etching step to remove the damage layer is skipped (step S1302). As shown in the second figure in Fig. As shown in Figure 14, the damage layer 1101 is left behind. Next, the AlSi electrode is formed (step S1303). As shown in the third figure in Fig. As shown in Figure 4, the anode electrode AE ​​is formed.

[0046] Finally, the alkaline liquid is introduced through the polyimide formation step, but the chemical liquid introduced through the subsequent heating processing step is evaporated (step S1304). As shown in the last figure in Fig. As shown in Figure 14, the silicon pits are not created in the semiconductor device.

[0047] In this way, to suppress the formation of silicon pits that are created during the formation of the polyimide after the formation of the metal film, a manufacturing process for the semiconductor device can be provided in which the damage layer is left behind and the metal film is formed on the upper surface of the semiconductor substrate.

[0048] Additionally, the semiconductor device produced in this way has the insulating film selectively applied to the semiconductor substrate, the electrode formed by the metal film selectively applied to the semiconductor substrate, and the polyimide on the electrode. Furthermore, the semiconductor device has the damage layer under the electrode at the time of selective removal of the insulating film. EXPLANATION OF THE SECOND MANUFACTURING PROCESS OF THE SEMICONDUCTOR COMPONENT ACCORDING TO THE PRESENT DISCLOSURE

[0049] Fig. Figure 15 is a cross-sectional view of a second manufacturing step of the semiconductor device according to the present disclosure. Fig. Figure 16 is a cross-sectional view showing a generation principle of silicon pits. Fig. Figure 17 is a representation showing a relationship between the width and depth of the silicon pit. Fig. Figure 18 is a representation showing a current path when a probe is applied to a position where the silicon pits are created. Fig. Figure 19 is a representation showing a current path when a bond wire is applied at the position where the silicon pits are created. Fig. Figure 20 is a representation that shows a consideration regarding the spacing of the silicon pits. Fig. Figure 21 is a representation showing a simulation result of a relationship between the distance between the silicon pits and VR characteristics. A second manufacturing process of the semiconductor device according to the present disclosure is described with reference to Fig. 15 to Fig. 21 explained.

[0050] The second manufacturing process of the semiconductor device according to the present disclosure consists of controlling the generation of the silicon pits. As shown in the figure above in Fig. As shown in Figure 15, the damage layer 1101 is formed in the opening for an anode electrode contact. Next, as shown in the second figure in Fig. Figure 15 shows that the damaged layer 1101 is selectively removed by forming a mask 1103. The light etching time at this point is preferably 10 to 20 seconds.

[0051] Next, as shown in the third figure in Fig. Figure 15 shows the formation of the anode electrode AE. At this point, the trench 1102, which reaches silicon, is formed in the anode electrode AE. Next, as shown in the last figure in Fig. Figure 15 shows that after the formation of the polyimide, the silicon pits are formed by melting the anode electrode AE. However, the silicon pits are not formed in a section where the damage layer is not removed, and one location of the silicon pit is also formed selectively.

[0052] By selectively removing the damaged layer in this way, the manufacturing process of the semiconductor device, in which the generation of the silicon pits is controlled, and the semiconductor device thus formed are preserved.

[0053] Fig. Figure 16 shows the etching of silicon due to the introduction of the alkaline liquid. As in Fig. As shown in Figure 16, if the opening of the damage layer exists, the P-conducting body region 14 is etched such that it forms an angle of tan -1 √2 = 54.7 degrees (tan -1 (2) 1 / 2 = 54.7 degrees) to the upper surface. This is because, if the upper surface is assumed to have a plane orientation of {100}, its side face has a plane orientation of {111}. If its depth is assumed to be D, then D is given by D = (size X of the opening) multiplied by tan (54.7 degrees) / 2, as in Fig. Figure 17 shows that if the size X, which removes the damage layer, is 2 multiplied by (thickness to depletion) / tan (54.7 degrees), the silicon pit never reaches the depletion layer.

[0054] Therefore, the area where the damage layer is removed is preferably smaller than (thickness of the depletion layer of the semiconductor device) multiplied by 2 / tan (54.7 degrees). For example, if the depletion layer is generated starting at 500 nm, the area where the damage layer is removed preferably has a width of 708 nm. In this way, the depth of the silicon pit can be controlled by controlling the width for removing the damage layer.

[0055] As in Fig. As shown in Figure 18, a probe 1801 for a wafer test can be placed in an area where the silicon pits are generated. As shown in Fig. As shown in Figure 12, due to the VF characteristic curves, current flows more easily at an etch time of 0, whereas, when the light etching is performed, the current becomes more difficult to flow. Therefore, by placing the probe tip 1801 in the area where the selectively formed silicon pits are created, current concentration due to the probe tip 1801 can be prevented. Thus, the area where the damage layer is selectively removed is preferably suitable for combination with an area for placing the probe tip 1801.

[0056] As in Fig. As shown in Figure 19, a bond wire 1901 can be placed in the area where the silicon pits are generated. By placing the bond wire 1901 in the area where the selectively formed silicon pits are created, a current concentration due to the bond wire 1901 can be prevented, similar to that caused by the probe tip 1801. Therefore, the area where the damage layer 1101 is selectively removed is preferably suitable for combination with the area for placing the bond wire 1901.

[0057] A pit distance is defined with reference to Fig. 20 and Fig. 21 considered. As in Fig. 20 and Fig. As shown in Figure 21, when a simulation is performed by changing a pit distance, the pit distance becomes an avalanche breakdown point due to an electric field concentration at a tip of the silicon pit, and a decrease in breakdown voltage depending on the pit shape can be observed. Fig. As shown in Figure 21, the simulation reveals that VR characteristics, which are breakdown voltage characteristics, increase when the pit spacing is 10 micrometers or less, for example, at 5 micrometers. Reducing the pit spacing allows for a field plate effect, reducing the electric field at the pit tip and improving the breakdown voltage characteristics. Therefore, as shown in Figure 21, the VR characteristic curves increase when the pit spacing is 10 micrometers or less, for example, at 5 micrometers. Fig. Figure 20 shows that by selectively removing the damage layer the pit spacing is 10 micrometers or less, preferably 5 micrometers or less. EXPLANATION OF THE SECOND SEMICONDUCTOR ELEMENT ACCORDING TO THE PRESENT DISCLOSURE

[0058] Fig. Figure 22 is a top view of a second semiconductor device according to the present disclosure. Fig. Figure 23 is a cross-sectional view along line XXI-XXI of the semiconductor device. Fig. 22. A second semiconductor device according to the present disclosure is described with reference to Fig. 22 and Fig. 23 explained.

[0059] As in Fig. 22 and Fig. As shown in Figure 23, carriers from a peripheral configuration flow near the end section of the anode electrode AE ​​during a recovery process, making current concentration more likely than at the anode electrode AE ​​itself. To prevent this current concentration, light etching is performed near the end section of the anode electrode AE. This means that the end section of the anode electrode AE ​​is combined with the area where the damage layer 1101 is removed. This suppresses damage during the recovery process. The "near the end section" is, for example, a region extending from approximately 5 micrometers to 100 micrometers from the end section.

[0060] For example, the semiconductor device according to the above embodiment can have a configuration in which the conductivity type (p-type or n-type) of the semiconductor substrate, semiconductor layer, diffusion layer (diffusion area), and the like is reversed. Therefore, if one conductivity type is an n-type and the other a p-type, and the other a second conductivity type, this allows the first conductivity type to be set to the p-type and the second conductivity type to the n-type, and vice versa.

[0061] As described above, the invention made by the present inventor has been specifically explained on the basis of the embodiment, but the present invention is not limited to the embodiment mentioned above and can of course be variably modified within a range that does not deviate from its core. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2024-145046

[0001] JP 2024-054039 A

[0004]

Claims

[1] Method for manufacturing a semiconductor device, the method comprising: Forming an insulating film on a semiconductor substrate; selective removal of the insulating film; Forming a metal film on the semiconductor substrate by leaving a damage layer on the surface of the semiconductor substrate, wherein the damage layer is created when the insulating film is selectively removed; Forming an electrode by selectively removing the metal film; and Formation of polyimide on the electrode. [2] Method according to claim 1, wherein the damage layer on the surface of the semiconductor substrate which is generated when the insulating film is selectively removed is selectively removed. [3] Method according to claim 2, wherein an area in which the damage layer is removed is smaller than (a thickness of a depletion layer of the semiconductor device) multiplied by 2 / tan (54.7 degrees). [4] Method according to claim 2, wherein the removal of the damaged layer is carried out by performing wet sets for 10 seconds to 20 seconds. [5] Method according to claim 2, wherein a probe tip or bond wire for a wafer test is placed in an area where the damage layer is removed. [6] Method according to claim 2, wherein the distance of an area in which the damage layer is removed is 5 micrometers or less. [7] Method according to claim 2, wherein an area in which the damage layer is removed is located near an end section of the electrode. [8] Semiconductor device, comprising: an insulating film that is selectively arranged on a semiconductor substrate; an electrode formed by a metal film selectively arranged on the semiconductor substrate; and Polyimide on the electrode, wherein The semiconductor device exhibits a damage layer under the electrode upon selective removal of the insulating film. [9] Semiconductor device according to claim 8, wherein the damage layer is selectively removed. [10] Semiconductor device according to claim 9, wherein an area in which the damage layer is removed is smaller than (a thickness of a depletion layer of the semiconductor device) multiplied by 2 / tan (54.7 degrees). [11] Semiconductor device according to claim 9, wherein a probe tip or bond wire for a wafer test is placed in an area where the damage layer is removed. [12] Semiconductor device according to claim 9, wherein the distance of a region in which the damage layer is removed is 5 micrometers or less. [13] Semiconductor device according to claim 9, wherein an area in which the damage layer is removed is located near an end section of the electrode.

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