Signal generation in and / or for a radio device

Abstract

A method comprises generating an output clock in a digitally controlled oscillator, splitting the output clock to generate a split clock, generating a feedback clock based on the split clock, generating an error signal based on a phase difference between a reference clock and the feedback clock, and controlling the digitally controlled oscillator based on the error signal, wherein generating the feedback clock involves connecting a first current source to a capacitor according to a fixed delay with respect to the split clock, and connecting a second current source to the capacitor before the fixed delay according to a first programmable selection parameter.This involves connecting a third current source to the capacitor before the fixed delay according to a second programmable selection parameter and generating the feedback clock based on a voltage of the capacitor after connecting the first, second and third current sources to the capacitor.

Description

TECHNICAL AREA

[0001] The present disclosure relates to the field of communication and in particular to signal generation in and / or for a radio device. BACKGROUND

[0002] Low-power networked devices, such as Internet of Things (IoT) devices, require energy efficiency. Large networks of low-power, battery-operated IoT devices are limited by their battery consumption. Application areas such as home automation require IoT devices operating in random-sparse event modes, which result in high power consumption due to the listening time while a transceiver is in standby mode. OVERVIEW

[0003] This overview is provided to present a selection of concepts in a simplified form, which are described in more detail below. This overview is not intended to identify key factors or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0004] In one embodiment, a method includes generating an output clock signal in a digitally controlled oscillator, splitting the output clock signal to generate a split clock signal, generating a feedback clock signal based on the split clock signal, generating a phase error signal based on a phase difference between a reference clock signal and the feedback clock signal, and controlling the digitally controlled oscillator based on the phase error signal, wherein generating the feedback clock signal involves connecting a first current source to a capacitor according to a fixed delay with respect to the split clock signal, and connecting a second current source to the capacitor before the fixed delay according to a first programmable selection parameter.This involves connecting a third current source to the capacitor before the fixed delay according to a second programmable selection parameter and generating the feedback clock signal based on a voltage across the capacitor after connecting the first, second, and third current sources to the capacitor.

[0005] In one embodiment, a system includes a means for generating an output clock signal in a digitally controlled oscillator, a means for splitting the output clock signal to generate a split clock signal, a means for generating a feedback clock signal based on the split clock signal, a means for generating a phase error signal based on a phase difference between a reference clock signal and the feedback clock signal, and a means for controlling the digitally controlled oscillator based on the phase error signal, wherein the means for generating the feedback clock signal includes a means for connecting a first current source to a capacitor according to a fixed delay with respect to the split clock signal, and a means for connecting a second current source to the capacitor before the fixed delay according to a first programmable selection parameter.The device includes a means for connecting a third current source to the capacitor before the fixed delay according to a second programmable selection parameter and a means for generating the feedback clock signal based on a voltage across the capacitor after connecting the first, second, and third current sources to the capacitor.

[0006] In one embodiment, a frequency synthesizer includes a digitally controlled oscillator configured to generate an output clock signal based on a digital control word, a clock divider configured to split the output clock signal to generate a split clock signal, a digital-to-digital converter configured to generate a feedback clock signal based on the split clock signal, a time-to-digital converter configured to generate a phase error signal based on a bias control word and a phase difference between a reference clock signal and the feedback clock signal, and a loop filter configured to generate the digital control word based on the phase error signal, wherein the digital-to-digital converter includes a delay circuit comprising a capacitor, a first current source, a second current source, a third current source, and a buffer configured toto generate the feedback clock signal based on a voltage of the capacitor, includes, and includes a precharge generator configured to generate a first timing signal to connect the first current source to the capacitor according to a fixed delay with respect to the split clock signal, a second timing signal to connect the second current source to the capacitor according to a first programmable selection parameter, and a third timing signal to connect the third current source to the capacitor according to a second programmable selection parameter.

[0007] In one embodiment, a radio includes an antenna connector, a transmit / receive switch connected to the antenna connector, a receive path connected to the transmit / receive switch, a transmit path connected to the transmit / receive switch, and a processor configured to connect the receive path to the transmit / receive switch in a receive mode of the radio and to connect the transmit path to the transmit / receive switch in a transmit mode of the radio, wherein the transmit path includes a frequency synthesizer configured to generate an output clock signal, a local oscillator generator configured to generate a local oscillator signal based on the output clock signal, and a power amplifier connected to the transmit / receive switch and configured to amplify the local oscillator signal to generate a transmit signal.wherein the frequency synthesizer includes a digitally controlled oscillator configured to generate the output clock signal based on a digital control word, a clock divider configured to split the output clock signal to generate a split clock signal, a digital-to-digital converter configured to generate a feedback clock signal based on the split clock signal, a time-to-digital converter configured to generate a phase error signal based on a bias control word and a phase difference between a reference clock signal and the feedback clock signal, and a loop filter connected to the time-to-digital converter and configured to generate the digital control word based on the phase error signal, wherein the digital-to-digital converter includes a delay circuit comprising a capacitor, a first current source, a second current source,It includes a third current source and a buffer configured to generate the feedback clock signal based on a voltage of the capacitor, and a precharge generator configured to generate a first timing signal to connect the first current source to the capacitor according to a fixed delay with respect to the split clock signal, a second timing signal to connect the second current source to the capacitor according to a first programmable selection parameter, and a third timing signal to connect the third current source to the capacitor according to a second programmable selection parameter.

[0008] To achieve the foregoing and related purposes, the following description and the accompanying drawings present certain illustrative aspects and implementations. These indicate only some of the various ways in which one or more aspects may be employed. Other aspects, advantages, and novel features of the disclosure will become apparent from the following detailed description when considered in conjunction with the accompanying drawings. DESCRIPTION OF THE FIGURES Fig. Figure 1 is a diagram of a radio device according to some embodiments. Fig. Figure 2 is a diagram illustrating a frequency synthesizer according to some embodiments. Fig. 3 and Fig. Figure 4 shows diagrams of a digital time converter (DTC) according to some embodiments. Fig. 5A, Fig. 5B and Fig. 5C are timing diagrams that illustrate the operation of a DTC according to some embodiments. Fig. Figure 6 is a diagram illustrating an exemplary method for generating a timing control signal according to some embodiments. Fig. Figure 7 is a diagram illustrating an exemplary computer-readable medium according to some embodiments. DETAILED DESCRIPTION

[0009] The claimed subject matter is now described with reference to the drawings, using the same reference numerals throughout to refer to the same elements. Numerous specific details are set forth in the following description for the purpose of clarification and to provide a thorough understanding of the claimed subject matter. However, it may be obvious that the claimed subject matter can be practiced without these specific details. In other cases, well-known structures and devices are shown in block diagram form to facilitate the description of the claimed subject matter.

[0010] It is understood that the following description of embodiments is not to be understood in a limiting sense. The scope of this disclosure is not to be limited by the embodiments described below or by the drawings, which are to be regarded as illustrative only. The drawings are to be regarded as schematic representations, and the elements illustrated in the drawings are not necessarily shown to scale. Rather, the various elements are depicted in such a way that their function and general purpose become obvious to a person skilled in the art.

[0011] All numerical values ​​within the detailed description and claims herein are modified by "about" or "approximately" to reflect the stated value and take into account experimental errors and variations that would be expected by an average person skilled in the art.

[0012] Fig. Figure 1 is a simplified block diagram of a radio device 100 according to some embodiments. The radio device 100 can support one or more communication protocols, such as Bluetooth (BT), Bluetooth Low Energy (BLE), Wi-Fi, or another communication protocol. According to some embodiments, the radio device includes a processor 102, such as a digital baseband processor, and a transmit / receive switch (SE switch) 104 configured to selectively connect an antenna 106 to a transmit path 108 or a receive path 110.In some embodiments, the transmit path 108 includes a frequency synthesizer 112 configured to generate an output clock signal, a local oscillator (LO) generator 114 configured to generate an LO signal based on the output clock signal, and a power amplifier 116 connected to the SE switch 104 and configured to amplify the LO signal to generate a transmit signal. In some embodiments, the receive path 110 includes a low-noise amplifier 118 for amplifying a receive signal, a mixer 120 for mixing the receive signal and the LO signal, a filter 122, such as a baseband filter or an intermediate frequency filter (depending on the radio architecture), for demodulating the receive signal, and the digital-to-analog converter (DAC) 124 for digitizing the receive signal.

[0013] The Processor 102 implements a software or firmware application that controls communication through the Radio 100. The Processor 102 comprises one or more processors, microprocessors, data processors, coprocessors, application-specific integrated circuits (ASICs), controllers, programmable logic devices, chipsets, field-programmable gate arrays (FPGAs), application-specific instruction set processors (ASIPs), system-on-chips (SoCs), central processing units (CPUs) (e.g., one or more cores), microcontrollers, and / or another type of component that interprets and / or executes instructions and / or data. The Processor 102 can be implemented as hardware (e.g., a microprocessor, etc.) or a combination of hardware and software (e.g., an SoC, an ASIC, etc.) and can include one or more memories (e.g.,Cache, random access memory (RAM), dynamic random access memory (DRAM), cache, read-only memory (ROM), programmable read-only memory (PROM), static random access memory (SRAM), single inline memory module (SIMM), dual inline memory module (DIMM), flash memory and / or other suitable type of memory).

[0014] The processor 102 controls the SE switch 104 to switch between transmit and receive modes, so that the transmit path 108 is connected to the antenna 106 during a transmit mode and the receive path 110 is connected to the antenna 106 during a receive mode. The radio 100 can have fewer components, additional components, different components, and / or a different arrangement of components than those shown in Fig. 1 illustrated include.

[0015] Fig. Figure 2 is a simplified block diagram of the frequency synthesizer 112 according to some embodiments. In some embodiments, the frequency synthesizer 112 employs a digital phase-locked loop (DPLL) topology. The frequency synthesizer 112 includes a crystal oscillator (XO) 200 configured to generate an analog reference clock signal (CKR), a time-to-digital converter (TDC) 202 configured to generate a phase error signal (tdc0[k]) based on a phase difference between the reference clock signal (CKR) and a feedback clock signal (CKF), and a digital loop filter 204 configured to filter the phase error signal, tdc0[k], to produce a control signal (tw). DCO [k]) to generate, and a digitally controlled oscillator 206 to generate an output clock signal (CKV) based on the control signal (tw DCO[k]) to generate. In some embodiments, the feedback clock signal (CKF) is generated by a multimodulus divider (MMD) 208 configured to split the output clock signal (CKV) to generate a split clock signal (CKD), and a digital time converter (DTC) 210 configured to suppress quantization noise generated in the MMD 208 and to generate the analog feedback clock signal (CKF).

[0016] In some embodiments, a frequency control word (FCW) is provided to a sigma-delta modulator (SDM) 216. Multiplying the FCW by the frequency of the reference clock signal (CKR) defines the target frequency of the frequency synthesizer 112. An output of the SDM 216 is provided to the MMD 208, and a factor representing an accumulated quantization error of the SDM 216 is compensated by a gain factor (g). DTC ) scaled in a multiplication unit 218 and provided to the DTC 210.

[0017] Fig. Figure 3 is a block diagram of the DTC 210 according to some embodiments. In some embodiments, the DTC 210 includes a delay circuit 300 configured to generate the feedback clock signal (CKF), a precharge generator 302 configured to generate timing signals for the delay circuit 300 based on the output clock signal (CKV) and the split clock signal (CKD), and a power management unit 304 configured to generate a gate-controlled clock signal (CKG) for the precharge generator 302 to save power. In some embodiments, the delay circuit 300 implements an inverse constant slope (ICS) topology.

[0018] Fig. Figure 4 is a detailed block diagram of the DTC 210 according to some embodiments. In some embodiments, the delay circuit includes 300 n current sources 400 (xM1...xM) n), which are connected by switch 402, for charging a capacitor 404, a buffer 406 for generating the feedback clock signal (CKF) in response to a voltage across the capacitor 404 reaching a threshold value (Vsw), and a switch 408 configured to discharge the capacitor 404 to ground in response to a RESET signal from the precharge generator 302.

[0019] In some embodiments, the precharge generator 302 generates timing control signals (ϕ1...ϕ). n ) to control switches 402 to set a programmable delay between the split clock signal (CKD) and the feedback clock signal (CKF). The timing control signals (ϕ1...ϕ nThe charging rate of capacitor 404 is controlled by sequentially connecting the current sources 400 through the switches 402. Connecting additional current sources 400 to capacitor 404 increases the charging rate. By controlling the timing of the connection between the current sources 400 and capacitor 404, the precise time required to charge capacitor 404 to reach the threshold (Vsw) and generate the feedback clock signal (CKF) can be controlled.

[0020] In some embodiments, the precharge generator 302 generates the timing control signals (ϕ1...ϕ). n ) for controlling the delay circuit 300. The precharge generator 302 includes a series of m flip-flops 410 that sample the CKD signal and the timing control signal ϕ n after a fixed delay at mT dcogenerate. The precharge generator 302 includes n-1 timing signal stages 412, each controlled by a precharge selection parameter (sel pc1 ...sel pcn-1 ) are configurable. Thus, the first timing signal stage 412 generates ϕ1 and the last timing signal stage 412 generates ϕ n-1 . Each timing control signal stage 412 includes a multiplexer 414, which is used to generate an intermediate-stage timing control signal ϕ' x for an xth timing signal stage 412, which ϕ n anticipated, by selecting one of the m flip-flops 410 based on the preload selection parameter (sel pcx ) is configured, therefore ϕn−ϕx'=selpcx⋅Tdco, In some embodiments, the flip-flops 416A, 416B sense the positive and negative edges of the signal, respectively. ϕx' Signals off. A 418 multiplexer is defined by an edge selection parameter (sel ϕx) configurable to determine which edge to use to generate the timing signal ϕ x is used, thereby increasing the resolution of the DTC 210 according to ϕn−ϕx'=selpcx⋅Tdco / 2 is doubled, where T dco The duration of the CKV signal generated by the DCO 206.

[0021] Fig. 5A and Fig. Figure 5B contains timing diagrams 500 and 502 illustrating the operation of the DTC 210 in a simplified example using two current sources 400 according to some embodiments. Two current generators I1 and I2, exhibiting currents in a ratio of M2:M1, are connected to charge the capacitor 404 by closing the switches 402 in response to the timing signals ϕ1 and ϕ2. When the voltage across the capacitor 404 reaches V c (t) the threshold V SWWhen buffer 406 is crossed, CKF is triggered. The control of the timer that closes the first and second switches 402 determines the DTC delay (T). dtc ), which is defined as the time between the switching of the last timing signal ϕ2 at t0 and the time at which the threshold V SW of the buffer of v c (t) is crossed, is measured. The time by which ϕ1 anticipates ϕ2 is T. pc , programmable via the parameters sel pc1 and sel ϕ1 according to the expression T pc1 = sel pc1 · T dco , if sel ϕ1 = 0, and T pc1 = sel pc1 · T dco + T dco / 2, if sel ϕ1 = 1. The voltage v c (t) at time t0 depends on the selected T pc ab: A longer T pcThis results in a higher starting voltage at the time the second switch closes, since I1 had more time to charge capacitor 404. At t0, the second (last) switch 402 closes, and capacitor 404 continues to be charged by the sum of the currents from I1 and I2 towards VDD.

[0022] To illustrate the intrinsic linearity of the delay circuit 300, consider the load capacity and its characteristic equation: dt=C(V)l(V)⋅dV, where the explicit dependence of the capacitance and current at the output node is highlighted (e.g., due to drain modulation and other nonlinear effects). Considering the first integration period, during which I1 is active, equation 1 becomes: Tpc=∫0VpcC(V)I1(V)⋅dV=1M1∫0VpcC(V)I1(V)⋅dV.

[0023] Taking into account the second integration period, in which both I1 and I2 are activated: Tdtc=∫VpcVSWC(V)I1(V)+I2(V)⋅dV=1M1+M2∫VpcVSWC(V)I1(V)+I2(V)⋅dV, it follows: Tdtc=1M1+M2⋅∫0VSWC(V)I1(V)⋅dV−M1M1+M2⋅Tpc.

[0024] The delay of the DTC 210 exhibits a linear dependence on T. PC with a slope M1 / (M1 + M2). The effects of channel length modulation and other nonlinear capacitor effects are included in the first integral, which is a constant since the integration limits are fixed; therefore, they do not affect the linearity of the DTC 210.

[0025] By extending this example to n levels, the propagation delay can be described as follows: Tdc=M1∑i=1nMi⋅(∫0VSWC(V)I1(V)⋅dV−∑i=1nTpc,i⋅Mi).

[0026] The achievable time resolution of the DTC 210 is: LSBdtc=LSBpcM1∑i=1nMi, where the value of LSB dtc decreases with increasing value of n.

[0027] To provide a continuous property of the segmented delay circuit 300, the ratio between two adjacent current sources 400 is equal to the number of timing signal stages 412 in the precharge generator 302: N=MiMi−1, with the exception of the last power source 400, which is dimensioned as follows: Mn=Nn−∑i=1nMi.

[0028] Fig. Figure 5C is a timing diagram 504 illustrating the operation of the DTC 210 using n current sources 400 according to some embodiments. Each timing signal stage 412 is defined by the pre-charge selection parameter (sel pcx ) and the flank selection parameter (sele ϕx) configurable to determine the individual charging contribution of each time control signal stage 412, which are combined to determine the overall delay of the DTC 210.

[0029] The flip-flops 410 in the precharge generator 302 are clocked at or near the frequency of the DCO 206, resulting in significant power consumption. In some embodiments, for low-power applications, the power consumption of the precharge generator 302 can be reduced by the power management unit 304. The power management unit 304 generates a gate-controlled clock signal (CKG). A logic gate 420 detects when CKG is high and ϕ n low to activate the gate-controlled clock signal (CKG). As soon as the rising edge of CKG reaches ϕ n (i.e. after mT) dcoAs the signal propagates, the logic gate 420 detects that all timing signal stages 412 have generated outputs and sets CKG to ground by switching a multiplexer 422. The power management unit 304 can be configured to activate CKG on the rising or falling edge of CKD. In an embodiment where the number of flip-flops 410 in each timing signal stage 412 is 10 and the ratio of CKV to CKD is greater than 100, the power management unit 304 can achieve a power saving of approximately 90%.

[0030] In some embodiments, the RESET signal is generated by the reset circuit 423, which includes a logic gate 424 that detects when CKE is high and CKD is low (i.e., the falling edge of CKD), and a flip-flop 426 controlled by CKV gate that buffers the output of the logic gate 424.

[0031] Fig. Figure 6 is a diagram illustrating an exemplary method 600 for generating a timing control signal according to some embodiments. At 602, an output clock signal is generated in a digitally controlled oscillator 206. At 604, the output clock signal is split to generate a split clock signal. At 606, a feedback clock signal is generated based on the split clock signal. At 608, a phase error signal is generated based on a phase difference between a reference clock signal and the feedback clock signal. At 610, the digitally controlled oscillator 206 is controlled based on the phase error signal. Generating the feedback clock signal at 606 involves connecting a first current source 400 to a capacitor 404 with a fixed delay relative to the split clock signal at 612.At 614, a second current source 400 is connected to the capacitor 404 before the fixed delay according to a first programmable selection parameter. At 616, a third current source 400 is connected to the capacitor 404 before the fixed delay according to a second programmable selection parameter. At 618, the feedback clock signal is generated based on a voltage across the capacitor 404.

[0032] Fig.Figure 7 illustrates an exemplary embodiment 700 of a computer-readable medium 702 according to some embodiments. One or more embodiments involve a computer-readable medium containing processor-executable instructions configured to implement one or more of the techniques presented herein. The embodiment 700 includes a non-volatile, computer-readable medium 702 (e.g., a CD-R, DVD-R, flash drive, disk of a hard disk drive, etc.) on which computer-readable data 704 is encoded.These computer-readable data 704 in turn include a set of processor-executable computer instructions 706, which, when executed by a computing device 708 comprising a reader 710 for reading the processor-executable computer instructions 706 and a processor 712 for executing the processor-executable computer instructions 706, are configured to enable operations according to one or more of the principles set forth herein. In some embodiments, the processor-executable computer instructions 706, when executed, are configured to enable the performance of a method 714, such as at least some of the aforementioned method(s). In some embodiments, the processor-executable computer instructions 706, when executed, are configured to enable the implementation of a system, such as at least some of the one or more aforementioned systems.Many such computer-readable media can be developed by average professionals who are configured to work according to the techniques presented herein.

[0033] The term "computer-readable media" can encompass communication media. Communication media typically contain computer-readable instructions or other data in a "modulated data signal," such as a carrier wafer or other transport mechanism, and include any information delivery medium. The term "modulated data signal" can encompass a signal in which one or more of its properties are set or modified to encode information within the signal.

[0034] In one embodiment, a method includes generating an output clock signal in a digitally controlled oscillator, splitting the output clock signal to generate a split clock signal, generating a feedback clock signal based on the split clock signal, generating a phase error signal based on a phase difference between a reference clock signal and the feedback clock signal, and controlling the digitally controlled oscillator based on the phase error signal, wherein generating the feedback clock signal involves connecting a first current source to a capacitor according to a fixed delay with respect to the split clock signal, and connecting a second current source to the capacitor before the fixed delay according to a first programmable selection parameter.This involves connecting a third current source to the capacitor before the fixed delay according to a second programmable selection parameter and generating the feedback clock signal based on a voltage across the capacitor after connecting the first, second, and third current sources to the capacitor.

[0035] In one embodiment, the method includes providing the shared clock signal for a set of serial flip-flops clocked by a first clock signal, and generating a first timing signal to connect the first current source to the capacitor at an output of a last flip-flop in the set of serial flip-flops.

[0036] In one embodiment, the method involves suppressing the first clock signal after generating the first timing signal.

[0037] In one embodiment, the method includes generating a second timing signal to connect the second current source to the capacitor at an output of a first selected flip-flop in the set of serial flip-flops based on the first programmable selection parameter, and generating a third timing signal to connect the third current source to the capacitor at an output of a second selected flip-flop in the set of serial flip-flops based on the second programmable selection parameter.

[0038] In one embodiment, the method involves configuring a first multiplexer connected to each of the flip-flops in the set of serial flip-flops, based on the first programmable selection parameter, to connect to the first selected flip-flop to generate the second timing signal, and configuring a second multiplexer connected to each of the flip-flops in the set of serial flip-flops, based on the second programmable selection parameter, to connect to the second selected flip-flop to generate the third timing signal.

[0039] In one embodiment, the method involves configuring a first multiplexer connected to each of the flip-flops in the set of serial flip-flops, based on the first programmable selection parameter, to connect to a first selected flip-flop to generate an intermediate timing signal; connecting the first multiplexer to a first flip-flop clocked by a rising edge of the output clock signal; connecting the first flip-flop to a second flip-flop clocked by a falling edge of the output clock signal; and selecting an output from either the first flip-flop or the second flip-flop to generate a second timing signal for connecting the second current source to the capacitor.

[0040] In one embodiment, the method involves discharging the capacitor after generating the feedback clock signal.

[0041] In one embodiment, a frequency synthesizer includes a digitally controlled oscillator configured to generate an output clock signal based on a digital control word, a clock divider configured to split the output clock signal to generate a split clock signal, a digital-to-digital converter configured to generate a feedback clock signal based on the split clock signal, a time-to-digital converter configured to generate a phase error signal based on a bias control word and a phase difference between a reference clock signal and the feedback clock signal, and a loop filter configured to generate the digital control word based on the phase error signal, wherein the digital-to-digital converter includes a delay circuit comprising a capacitor, a first current source, a second current source, a third current source, and a buffer configured toto generate the feedback clock signal based on a voltage of the capacitor, includes, and includes a precharge generator configured to generate a first timing signal to connect the first current source to the capacitor according to a fixed delay with respect to the split clock signal, a second timing signal to connect the second current source to the capacitor according to a first programmable selection parameter, and a third timing signal to connect the third current source to the capacitor according to a second programmable selection parameter.

[0042] In one embodiment, the precharge generator includes a set of serial flip-flops connected to the shared clock signal and clocked by a first clock signal, and the first timing signal is generated at an output of a last flip-flop in the set of serial flip-flops.

[0043] In one embodiment, the digital time converter includes a power management unit configured to suppress the first clock signal after the first timing control signal has been generated.

[0044] In one embodiment, the precharge generator includes a first multiplexer connected to each of the flip-flops in the set of serial flip-flops and configured, based on the first programmable selection parameter, to connect to a first selected flip-flop to generate the second timing signal, and a second multiplexer connected to each of the flip-flops in the set of serial flip-flops and configured, based on the second programmable selection parameter, to connect to a second selected flip-flop to generate the second timing signal.

[0045] In one embodiment, the precharge generator includes a first multiplexer connected to each of the flip-flops in the set of serial flip-flops and configured, based on the first programmable selection parameter, to connect to a first selected flip-flop to generate an intermediate timing signal; a first flip-flop connected to the first multiplexer and clocked by a rising edge of the output clock signal; a second flip-flop connected to the first flip-flop and clocked by a falling edge of the output clock signal; and a second multiplexer connected to the first and second flip-flops and configured to select an output from either the first or second flip-flop to generate the second timing signal for connecting the second current source to the capacitor.

[0046] In one embodiment, the digital time converter includes a switch that selectively connects the capacitor to ground, and a reset circuit configured to generate a reset signal to control the switch to discharge the capacitor after generating the feedback clock signal.

[0047] In one embodiment, the first current source has a first quantity, the second current source has the first quantity, and the third current source has a second quantity that differs from the first quantity.

[0048] In one embodiment, a radio includes an antenna connector, a transmit / receive switch connected to the antenna connector, a receive path connected to the transmit / receive switch, a transmit path connected to the transmit / receive switch, and a processor configured to connect the receive path to the transmit / receive switch in a receive mode of the radio and to connect the transmit path to the transmit / receive switch in a transmit mode of the radio, wherein the transmit path includes a frequency synthesizer configured to generate an output clock signal, a local oscillator generator configured to generate a local oscillator signal based on the output clock signal, and a power amplifier connected to the transmit / receive switch and configured to amplify the local oscillator signal to generate a transmit signal.wherein the frequency synthesizer includes a digitally controlled oscillator configured to generate the output clock signal based on a digital control word, a clock divider configured to split the output clock signal to generate a split clock signal, a digital-to-digital converter configured to generate a feedback clock signal based on the split clock signal, a time-to-digital converter configured to generate a phase error signal based on a bias control word and a phase difference between a reference clock signal and the feedback clock signal, and a loop filter connected to the time-to-digital converter and configured to generate the digital control word based on the phase error signal, wherein the digital-to-digital converter includes a delay circuit comprising a capacitor, a first current source, a second current source,It includes a third current source and a buffer configured to generate the feedback clock signal based on a voltage of the capacitor, and a precharge generator configured to generate a first timing signal to connect the first current source to the capacitor according to a fixed delay with respect to the split clock signal, a second timing signal to connect the second current source to the capacitor according to a first programmable selection parameter, and a third timing signal to connect the third current source to the capacitor according to a second programmable selection parameter.

[0049] In one embodiment, the precharge generator includes a set of serial flip-flops connected to the shared clock signal and clocked by a first clock signal, a first multiplexer connected to each of the flip-flops in the set of serial flip-flops and configured, based on the first programmable selection parameter, to connect to a first selected flip-flop to generate the second timing signal, and a second multiplexer connected to each of the flip-flops in the set of serial flip-flops and configured, based on the second programmable selection parameter, to connect to a second selected flip-flop to generate the second timing signal.

[0050] In one embodiment, the digital time converter includes a power management unit configured to suppress the first clock signal after the first timing control signal has been generated.

[0051] In one embodiment, the first timing signal for connecting the first current source to the capacitor is generated at an output of a last flip-flop in the set of serial flip-flops.

[0052] In one embodiment, the digital time converter includes a switch that selectively connects the capacitor to ground, and a reset circuit configured to generate a reset signal to control the switch to discharge the capacitor after generating the feedback clock signal.

[0053] In one embodiment, the first current source has a first quantity, the second current source has the first quantity, and the third current source has a second quantity that differs from the first quantity.

[0054] Although the subject matter was described in a language specific to structural features and / or methodological actions, it is understood that the subject matter defined in the attached claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms of implementing the claims.

[0055] As used in this application, the terms "component", "module", "system", "interface", and the like are generally intended to refer to a computer-related entity, either hardware, a combination of hardware and software, software, or software in execution. One or more components may be located on a single computer and / or distributed between two or more computers.

[0056] Furthermore, the claimed subject matter can be implemented as a method, device, or manufactured article using standard programming and / or engineering techniques to generate software, firmware, hardware, or any combination thereof for controlling a computer to implement the disclosed subject matter. The term "manufactured article," as used herein, is intended to include a computer program accessible from any computer-readable device, any computer-readable medium, or any computer-readable medium. The person skilled in the art will naturally recognize that many modifications to this configuration can be made without altering the scope or concept of the claimed subject matter.

[0057] Various operations of embodiments are provided herein. In one embodiment, one or more of the described operations may represent computer-readable instructions stored on one or more computer-readable media, which, when executed by a computing device, cause the computing device to perform the described operations. The order in which some or all of the operations are described should not be interpreted as implying that these operations are necessarily dependent on the order. An alternative order will be apparent to a person skilled in the art who benefits from this description. Furthermore, it is understood that not all operations are necessarily present in every embodiment provided herein.

[0058] Any aspect or design described herein as an “example” and / or the like is not necessarily to be interpreted as being advantageous over other aspects or designs. Instead, the use of the word “example” is intended to represent a possible aspect and / or implementation that may relate to the techniques presented herein. Such examples are not necessary for such techniques, nor are they intended to be limiting. Different embodiments of such techniques may include such an example alone or in combination with other features, and / or may vary and / or omit the illustrated example.

[0059] As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is to say, unless otherwise specified or clear from the context, "X substitutes A or B" is intended to mean any of the natural inclusive permutations. That is to say, if X substitutes A, X substitutes B, or X substitutes both A and B, then "X substitutes A or B" is satisfied in each of the foregoing cases. Furthermore, the articles "a" and "an", as used in this application and the attached claims, may generally be interpreted as meaning "one or more", unless otherwise specified or it is clear from the context that they refer to a singular form. Also, unless otherwise specified, "first", "second", or the like are not intended to imply any temporal aspect, spatial aspect, order, etc. Rather, such terms are used merely as identifiers, names, etc.Used for features, elements, units, etc. For example, a first element and a second element generally correspond to element A and element B, or to two different elements, or to two identical elements, or to the same element.

[0060] Although the disclosure has been shown and described with respect to one or more implementations, equivalent changes and modifications will occur to other skilled persons based on reading and understanding this patent specification and the accompanying drawings. The disclosure includes all such modifications and changes and is limited only by the scope of the following claims. In particular, with respect to the various functions performed by the components described above (e.g., elements, resources, etc.), the terms used to describe such components, unless otherwise specified, shall correspond to any component that performs the specified function of the described component (e.g.,(which is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary implementations of the disclosure illustrated herein. Although a particular feature of the disclosure may have been disclosed with respect to only one of several implementations, such a feature may also be combined with one or more other features of the other implementations, as may be desired and advantageous for a given or particular application. Furthermore, to the extent that the terms "comprises," "incorporating," "featuring," "with," or variations thereof are used either in the detailed description or the claims, such terms are to be understood as inclusive in a similar way to the term "containing."

[0061] Although the subject matter has been described with reference to illustrative embodiments, this description is not to be interpreted in a restrictive sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the present disclosure, will be obvious to the person skilled in the art with reference to the description. It is therefore intended that the appended claims encompass all such modifications or embodiments.