Device for integrating existing silicon chips into three-dimensionally integrated stacks

Abstract

Device comprising the following: a logic chip (110) with a component side (120) facing a rear side (125), wherein the logic chip (110) has a plurality of vias (130) through silicon; a memory chip (210) above the back (125) of the logic chip (110), wherein the memory chip (210) has a component side opposite a back, the component side of the memory chip (210) facing the back (125) of the logic chip (110), and wherein the memory chip (210) has a plurality of contact pads (220); and a heat sink (400) above the back of the memory chip (210), wherein the device further comprises a housing which is connected to the component side (120) of the logic chip (110), and the device further comprises a redistribution layer (150) to connect the plurality of vias (130) to a plurality of contact pads (220) on the component side of the memory chip (210), and a spacer material made of a dielectric material on the back (125) of the logic chip (110).

Description

Field of invention

[0001] The invention relates to the field of housing technology and encapsulation of integrated circuits. In particular, the invention relates to a device for accommodating existing silicon chips in three-dimensionally integrated stacks. Background of the invention

[0002] Efforts are underway to stack chips or semiconductor wafers to increase performance without requiring more space (e.g., a larger portion of the surface area) on a printed circuit board. These efforts are driven in particular by the demands of sophisticated mobile phones, smartphones, and other mobile devices. Chip manufacturers have integrated dynamic RAM and static RAM (DRAM and SRAM), flash memory, and other memory into a single structure or stack of interconnected integrated circuits. However, these integration efforts have historically been limited by the additional space required for the wiring technology (e.g., wire bonding) used to connect the chips.Chip or semiconductor stacking technology connects two or more semiconductor chips to form a structure of interconnected integrated circuits. The chips or semiconductor chips can be connected using interconnect wires along the sides of the stack or using metallic vias at the junctions between them.

[0003] A common approach to stacking chips or semiconductor wafers is called face-to-face bonding. In this configuration, the component sides of approximately two semiconductor wafers are stacked on top of each other so that the component sides face each other, and metallic vias electrically connect the semiconductor wafers at the interface between them. In a representation of a face-to-face bonded structure with interconnected integrated circuits, a central processing unit (CPU) or logic chip and a memory chip (e.g., an SRAM chip or a DRAM chip) are stacked together in a face-to-face bonded configuration.A heat sink can be attached to the main part of the CPU or logic chip, and the power consumption and input / output (I / O) connections to the package or printed circuit board are attached to the main part of the memory semiconductor wafer using bump technology. Through-silicon vias (TSVs) can be used to pass through the memory semiconductor wafer and create a connection to the metallic junction between the two wafers.

[0004] In the example above, since the silicon vias pass through the active silicon region of the memory of the second semiconductor chip (e.g., a memory semiconductor chip), a sufficient area must be allocated in the circuit to accommodate the silicon vias. These vias may be larger (more than ten times) than the minimum design requirements for a given process due to power / energy delivery requirements. Power / energy for both semiconductor chips is supplied via the silicon vias. Power / energy requirements dictate that approximately one silicon via should be provided per prong contact.In flip-chip technology, the bumps are typically arranged in a uniform pattern with wide spacing across the entire two-dimensional chip, enabling a high number of uniform power and ground connections in the top metal layer. This necessitates that the circuitry in the second chip (e.g., memory semiconductor wafers) be designed to accommodate these vias with appropriate spacing to adjacent geometries. This implies that the second chip would need to be specifically designed to precisely meet the via requirements of the first chip.

[0005] Another bonding configuration is face-to-back bonding. To continue with the example of a CPU chip and a memory chip, in a face-to-back bonding configuration the positions of the two semiconductor chips are reversed. For example, the signal and data lines of the first semiconductor chip (CPU chip) are connected to the package in a conventional manner using standard bump technology. The data and signal connections for the second semiconductor chip (e.g., memory chip) are routed through the first semiconductor chip using vias through silicon. The power / energy requirements of a memory chip are typically lower than those of a CPU or logic chip, so the number of vias through silicon made by the first semiconductor chip (e.g., memory chip) is generally lower.The amount of material that would have to run on the CPU chip could be significantly less and would not need to be uniformly distributed across the chip. This means that the design and layout of the CPU chip are affected to a much lesser extent by the three-dimensional bonding of a second chip.

[0006] US 2006 / 0113598A1 concerns semiconductor processes and devices that use silicon-on-insulator (SOI) technology to provide a double-sided chip structure. One example of a semiconductor package described therein comprises an SOI wafer with a first side containing an integrated circuit system and a second side facing the first side, forming at least one cavity. At least one chip or component is located in the cavity. A continuous buried oxide compound connects the chip to the integrated circuit system.

[0007] US 6,175,160 B1 relates to a flip chip with a cache memory device attached to its back. An example described therein is a flip chip with an on-chip cache memory component. The flip chip comprises a semiconductor substrate with a first and a second opposing surface, the first surface having circuit elements. A plurality of raised contact points are located on the first surface and are connected to the circuit elements. Additionally, a plurality of electrical connections are located on the second surface, which is connected to the circuit elements. A cache memory device is electrically connected to the plurality of electrical connections located on the second surface.

[0008] US 6,150,724 A relates to a manufacturing process for a compact flip-chip semiconductor device with a ball grid array (BGA) containing multiple integrated circuits (ICs). The flip-chip semiconductor device is formed by fabricating a parent chip with a first set of bumps and a second set of bump contacts. A daughter chip, also featuring conductive bumps, is fabricated. The daughter chip and parent chip are oriented towards each other, and contact is established between the bumps of the daughter chip and the bump contact areas of the parent chip. After the daughter chip and parent chip are connected, the parent chip is contacted to an IC package via the bumps. The package uses a variety of metal layers selectively connected by conductive junctions to conduct signals between the parent chip, the daughter chip, and external terminals of the package. Summary of the invention

[0009] It can therefore be considered an object of the present invention to propose a device for efficient utilization of the space on a printed circuit board.

[0010] The foregoing problem is solved according to the invention with the device according to main claim 1. The dependent claims define further developments of the device according to the invention. Brief description of the drawings

[0011] Certain features, aspects and advantages of the embodiments will become clearer with reference to the following detailed description, the attached claims and accompanying drawings: Fig. Figure 1 shows an exploded view of a structure with interconnected integrated circuits comprising a first chip and several singulated or non-singulated chips arranged to occupy a surface region of the first chip. Fig. 2 shows a view of the top of the structure. Fig. 1 and shows bond surfaces that are assigned to each of the second chips. Fig. Figure 3 shows a side view along line 3-3'. Fig. 4 shows the structure from Fig. 2 along line 3-3' and represents a redistribution layer for electrically connecting the contacts on the second chips with through-contacts through silicon on the first chip. Fig. Figure 5 shows an embodiment of a surface of the first chip. Fig. Figure 6 shows another embodiment of a structure with connected integrated circuits, comprising a first chip and several second chips. Fig. Figure 7 shows a flowchart of an embodiment of a method for forming a structure with connected integrated circuits. Fig. Figure 8 shows a schematic side view of an electronic assembly as part of a desktop calculator. Detailed description

[0012] The Fig. Figures 1 to 3 show different views of an embodiment of a structure with interconnected integrated circuits, including a first chip 110 and a number of singulated or non-singulated second chips 210 connected to / on chip 110. Chip 110 is, for example, a CPU or a logic chip. In one embodiment, the chips 210 (including individual chips 210A, 210B, 210C, and 210D) are memory chips (e.g., SRAM, DRAM) or other chips, or a combination of different chips (e.g., logic and memory). The multiple chips represented by chips 210 together have a chip dimension (surface area) that is close to or equal to the dimension (surface area) of the first chip 110. For example, chip 110, which is a CPU or a logic chip, may have a surface area of ​​400 mm². 2Each of the chips 210 (chip 210A, chip 210B, chip 210C, chip 210D) in this example has a surface area of ​​100 mm². 2 so that the total surface area occupied by the chips 210 is also 400 mm² 2 If the chips are 210 memory structures, e.g., DRAM, the chips can be selected so that together they provide an acceptable balance between DRAM density and chip dimensions. Regarding density, a DRAM chip size of 1 GB can be achieved using current technologies, with the number of chips being four, as shown. Alternatively, for a smaller DRAM capacity (e.g., 512 KB or 256 KB), the number of chips can be 210 or higher (e.g., eight 512 KB chips with a 60 mm² chip size). 2 per chip (480 mm 2 )).

[0013] Fig. Figure 1 shows two examples of Chip 210. In one example, each of the Chip 210 (Chip 210A, Chip 210B, Chip 210C and Chip 210D) is singulated and assembled as a distinguishable unit on Chip 110. Alternatively, the multiple chips can be scribed as a single unit and attached to Chip 110.

[0014] Memory chips (e.g., SRAM, DRAM) are available either as chips or in wafer form. These chips are commonly used in wire-bonded applications. For example, these chips can have 4-32 I / O plus feed bond pads per chip. These bond pads are typically arranged in a narrow column, one or two bond pads wide, through the center of the chip. Fig. Figure 2 shows the chips 210 (e.g., chip 210A, chip 210B, chip 210C, and chip 210D) with a column of bond pads 220, two bond pads wide, through the center of each chip (represented by dashed lines to show that the bond pads, in the view of the Fig. 2, are arranged on opposite surfaces of the chips).

[0015] In one embodiment, chip 110 can be a multi-core processor. A multi-core processor generally has several complete execution cores within a single physical processor, each operating at the same frequency. The cores typically share the same encapsulation / package. With reference to Fig. 1. The chip 110 can be, for example, a dual-core processor or a quad-core processor (shown) or a processor with an even larger number of cores.

[0016] In one embodiment, chip 110 and chips 210 are connected in a face-to-back bond configuration. Referring to the Fig. 3 The chip 110 has a number of through-silicon vias (TSVs) 130 formed therein. The through-silicon vias 130 comprise a conductive material, e.g., copper, which is used to connect the chip 110 and / or the contacts 320 on the package 310 to contacts (e.g., bond pads) on the chips 210 (chip 210C and chip 210D, as shown). Fig. Figure 3 shows the chip 110 with the component side 120 adjacent to and connected to the package 310 by means of vias through silicon 130, which extend through the chip 110 (from one component side to a back side (surface 125)). The vias through silicon made of a conductive material, such as copper, can be formed as part of the process steps used to manufacture the chip 110. In this way, the vias through silicon 130 can be structured so that they align with the contact pads 220 (see Figure 3). Fig. 2) are aligned with the second chips. Fig. Figure 3 shows vias through silicon 130, which extend from the electrical contacts 320 (e.g., solder pads on bonding surfaces) to the bonding surfaces 220 of the second chips 210C and 210D. The chips 210 can be arranged such that one component side (bonding surface side) of each chip is located on the back of the chip 110. Fig. Figure 3 further shows a heat sink / cooling plate 410, which is connected to a rear side of the chips 210.

[0017] In some embodiments, the vias through silicon associated with chip 110 are not aligned with contacts (e.g., bond pads) of chips 210. In such situations, an electrically conductive redistribution layer, e.g., in the form of a metallic layer such as copper, can be structured on either the back side of chip 110 or the component side of chips 210. Such a redistribution layer can serve as an intermediate connection between the contact points (e.g., bond pads) of chips 210 and the vias through silicon 130. Fig. Figure 4 shows the structure with connected integrated circuits of the Fig. 2 along the layer by lines 3-3' according to a further embodiment. In this example, the contact points 220 of chip 210C and chip 210D are not aligned with the through-contacts through silicon 130, which extend between the housing 310 and through chip 110. Fig. Figure 4 shows a redistribution layer 150 made of, for example, a conductive material such as copper, which in one embodiment is structured on a back side of the chip 110. Fig. Figure 5 shows a rear surface of the chip 110 with vias through silicon 130A and 130B, which extend through the chip 110 to the rear surface. Fig. Figure 5 further shows a structured redistribution layer 150, which extends laterally from each via through silicon 130A. In this example, the vias through silicon 130B would be aligned with contact points of the second chips 210. For example, the redistribution layer 150 can consist of a conductive material, such as copper, which is structured using photolithographic techniques. For instance, a copper material is applied to a back surface of chip 110, followed by a masking step to define the redistribution layer 150 and an etching step to structure the redistribution layer as fingers that extend laterally from the vias through silicon 130A to a desired position for electrical contact with the contact points of the second chips 210C and 210D.The redistribution layer 150 can be connected to contact points of the chips 210, for example by means of solder connections, as can the vias through silicon 130B.

[0018] Where necessary, a spacer material, e.g., made of a dielectric material in conjunction with the redistribution layer, can be formed on a surface of chip 110 or chips 210 to fill any gaps between the chips. Fig. Figure 4 shows a spacer material 160, which is formed with the redistribution layer 150 on a surface of the chip 110.

[0019] The description refers to the Fig. Figures 1 to 5 show four chips 210, e.g., memory chips (e.g., DRAM or SRAM), each chip having a similar size. It is evident that in other embodiments, chips with different functions and dimensions can be stacked on top of each other. Fig. Figure 6 shows a top view of a structure with connected integrated circuits of chip 510, for example, a CPU or logic chip. Chips 610A and 610B, for example, of a DRAM memory, are arranged on one surface (e.g., a back surface) of chip 510. Also located on the back of chip 510 is chip 620, which has a larger cross-sectional area than either chip 610A or chip 610B. Chip 620 is, for example, an SRAM memory. In this example, chip 610A, chip 610B, and chip 620 are described as memory chips, but it is evident that other chip types, such as CPU or logic chips, could be used as well.

[0020] Fig. Figure 7 shows a flowchart of a method for forming a structure with interconnected integrated circuits. In this embodiment, memory chips are assembled on a surface, for example, a back surface of a CPU or a logic chip. As noted above, it is evident that the choice of chip type can vary.

[0021] With reference to Fig. 7. Initially, the memory requirements for an interconnected integrated circuit structure are determined (Block 710). For example, the desired memory requirements may correspond to 1 GB of DRAM memory for an interconnected integrated circuit structure.

[0022] Once the memory requirements have been determined, a number of memory chips are selected such that the sum of the surface areas of several chips closely approximates the surface area (e.g., the back surface) of a CPU logic chip (Block 720). For example, if the surface area of ​​a CPU or logic chip is 400 mm² 2 and 1 GB DRAM memory chips are available with a surface area of ​​100 mm² 2 , corresponds to four DRAM memory chips (4 · 100 mm²) 2 ) a surface of the CPU or logic chip.

[0023] Following the selection of the memory chips, the contact points (feed and I / O contact points) of the memory chips are examined, and a pattern is compared with a via pattern desired for the CPU logic chip. At this point, a determination is made as to whether a redistribution layer is required (Block 730). If no redistribution layer is required, the contacts on the back side of the CPU or logic chip can be patterned (Block 740). If a redistribution layer is necessary, a redistribution layer is patterned on a back surface of a CPU or logic chip, and contacts to the redistribution layer are provided (Block 750).

[0024] Once contacts are provided on a surface (e.g., a back surface) of a CPU chip, the multiple memory chips are connected to the CPU or logic chip, for example, by soldering (Block 760). Following the connection of the memory chips to the CPU or logic chip, the assembled chip stack can be connected to a substrate package, including the vias through the silicon extending through the memory chips (Block 770). A heat sink and all other process techniques typically used in assembling package substrates can then follow.

[0025] Fig. Figure 8 shows a side view of an electronic assembly including a structure with interconnected integrated circuits, which can be physically and electrically connected to a printed circuit board (PCB). The electronic assembly can be part of an electronic system, such as a computer (e.g., desktop, laptop, handheld, server, etc.), a wireless communication device (e.g., mobile phone, cordless phone, pager, etc.), computer accessories (e.g., printer, scanner, monitor, etc.), consumer electronics (e.g., television, radio, stereo system, tape and compact disc player, video cassette recorder, MP3 player, audio layer 3 player, etc.), and the like. Fig. Figure 8 depicts the case as part of a desktop computer. Fig.Figure 8 shows an electronic assembly 800, which includes a structure with integrated circuits 805 that is physically and electrically connected to the package substrate 810. The package substrate 810 can be used to connect the chip 100 to the printed circuit board 820, such as a motherboard or other circuit board. Other aspects of the invention include: 1. Device comprising: a first chip comprising multiple conductive substrate vias (TSVs), wherein the first chip has a surface area; and several second chips, each comprising several contact points coupled to the TSVs of the first chip, the multiple second chips being arranged to enclose together a surface area corresponding to the surface area of ​​the first chip. 2. Device according to claim 1, wherein the first chip and the multiple second chips are coupled in a face-to-back bonding configuration. 3. Device according to claim 2, wherein the first chip comprises a CPU or a logic chip. 4. Device according to claim 3, wherein the multiple second chips comprise memory units. 5. Device according to claim 3, wherein the multiple second chips comprise DRAM memory units. 6. Device according to claim 1, wherein the first chip comprises a multi-core processor and the multiple second chips are arranged such that each of the second chips is located on a respective core of the multi-core processor. 7. Device according to claim 1, wherein the first chip further comprises several contact points coupled to the TSVs via a conductive redistribution layer, and the several contact points of each second chip are connected to the several contacts of the first chip. 8. Procedure, which includes: Arranging multiple second chips on a first chip such that the second chips together enclose a surface area equal to the surface area of ​​the first chip; and Electrical coupling of multiple second chips with multiple conductive substrate vias (TSVs) of the first chip. 9. The method of claim 8, wherein the first chip and the multiple second chips are coupled in a face-to-back bonding configuration. 10. The method of claim 9, wherein the first chip comprises a CPU or a logic chip. 11. Method according to claim 10, wherein the multiple second chips comprise memory units. 12. The method of claim 10, wherein the multiple second chips comprise DRAM memory units. 13. The method of claim 8, wherein the first chip comprises a multi-core processor and the arrangement of the multiple second chips on the first chip comprises an arrangement such that each of the second chips is coupled to a respective core of the multi-core processor. 14. Method according to claim 8, wherein the first chip comprises several contact points coupled to the TSVs by a conductive redistribution layer, and the coupling of the several second chips comprises coupling contact points of the several second chips to the several contact points of the first chip. 15. System, which includes: an electronic device comprising a printed circuit board and a module coupled to the printed circuit board, wherein the module comprises: a first chip comprising several conductive substrate vias (TSVs), wherein the first chip has a surface area; and several second chips, each comprising several contact points coupled to the TSVs of the first chip, wherein the several second chips are arranged such that together they comprise a surface area corresponding to the surface area of ​​the first chip.

Claims

[1] Device comprising the following: a logic chip (110) with a component side (120) facing a rear side (125), wherein the logic chip (110) has a plurality of vias (130) through silicon; a memory chip (210) above the back (125) of the logic chip (110), wherein the memory chip (210) has a component side opposite a back, the component side of the memory chip (210) facing the back (125) of the logic chip (110), and wherein the memory chip (210) has a plurality of contact pads (220); and a heat sink (400) above the back of the memory chip (210), wherein the device further comprises a housing which is connected to the component side (120) of the logic chip (110), and the device further comprises a redistribution layer (150) to connect the plurality of vias (130) to a plurality of contact pads (220) on the component side of the memory chip (210), and a spacer material made of a dielectric material on the back (125) of the logic chip (110). [2] Device according to claim 1, wherein the logic chip (110) has a larger base area than the base area of ​​the memory chip (210). [3] Device according to claim 1 or 2, further comprising: a second memory chip, which is adjacent to the memory chip (210) on the side. [4] Device according to one of claims 1-3, wherein the memory chip (210) and the second memory chip are completely within a base area of ​​the logic chip (110).

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