Hybrid core through-holes and through-contacts

Abstract

Semiconductor device substrate (100) for multiple processors, comprising the following: a first core (110) with a front surface (114) and a rear surface (116); a laminate core substrate (134) built on the front surface (114) and the rear surface (116) of the first core (110), wherein the laminate core substrate (134) comprises a front circuit board section (102F) and a rear circuit board section (102B), and wherein the rear circuit board section (102B) comprises an integral induction coil; wherein the first core (110) contains a plated through-hole (PTH) (124) and front and rear conductive PTH contact islands (1F, 1B) in contact with the plated through-hole (124), wherein the plated through-hole (124) is a circular cylindrical plated through-hole (124), and wherein the plated through-hole (124) is an air core plated through-hole (124); wherein the laminate core substrate (134) contains a tapered contact (136, 137) in each of the front and rear board sections (102F, 102B) that expose the conductive PTH contact islands (1F, 1B) and contain the front and rear tapered contacts (136, 137) that contact the conductive PTH contact island (1F, 1B), and each contain conductive PTH contact islands (136, 137) with tapered contacts (136, 137) that are coupled to the front and rear tapered contacts (136, 137), wherein the integral induction coil includes the rear first conductive PTH contact island (1B) having a simulated crescent shape which is in contact with the plated through hole (124), and wherein furthermore the integral induction coil includes a complementary rear first conductive PTH contact island (1BC) having a simulated crescent shape which is in contact with a complementary plated through hole (224C).

Description

[0001] Disclosed embodiments relate to semiconductor device substrates and processes for coupling them with semiconductor devices. STATE OF THE ART

[0002] From JP 2008-270 532 A, a substrate with an integrated inductor is known. The substrate comprises an inductor bonded to it and wiring layers, each electrically connected to a first connection at one end of the inductor and a second connection at the other end. The inductor is thicker than the wiring layers. The inductor is formed by bonding an inductor element, obtained by pressing it with a metal plate, to the substrate using an adhesive layer.

[0003] JP 2007-150 111 A describes a printed circuit board comprising a core with a tubular through-hole conductor and filler material for its interior. The filler material consists of a resin containing an inorganic filler. The end face of the filler material is covered by a cap conductor connected to the through-hole conductor.

[0004] JP 2006-86 339 A discloses a multilayer substrate comprising several laminated insulating layers and a wiring pattern formed between the respective insulating layers. The wiring pattern includes a first wiring pattern with a predetermined thickness and a second wiring pattern that is thinner than the first. The second wiring pattern is constructed as a laminate of several conductive layers with different etch rates.

[0005] The KR 10 0 733 279 B1 describes a manufacturing process for a printed circuit board with an embedded inductor. SUMMARY OF THE INVENTION

[0006] The invention relates to a semiconductor device substrate with the features of claim 1. Further advantageous embodiments are defined in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] To understand how embodiments are manufactured, a more detailed description of various embodiments briefly described above follows, with reference to the accompanying drawings. These drawings depict embodiments that are not necessarily drawn to scale and are not to be understood in a way that limits the scope of application. Some embodiments are described and explained with particular specificity and detail with reference to the accompanying drawings, which show the following: Fig. Figure 1a is a cross-sectional view of a semiconductor device substrate during processing according to an exemplary embodiment; Fig. 1b is a cross-sectional view of the in Fig. 1a Semiconductor component substrate shown after further processing according to one embodiment; Fig. 1c is a cross-sectional view of the in Fig. 1b shown first semiconductor device substrate after further processing according to an embodiment; Fig. 1d is a cross-sectional view of the in Fig. 1c semiconductor component substrate shown after further processing according to one embodiment; Fig. Figure 2 is a perspective elevation of a section of a semiconductor device substrate according to an exemplary embodiment; Fig. Figure 3 is a top view of a section of a semiconductor device substrate according to an exemplary embodiment; Fig. Figure 4 is a cross-sectional view of selected structural elements of a semiconductor device substrate according to an exemplary embodiment; Fig. 5 is a process and procedure flow diagram according to various embodiments; and Fig. Figure 6 is a diagram of a computer system according to one embodiment. DETAILED DESCRIPTION

[0008] Let us now turn to the drawings, in which identical structures may be designated with the same suffix reference designations. To illustrate the structures of different embodiments more clearly, the drawings included in this text are diagrammatic representations of integrated circuit structures. Thus, the actual appearance of the manufactured integrated circuit structures, for example in a photomicrogram, may differ, while still containing the claimed structures of the illustrated embodiments. Furthermore, it is possible that the drawings only show the structures relevant to understanding the illustrated embodiments. The depiction of additional structures known to those skilled in the art may have been omitted to maintain the clarity of the drawings.

[0009] Fig. Figure 1a is a cross-sectional view of a semiconductor device substrate 100 during processing according to an exemplary embodiment. The semiconductor device substrate 100 was processed with a first core 110 into which a through-hole 112 was drilled, creating a connection between a front first surface 114 and a rear first surface 116. The first core 110 as a whole has a thickness 122 in a range of 400 µm to 700 µm according to one embodiment where the finished device is used as part of a server blade. In one embodiment, the through-hole 112 was drilled with a mechanical drill such that the through-hole 112 has a substantially circular cylindrical form factor with a width 118 and a thickness 122. The embodiments serve as dimensional descriptions. In one embodiment, the through-hole 112 was formed by a laser drilling process, so that the form factor can be tapered.As shown, the through-hole 112 has a circular cylindrical form factor.

[0010] In one embodiment, the first core 110 is a prepreg material, such as a glass fabric and epoxy (FR4) material. Other structures can also be used for the first core 110 according to the requirements of a specific application.

[0011] The through-hole 112 can have a width 118 in a range of 80 micrometers (µm) to 200 µm. In one embodiment, the through-hole 112 has a width in a range of 100 µm to 120 µm. The first core 110 is divided orthogonally to the Z-direction, with an axis of symmetry 120 running in a plane of XY directions (Y leads into and out of the plane of the figure).

[0012] Fig. 1b is a cross-sectional view of the in Fig. Figure 1a shows the semiconductor device substrate after further processing according to one embodiment. The semiconductor device substrate 101 was processed to form a through-hole plating on the through-hole walls, resulting in a PTH 124 (plated through-hole). According to one embodiment, the formation of the PTH 124 is achieved by a chemical plating process. After the formation of the PTH 124, the front surface 114 and the rear surface 116 are polished to remove any plating that is not within the form factor of the PTH 124.

[0013] In one embodiment, PTH 124 is a copper metal. In one embodiment, a chemical copper plating technique is used to form PTH 124. This is done using a copper solution with ethylenediaminetetraacetic acid (EDTA) at a pH of 13 and a temperature of 50°C, with cytosine as a stabilizer. In an exemplary embodiment, rapid chemical plating is carried out using a copper solution with EDTA at a pH of 13 and a temperature of 50°C, with benzotriazole as a stabilizer. In an exemplary embodiment, rapid chemical plating is carried out using a copper solution with EDTA at a pH of 13 and a temperature of 50°C, with 2-mercaptobenzothiazole as a stabilizer.

[0014] The PTH 124 was filled with a filler material 126, such as an epoxy material with low magnetic properties or no magnetic properties. Therefore, if the filler material 126 is non-magnetic, it can be referred to as an "air core" filler material 126. The formation of the filler material 126 can be achieved by injecting flowable filler material 126 into the PTH 124 and curing and planarizing the front surface 114 and the rear surface 116 to remove any external filler material that is not within the form factor of the PTH 124. In one embodiment, the filler material 126 is a bulk organic material with a particulate inorganic filler. In another embodiment, the filler material 126 is a bulk epoxy material with a particulate silicon dioxide filler. Materials other than the volume filler material and the particle-like filler material can also be used.

[0015] After the filler material 126 has been introduced, the PTH 124 is further processed with a PTH cap 128, for example by electroplating, with the PTH 124 serving as the cathode. Subsequently, further polishing and planarizing are performed to remove all external electrically conductive material of the PTH cap 128 that lies outside the form factor of the PTH 124. In one embodiment, the plating of the PTH 124 consists of chemically deposited copper, and the PTH cap 128 is electroplated copper. The entire structure within the form factor of the PTH 124, including the filler material 126 and the PTH cap 128, may hereinafter be referred to as the PTH 124 unless expressly stated otherwise.

[0016] Fig. 1c is a cross-sectional view of the in Fig. 1b shows the semiconductor device substrate after further processing according to one embodiment. The semiconductor device substrate 102 was processed by subtractive structuring of metal films to form a first front conductive through-hole contact island 1F, which is in contact with the PTH 124 on the first side 114 (see Fig. 1b), as well as forming a first rear conductive through-hole contact island 1B, which is in contact with the PTH 124 on the second side 116. Hereinafter, the first front conductive through-hole contact island 1F is referred to as the front first contact island 1F. Hereinafter, the first rear conductive through-hole contact island 1B is referred to as the rear first contact island 1B. It can be seen that the front first contact island 1F has a front dimension 130 in the X-direction and that the rear first contact island 1B has a rear dimension 132, which differs from that of the front first contact island 1F. The rear first contact island 1B is part of an induction coil structure, as will be illustrated in more detail below. The rear first contact island 1B can also be thicker than other conductive through-hole contact islands, as illustrated.

[0017] The semiconductor component substrate 102 can be designated, by reference to sections, as a front PCB section 102F and a rear PCB section 102B. The front PCB section 102F is typically located closer to the semiconductor components, such as server-type processors, and the rear PCB section 102B is typically located closer to a motherboard, such as a blade motherboard, power sources, and power source connectors, such as AC power supplies. The rear PCB section 102B contains an integral induction coil for use with a server processor, which, according to one embodiment, is mounted above the front PCB section 102F.

[0018] The further processing involves forming a second core 134 (comprising a front second core 134F and a rear second core 134B) arranged to form part of both the front circuit board section 102F and the rear circuit board section 102B. The second core 134 can be referred to as a laminated second core 134 or a laminated core substrate. The second core 134 can be formed by spin-casting a flowable material, curing, planarizing, and repeating for the front and rear sections. Subsequently, a laser drilling technique is employed to create through-holes that generally or at least partially fit the form factor of the PTH 124 in a vertical projection (in the Z directions). As illustrated, a front first tapered contact 136 has a tapered form factor because the second core 134 was laser drilled.The formation of the front first tapered contact 136 and the rear first tapered contact 137 is achieved by electroplating, for example, copper, followed by planarization to obtain a front second surface 214 and a rear second surface 216. The front first tapered contact 136 has a top width 146 that lies within—or at least partially within—the Z-direction projection (through-hole width 118) of the PTH 124. Some misalignment may occur during processing, which can be advantageous according to certain design rules, but the continuity of the electrical connection is maintained by the presence of the front first conductive contact island 1F.

[0019] The vertical spacing of layers for the semiconductor device substrate 102 includes both the thickness of the conductive contact islands and the thickness of the second core 134. In one embodiment, the rear first conductive contact island 1B has a thickness 138 in a range of 30 µm to 70 µm. In another embodiment, the rear first conductive contact island 1B has a thickness 138 of 35 µm. In one embodiment, the front first conductive contact island 1F has a thickness 140 in a range of 30 µm to 70 µm. In another embodiment, the front first conductive contact island 1F has a thickness 140 of 35 µm.

[0020] The thickness (in the Z-direction) of the second core 134 is measured as the portion added to the thickness of the conductive contact islands. In one embodiment, the front second core 134F and the rear second core 134B have an additional thickness 142 and 144, respectively, in the range of 50–100 µm. In another embodiment, the front second core 134F and the rear second core 134B have an additional thickness 142 and 144, respectively, in the range of 60–75 µm.

[0021] Further processing includes forming a front second conductive contact island 2F with a tapered contact and a rear second conductive contact island 2B with a tapered contact. Hereinafter, the front second conductive contact island 2F is referred to as a front second contact island 2F, and the rear second conductive contact island 2B with a tapered contact is referred to as a rear second contact island 2B. The thicknesses of these conductive contact islands with tapered contacts can be in the same range as the thicknesses of the first front and rear conductive through-hole contact islands 1F and 1B, respectively, as set forth in this disclosure.

[0022] Fig. 1d is a cross-sectional view of the in Fig. Figure 1c shows the semiconductor substrate after further processing according to one embodiment. The semiconductor substrate 103 can be referred to, by reference to sections, as a front board section 103F and a rear board section 103B. The semiconductor substrate 103 can also be described as a semiconductor substrate 103 containing an induction coil. It can be seen that the rear board section 103B is a reinforced rear board section 103B, as shown in Figure 1c. Fig. Figure 1c can be seen. It can also be seen that the front PCB section 103F is a reinforced front PCB section 103F. As a whole, the semiconductor device substrate 103 can be described as a hybrid core semiconductor device substrate.

[0023] The semiconductor component substrate 103 was processed with a subsequent core 148, which includes a subsequent front core 148F and a subsequent rear core 148B. The subsequent core 148 can be referred to as a laminated subsequent core 148. As a whole, the front board section 103F and the rear board section 103B can be referred to as a laminated core substrate laminated onto the first core 110.

[0024] The processing also includes laser drilling of subsequent through-holes, which are laminate core through-holes. The laminate core through-holes are filled with a front subsequent tapered contact 150 and a rear subsequent tapered contact 152, respectively. Further processing also includes the subtractive formation of a front subsequent conductive through-hole contact island 3F and a rear subsequent conductive through-hole contact island 3B. Hereinafter, the front subsequent conductive through-hole contact island 3F is referred to as the front subsequent contact island 3F, and the rear subsequent conductive through-hole contact island 3B is referred to as the rear subsequent contact island 3B.

[0025] It can now be seen that more than two laminate core layers can be produced on the first core layer 110 to form a laminate core substrate, depending on the requirements of a specific application. In one exemplary embodiment, the front and rear second core layers are formed between the respective front and rear first and subsequent core layers. The nomenclature uses "subsequent" to mean the last laminate core layer, so that in this embodiment, the number of first, second, and subsequent laminate core layers on the front board section 103F is three, and the number on the rear board section 103B is three. In another embodiment, the number of laminate core layers is between one and five for the front board section 103F and for the rear board section 103B.In one embodiment, the number of laminate core layers is between six and 10 for the front circuit board section 103F and for the rear circuit board section 103B.

[0026] The total thickness of the semiconductor device substrate 103 can range from approximately 850 µm to 1,400 µm. In one embodiment, each conductive through-hole contact island has a thickness of 35 µm, and each laminate core layer adds an additional height of 60 µm, resulting, together with the first core layer 110 of 400 µm thickness, in a total thickness of 650 µm for the semiconductor device substrate 103. In another embodiment, each conductive through-hole contact island has a thickness of 35 µm, and each laminate core layer adds an additional height of 60 µm, resulting, together with the first core layer 110 of 700 µm thickness, in a total thickness of 950 µm. In one embodiment, each conductive through-hole contact island has a thickness of 35 µm, and each laminate core layer adds an additional height of 75 µm, resulting in a total thickness of 910 µm together with the first core layer of 110 of 400 µm.In one embodiment, each conductive through-hole contact island has a thickness of 35 µm, and each laminate core layer adds an additional height of 75 µm, resulting in a total thickness of 1,210 µm together with the first core layer (110 of 700 µm). In another embodiment, a substrate consisting of five laminate core layers has a total thickness of 1,400 µm.

[0027] It can be seen that the semiconductor device substrate 103 contains three laminated layers. It can be recognized that the semiconductor device substrate 103 can be designated as two laminate core layers 134F and 134B, two laminate core layers 148F and 148B, and a first core layer 110. It is convenient to refer to each core layer as a laminated layer in conjunction with each other layer.

[0028] Fig. Figure 2 is a perspective elevation of a section of a semiconductor device substrate 200 according to an exemplary embodiment. The semiconductor device substrate 200 can be described as a semiconductor device substrate 200 containing an induction coil. The semiconductor device substrate 200 has rear-facing structures located in a similar position to the rear circuit board section 103B, which is located below the axis of symmetry 120 in Fig. Figure 1d shows an analogous axis of symmetry 220. The axis of symmetry 220 refers to a symmetrical magnitude of the PTH 224 below and above the axis 220. It can be seen that the PTH 224 is a coupling that transmits a current modified by the induction coil from the integral induction coil.

[0029] A PTH 224 is mounted on a rear first conductive through-hole contact island 1B (“rear first contact island 1B”). Not visible, but present, is a rear first tapered contact similar to the rear first tapered contact 138 of Fig. 1d as well as a rear second filled through contact with a similar position to the rear subsequent tapered contact 152, which is also in Fig. Figure 1d shows the rear first tapered contact located essentially directly beneath the projected form factor of the PTH 224, and the rear first tapered contact establishes an electrical connection between the rear first contact island 1B and a rear second contact island 2B. The rear second filled through contact establishes an electrical connection between the rear second contact island 2B and a rear third contact island 3B.

[0030] A rear third filled through-contact is present, similar to the rear second filled through-contact and the rear first tapered contact. The rear third filled through-contact is not shown, but it provides an electrical contact between the rear third contact island 3B and a rear subsequent contact island 4B. It can be seen that in the illustrated embodiment, the rear subsequent contact island 4B is a fourth conductive through-hole contact island 4B, and it is shown in this embodiment as the bottom, or in this embodiment as the last conductive contact island, in the semiconductor device substrate 200.

[0031] A complementary structure is shown as part of the semiconductor device substrate 200, which includes a complementary PTH 224C and a complementary axis of symmetry 220C located at the same height as the axis of symmetry 220. The complementary PTH 224C is mounted on a complementary rear first conductive through-hole contact island 1BC (“complementary rear first contact island 1BC”). Not shown, but present, is a complementary rear first tapered contact similar to the one shown in Fig. Figure 1d shows the rear first tapered contact 138 and a complementary rear second filled through contact of a similar position to the rear subsequent tapered contact 152. The complementary rear first tapered contact establishes an electrical contact between the complementary rear contact island 1BC and a complementary rear second contact island 2BC. The complementary rear second filled through contact establishes an electrical contact between the complementary rear second contact island 2BC and a complementary rear third contact island 3BC.

[0032] A complementary rear third filled through-contact is not shown, but it establishes an electrical contact between the complementary rear third contact island 3BC and a complementary rear adjoining contact island 4BC. It can be seen that in the illustrated embodiment, the complementary rear adjoining contact island 4BC is a complementary fourth contact island 4BC, and it is shown in this embodiment as the complementary conductive bottom contact island 4BC in the semiconductor device substrate 200. In one embodiment, connector through-contacts 260 and 262, which are shown in the foreground, are used. Connector through-contacts can also be used on the semiconductor device substrate 200 behind or in the background, which is obscured in the figure.

[0033] An induction coil is created within the semiconductor device using only the complementary rear first contact island 1BC and the rear first contact island 1B. An induction effect is induced by first passing current through the complementary rear first contact island 1BC and then to the rear first contact island 1B. Once the induction effect has been induced, the current flows upwards in the PTH 224 to a processor mounted above the front board section (not shown).

[0034] In one embodiment, the induction coil can be formed by first flowing current into the complementary rear adjoining contact island 4BC. Behind the semiconductor substrate 200, there is an electrical connection between the complementary rear adjoining contact island 4BC and the adjoining rear contact island 4B. The current jumps up one level and flows to the complementary rear third contact island 3BC. Behind the semiconductor substrate 200, there is an electrical connection between the complementary rear third contact island 3BC and the rear third contact island 3B. The current jumps up one level and flows to the complementary rear second contact island 2BC. Behind the semiconductor substrate 200, there is an electrical connection between the complementary rear second contact island 2BC and the rear second contact island 2B.The current jumps up one level and flows to the complementary rear first contact island 1BC. Behind the semiconductor device substrate 200, an electrical connection exists between the complementary rear first contact island 1BC and the rear first contact island 1B. Behind the rear first conductive through-hole contact island 1B, the electric current flows in the Z direction into the PTH 224 when it passes the symmetry axis 220 to a front structure of a similar position to a front board section, such as the front board section 102F, which is located in . Fig. As shown in Figure 1d, the circuit is crossed. It can be seen that an insulating ring 264 electrically isolates the complementary PTH 224C from the various complementary conductive contact islands. Accordingly, the energy or signal current utilizes at least two of the conductive contact islands to generate an induction effect before flowing through the PTH 224.

[0035] It now becomes clear that the quality of the required induction coil can be modified by the number of coils as well as by the specific overall shape of the induction coil. A simple coil consists only of the complementary rear first contact island 1BC and the first contact island 1B. A double coil can be formed from the complementary rear second contact island 2BC, the rear second contact island 2B, the complementary rear first contact island 1BC, and the first contact island 1B.

[0036] In one exemplary embodiment, conductive contact islands are connected side-by-side to multiply the current flow while maintaining a specific, useful vertical (Z-direction) form factor. This embodiment of side-by-side conductive contact islands is seen particularly in Fig. 2, where the complementary rear adjoining and third contact islands 4BC and 3BC, respectively, are parallel-connected by connector through-holes 260. In this embodiment, the current begins in parallel in the rear adjoining contact island 4B and the rear third contact island 3B and then flows clockwise (in the XY plane) to the complementary rear adjoining and third contact islands 4BC and 3BC. Connector through-holes 262 allow the current to jump up to the rear second contact island 2B, where it can continue to flow in a circuit through the semiconductor substrate 200 in the rear board section 200B to generate a useful induction effect. Connector through-holes 260 and 262 can be created at the same time as a specific laser-drilled through-hole is formed.

[0037] It can be seen that the semiconductor device substrate 200 contains three laminated layers that do not contain the first core layer.

[0038] After the current has exerted its useful induction effect, it crosses the symmetry axis 220 through the PTH 224 or its complementary PTH 224C. As can be seen, the insulator ring 264 is intended to prevent current from flowing upwards in the complementary PTH 224C. From the PTH 224, current flows to a front circuit board section, where the current can be split into various connecting wires that power multiple chips, such as Intel chips. ® Xeon ® -Processors mounted above the front PCB section of the semiconductor component substrate 200. Other processors may also be used if advisable.

[0039] Fig. Figure 3 is a top view of a section of a semiconductor device substrate 300 according to an exemplary embodiment. The semiconductor device substrate 300 can be described as an integral induction coil semiconductor device substrate 300. Each of the various conductive through-hole contact islands has a simulated crescent shape. The semiconductor device substrate 300 is part of a rear circuit board section analogous to the other disclosed embodiments. The semiconductor device substrate 300 has several structures containing a first coil 301 to an eighth coil 308. The first coil 301 contains a first rear conductive contact island 1B with a tapered contact (“rear first contact island 1B”) and a complementary first rear conductive contact island 1BC with a tapered contact (“complementary rear first contact island 1BC”). The semiconductor device substrate 300 also features a PTH 324 and a complementary PTH 324C.If it is advantageous to induce an induction effect at a front circuit board section of the semiconductor device substrate 300, the current can flow through the complementary rear first contact island 1BC, can flow through a connector through-contact 360 to the rear first contact island 1B, and can then flow vertically (orthogonal to the plane of the figure) to a front circuit board section. A visual inspection of the proportions reveals, according to one embodiment, a substantially circular path for the current flow (represented by the curved arrow 309) around the complementary first contact island 1BC or the first contact island 1BC. It can be seen that an off-center current flow can be generated depending on a specific configuration of the original and complementary contact islands.

[0040] Fig. Figure 4 shows a cross-sectional view of selected structural elements of a semiconductor device substrate 400 according to an exemplary embodiment. The semiconductor device substrate 400 can be described as a semiconductor device substrate 400 containing an integral induction coil. As a whole, the semiconductor device substrate 400 can be described as a hybrid core semiconductor device substrate 400.

[0041] Not shown is the first core, which would fill the thickness 422. Likewise, not shown are the various laminated cores that would fill the gaps between the different tapered conductive contact islands. As can be seen, the semiconductor device substrate 400 has both a primary and a complementary structure. The thickness 422 of the first core can be in a range of 400 µm to 700 µm. When the induction coil exits the first rear contact island 1B, insulating rings 464 electrically isolate the complementary PTH 424C and the complementary tapered contacts from the different complementary conductive contact islands.

[0042] The front board section 400F is shown with a total of six front conductive through-hole contact islands 1F, 2F, 3F, 4F, 5F, and 6F, where the sixth front contact island 6F can also be referred to as a front adjoining contact island 6F. Similar terminology can be used for the front complementary structure of the front board section 400F, which has a total of six complementary front conductive through-hole contact islands 1FC, 2FC, 3FC, 4FC, 5FC, and 6FC, where the sixth front complementary contact island 6FC can also be referred to as a complementary front adjoining contact island 6FC.

[0043] The rear board section 400B is shown with a total of 10 rear conductive through-hole contact islands 1B, 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, and 10B, the rear 10th contact island 10B also being referred to as a rear adjoining contact island 10B. Similar terminology can be used for the front complementary structure of the rear board section 400B, which has a total of 10 complementary rear conductive through-hole contact islands 1BC, 2BC, 3BC, 4BC, 5BC, 6BC, 7BC, 8BC, 9BC, and 10BC, the complementary rear 10th contact island 10BC also being referred to as a complementary rear adjoining contact island 10BC.

[0044] It can now be seen that the number of front contact islands can differ from the number of rear contact islands. If a useful stiffness of a particular semiconductor device substrate is required and an integral induction coil with a specific number of coil windings is needed, then more conductive contact islands may be present in the front section than in the rear section, or vice versa. Likewise, if a useful stiffness of a particular semiconductor device substrate is required and an integral induction coil with a specific number of coil windings is needed, the same number of coil contact islands may be present in the front section as in the rear section. For example, one can Fig. 1d as an abbreviation of Fig. 4. Consequently, the number of front and rear contact islands can be the same. It can now be seen that one embodiment contains up to 10 front and 10 rear contact islands, which can be part of the semiconductor device substrate 400, but the number of front contact islands can be greater than the number of rear contact islands. It can now be seen that up to 10 front and 10 rear contact islands can be part of the semiconductor device substrate 400, but the number of front contact islands can be less than the number of rear contact islands.

[0045] It can now be seen that the total number of original and complementary back contact islands can all be coupled individually to form an induction coil with up to 10 turns. It can now be seen that the total number of original and complementary back contact islands can be connected side-by-side to form an induction coil with up to nine turns. For example, any two original and complementary back contact islands can be connected side-by-side to form an induction coil with five turns. It can now be seen that a subset of original and complementary back contact islands can be arranged individually, while another subset of original and complementary back contact islands can be connected side-by-side to form an induction coil with up to eight turns. For example, Fig. 2 can be viewed as a four-contact island structure, which is an induction coil with three turns, with the subsequent and the third rear contact island being parallel connected.

[0046] It can be seen that the semiconductor device substrate 400 contains 17 laminated layers. It is understood that the semiconductor device substrate 400 can be described as six laminate core layers in the front section 400F, 10 laminate core layers in the rear section 400B, and a first core layer that accommodates a thickness of 422. It is useful to refer to each core layer as a laminated layer in conjunction with each other layer.

[0047] Further features of the various embodiments include an aspect ratio of the height 490 of the stack of rear contact islands divided by the width 492 of the rear contact islands. In one embodiment, the aspect ratio is less than one. In one embodiment, the aspect ratio is 0.5. In one embodiment, the aspect ratio is one. In one embodiment, the aspect ratio is greater than one. In one embodiment, the aspect ratio is 1.5. In one embodiment, the aspect ratio is 2. In one embodiment, the aspect ratio is greater than 2, for example, 3.

[0048] Fig. Figure 5 is a process and procedure flow diagram 500 according to various embodiments.

[0049] In 510, the process involves drilling a through-hole in a first substrate. In a non-restrictive exemplary embodiment, a drill bit with a thickness between 100 µm and 120 µm is used to form the through-hole 112 in the first core 110. In one embodiment, the through-hole 112 has a thickness of 400 µm. In another embodiment, the through-hole 112 has a thickness of 700 µm. In yet another embodiment, the through-hole 112 has a thickness greater than 400 µm and less than 700 µm.

[0050] At 520, the process includes the formation of a plated through-hole. In a non-restrictive exemplary embodiment, the PTH 124 is formed from chemically plated copper, the filler material 126 is formed into an air core, and the PTH cap 128 is formed from copper by electroplating, with the PTH 124 being used as the cathode.

[0051] At 530, the process includes forming front and rear through-hole bond islands in the PTH. In a non-restrictive exemplary embodiment, the front first contact island 1F and the rear first contact island 1B are formed by subtractive plating techniques.

[0052] At 540, the laminated cores are formed. At 540, the process includes, as a non-limiting example, an algorithm from one to 10 for forming the laminated cores. In an exemplary embodiment, this is described in Fig. Figure 1d shows the semiconductor device substrate 103 formed at 540 by setting i=1 to 3, with the third iteration forming the front and rear adjoining contact islands 3F and 3B, respectively. It can now be seen that the formation of the complementary structures is also accomplished simultaneously at 540.

[0053] It can now be seen that the algorithm shown at 540 may contain a different i=1 to "subsequently" for the front section compared to the back section.

[0054] The processing includes laminating front and back laminate core substrates, followed by laser drilling of through-holes and the formation of filled vias. Next, the processing includes forming front and back conductive through-hole contact islands on the front and back filled vias, respectively.

[0055] It can now be seen that the process at 540 involves configuring the number of conductive contact islands, which may include parallel-connecting some or all of them. It also becomes clear that after a certain iteration, the algorithm can be repeated to create additional back-side structures, but not additional front-side structures.

[0056] In document 550, one embodiment of the process involves mounting the semiconductor substrate to a computer system. In a non-limiting exemplary embodiment, processors are mounted above the front circuit board section 103F of the semiconductor substrate 103, as shown in Fig. Figure 1d illustrates this. In a non-restrictive exemplary embodiment, processors are mounted above the front circuit board section (not shown), which is coupled to the rear circuit board section 200B of the semiconductor device substrate 200, as shown in Fig. Figure 2 illustrates this. The semiconductor substrate 200 is mounted on a server blade which, according to one embodiment, contains a server processor. In a non-limiting exemplary embodiment, several processors are mounted above the semiconductor substrate 300, and at least the contact islands 1B and 1BC form an integral induction coil in the rear section 200B.

[0057] Fig.Figure 6 is a diagram of a computer system 600 according to one embodiment. The computer system 600 (also referred to as the electronic system 600) can, as shown, embody a semiconductor substrate containing an induction coil according to one of the various disclosed embodiments and their equivalents, as set forth in this disclosure. The computer system 600 can be part of or an accessory to a server blade with an embodiment of a semiconductor substrate containing an induction coil, installed in a server farm. The computer system 600 can be a motherboard with the semiconductor substrate containing an induction coil in a multiprocessor device. The computer system 600 can be a desktop computer.

[0058] The Computer System 600 can be a mobile device, such as a netbook computer. The Computer System 600 can be a mobile device, such as a wireless smartphone. The Computer System 600 can be a handheld reading device. The Computer System 600 can be installed in a car. The Computer System 600 can be installed in a television.

[0059] In one embodiment, the electronic system 600 is a computer system that includes a system bus 620 for electrically coupling the various components of the electronic system 600. According to different embodiments, the system bus 620 is a single bus or any combination of buses. The electronic system 600 includes a voltage source 630 that supplies power to the integrated circuit 610. In some embodiments, the voltage source 630 supplies power to the integrated circuit 610 via the system bus 620.

[0060] The integrated circuit 610 is electrically coupled to the system bus 620 and, according to one embodiment, contains any circuit or combination of circuits. In one embodiment, the integrated circuit 610 includes a processor 612, which can be of any type. For the purposes of this text, the processor 612 is any type of circuit, such as a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or any other processor. In one embodiment, SRAM implementations are found in memory caches of the processor.Other types of circuits that may be included in the integrated circuit 610 include a special-purpose circuit or an application-specific integrated circuit (ASIC), such as a communication circuit 614 for use in wireless devices, such as cordless phones, smartphones, pagers, portable computers, walkie-talkies, and similar electronic systems. In one embodiment, the processor 610 includes an on-chip memory 616, such as a static random-access memory (SRAM). In another embodiment, the processor 610 includes an embedded on-chip memory 616, such as an embedded dynamic random-access memory (eDRAM).

[0061] In one embodiment, the integrated circuit 610 is augmented by a subsequent integrated circuit 611, such as a subsequent processor in a server blade, which is supported by an embodiment of a semiconductor device substrate containing an induction coil in conjunction with a more general processor 610. In another embodiment, the integrated circuit 610 is augmented by a subsequent integrated circuit 611 that is coupled to the integrated circuit 610. Viable embodiments include a dual processor 613 and a dual communication circuit 615 and dual on-chip memory 616, such as an SRAM. In one embodiment, the dual integrated circuit 610 includes embedded on-chip memory 616, such as an eDRAM.

[0062] In one embodiment, the electronic system 600 also includes an external memory 640, which in turn may contain one or more memory elements suitable for the specific application, such as a main memory 642 in the form of RAM, one or more hard disks 644, and / or one or more drives for removable storage media 646, such as floppy disks, compact discs (CDs), digital variable discs (DVDs), flash memory drives, and other removable storage media known to those skilled in the art. According to one embodiment, the external memory 640 may also be an embedded memory 648.

[0063] In one embodiment, the electronic system 600 also includes a display device 650 and an audio output 660. In another embodiment, the electronic system 600 includes an input device, such as a control unit 660, which may be a keyboard, a mouse, a trackball, a game controller, a microphone, a speech recognition device, or any other input device that feeds information into the electronic system 600. In one embodiment, an input device 670 is a camera. In another embodiment, an input device 670 is a digital sound recording device. In yet another embodiment, an input device 670 is both a camera and a digital sound recording device.

[0064] The computer system 600 can also include passive components 680 coupled with active components, such as the integrated circuit 610. In one embodiment, the passive component 680 is an induction coil used for an RF circuit. In another embodiment, the passive component 680 is an embodiment of a semiconductor component substrate containing an induction coil.

[0065] A foundation substrate 690 can be part of the computer system 600. In one embodiment, the foundation substrate 690 is a motherboard containing an embodiment of a semiconductor device substrate including an induction coil. In another embodiment, the foundation substrate 690 is a circuit board on which an embodiment of a semiconductor device substrate containing an induction coil is mounted. In another embodiment, the foundation substrate 690 includes at least one of the functions located within the dashed line 690 and is a substrate, such as the user interface of a wireless communication device.

[0066] As shown in the present text, the integrated circuit 610 can be implemented in a number of different embodiments, including an embodiment of a semiconductor device substrate containing an induction coil according to one of the various disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods for producing an embodiment of a semiconductor device substrate containing an induction coil, and one or more methods for producing an embodiment of a semiconductor device substrate containing an induction coil according to one of the various disclosed embodiments, as set out in the present text in the various embodiments and their equivalents recognized in the prior art.The elements, materials, geometries, dimensions, and sequence of steps can all be varied to adapt them to specific I / O coupling requirements, including array contact count and array contact configuration for an embodiment of an induction coil-containing semiconductor device substrate according to one of the various disclosed embodiments of an induction coil-containing semiconductor device substrate and their equivalents.

[0067] Although the term "chip" may refer to a processor chip, an RF chip or a memory chip may also be mentioned in the same sentence; however, this should not be understood as meaning that these are equivalent structures. When this disclosure refers to "an embodiment," it means that a particular feature, structure, or property described in connection with the embodiment is included in at least one embodiment of the present invention. The phrase "in an embodiment" at various points in this disclosure does not necessarily always refer to the same embodiment. Furthermore, the particular features, structures, or properties may be combined in any suitable way in one or more embodiments.

[0068] Terms such as "upper" and "lower", "above" and "below" can be understood using the illustrated XZ coordinates, and terms such as "adjacent" can be understood using the XY coordinates or non-Z coordinates.

[0069] The summary is written in accordance with 36 CFR paragraph 1.72(b), which requires a summary that enables the reader to quickly grasp the nature and essence of the technical disclosure. The summary is based on the understanding that it is not intended to interpret or limit the scope or meaning of the claims.

[0070] In the above Detailed Description, various features of a single embodiment have been combined to streamline the disclosure. This manner of disclosure should not be interpreted as implying that the claimed embodiments of the invention require more features than are expressly mentioned in each claim. Rather, as the following claims make clear, the inventive step lies in fewer than all the features of a single disclosed embodiment. Therefore, the following claims are hereby incorporated into the Detailed Description, each claim representing a separate preferred embodiment.

[0071] It is obvious to a person skilled in the art that various changes can be made to the details, materials and arrangements of the parts and process steps that have been described and illustrated to explain the nature of this invention without deviating from the principles and scope of the invention as expressed in the following claims. Reference symbol list 100 semiconductor device substrate 110 first core 134 Laminate core substrate 114 front surface of the first nucleus 116 rear surface of the first nucleus 102F front board section 102B rear board section 124 Plated Through-Hole (PTH) 1F front conductive PTH contact island 1B rear conductive PTH contact island 136 front tapered contacts 137 posterior tapered contacts 1B rear first conductive PTH contact island 1BC complementary posterior first conductive PTH contact island 224C complementary plated through hole 134F, 148F first laminate core layers 134B, 148B second laminate core layers

Claims

[1] A semiconductor device substrate (100) for multiple processors, comprising: a first core (110) having a front surface (114) and a rear surface (116); a laminate core substrate (134) constructed on the front surface (114) and the rear surface (116) of the first core (110), the laminate core substrate (134) including a front board portion (102F) and a rear board portion (102B), and the rear board portion (102B) including an integral induction coil; wherein the first core (110) includes a plated through-hole (PTH) (124) and front and rear PTH conductive contact pads (1F, 1B) in contact with the plated through-hole (124), wherein the plated through-hole (124) is a circular cylindrical plated through-hole (124), and wherein the plated through-hole (124) is an air core plated through-hole (124); wherein the laminate core substrate (134) includes a tapered contact (136, 137) in each of the front and rear board sections (102F, 102B) exposing the conductive PTH contact pads (1F, 1B) and including the front and rear tapered contacts (136, 137) contacting the conductive PTH contact pad (1F, 1B), and each including conductive PTH contact pads (136, 137) with tapered contacts (136, 137) coupled to the front and rear tapered contacts (136, 137), wherein the integral inductor includes the rear first conductive PTH contact pad (1B) having a simulated crescent shape in contact with the plated through-hole (124), and further wherein the integral inductor includes a complementary rear first conductive PTH contact pad (1BC) having a simulated crescent shape in contact with a complementary plated through-hole (224C). [2] The semiconductor device substrate (100) of claim 1, wherein the front board portion (102F) includes couplings for the plurality of processors, and wherein at least one coupling outputs an inductor-varied current from the integral inductor. [3] The semiconductor device substrate (100) according to claim 1, wherein the back board portion (102B) includes at least three laminated layers, and two of the at least three laminated layers are shunted together. [4] The semiconductor device substrate (100) of claim 1, wherein the front board portion (102F) includes a plurality of first laminate core layers (134F, 148F), wherein the rear board portion (102B) includes a plurality of second laminate core layers (134B, 148B), and wherein the first plurality is smaller than the second plurality. [5] The semiconductor device substrate (100) of claim 1, wherein the front board portion (102F) includes a plurality of first laminate core layers (134F, 148F), wherein the rear board portion (102B) includes a plurality of second laminate core layers (134B, 148B), and wherein the first plurality is equal to the second plurality. [6] The semiconductor device substrate (100) of claim 1, wherein the front board portion (102F) includes a plurality of first laminate core layers (134F, 148F), wherein the rear board portion (102B) includes a plurality of second laminate core layers (134B, 148B), and wherein the first plurality is greater than the second plurality. [7] The semiconductor device substrate (100) of claim 1, wherein the front board portion (102F) includes a plurality of first laminate core layers (134F, 148F), wherein the rear board portion (102B) includes two laminate core layers (134B, 148B). [8] The semiconductor device substrate (100) of claim 1, wherein the front board portion (102F) includes two laminate core layers (134F, 148F), wherein the rear board portion (102B) includes two laminate core layers (134B, 148B). [9] The semiconductor device substrate (100) of claim 1, wherein the integral inductor has a height to width aspect ratio greater than one. [10] The semiconductor device substrate (100) of claim 1, wherein the integral inductor has a height to width aspect ratio equal to one. [11] The semiconductor device substrate (100) of claim 1, wherein the integral inductor has a height to width aspect ratio less than one. [12] The semiconductor device substrate (100) of claim 1, wherein the rear first conductive PTH contact pad (1B) is part of a stack of first rear PTH contact pads (1B - 10B), wherein the complementary rear first conductive PTH contact pad (1BC) is part of a stack of complementary rear first PTH contact pads (1BC - 10BC), and wherein the integral inductor has a height to width aspect ratio selected from greater than one, equal to one, and less than one. [13] The semiconductor device substrate (100) of claim 1, wherein the semiconductor device substrate (100) has a height in a range of 650 micrometers (µm) to 1,400 µm.

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