Semiconductor devices and methods for manufacturing them

Abstract

Semiconductor device comprising the following: - a silicon carbide substrate (11) of a first conductivity type; - a silicon carbide layer (12) which is provided on a surface on one of the sides in a thickness direction of the silicon carbide substrate (11) and which is of the first conductivity type; - a region of the second conductivity type (13) which is formed in a region of an adjacent region of a surface on one of the sides in a thickness direction of the silicon carbide layer (12) and which is of the second conductivity type; and - a multitude of transition termination regions (15, 25) which are formed in an area on an outer circumferential end side of the silicon carbide substrate (11) from the area of ​​the second conductivity type (13) in the adjacent area of ​​the surface on one of the sides in the thickness direction of the silicon carbide layer (12) and which are of the second conductivity type, - wherein the plurality of transition termination regions (15, 25) are formed adjacent to each other at least on the surface on one of the sides in the thickness direction of the silicon carbide layer (12), wherein the plurality of transition termination regions (15, 25) differ from each other in the density of defects of the second conductivity type, - a first-type conductivity region (16, 26) which is of the first conductivity type and has a higher or equal density of first-type conductivity defects as that of the silicon carbide layer (12), at least in an adjacent area of ​​a surface on one of the sides in a thickness direction of an area in which the transition termination regions (15, 25) are connected to each other, - wherein the area is formed from the first conductivity type (16, 26) across the adjacent transition closure areas (15, 25), and - wherein the transition termination regions (15, 25) are arranged such that the density of defects from the second conductivity type gradually decreases towards the outer circumferential end side of the silicon carbide substrate (11), and - wherein a side area and a bottom area of ​​the area of ​​the first conductivity type (16, 26) are in contact with the transition termination areas (15, 25) in a cross-sectional view.

Description

Technical area

[0001] The present invention relates to semiconductor devices and methods of manufacturing the same, and more particularly to semiconductor devices in which a JTE (junction termination extension) region is formed in a silicon carbide (SiC) substrate and methods of manufacturing the same. State of the art

[0002] A power semiconductor device includes a Schottky diode, a pn diode, a MOSFET (metal oxide semiconductor field-effect transistor), and the like, which use a silicon carbide (SiC) substrate. In these power semiconductor devices, various termination structures are introduced to prevent an electric field from concentrating at a pn junction region in the SiC substrate. The termination structure includes a JTE (junction termination extension) structure (see, for example, Non-Patent Document 1).

[0003] The JTE structure has the property of being easily formed by ion implantation. Furthermore, the JTE structure also has the property of being easy to design, since carrier enrichment of a JTE region is preferably designed to cause the JTE region to be perfectly depleted upon dielectric breakdown.

[0004] Regarding a semiconductor device having the JTE structure (hereinafter referred to as a "device" in some cases), the following methods have been proposed to reduce an electric field strength at a surface of the JTE region. For example, Patent Document 1 proposes a method of providing a JTE region with a concentration gradient. Furthermore, Patent Document 2 proposes a method of covering a pn junction and a JTE region with a third layer. These methods attempt to realize a semiconductor device with high withstand voltage.

[0005] Patent Document 3 describes a semiconductor device comprising a semiconductor body having an active region and a peripheral region surrounding the active region.

[0006] Patent Document 4 relates to a semiconductor device having a planar structure comprising a pn junction of a first interconnection layer and a second interconnection layer.

[0007] Patent Document 5 discloses a semiconductor device having a central region and an end region surrounding the central region.

[0008] Patent Document 6 describes a semiconductor layer provided on a substrate with n-type doping, wherein a dopant concentration of an area surrounding an active area having a semiconductor element is increased.

[0009] Patent Document 7 discloses an electronic device having a SiC layer and a junction termination region.

[0010] In addition, reference is made to non-patent documents 2 to 4. State of the art documentsPatent documents Patent document 1: JP 2000 - 516 767 A Patent document 2: JP 2002 - 507 325 A Patentdokument 3: DE 10 2006 023 598 B3 Patentdokument 4: US 5 932 894 A Patentdokument 5: JP 2008 - 227 236 A Patentdokument 6: JP H10 - 270 370 A Patentdokument 7: US 2010 / 0 289 032 A1 Nicht-Patentdokument Nicht-Patent-Dokument 1: B. Jayant Baliga, „FUNDAMENTALS OF POWER SEMICONDUCTOR DEVICES“, S. 149 - S. 155 Nicht-Patent-Dokument 2: P.A. Losee, „HIGH-VOLTAGE 4H-SIC PIN RECTIFIERS WITH SINGLE-IMPLANT, MULTI-ZONE JTE TERMINATION“, Proceeding of ISPSD, 2004, S. 301-304 Nicht-Patent-Dokument 3: R. Huang, „CONCEPTION, SUIVI DE FABRICATION ET CARACTERISATION ELECTRIQUE DE COMPOSANTS HAUTE TENSION EN SIC“, INSA, Lyon, 2011, S. 33-53 Nicht-Patent-Dokument 4: R. Stengl et al., „VARIATION OF LATERAL DOPING AS A FIELD TERMINATOR FOR HIGH-VOLTAGE POWER DEVICE“, IEEE Transactions on Electron devices, Vol. 33, 1986, No. 3, S. 426-428 Brief description of the inventionProblems to be solved by the invention

[0011] In the high-withstand voltage semiconductor devices disclosed in Patent Document 1 and Patent Document 2, a peak electric field strength is generated between JTE regions or in a junction of the JTE region and an epitaxial layer when a relatively high reverse voltage is applied to a pn junction. There is a problem in that a creeping discharge is generated on an outer surface of a substrate, and thus the withstand voltage of the semiconductor device decreases considerably when a peak electric field strength reaching a surface of the substrate is large. In addition, there is a problem in that the peak electric field strength gradually increases with an increase in the withstand voltage in a withstand voltage specification of the semiconductor device.

[0012] The JTE structure for controlling the peak value of the electric field strength includes a structure in which the JTE region is provided with a concentration gradient as disclosed in Patent Document 1, and a structure in which the pn junction and the JTE region are covered with the third layer as disclosed in Patent Document 2.

[0013] However, in the JTE structure disclosed in Patent Document 1 and Patent Document 2, the JTE regions do not always have a regressive distribution. The "regressive distribution" refers to a distribution with a peak of impurity density at a back side of a substrate, i.e., an inner side, from a surface on one of the sides in the thickness direction of the JTE region.

[0014] A more detailed description follows. In the JTE structures disclosed in Patent Document 1 and Patent Document 2, the high-impurity region, which has a relatively high impurity density, is formed to extend to the surface of the JTE region. Accordingly, there is a problem in that the peak electric field strength reaching the surface of the JTE region or the device surface cannot be sufficiently reduced.

[0015] Furthermore, in the JTE structure disclosed in Patent Document 2, the third layer covering the pn junction and the JTE region does not always have a higher impurity density than the drift layer. Accordingly, when a relatively high reverse voltage is applied to the device, the third layer is perfectly depleted to maintain the electric field. Therefore, a problem arises in that it is not possible to sufficiently reduce the peak electric field strength reaching the device surface.

[0016] The object of the present invention is to provide a semiconductor device with a high withstand voltage in which a stable withstand voltage can be achieved, and a method for producing the same. Means to solve the problems

[0017] The object underlying the invention is achieved by a semiconductor device having the features of independent claim 1 and independent claim 2, respectively, and by a method for producing a semiconductor device having the features of independent claim 9 and independent claim 10, respectively. Advantageous developments of the semiconductor device according to the invention are specified in dependent claims 3 to 8. Advantageous developments of the method according to the invention are specified in dependent claims 11 to 13. Effects of the invention

[0018] In the semiconductor device according to the present invention, the first conductivity type region serves as an electric field shield when a relatively high reverse voltage is applied to the pn junction. Furthermore, depletion in the surface on one of the sides in the thickness direction of the junction termination region can be suppressed by the first conductivity type region. Therefore, a region in the junction termination region where an electric field strength is highest can be located on the other side in the thickness direction from the surface on one of the sides in the thickness direction of the junction termination region.

[0019] As a result, it is possible to reduce a peak value of the electric field strength reaching the surface on one of the sides in the thickness direction of the junction termination region or the surface on one of the sides in the thickness direction of the silicon carbide layer containing the junction termination region. Therefore, it is possible to suppress a creeping discharge on an outer side of a substrate formed by the silicon carbide layer and the silicon carbide substrate.

[0020] Accordingly, it is possible to prevent the withstand voltage of the semiconductor device from decreasing. Consequently, it is possible to realize a semiconductor device with a high withstand voltage in which a stable withstand voltage can be achieved.

[0021] Moreover, in the method for manufacturing a semiconductor device according to the present invention, it is possible to provide the semiconductor device with a high withstand voltage according to the present invention in which a stable withstand voltage as described above can be achieved.

[0022] These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. Brief description of the drawings Fig. 1 is a sectional view showing a structure of a semiconductor device 1 according to a first embodiment of the present invention. Fig. 2 is a graph showing a relationship between electric field strengths reaching substrate surfaces S0 in two types of JTE structures and a distance from a SiC region of the second conductivity type 13. Fig. Figure 3 is a graph showing a simulation result of a comparison JTE structure B. Fig. Figure 4 is a graph showing a simulation result of the present JTE structure A. Fig. Figure 5 is a graph showing an impurity profile of a comparison JTE structure D. Fig. Figure 6 is a graph showing an impurity profile of the present JTE structure C. Fig. Figure 7 is a graph showing a relationship between electric field strengths reaching substrate surfaces S0 in the two types of JTE structures C and D and a lateral distance of a substrate. Fig. 8 is a sectional view showing a state of a stage in which the formation of the second conductivity type SiC region 13 is completed. Fig. 9 is a sectional view showing a state of a stage in which the formation of a conductive region 14 is completed. Fig. 10 is a sectional view showing a state of a stage in which the formation of a JTE region 15 is completed. Fig. 11 is a sectional view showing a state of a stage in which the formation of a first conductivity type SiC region 16 is completed. Fig. 12 is a sectional view showing a state of a stage in which the formation of a protective layer 17 is completed. Fig. 13 is a sectional view showing a state of a stage in which the formation of an opening portion 18 is completed. Fig. 14 is a sectional view showing another example of the first conductivity type SiC region. Fig. 15 is a sectional view showing yet another example of the first conductivity type SiC region. Fig. 16 is a sectional view showing yet another example of the first conductivity type SiC region. Fig. 17 is a sectional view showing a structure of a semiconductor device 2 according to a second embodiment of the present invention. Fig. 18 is a sectional view showing a state of a stage in which the formation of a JTE region 15 is completed. Fig. 19 is a sectional view showing a state of a stage in which the formation of a first conductivity type SiC region 16 is completed. Fig. 20 is a sectional view showing a state of a stage in which the formation of a protective layer 17 is completed. Fig. 21 is a sectional view showing a state of a stage in which the formation of an opening portion 18 is completed. Fig. 22 is a sectional view showing another example of the first conductivity type SiC region. Fig. 23 is a sectional view showing yet another example of the first conductivity type SiC region. Embodiments according to the inventionFirst embodiment

[0023] Fig. 1 is a sectional view showing a structure of a semiconductor device 1 according to a first embodiment of the present invention. The semiconductor device 1 according to the present embodiment is a pn diode. The semiconductor device 1 is formed to include a silicon carbide (SiC) substrate 11, a SiC epitaxial layer 12, a second conductivity type SiC region 13, an ohmic contact region 14, a junction termination extension (JTE) region 15, a first conductivity type SiC region 16, a protective layer 17, an anode electrode 19, and a cathode electrode 20.

[0024] The SiC epitaxial layer 12 corresponds to a silicon carbide layer. The SiC region of the second conductivity type 13 corresponds to a region of the second conductivity type. The JTE region 15 corresponds to a junction termination region. The SiC region of the first conductivity type 16 corresponds to a region of the first conductivity type.

[0025] In the following description, the combination of the SiC substrate 11, the SiC layer constituting the semiconductor layer provided on the SiC substrate 11, and the SiC epitaxial layer 12 in the present embodiment is referred to as a “SiC substrate” or a “substrate” in some cases.

[0026] In these cases, the substrate is plate-shaped and contains the respective regions formed in the SiC epitaxial layer 12, that is, the SiC region of the second conductivity type 13, the ohmic contact region 14, the JTE region 15 and the SiC region of the first conductivity type 16.

[0027] Fig. 1 shows only an outer peripheral end of the substrate (which will be referred to as an “outermost edge” in some cases hereinafter) and the vicinity thereof, and an inner portion thereof is not shown. In Fig. 1, a right side of the diagram corresponds to the outer peripheral end side of the substrate, and a left side corresponds to an inner side of the outer peripheral end of the substrate. In the present embodiment, the "outer peripheral end of the substrate" corresponds to the "outer peripheral end of the SiC substrate 11," and the "inner side of the outer peripheral end of the substrate" corresponds to the "inner side of the outer peripheral end of the SiC substrate 11."

[0028] The SiC epitaxial layer 12 is provided on a surface on one of the sides in a thickness direction of the SiC substrate 11. The SiC substrate 11 and the SiC epitaxial layer 12 are of a first conductivity type.

[0029] The JTE region 15 is formed in a neighboring area of ​​a surface on one of the sides in a thickness direction of the SiC epitaxial layer 12. The "neighboring area of ​​the surface" includes the surface and the neighboring area thereof. The semiconductor device 1 includes a plurality of JTE regions 15. Although in Fig. 1 three JTE regions 15 are shown, four or more JTE regions 15 may also be provided.

[0030] The JTE regions 15 are arranged side by side in a direction perpendicular to the thickness direction of the SiC substrate 11 (which is referred to as a “side direction” in some cases hereinafter) toward the outermost edge of the semiconductor device 1. In Fig. 1 the lateral direction is equivalent to a transverse direction in the plane of the paper.

[0031] In the present embodiment, the JTE regions 15 are provided adjacent to each other in the lateral direction. Herein, "adjacent to each other" means that they are arranged in contact with each other without a gap. Accordingly, each of the JTE regions 15 is connected to the other JTE region 15 adjacent to it in the lateral direction.

[0032] The second conductivity type SiC region 13 is formed in a region on an inner side of the substrate from the JTE region 15 in the lateral direction in the adjacent area of ​​the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12. The second conductivity type SiC region 13 is arranged in contact with any of the JTE regions 15 provided on an innermost side of the substrate in the lateral direction.

[0033] The second conductivity type SiC region 13 is formed over a central region in the thickness direction of the SiC epitaxial layer 12, starting from the surface on one of the sides in the thickness direction. The second conductivity type SiC region 13 is of the second conductivity type.

[0034] The ohmic contact region 14 is formed separately from the JTE region 15 in a portion of the adjacent region of the surface on one of the sides in the thickness direction of the second conductivity type SiC region 13. The ohmic contact region 14 is formed shallower than the second conductivity type SiC region 13. For example, the ohmic contact region 14 is formed to a depth of approximately two-fifths (2 / 5) of a depth of the second conductivity type SiC region 13 from the surface on one of the sides in the thickness direction of the second conductivity type SiC region 13. The ohmic contact region 14 is of the second conductivity type. An impurity density of the conductive region 14 is higher than an impurity density of the second conductivity type SiC region 13.

[0035] Any one of the JTE regions (hereinafter referred to in some cases as the "inner-side JTE region") 15 to be provided on the innermost side of the substrate in the lateral direction is disposed adjacent to the second-conductivity-type SiC region 13 in the lateral direction. Specifically, the inner-side JTE region 15 is adjacent to the second-conductivity-type SiC region 13 as viewed from one of the sides in the thickness direction of the substrate and is provided to surround the second-conductivity-type SiC region 13. The other JTE regions 15 are adjacent to the inner-side JTE regions 15 as viewed from one of the sides in the thickness direction of the substrate and are provided to surround the inner-side JTE region 15.

[0036] In the present embodiment, the SiC substrate 11 assumes a rectangular, flat shape when viewed from one of the sides in the thickness direction. The second conductivity type SiC region 13 is formed to assume an annular, flat shape when viewed from one of the sides in the thickness direction, specifically, an almost rectangular and annular shape along the outer peripheral end of the SiC substrate 11.

[0037] Each of the JTE regions 15 is formed to assume an annular, planar shape as viewed from one of the sides in the thickness direction, more specifically, an almost rectangular and annular shape along the second conductivity type SiC region 13.

[0038] Each of the JTE regions 15 is of the second conductivity type. The impurity density of each of the JTE regions 15 is lower than the impurity density of the second conductivity type SiC region 13. The impurity density of each of the JTE regions 15 has a density distribution for a gradual decrease in the lateral direction from the second conductivity type SiC region 13 toward the SiC epitaxial layer 12, that is, in the lateral direction from the inner side of the substrate to the outermost edge side. Different from the present embodiment, the impurity density of each of the JTE regions 15 may have a uniform density distribution in the lateral direction as a whole.

[0039] The JTE regions 15 are arranged on the outermost edge side from the inner side of the substrate in descending order of the surface density of second conductivity type impurities (hereinafter referred to as "second conductivity type impurities" in some cases). In other words, the JTE regions 15 are arranged such that the surface density of second conductivity type impurities gradually decreases from the inner side of the substrate to the outermost edge side.

[0040] The surface density is equal to the integral of the bulk impurity density over the thickness of an impurity region. In the case where the bulk impurity density is constant over the thickness of the impurity region, the surface density is equal to the product of the bulk impurity density and the thickness of the impurity region.

[0041] The first conductivity type SiC region 16 is provided in a region (hereinafter referred to as a "transition region" in some cases) where the JTE regions 15 are connected to each other, in the adjacent region of the surface on one of the sides in the thickness direction of the JTE region 15. In other words, the first conductivity type SiC region 16 is provided across the two of the JTE regions 15 that are adjacent to each other in the lateral direction.

[0042] The first conductivity type SiC region 16 is provided in each of the transition areas of the JTE regions 15. In other words, the semiconductor device 1 includes the first conductivity type SiC regions 16. The first conductivity type SiC regions 16 are arranged adjacent to each other at a predefined distance in the lateral direction.

[0043] Each of the first conductivity type SiC regions 16 is formed shallower than the JTE region 15. For example, each of the first conductivity type SiC regions 16 is formed to a depth of approximately one-third (1 / 3) of the thickness of the JTE region 15 from the surface on one of the sides in the thickness direction of the JTE region 15. Each of the first conductivity type SiC regions 16 is of the first conductivity type.

[0044] The protective layer 17 is provided on the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12. The protective layer 17 has an opening portion 18 at a location corresponding to a region where the ohmic contact region 14 is formed. An opening opening to one of the sides in the thickness direction of the substrate is formed in the opening portion 18. The ohmic contact region 14 is exposed to one of the sides in the thickness direction through the opening formed in the opening portion 18.

[0045] The anode electrode 19 is provided in the opening of the opening region 18 of the protective layer 17. The anode electrode 19 is provided in contact with the ohmic contact region 14. The anode electrode 19 is electrically connected to the second conductivity type SiC region 13 through the ohmic contact region 14.

[0046] The cathode electrode 20 is provided on a surface on the other side in the thickness direction of the SiC substrate 11. The cathode electrode 20 is provided opposite to the anode electrode 19, as shown in Fig. 1 shown.

[0047] In the present embodiment, the first conductivity type is specified as n-type, and the second conductivity type is specified as p-type. Accordingly, the SiC substrate 11, the SiC epitaxial layer 12, and the first conductivity type SiC region 16 have n-type conductivity, and the second conductivity type SiC region 13, the ohmic contact region 14, and the JTE region 15 have p-type conductivity.

[0048] As described above, in the semiconductor device 1 according to the present embodiment, the first conductivity type SiC region 16 is present in the adjacent portion of the surface on one of the sides in the thickness direction in the junction region of the JTE regions 15, and further, the second conductivity type SiC region 13 is present from the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12 to a deeper position than the first conductivity type SiC region 16.

[0049] Therefore, even in the case where an electric field is concentrated at the junction of the JTE regions 15, so that a peak electric field strength is generated when a relatively high reverse voltage is applied to the pn junction, it is possible to reduce the peak electric field strength reaching the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12. Accordingly, it is possible to realize the semiconductor device 1 with a high withstand voltage in which a stable withstand voltage can be achieved.

[0050] The effects of the semiconductor device 1 according to the present embodiment were confirmed by the following simulation results. The simulation will be described in detail below. Regarding the simulation investigated by the present inventors, each element is set to the following values, assuming that a semiconductor device with a withstand voltage of 3300 V, specifically a pn diode, is manufactured.

[0051] The impurity density of the SiC epitaxial layer 12 is 3 × 10 15 / cm 3 , and the thickness direction (hereinafter referred to as "thickness") is set to 30 µm. Furthermore, the impurity density of the second conductivity type SiC region 13 is set to 3 × 10 18 / cm 3, and a thickness, that is, a depth from the surface on one of the sides in the thickness direction, of the SiC epitaxial layer 12 is set to be less than or equal to 0.8 µm. Furthermore, three JTE regions 15 are formed as JTE regions, and implantation surface densities toward the outermost edge are set to 1.2 × 10 13 / cm 2 , 7.8 × 10 12 / cm 2 or 3.9 × 10 12 / cm 2 The "implantation surface density" indicates a surface density of impurities during ion implantation. In addition, the thickness of each of the JTE regions 15, that is, the depth from the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12, is set to be less than or equal to 0.8 µm.

[0052] For comparison, it is assumed that two types of JTE structures are formed. In a first type of JTE structure, the JTE region 15 is formed with an implantation profile such that an impurity density is constant in the depth direction of the JTE region 15.

[0053] In a second type of JTE structure, the JTE region 15 is formed with an implantation profile such that the impurity density in the adjacent area of ​​the surface on one of the sides in the thickness direction of the JTE region 15 is lower than an implantation peak, which is a peak value of the impurity density during ion implantation. In other words, in the second type of JTE structure, the density of impurities of the second conductivity type in each of the JTE regions 15 has a maximum value on the other side in the thickness direction of each of the JTE regions 15, compared to the surface on one of the sides in the thickness direction.

[0054] Furthermore, in the second type of JTE structure, the first conductivity type SiC region 16 is formed in the adjacent portion of the surface of the junction region between the JTE regions 15. In other words, the second type of JTE structure serves as a JTE structure in the semiconductor device 1 according to the present embodiment.

[0055] The impurity density of the SiC region of the first conductivity type 16 in the second type of JTE structures is 1 × 10 17 / cm 3 The thickness, that is, a depth from the surface on one of the sides in the thickness direction, of the SiC epitaxial layer 12 is set to 0.1 µm. In the following description, in some cases, the second of the types of JTE structures is referred to as a "JTE structure A according to the present application," and the first of the types of JTE structures is referred to as a "comparative JTE structure B."

[0056] Moreover, their combination is sometimes referred to as "JTE structures A and B." In these two types of JTE structures A and B, the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12 is sometimes referred to as a "substrate surface S0." It is assumed that a relatively high reverse voltage of 3300 V is applied to the pn diode serving as the semiconductor device 1 in which these two types of JTE structures A and B are formed.

[0057] Fig. Figure 2 is a graph showing a relationship between electric field strengths reaching the substrate surface S0 in the two types of JTE structures and a distance from the SiC region of the second conductivity type 13. The Fig. 3 and Fig. 4 are graphs showing a simulation result as an electric field distribution.

[0058] Fig. 3 is a graph showing a simulation result for the comparison JTE structure B, and Fig. 4 is a graph showing a simulation result for the JTE structure A according to the present invention. In Fig. 2, the abscissa axis indicates the distance from the SiC region of the second conductivity type 13 and the ordinate axis indicates an electric field strength.

[0059] In the Fig. 3 and Fig. 4, the abscissa axis indicates a distance X [µm] from the SiC region of the second conductivity type 13, and the ordinate axis indicates a distance Y [µm] from the substrate surface S0. The direction of the abscissa axis in the Fig. 2 to 4 corresponds to the lateral direction of the substrate, i.e. the transverse direction in the plane of the paper, in Fig. 1.

[0060] In Fig. 2, the electric field reaching the substrate surface S0 is given with respect to the two types of JTE structures A and B as a function of the distance from the SiC region of the second conductivity type 13. In the Fig. 3 and Fig. Figure 4 shows a distribution of the electric field in the transition region between the JTE regions 15, in which the electric field is highest, with respect to the two types of JTE structures A and B.

[0061] From the Fig. 3, it was determined that the peak value of the electric field strength reaching the substrate surface S0 in the transition region between the JTE regions 15 is 1.07 MV / cm in the case of the comparative JTE structure B in which the JTE region 15 is formed with such an implantation profile that the impurity density in the depth direction of the JTE region 15 is constant.

[0062] From the Fig. Furthermore, from the simulation result shown in Fig. 4, it was determined that the peak value of the electric field intensity reaching the substrate surface S0 in the junction region between the JTE regions 15 is 0.96 MV / cm in the case of the JTE structure A according to the present invention, in which the JTE region 15 is formed with such an implantation profile that an impurity density on the surface side on one of the sides in the thickness direction of the JTE region 15 is lower than an implantation peak value, and the first conductivity type SiC region 16 is formed in the adjacent portion of the surface of the junction region between the JTE regions 15. From the results described above, it is apparent that the following effects can be achieved.

[0063] In the JTE structure A according to the present invention, the JTE region 15 is formed with such an implantation profile that the impurity density on the surface side on one of the sides in the thickness direction of the JTE region 15 is lower than the implantation peak value, and the first conductivity type SiC region 16 is formed in the adjacent area of ​​the surface on one of the sides in the thickness direction in the transition region between the JTE regions 15, as described above.

[0064] Consequently, in the case where a relatively high reverse voltage is applied to the pn junction, an electric field concentrates only in a region with a relatively higher impurity density (which will be referred to as a “high impurity density region” in some cases hereinafter) at a back side of the substrate, more specifically, an inner side of the surface on one of the sides in the thickness direction in the JTE region 15.

[0065] In addition, the first conductivity type SiC region 16 serves as a shield against the electric field, making it possible to reduce the peak value of the electric field strength reaching the substrate surface S0. Accordingly, creeping discharge on the outside of the substrate is suppressed. Therefore, it is possible to prevent a decrease in the withstand voltage of the semiconductor device and realize the semiconductor device 1 with a high withstand voltage in which a stable withstand voltage can be achieved.

[0066] Preferably, the density of the second conductivity type impurities in the surface on one of the sides in the thickness direction of each of the JTE regions 15 should be less than or equal to one-tenth (1 / 10) of the maximum value in the thickness direction. By setting the density of the second conductivity type impurities in the surface on one of the sides in the thickness direction of each of the JTE regions 15 to a value less than or equal to one-tenth (1 / 10) of the maximum value in the thickness direction, it is possible to further reduce the peak value of the electric field strength reaching the surface of the substrate compared to the case where the density of the second conductivity type impurities is higher than one-tenth of the maximum value in the thickness direction.

[0067] As a result, it is possible to further suppress creeping discharge on the outside of the substrate. Therefore, it is possible to more reliably prevent the decline in the withstand voltage of the semiconductor device 1. Accordingly, it is possible to realize a semiconductor device with a high withstand voltage in which a more stable withstand voltage can be achieved.

[0068] As described above, according to the present invention, the inventors compared the two types of JTE structures A and B by simulation. Regarding the comparative JTE structure B, the JTE region 15 is formed with such an implantation profile that the impurity density is constant in the depth direction of the JTE region 15.

[0069] Regarding the JTE structure A according to the present invention, the JTE region 15 is formed with such an implantation profile that the impurity density in the adjacent portion of the surface on one of the sides in the thickness direction of the JTE region 15 is lower than the implantation peak value, which is the peak value of the impurity density in the ion implantation, and the first conductivity type SiC region 16 is formed in the adjacent portion of the surface of the junction region between the JTE regions 15.

[0070] The inventors of the present application further conducted the study by simulation. As a result, it was found that the peak value of the electric field strength reaching the substrate surface can be drastically reduced by deliberately increasing the impurity density of the first conductivity type SiC region 16 formed in the adjacent area of ​​the surface of the junction region between the JTE regions 15 compared to the impurity density of the SiC epitaxial layer 12 serving as the drift layer.

[0071] The effect was confirmed based on the simulation results described below. The simulation is described in detail below. Regarding the simulation investigated by the present inventors, each element is set to the following values, assuming that the semiconductor device is manufactured with a withstand voltage of 3300 V, specifically as a pn diode.

[0072] Nitrogen (N) is specified as the n-type impurities, which are to be the impurities of the first conductivity type. Aluminum (Al) is specified as the p-type impurities, which are to be the impurities of the second conductivity type. The impurity density of the SiC epitaxial layer 12 is set to 3 × 10 15 / cm 3 and a thickness of 30 µm. Furthermore, the impurity density of the SiC region of the second conductivity type 13 is set to 3 × 10 18 / cm 3and the thickness, that is, a depth from the surface on one of the sides in the thickness direction, of the SiC epitaxial layer 12 is set to about 1.5 µm.

[0073] Furthermore, as the JTE region 15, three JTE regions 15 are formed adjacent to each other in the lateral direction of the substrate. The three JTE regions 15 are formed as a first JTE region 15, a second JTE region 15, and a third JTE region 15 in this order from the inner side of the substrate to the outermost edge, and a prerequisite for forming each of the JTE regions 15 is as follows.

[0074] Regarding the first JTE region 15, an implantation energy is set to 500 keV and an implantation dose is set to 1.5 × 10 13 / cm 2 With respect to the second JTE region 15, an implantation energy is set to 500 keV, and an implantation dose is set to 1.0 × 10 13 / cm 2Regarding the third JTE region 15, an implantation energy is set to 500 keV, and an implantation dose is set to 5.0 × 10 12 / cm 2 set.

[0075] For comparison, two types of JTE structures are assumed to be formed. A first type of JTE structure is a structure in which the first conductivity type SiC region 16 is formed in the adjacent area of ​​the surface of the transition region between the JTE regions 15 (hereinafter referred to in some cases as a "JTE structure C according to the present application").

[0076] A second of the types of JTE structures is a structure in which the first conductivity type SiC region 16 is not formed in the adjacent area of ​​the surface of the transition region between the JTE regions 15 (which will be referred to as a "comparative JTE structure D" in some cases hereinafter).

[0077] Regarding the JTE structure C according to the present application, as a prerequisite for forming the SiC region of the first conductivity type 16, an implantation energy of 75 keV and an implantation dose of 1.0 × 10 12 / cm 2 To simplify the simulation, it is further assumed that the SiC region of the first conductivity type 16 is formed over the entire adjacent area of ​​the surface on one of the sides in the thickness direction of the termination region formed by the JTE regions 15, as shown in Fig. 15, which is described below. Such a SiC region of the first conductivity type is shown in Fig. 15 is designated by the reference symbol “31”.

[0078] The combination of the JTE structure C according to the present application and the comparative JTE structure D is referred to in some cases as “JTE structures C and D” below. Fig. 5 and Fig. 6 are graphs showing an impurity profile in the thickness direction of the substrate in the JTE structures C and D.

[0079] Fig. Figure 5 is a graph showing the impurity profile of the comparison JTE structure D, and Fig. Figure 6 is a graph showing the impurity profile of the JTE structure C according to the present application. Fig. 5 and Fig. 6, the abscissa axis indicates a depth from the substrate surface S0 (which is referred to as a “depth” in some cases) [µm] and the ordinate axis indicates an impurity density [cm -3 ] on.

[0080] In the Fig. 5 and Fig. 6, the density of the first conductivity type impurities of the SiC epitaxial layer 12 is designated by reference symbol "50," and the density of the second conductivity type impurities of the first JTE region 15 formed on the innermost side of the substrate in the three JTE regions 15 is designated by reference symbol "51." In Fig. 6, the density of the impurities of the first conductivity type of the region of the first conductivity type 16 is further designated by the reference symbol “52”.

[0081] In the present simulation, each of the JTE regions 15 having the JTE structures C and D is formed by performing an ion implantation treatment with a single implantation energy as described above. Accordingly, a peak of the impurity density of the first JTE region 15 is formed at a deeper position than the substrate surface S0, as shown in the Fig. 5 and Fig. 6. More specifically, the peak of the impurity density of the first JTE region 15 is located at a position having a depth of approximately 0.8 µm from the substrate surface S0.

[0082] As in Fig. 5, in the comparative JTE structure D, the density of nitrogen (N), which is to be the n-type impurities of the SiC epitaxial layer 12, is higher at a depth of approximately 0.3 µm or less than the density of aluminum (Al), which is to be the p-type impurities implanted to form the JTE region 15.

[0083] Accordingly, the first conductivity type SiC region having an impurity density equal to or lower than the impurity density of the SiC epitaxial layer 12 serving as a drift layer is formed at a depth of approximately 0.3 µm on the substrate surface S0 side from the JTE region 15.

[0084] On the other hand, in the JTE structure C according to the present application, the SiC region of the first conductivity type 16, which apparently has a higher impurity density than that of the SiC epitaxial layer 12 serving as a drift layer, is formed at a depth of approximately 0.3 µm on the side of the substrate surface S0 from the JTE region 15, as shown in Fig. 6 shown.

[0085] The case is assumed in which a relatively high reverse voltage of 3300 V is applied to the pn diode in which these two types of JTE structures C and D are formed. Fig. Figure 7 is a graph showing a relationship between an electric field strength reaching the substrate surface S0 in the two types of JTE structures C and D and a lateral position of the substrate.

[0086] In Fig. 7, the abscissa axis indicates the lateral position [µm] of the substrate and the ordinate axis indicates an electric field strength [MV / cm]. The lateral position of the substrate refers to a position in the lateral direction of the substrate. A direction of the abscissa axis in Fig. 7 corresponds to a transverse direction of the paper in Fig. 1.

[0087] In Fig. 7, a result of the comparative JTE structure D is designated by reference numeral “60,” and a result of the JTE structure C according to the present application is designated by reference numeral “61.” In Fig. 7, moreover, an end of the SiC region of the second conductivity type 13, that is, a region intended to be in contact with the JTE region 15, is designated by an arrow “62”.

[0088] As in Fig. 7, it was found that the maximum value of the electric field strength reaching the substrate surface S0 is 1.44 MV / cm in the comparative JTE structure D and 1.02 MV / cm in the JTE structure C according to the present invention, which corresponds to a reduction of approximately 30%.

[0089] In other words, the reduction amount ΔE of the maximum value of the electric field strength reaching the substrate surface S0 achieved by switching from the comparative JTE structure D to the JTE structure C according to the present application was approximately 30%. From the results described above, it is clear that the following effects can be achieved.

[0090] In the JTE structure C according to the present application, the first conductivity type SiC region 16, as described above, is formed with a higher impurity density than that of the SiC epitaxial layer 12 serving as a drift layer at least in the adjacent region of the surface of the junction region between the JTE regions 15 on the substrate surface S0 side from the JTE region 15.

[0091] Depletion in the surface on one of the sides in the thickness direction of the JTE region 15 is suppressed by the first conductivity type SiC region 16. Therefore, a region with the highest electric field strength in the JTE region 15 can be located on the back side of the JTE region 15, more specifically, on the other side in the thickness direction of the JTE region 15 from the surface on one of the sides in the thickness direction. Consequently, it is possible to reduce the peak value of the electric field strength reaching the substrate surface S0.

[0092] Thus, it is possible to suppress creeping discharge on the outside of the substrate. Accordingly, it is possible to prevent a decrease in the withstand voltage of the semiconductor device 1. Consequently, it is possible to realize the semiconductor device 1 with a high withstand voltage, in which a stable withstand voltage can be achieved.

[0093] With the structure in which the SiC region of the first conductivity type 16 is located only in the adjacent area of ​​the surface of the transition region between the JTE regions 15, as in Fig. 1, the effects of the SiC region of the first conductivity type 16 can be achieved accordingly. As shown in Fig. 17, which will be described below, the effects can also be achieved in the structure in which the first conductivity type SiC region 16 is located only in an adjacent portion of a surface of a junction region between the JTE region 15 and the SiC epitaxial layer 12.

[0094] In other words, the effects of the first conductivity type SiC region 16 can be achieved when the first conductivity type SiC region 16 is formed at least in the adjacent region of the surface of the junction region between the JTE regions 15 or between the JTE region 15 and the SiC epitaxial layer 12 on the substrate surface S0 side from the JTE region 15.

[0095] A method for manufacturing the semiconductor device 1 according to the first embodiment of the present invention will be described below. Fig. 8 to 13 are views for explaining the method of manufacturing the semiconductor device 1 according to the first embodiment of the present invention.

[0096] Fig. Fig. 8 is a sectional view showing a state of a stage in which the formation of the second conductivity type SiC region 13 is completed. First of all, an epitaxial growth treatment using a predetermined dopant material is performed over the surface on one of the sides in the thickness direction of the first conductivity type SiC substrate 11. As shown in Fig. 8, the SiC epitaxial layer 12, which is of the first conductivity type, is thus formed on the surface on one of the sides in the thickness direction of the SiC substrate 11.

[0097] The step of forming the SiC epitaxial layer 12 corresponds to a step of forming a silicon carbide layer. In the present embodiment, the n-type SiC substrate 11 is used as the SiC substrate 11, and the first conductivity type dopant, specifically the n-type dopant, is used as the predefined dopant material. For example, nitrogen (N), phosphorus (P), or the like is used as the n-type dopant.

[0098] Then, a treatment for implanting an ion of the predefined dopant material (which will be referred to as an "ion implantation treatment" in some cases hereinafter) is performed over a region predefined as a region for forming the second conductivity type SiC region 13 in the adjacent region of the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12. In the present embodiment, the ion implantation treatment is performed such that the ions are implanted over the vicinity of a central region in the thickness direction of the SiC epitaxial layer 12 from the surface on one of the sides in the thickness direction.

[0099] As in Fig. As shown in Figure 8, the second conductivity type SiC region 13, which is of the second conductivity type, is thus formed in a region adjacent to the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12, more specifically, in the predefined region. The step of forming the second conductivity type SiC region 13 corresponds to a step of forming a second conductivity type region.

[0100] The ion implantation treatment in the present step for forming the second conductivity type SiC region 13 may be performed with a single implantation energy or may be performed while changing the implantation energy stepwise, for example, making a stepwise change from high energy to low energy.

[0101] Furthermore, in the present embodiment, the predefined dopant to be used in the ion implantation treatment in the present step is the second conductivity type dopant, more specifically the p-type dopant. For example, aluminum (Al) or boron (B) is used as the p-type dopant.

[0102] Fig. 9 is a sectional view showing a state of a stage in which the formation of the conductive region 14 is completed. After the second conductivity type SiC region 13 has been formed, the ion implantation treatment is performed over a region predefined as a region for forming the conductive region 14 in the region in which the second conductivity type SiC region 13 is formed. As shown in Fig. 9, the ohmic contact region 14, which has a higher impurity density than the second conductivity type SiC region 13 and is of the second conductivity type, is thus formed in the second conductivity type SiC region 13.

[0103] The ion implantation treatment in the present step for forming the conductive region 14 may be performed with a single implantation energy or may be performed while gradually changing the implantation energy, for example, gradually changing from high energy to low energy. Furthermore, in the present embodiment, the p-type dopant is used as the predefined dopant material to be used in the ion implantation treatment in the present step. For example, aluminum (Al) or boron (B) is used as the p-type dopant.

[0104] Fig. 10 is a sectional view showing a state of a stage in which the formation of the JTE region 15 is completed. After the ohmic contact region 14 is formed, the ion implantation treatment is performed several times with an implantation mask change in a region adjacent to the second conductivity type SiC region 13 in the side direction of the substrate in the adjacent area of ​​the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12.

[0105] As in Fig. As shown in Figure 10, the JTE regions 15 are formed adjacent to the second conductivity type SiC region 13. The JTE regions 15 are formed adjacent to each other in the lateral direction.

[0106] The step of forming the JTE region 15 corresponds to a step of forming a termination region. Moreover, the region adjacent to the second conductivity type SiC region 13 in the substrate lateral direction corresponds to a region on the outer peripheral end side of the SiC substrate 11 from the second conductivity type SiC region 13, that is, a region adjacent to the second conductivity type SiC region 13.

[0107] Each of the JTE regions 15 is formed to be of the second conductivity type. Moreover, each of the JTE regions 15 is formed so that its impurity density is lower than the impurity density of the second conductivity type SiC region 13. Further, each of the JTE regions 15 is formed so that the impurity density has a density distribution for a gradual decrease in the lateral direction from the second conductivity type SiC region 13 toward the SiC epitaxial layer 12, that is, in the lateral direction from the inner side of the substrate to the outermost edge side. Different from the present embodiment, each of the JTE regions 15 may be formed so that the impurity density as a whole has a uniform density distribution in the lateral direction.

[0108] In the present step, moreover, the JTE regions 15 are formed such that the surface density of the second conductivity type impurities decreases toward the outer peripheral end side of the SiC substrate 11 by regulating the ion implantation amount during the ion implantation treatment. The ion implantation treatment in the present step for forming the JTE region 15 may be performed with a single implantation energy or may be performed while gradually changing the implantation energy, for example, gradually changing from high energy to low energy.

[0109] During ion implantation, ions are implanted deeper when the implantation energy is higher. Accordingly, when the ion implantation is performed with a single implantation energy, it is possible to realize the impurity density distribution with an impurity density peak at a deeper position from the surface on one side in the thickness direction of the SiC epitaxial layer 12 when the implantation energy is higher.

[0110] By taking advantage of this fact, in the present embodiment, each of the JTE regions 15 is formed such that the ion implantation energy in the ion implantation treatment is regulated, and the density of the second conductivity type impurities in each of the JTE regions 15 thus has a maximum value on the other side in the thickness direction of each of the JTE regions 15 from the surface on one of the sides in the thickness direction.

[0111] In the present embodiment, the predefined dopant to be used in the ion implantation treatment in the present step is the second conductivity type dopant, more specifically the p-type dopant. For example, aluminum (Al) or boron (B) is used as the p-type dopant.

[0112] Fig. 11 is a sectional view showing a state of a stage in which the formation of the first conductivity type SiC region 16 is completed. After the JTE region 15 is formed, the ion implantation treatment is performed at least over the adjacent portion of the surface on one of the sides in the thickness direction in the region where the JTE regions 15 are connected to each other.

[0113] In the present embodiment, the ion implantation treatment is performed over the junction region of the JTE regions 15 in the adjacent region of the surface on one of the sides in the thickness direction of the region in which the JTE regions 15 are connected to each other, that is, in the adjacent region of the surface on one of the sides in the thickness direction of the JTE region 15. As shown in Fig. 11, the first conductivity type SiC region 16 is thus formed in the transition region of the JTE regions 15 in the adjacent region of the surface on one of the sides in the thickness direction of the JTE region 15.

[0114] The first conductivity type SiC region 16 is formed to a depth of, for example, one-third (1 / 3) of the thickness of the JTE region 15 from the surface on one of the sides in the thickness direction of the JTE region 15. The step of forming the first conductivity type SiC region 16 corresponds to a step of forming a first conductivity type region.

[0115] In the present step of forming the first conductivity type SiC region 16, by regulating the implantation energy in the ion implantation treatment, it is possible to form the first conductivity type SiC region 16 down to a depth not reaching from the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12, more specifically, the surface on one of the sides in the thickness direction of the JTE region 15, to a lower portion of the JTE region 15.

[0116] As in Fig. 11, it is therefore possible to achieve a structure in which the first conductivity type SiC region 16 is present in the adjacent portion of the surface on one of the sides in the thickness direction in the junction region of the JTE regions 15, and further the second conductivity type SiC region 13 is formed up to a position deeper than the first conductivity type SiC region 16 from the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12.

[0117] After each of the ion implantation treatments described above, an activation annealing treatment is performed. Consequently, each dopant subjected to ion implantation in each step can be electrically activated. Furthermore, the activation annealing treatment simultaneously restores crystallinity to the ion implantation region.

[0118] Fig. Fig. 12 is a sectional view showing a state of a stage in which the formation of the protective layer 17 is completed. After the first conductivity type SiC region 16 has been formed, the protective layer 17 is formed on the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12, as shown in Fig. 12. The protective layer 17 is realized by an insulating layer consisting of an insulating material such as SiO2 or polyimide.

[0119] Fig. Fig. 13 is a sectional view showing a state of a stage in which the formation of the opening portion 18 is completed. After the protective layer 17 has been formed, the opening portion 18 is formed in the protective layer 17 as shown in Fig. 13. The opening portion 18 is formed such that the ohmic contact portion 14 is exposed from a lower portion of the opening portion 18, as shown in Fig. 13 shown.

[0120] After the opening area 18 has been formed, the Fig. 1 is formed such that it is electrically connected to the ohmic contact region 14 exposed from the lower region of the opening region 18. Moreover, the Fig. 1 is formed on a surface on the other side in the thickness direction of the SiC substrate 11.

[0121] By following the steps described above you will get the Fig. 1 according to the first embodiment of the present invention. In the present embodiment, it is possible to obtain the semiconductor device 1 in which the first conductivity type SiC region 16 is present in the adjacent portion of the surface on one of the sides in the thickness direction in the region where the JTE regions 15 are connected to each other, and further, the second conductivity type SiC region 13 is present at the position deeper than the first conductivity type SiC region 16 from the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12.

[0122] The semiconductor device 1 having the structure can reduce the peak value of the electric field intensity reaching the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12 even in the case where the electric field concentrates at the junction portion of the adjacent JTE regions 15, so that the peak value of the electric field intensity is generated when the relatively high reverse voltage is applied to the pn junction, as described above.

[0123] Therefore, with the method for manufacturing a semiconductor device according to the present embodiment, it is possible to manufacture a semiconductor device 1 with a high withstand voltage in which a stable withstand voltage can be achieved.

[0124] Furthermore, in the present embodiment, the implantation energy in the ion implantation treatment is regulated to adjust the impurity density distribution of the JTE region 15. Accordingly, by setting the ion implantation energy into one type, for example, it is possible to easily manufacture the semiconductor device 1 with a high withstand voltage in which a stable withstand voltage can be achieved as described above.

[0125] Although the JTE region 15 is formed by the ion implantation treatment and then the ion implantation treatment is further carried out to form the first conductivity type SiC region 16 as shown in the Fig. 10 and Fig. 11 in the present embodiment described above, the first conductivity type SiC region may also be formed by another manufacturing method.

[0126] Fig. 14 is a sectional view showing another example of the first conductivity type SiC region. Fig. 14 shows a state of a stage in which the formation of a first conductivity type SiC region 26 according to another example of the first conductivity type SiC region is completed. As shown in Fig. 14, the first conductivity type SiC region 26 may be formed by utilizing a side scattering effect during ion implantation to form a JTE region 25.

[0127] In this case, the position at which the ions are to be implanted is set in the ion implantation treatment for forming the JTE region 25 so that the adjacent JTE regions 25 are connected by utilizing the side scattering effect in the ion implantation at a deeper position than the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12.

[0128] Consequently, a region where the JTE regions 25 are not connected to each other is formed in the adjacent region of the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12. The region where the JTE regions 25 are not connected to each other, that is, the SiC epitaxial layer 12 remaining between the separately provided JTE regions 25, serves as the first conductivity type SiC region 26.

[0129] Here, the JTE region 25 corresponds to a transition termination region. The SiC region of the first conductivity type 26 corresponds to a region of the first conductivity type. Fig. Accordingly, according to the structure shown in Fig. 14, it is possible to achieve the same effects as those in the present embodiment.

[0130] Although in Fig. 14, the first conductivity type SiC region 26 is shown with a different hatching than the SiC epitaxial layer 12, but these are actually identical to each other. As described above, the SiC epitaxial layer 12 remaining between the JTE regions 25 after the ion implantation treatment to form the JTE region 25 serves as the first conductivity type SiC region 26.

[0131] By forming the first conductivity type SiC region 26 in this way by utilizing the side scattering effect during ion implantation to form the JTE region 25, it is possible to omit the step of ion implantation treatment for forming the first conductivity type SiC region 26. Accordingly, the high withstand voltage semiconductor device in which a stable withstand voltage can be achieved as described above can be manufactured more easily and at a lower cost compared to the present embodiment.

[0132] Moreover, the adjacent JTE regions 25 may be connected to each other at the position deeper than the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12 to form the first conductivity type SiC region 26 by another method.

[0133] In another method, for example, it is possible to use a method of tapering a resist serving as an implantation mask or a method of performing ion implantation treatment over the SiC substrate 11 in an oblique direction. Even in the case where the first conductivity type SiC region 26 is formed in this way, it is possible to achieve the same effects as those in the present embodiment.

[0134] In the present embodiment, the ion implantation treatment is further performed over the SiC epitaxial layer 12 to form the JTE region 15. In the ion implantation treatment for forming the JTE region 15, it is desirable to perform the ion implantation treatment such that an average value of the implantation surface density over the entire termination implantation region formed by the JTE regions 15 adjacent to the second conductivity type SiC region 13 is 0.5 × 10 13 / cm 2 up to 3 × 10 13 / cm 2 amounts.

[0135] The implantation surface density is equal to the integral of the bulk impurity density over the thickness of the impurity region. In the case where the bulk impurity density is constant over the thickness of the impurity region, the implantation surface density is equal to the product of the bulk impurity density and the thickness of the impurity region.

[0136] In the present embodiment, the thickness of each of the JTE regions 15, that is, a depth from the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12, is approximately 0.6 μm to 1.0 μm. Moreover, an implantation width of each of the JTE regions 15 is approximately 30 μm to 300 μm. The impurity density of the first conductivity type SiC region 16 is approximately 10 16 / cm 3 up to 10 17 / cm 3 , and the thickness thereof, that is, a depth from the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12, is approximately 0.1 µm to 0.3 µm.

[0137] Furthermore, in the present embodiment, the description referred to the case where the semiconductor device 1 is a pn diode. However, the present invention is not limited to a pn diode, but the structure of the semiconductor device 1 according to the present embodiment can be applied to any termination structure including the JTE region 15. For example, it is also possible to apply the structure of the semiconductor device 1 according to the present embodiment to a Schottky diode using SiC, a MOSFET using SiC, an insulated gate bipolar transistor (abbreviation: IGBT) using SiC, or the like.

[0138] A more detailed description follows below. In the present embodiment, an implantation profile for forming the JTE region 15 is selected such that the impurity density in the adjacent surface area on one of the sides in the thickness direction of the JTE region 15 is lower than the implantation peak value. The first conductivity type SiC region 16 is present in the adjacent surface area on one of the sides in the thickness direction of the transition region between the JTE regions 15.

[0139] Moreover, the second conductivity type SiC region 13 is present from the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12 to the position deeper than the first conductivity type SiC region 16. Such a structure can also be used for a semiconductor device using SiC that has the JTE region 15, for example, a Schottky diode, a MOSFET, an IGBT, or the like.

[0140] Moreover, although the description in the present embodiment referred to the structure in which the first conductivity type SiC region 16 is located only in the adjacent area of ​​the surface of the transition region between the adjacent JTE regions 15, the first conductivity type SiC region may have a different structure.

[0141] The Fig. 15 and Fig. 16 are sectional views showing another example of the first conductivity type SiC region. Fig. 15 and Fig. 16 shows a state of a stage in which the formation of first conductivity type SiC regions 31 and 32 according to another example of the first conductivity type SiC region is completed. The first conductivity type SiC regions 31 and 32 correspond to the first conductivity type region.

[0142] The SiC region of the first conductivity type can be prepared in the same way as in Fig. 15 may be formed over the entire adjacent area of ​​the surface on one of the sides in the thickness direction of the termination region formed by the JTE regions 15.

[0143] Moreover, the SiC region of the first conductivity type can be formed in the same way as in Fig. 16 may be formed over the entire adjacent area of ​​the surface on one of the sides in the thickness direction of the device including the SiC region of the second conductivity type 13 and the ohmic contact region 14 in addition to the termination region. Fig. 15 and Fig. 16, it is possible to achieve the same effects as those in the present embodiment. Second embodiment

[0144] Fig. 17 is a sectional view showing a structure of a semiconductor device 2 according to a second embodiment of the present invention. The semiconductor device 2 according to the present embodiment has a structure similar to that of the semiconductor device 1 according to the first embodiment.

[0145] Therefore, in the present embodiment, components different from the semiconductor device 1 according to the first embodiment will be described, components corresponding to the semiconductor device 1 will have the same reference numerals, and a general explanation will be omitted. Furthermore, in the present embodiment, in the same manner as in the first embodiment, a first conductivity type is specified as an n-type, and a second conductivity type is specified as a p-type.

[0146] The semiconductor device 2 according to the present embodiment is a pn diode, just like the semiconductor device 1 according to the first embodiment. Like the semiconductor device 1 according to the first embodiment, the semiconductor device 2 according to the present embodiment is formed to include a silicon carbide (SiC) substrate 11, a SiC epitaxial layer 12, a second conductivity type SiC region 13, an ohmic contact region 14, a JTE region 15, a first conductivity type SiC region 16, a protective layer 17, an anode electrode 19, and a cathode electrode 20.

[0147] Regarding the semiconductor device 1 according to the first embodiment, as shown in Fig. 1, the JTE regions 15 are provided adjacent to each other in the lateral direction toward the outermost edge of the semiconductor device 1. On the other hand, in the semiconductor device 2 according to the present embodiment, the JTE regions 15 are each provided at a predefined distance in a lateral direction toward an outermost edge of the semiconductor device 2, as shown in Fig. 17 shown.

[0148] In other words, the JTE regions 15 are separated from each other and not in contact with each other. The SiC epitaxial layer 12 is provided between the adjacent JTE regions 15.

[0149] The first conductivity type SiC region 16 is formed in an adjacent portion of a surface on one of the sides in a thickness direction of the JTE region 15 and the SiC epitaxial layer 12 in a junction region of the JTE region 15 and the SiC epitaxial layer 12.

[0150] A method for manufacturing the semiconductor device 2 according to the second embodiment of the present invention will be described below. Fig. 18 to 21 are views for explaining the method of manufacturing the semiconductor device 2 according to the second embodiment of the present invention.

[0151] First of all, as described above, Fig. As shown in Figure 8, the SiC epitaxial layer 12 of the first conductivity type is formed on a surface on one of the sides in a thickness direction of the SiC substrate 11 of the first conductivity type, in the same way as in the first embodiment. Then, the SiC region 13 of the second conductivity type is formed in a region predefined as a region in which the SiC region 13 of the second conductivity type is to be formed in the adjacent portion of the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12.

[0152] Subsequently, the ohmic contact region 14, which has a higher impurity density than the second conductivity type SiC region 13 and is of the second conductivity type, is formed in a region predefined as a region in which the ohmic contact region 14 is to be formed in the adjacent region of the surface on one of the sides in the thickness direction of the region in which the second conductivity type SiC region 13 is formed.

[0153] Fig. 18 is a sectional view showing a state of a stage in which the formation of the JTE region 15 is completed. After the ohmic contact region 14 is formed, ion implantation treatment is performed several times with an implantation mask being changed to form the JTE regions 15 in the regions adjacent to the second conductivity type SiC region 13 in the lateral direction.

[0154] In the present embodiment, the JTE regions 15 are formed at a predefined distance from the outermost edge. In other words, the JTE regions 15 are formed separately from each other such that the SiC epitaxial layer 12 is provided between the adjacent JTE regions 15. The step of forming the JTE region 15 corresponds to a step of forming a termination region.

[0155] Each of the JTE regions 15 is formed to be of the second conductivity type. Each of the JTE regions 15 is formed so that its impurity density is lower than the impurity density of the second conductivity type SiC region 13. Further, each of the JTE regions 15 is formed to have a density distribution for a gradual decrease in the lateral direction from the second conductivity type SiC region 13 toward the SiC epitaxial layer 12, that is, from an inner region of a substrate to the outermost edge. Different from the present embodiment, the JTE region 15 may be formed to have a uniform density distribution.

[0156] Moreover, just as in the first embodiment, an ion implantation treatment in the present step of forming the JTE region 15 may be performed with a single implantation energy, or it may be performed while gradually changing the implantation energy, for example, gradually changing from high energy to low energy. In the ion implantation treatment, the higher the implantation energy, the deeper the ions are implanted.

[0157] Accordingly, in the case where the ion implantation treatment is carried out with a single implantation energy, it is possible to realize the impurity density distribution having an impurity density peak at a deeper position from the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12 as the implantation energy is higher.

[0158] Fig. 19 is a sectional view showing a state of a stage in which the formation of the first conductivity type SiC region 16 is completed. After the JTE region 15 is formed, the ion implantation treatment is performed over a region where the JTE region 15 and the SiC epitaxial layer 12 are connected to each other, at least in the adjacent region of the surface on one of the sides in the thickness direction of the JTE region 15 and the SiC epitaxial layer 12.

[0159] In the present embodiment, the ion implantation treatment is performed over the area where the JTE region 15 and the SiC epitaxial layer 12 are connected to each other, in the adjacent area of ​​the surface on one of the sides in the thickness direction of the JTE region 15 and the SiC epitaxial layer 12.

[0160] As in Fig. 19, the first conductivity type SiC region 16 is thus formed in the region where the JTE region 15 and the SiC epitaxial layer 12 are connected to each other, in the adjacent region of the surface on one of the sides in the thickness direction of the JTE region 15 and the SiC epitaxial layer 12.

[0161] The first conductivity type SiC region 16 is formed to a depth of, for example, one-third (1 / 3) of the thickness of the JTE region 15 from the surface on one side in the thickness direction of the JTE region 15 and the SiC epitaxial layer 12. The step of forming the first conductivity type SiC region 16 corresponds to a step of forming a first conductivity type region.

[0162] In the present step of forming the first conductivity type SiC region 16, by regulating the implantation energy in the ion implantation treatment, it is possible to form the first conductivity type SiC region 16 down to a depth not reaching from the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12, more specifically, the surface on one of the sides in the thickness direction of the JTE region 15, to a lower portion of the JTE region 15.

[0163] As in Fig. 19, it is therefore possible to achieve a structure in which the first conductivity type SiC region 16 is present in the adjacent portion of the surface on one of the sides in the thickness direction in the region where the JTE region 15 and the SiC epitaxial layer 12 are connected to each other, and further the second conductivity type SiC region 13 is formed up to a position deeper than the first conductivity type SiC region 16 from the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12.

[0164] After each of the ion implantation treatments described above, an activation annealing treatment is performed in the same manner as in the first embodiment. Consequently, each dopant subjected to ion implantation in each step can be electrically activated. Furthermore, the activation annealing treatment makes it possible to simultaneously restore the crystallinity of an ion implantation region.

[0165] Fig. Fig. 20 is a sectional view showing a state of a stage in which the formation of the protective layer 17 is completed. After the first conductivity type SiC region 16 is formed, the protective layer 17 is formed in the same manner as in the first embodiment on the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12, as shown in Fig. 20. The protective layer 17 is realized by an insulating layer consisting of an insulating material such as SiO2 or polyimide.

[0166] Fig. Fig. 21 is a sectional view showing a state of a stage in which the formation of an opening portion 18 is completed. After the protective layer 17 has been formed, the opening portion 18 is formed in the protective layer 17 as shown in Fig. 21. The opening portion 18 is formed such that the ohmic contact portion 14 is exposed from a lower portion of the opening portion 18, as shown in Fig. 21 shown.

[0167] After the opening area 18 has been formed, the Fig. 17 is formed in the same manner as in the first embodiment so as to be electrically connected to the ohmic contact portion 14 exposed from the lower portion of the opening portion 18.

[0168] In addition, the Fig. 17 is formed on a surface on the other side in the thickness direction of the SiC substrate 11.

[0169] Through the steps described above, the semiconductor device 2 according to the second embodiment of the present invention is obtained. In the present embodiment, it is possible to obtain the semiconductor device 2 in which the first conductivity type SiC region 16 is present in the adjacent portion of the surface on one of the sides in the thickness direction in the junction region of the JTE region 15 and the SiC epitaxial layer 12, and further, the second conductivity type SiC region 13 is present in a deeper position than the first conductivity type SiC region 16 from the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12.

[0170] Accordingly, in the semiconductor device 2 according to the present embodiment, it is possible to achieve the same effects as those described in the first embodiment. In other words, it is possible to reduce a peak of an electric field intensity reaching the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12 even in the case where the electric field concentrates at the portion where the JTE region 15 and the SiC epitaxial layer 12 are connected to each other, so that the peak of the electric field intensity is generated when a relatively high reverse voltage is applied to a pn junction. Therefore, it is possible to manufacture the semiconductor device 2 with a high withstand voltage in which a stable withstand voltage can be achieved.

[0171] In the present embodiment, the description referred to the case where the semiconductor device 2 is a pn diode. However, the present invention is not limited to a pn diode, but the structure of the semiconductor device 2 according to the present embodiment can be applied to any termination structure including the JTE region 15. For example, it is possible to apply the structure according to the present embodiment to a Schottky diode using SiC, a MOSFET using SiC, an IGBT using SiC, or the like.

[0172] In other words, it is also possible to use, for the Schottky diode using SiC, the MOSFET using SiC, the IGBT using SiC, or the like having the JTE region 15, the structure in which an implantation profile for forming the JTE region 15 is selected such that the impurity density in the adjacent region of the surface on one of the sides in the thickness direction of the JTE region 15 is lower than the implantation peak value, the first conductivity type SiC region 16 is present in the adjacent region of the surface on one of the sides in the thickness direction of the junction region of the JTE region 15 and the SiC epitaxial layer 12, and the second conductivity type SiC region 13 is formed from the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12 to the position deeper than the SiC region of the first conductivity type 16 is present.

[0173] By thus using the structure according to the present embodiment, it is possible to achieve the same effects as those in the present embodiment.

[0174] Moreover, although the description in the present embodiment has been made of the structure in which the first conductivity type SiC region 16 is located only in the adjacent area of ​​the surface of the junction region of the JTE region 15 and the SiC epitaxial layer 12, another structure may also be used.

[0175] The Fig. 22 and Fig. 23 are sectional views showing another example of the first conductivity type SiC region. Fig. 22 and Fig. 23 shows a state of a stage in which the formation of first conductivity type SiC regions 31 and 32 serving as first conductivity type SiC regions is completed.

[0176] The SiC region of the first conductivity type can be prepared in the same way as in Fig. 22 may be formed over the entire adjacent area of ​​the surface on one of the sides in the thickness direction of the termination region formed by the JTE regions 15.

[0177] Furthermore, the SiC region of the first conductivity type may be formed over the entire adjacent area of ​​the surface in the Fig. 23, which contains the SiC region of the second conductivity type 13 and the ohmic contact region 14. With the Fig. 22 and Fig. 23, it is accordingly possible to achieve the same effects as those in the present embodiment.

[0178] In the first and second embodiments described above, each of the JTE regions 15 and 25 has a second conductivity-type impurity density lower than the second conductivity-type SiC region 13. Consequently, it is possible to reduce the electric field strengths in the JTE regions 15 and 25. Therefore, it is possible to more reliably suppress creeping discharge on the outside of the substrate. Accordingly, it is possible to more reliably prevent a reduction in the withstand voltage of the semiconductor device.

[0179] Furthermore, in the first and second embodiments, the JTE regions 15 and 25 are arranged such that the density of the second conductivity type impurities decreases in the lateral direction from the inner side of the substrate to the outermost edge side. Consequently, the electric field strengths of the JTE regions 15 and 25 can be gradually reduced toward the outermost edge side of the substrate.

[0180] Therefore, it is possible to more reliably suppress creeping discharge on the outside of the substrate. Accordingly, it is possible to more reliably prevent a decrease in the withstand voltage of the semiconductor device.

[0181] Each of the JTE regions 15 and 25 can be formed such that the density of the second conductivity type impurities is equal to that of the second conductivity type SiC region 13. Consequently, it is possible to form the second conductivity type SiC region 13 and the JTE regions 15 and 25 in the same step. Therefore, it is possible to easily manufacture the high-withstand voltage semiconductor device in which a stable withstand voltage can be achieved as described above.

[0182] Furthermore, in the first and second embodiments, the inner JTE regions 15 and 25 to be formed on the innermost side of the substrate in the lateral direction in the JTE regions 15 and 25 are provided adjacent to the second conductivity type SiC region 13 in the lateral direction. The present invention is not limited to the structure, but the inner JTE regions 15 and 25 may be formed separately from the second conductivity type SiC region 13 in the lateral direction.

[0183] In other words, the inner JTE regions 15 and 25 and the second conductivity type SiC region 13 can be formed separately from each other in the lateral direction. Even in this structure, it is possible to achieve the same effects as those in the first and second embodiments.

[0184] Moreover, although in the first and second embodiments, the first conductivity type is specified as n-type and the second conductivity type is specified as p-type, the first conductivity type may be specified as p-type and the second conductivity type may be specified as n-type. In this case, the SiC substrate 11, the SiC epitaxial layer 12, and the first conductivity type SiC region 16 have p-type conductivity, and the second conductivity type SiC region 13, the ohmic contact region 14, and the JTE region 15 have n-type conductivity. Explanation of reference symbols 1, 2 semiconductor device 11 Silicon carbide (SiC) substrate 12 SiC epitaxial layer 13 SiC region of the second conductivity type 14 ohmic contact area 15 JTE area 16 SiC region of the first conductivity type 17 Protective layer 18 Opening area 19 Anode electrode 20 Cathode electrode 25 JTE area 26 SiC region of the first conductivity type 31 SiC region of the first conductivity type 32 SiC region of the first conductivity type

Claims

[1] Semiconductor device comprising: - a silicon carbide substrate (11) which is of a first conductivity type; - a silicon carbide layer (12) which is provided on a surface on one of the sides in a thickness direction of the silicon carbide substrate (11) and which is of the first conductivity type; - a second conductivity type region (13) formed in a portion of an adjacent portion of a surface on one of the sides in a thickness direction of the silicon carbide layer (12) and which is of the second conductivity type; and - a plurality of junction termination regions (15, 25) which are formed in a region on an outer peripheral end side of the silicon carbide substrate (11) from the second conductivity type region (13) in the adjacent region of the surface on one of the sides in the thickness direction of the silicon carbide layer (12) and which are of the second conductivity type, - wherein the plurality of junction termination regions (15, 25) are formed adjacent to one another at least in the surface on one of the sides in the thickness direction of the silicon carbide layer (12), wherein the plurality of junction termination regions (15, 25) differ from one another in the density of impurities of the second conductivity type, - a region of the first conductivity type (16, 26) which is of the first conductivity type and has a higher or equal density of impurities of the first conductivity type as that of the silicon carbide layer (12), at least in an adjacent region of a surface on one of the sides in a thickness direction of a region in which the junction termination regions (15, 25) are connected to one another, - wherein the region of the first conductivity type (16, 26) is formed across the junction termination regions (15, 25) which are adjacent to one another, and - wherein the junction termination regions (15, 25) are arranged such that the density of impurities of the second conductivity type gradually decreases towards the outer peripheral end side of the silicon carbide substrate (11), and - wherein a side region and a bottom region of the first conductivity type region (16, 26) are in contact with the junction termination regions (15, 25) in a cross-sectional view. [2] Semiconductor device comprising: - a silicon carbide substrate (11) which is of a first conductivity type; - a silicon carbide layer (12) which is provided on a surface on one of the sides in a thickness direction of the silicon carbide substrate (11) and which is of the first conductivity type; - a second conductivity type region (13) formed in a portion of an adjacent portion of a surface on one of the sides in a thickness direction of the silicon carbide layer (12) and which is of the second conductivity type; and - a plurality of junction termination regions (15, 25) which are formed in a region on an outer peripheral end side of the silicon carbide substrate (11) from the second conductivity type region (13) in the adjacent region of the surface on one of the sides in the thickness direction of the silicon carbide layer (12) and which are of the second conductivity type, - wherein the plurality of transition termination regions (15, 25) are formed at least in the surface on one of the sides in the thickness direction of the silicon carbide layer (12) separately from each other and not in contact with each other, - a region of the first conductivity type (16, 26, 31, 32), which is of the first conductivity type and has a higher or equal density of impurities of the first conductivity type as that of the silicon carbide layer (12), is formed at least in an adjacent region of a surface on one of the sides in a thickness direction of a region provided between the junction termination regions (15, 25) which are arranged separately from one another and not in contact with one another, - wherein the region of the first conductivity type (16, 26, 31, 32) is formed across the junction termination regions (15, 25) which adjoin one another, and - wherein at least a bottom portion of the first conductivity type region (16, 26, 31, 32) is in contact with the junction termination regions (15, 25) in a cross-sectional view. [3] A semiconductor device according to claim 1 or 2, wherein one of the junction termination regions (15, 25) has a density of second conductivity type impurities equal to that of the second conductivity type region (13). [4] A semiconductor device according to claim 1 or 2, wherein each of said junction termination regions (15, 25) has a density of second conductivity type impurities which is lower than that of said second conductivity type region (13). [5] A semiconductor device according to claim 2, wherein the junction termination regions (15, 25) are arranged so that the density of second conductivity type impurities gradually decreases toward the outer peripheral end side of the silicon carbide substrate (11). [6] A semiconductor device according to claim 1 or 2, wherein the density of second conductivity type impurities in each of said junction termination regions (15, 25) on the other side in the thickness direction than the surface on one of said sides in the thickness direction has a maximum value. [7] A semiconductor device according to claim 6, wherein each of said junction termination regions (15, 25) has the density of said second conductivity type impurities in the surface on one of said sides in the thickness direction which is less than or equal to one tenth of the maximum value. [8] A semiconductor device according to any one of claims 2 to 7, wherein the first conductivity type region (16, 26, 31, 32) is formed over an entire adjacent area of ​​a surface on one of the sides in the thickness direction of the plurality of junction termination regions (15, 25). [9] A method of manufacturing a semiconductor device, comprising: - a silicon carbide layer forming step of forming a silicon carbide layer (12) having a first conductivity type over a surface on one of the sides in a thickness direction of a silicon carbide substrate (11) having the first conductivity type; - a second conductivity type region formation step of forming a second conductivity type region (13) which is of the second conductivity type in a region of an adjacent region of a surface on one of the sides in a thickness direction of the silicon carbide layer (12); - a termination region formation step of performing ion implantation treatment over a region on an outer peripheral end side of the silicon carbide substrate (11) from the second conductivity type region (13) in the adjacent region of the surface on one of the sides in the thickness direction of the silicon carbide layer (12), whereby a plurality of junction termination regions (15, 25) of the second conductivity type are formed adjacent to each other at least in the surface on one of the sides in the thickness direction of the silicon carbide layer (12), the plurality of junction termination regions (15, 25) differing from each other in the density of second conductivity type impurities; and - a first conductivity type region formation step of performing an ion implantation treatment at least in an adjacent region of a surface on one of the sides in a thickness direction of a region in which the junction termination regions (15, 25) are connected to each other, thereby forming a first conductivity type region (16, 26) which is of the first conductivity type and has a higher or equal density of first conductivity type impurities as that of the silicon carbide layer (12), - wherein in the step of forming a region of the first conductivity type, the region of the first conductivity type (16, 26) is formed across the junction termination regions (15, 25) which are adjacent to one another, - wherein in the step of forming a termination region, an ion implantation amount in the ion implantation treatment is regulated to form the junction termination regions (15, 25) such that a density of second conductivity type impurities in the junction termination regions (15, 25) gradually decreases toward the outer peripheral end side of the silicon carbide substrate (11), and - wherein a side region and a bottom region of the first conductivity type region (16, 26) are in contact with the junction termination regions (15, 25) in a cross-sectional view. [10] A method of manufacturing a semiconductor device, comprising: - a silicon carbide layer forming step of forming a silicon carbide layer (12) having a first conductivity type over a surface on one of the sides in a thickness direction of a silicon carbide substrate (11) having the first conductivity type; - a second conductivity type region formation step of forming a second conductivity type region (13) which is of the second conductivity type in a region of an adjacent region of a surface on one of the sides in a thickness direction of the silicon carbide layer (12); - a termination region formation step of performing ion implantation treatment over a region on an outer peripheral end side of the silicon carbide substrate (11) from the second conductivity type region (13) in the adjacent region of the surface on one of the sides in the thickness direction of the silicon carbide layer (12), whereby a plurality of junction termination regions (15, 25) of the second conductivity type are formed at least in the surface on one of the sides in the thickness direction of the silicon carbide layer (12) separately from each other and not in contact with each other; and - a first conductivity type region formation step of performing an ion implantation treatment at least in an adjacent region of a surface on one of the sides in a thickness direction of a region provided between the junction termination regions (15, 25) which are arranged separately from each other and not in contact with each other, thereby forming a first conductivity type region (16, 26, 31, 32) which is of the first conductivity type and has a higher or equal density of first conductivity type impurities as that of the silicon carbide layer (12), - wherein in the step of forming a region of the first conductivity type, the region of the first conductivity type (16, 26, 31, 32) is formed across the junction termination regions (15, 25) which are adjacent to one another, and - wherein at least a bottom portion of the first conductivity type region (16, 26, 31, 32) is in contact with the junction termination regions (15, 25) in a cross-sectional view. [11] The method according to claim 10, wherein in the termination region forming step, an ion implantation amount in the ion implantation treatment is regulated to form the junction termination regions (15, 25) so that a density of second conductivity type impurities in the junction termination regions (15, 25) gradually decreases toward the outer peripheral end side of the silicon carbide substrate (11). [12] The method according to claim 9 or 10, wherein in the termination region forming step, an ion implantation amount in the ion implantation treatment is regulated to form each of the junction termination regions (15, 25) so that a density of second conductivity type impurities in each of the junction termination regions (15, 25) has a maximum value on the other side in the thickness direction of the silicon carbide layer (12) from the surface on one of the sides in the thickness direction of the silicon carbide layer (12). [13] The method according to any one of claims 10 to 12, wherein in the step of forming a first conductivity type region, the first conductivity type region (16, 26, 31, 32) is formed over an entire adjacent area of ​​a surface on one of the sides in the thickness direction of the plurality of junction termination regions (15, 25).

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