Semiconductor device and method for manufacturing the semiconductor device

Abstract

Method for manufacturing a semiconductor device comprising: a first step in forming an insulating layer structure containing a gate insulating film and a gate electrode on a front side of a silicon carbide substrate; a second step (S13) of forming a front-side electrode consisting of aluminium or an aluminium alloy over the front side of the silicon carbide substrate such that it is insulated from the gate electrode by an interlayer insulating film and that it covers the entire front side of the silicon carbide substrate in an active region, wherein the active region is a region in which a current flows when the semiconductor device is in a forward state; a third step (S17) of forming a metal film consisting of nickel, a nickel alloy, copper, palladium, titanium, platinum, gold or silver, or a metal layer film consisting of two or more metal films consisting of the metal materials, on a surface of the front-end electrode, wherein the metal film or metal layer film in the third step is formed such that it covers 60% to 90% of the surface of the front-end electrode; and a fourth step (S18) of carrying out annealing in a nitrogen gas atmosphere, a nitrogen-containing mixed gas atmosphere, a vacuum atmosphere or an argon gas atmosphere after the third step.

Description

TECHNICAL AREA

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. STATE OF THE ART

[0002] An insulated-layer field-effect transistor (hereinafter referred to as a SiC MOSFET) is known as a semiconductor device using a silicon carbide (SiC) semiconductor. A typical example of the front-end element structure of the SiC MOSFET includes a MOS-Gate (metal oxide film semiconductor insulating layer) structure with a silicon dioxide (SiO2) film as the gate insulating film, a phosphor silicate glass (PSG) film as the interlayer insulating film, and an aluminum (Al) electrode as the front-end electrode, all located on the front side of a SiC substrate.

[0003] The state-of-the-art SiC MOSFET design is described using the following examples: Fig. 16 described. Fig. Figure 16 is a sectional view illustrating the state-of-the-art structure of the SiC MOSFET. As shown in Fig. As illustrated in Figure 16, the state-of-the-art SiC MOSFET contains a MOS gate structure, including a p-base region 103, an n ++ -Source area 105, a p + -Contact area 106, a gate oxide film 108 and a gate electrode 109, an interlayer insulating film 110 and an aluminum-silicon (Al-Si) electrode 113, which are located on the front side of a surface formed by depositing a - -Epitaxial layer 102 on the front side of a SiC substrate 101 obtained epitaxial substrate are provided.

[0004] The intermediate layer insulating film 110 has a source contact hole through which the n ++ -Source area 105 and the p +-Contact area 106 are selectively exposed. The Al-Si electrode 113 is designed to cover the front of the substrate in an active area and is connected to parts of the n ++ -Source area 105 and the p + The contact regions 106, which are exposed through the source contact hole of the interlayer insulating film 110, are electrically connected. Furthermore, the Al-Si electrode 113 is electrically insulated from the gate electrode 109 by the interlayer insulating film 110. Reference numeral 104 denotes a p-epitaxial layer, and reference numeral 107 denotes an n-inversion region. Reference numeral 111 denotes a titanium nitride (TiN) film, and reference numeral 112 denotes a nickel (Ni) film.

[0005] A contact metal film 114 and a backside electrode 115 are formed sequentially on the back side of the epitaxial substrate, i.e., on the back side of the SiC substrate 101. The SiC MOSFET is mounted in a package, and an aluminum contact wire (not shown) is electrically connected by ultrasonic vibration to the Al-Si electrode 113, which is the frontside electrode, and to an external terminal. A metal film is formed on the surface of a portion of the Al-Si electrode 113 to which the contact wire is connected. In this way, solder adheres firmly to a system carrier whose base material is copper (Cu) instead of the Al-Si electrode 113.

[0006] A method for forming the metal film on the surface of the front electrode has been proposed, which continuously performs a step of contacting the material to be coated with an electroless gold plating bath without gold ions and a step of contacting the material to be coated with an electroless gold plating bath containing gold ions (see, for example, the following patent document 1). Furthermore, a method has been proposed which performs deposition on a conductive part formed on the surface of a substrate to successively form a Ni film with Ni as a major component and an Au film with gold (Au) as a major component, and performs a post-processing step to remove any Ni compound adhering to the surface of the Au film (see, for example, the following patent document 2).

[0007] Another proposed method involves a deposition process that forms a first Ni-P (phosphorus) metal film on a metal film and then, using the same process, a second metal film with Au as a major component on top of the first metal film (see, for example, patent document 3 below). In this process, a first nickel plating bath is prepared to form the first metal film with a P content of 3 wt% to 6 wt%, and a second nickel plating bath is prepared to form the first metal film with a P content of 6 wt% to 9 wt%. The first nickel plating bath is used to form the first metal film as a first layer on the surface of the metal film. The second nickel plating bath is then used to form the first metal film as a second layer.

[0008] Patent document 4 discloses a method for manufacturing a semiconductor device in which a plating layer is formed on a first surface of a semiconductor substrate. An electrode is formed on the first surface of the semiconductor substrate, and another electrode is formed on the second surface. A curing resin is applied to the electrode on the second surface, and a film is bonded to the curing resin and then cured. Subsequently, a coating process is carried out on the first surface. The film and the curing resin are then removed.

[0009] Patent document 5 discloses an intermediate in the manufacture of a MOSFET, comprising a silicon carbide wafer with a substrate and a drift layer on the substrate, wherein the drift layer has a plurality of source regions formed adjacent to an upper surface thereof; a first oxide layer on the upper surface of the drift layer; a plurality of polysilicon gates above the first oxide layer, wherein the plurality of polysilicon gates has a first gate adjacent to a first of the source regions; an oxide layer above the first source region with a greater thickness than the first oxide layer; and an oxide layer above the first gate with a significantly greater thickness than the oxide layer above the first source region. PRINTING FILMS DIRECTORY PATENT DOCUMENT Patent Document 1: JP 2000-223442 A Patent Document 2: JP 2004-107734 A Patent Document 3: JP 2006-131949 A Patent document 4: US 2010 / 0 197 127 A1 Patent document 5: US 8 035 112 B1 REVELATION OF THE INVENTION PROBLEM TO BE SOLVED BY THE INVENTION

[0010] However, in prior art SiC MOSFETs, when a negative voltage is applied to the gate electrode, the gate threshold voltage Vth is significantly lower than a desired setpoint. Applying a negative voltage to the gate electrode occurs, for example, when the gate potential is set negative relative to the source potential to reliably switch off the semiconductor device. The inventors conducted a thorough investigation and found that the gate threshold voltage Vth was approximately 8 V lower than the voltage before a base temperature stress test (hereinafter referred to as the BT test) was performed. In this test, the base temperature (hereinafter referred to as the BT temperature) was 200°C, a voltage of -20 V was applied to the gate electrode, and the processing time was 10 minutes.At a reduced gate threshold voltage Vth, the SiC MOSFET does not operate as a conventional MOSFET. For example, in this case, when the positive voltage is not applied to the gate electrode, the source and drain are electrically connected (hereinafter referred to as the forward ground state). Therefore, it is difficult to achieve the reliability required, for example, for a conventional semiconductor device using a silicon (Si) semiconductor.

[0011] The invention was made in view of the above-mentioned problems in the prior art, and one object of the invention is to provide a semiconductor device using a silicon carbide semiconductor and a method for manufacturing the semiconductor device which can suppress a drop in the gate threshold voltage. MEANS TO SOLVENT THE PROBLEM

[0012] To solve the aforementioned problems and fulfill the object of the invention, a method for fabricating a semiconductor device and a semiconductor device having the features of the respective independent claims are provided. The dependent claims relate to particular embodiments of the invention. Aspects and configurations that are helpful for understanding the invention are explained below. A method for fabricating a semiconductor device has the following characteristics. First, a first step of forming an insulating layer structure containing a gate insulating film and a gate electrode is carried out on a front face of a silicon carbide substrate.Then, a second step is performed in which a front electrode, made of aluminum or an aluminum alloy, is formed over the front of the silicon carbide substrate such that it is insulated from the gate electrode by an interlayer insulating film. A third step is performed in which a metal film, or a metal layer film consisting of two or more metal films made of these materials, consisting of nickel, a nickel alloy, copper, palladium, titanium, platinum, gold, or silver, is formed on the surface of the front electrode. A fourth step is then performed in which annealing is carried out in a nitrogen gas atmosphere, a nitrogen-containing mixed gas atmosphere, a vacuum atmosphere, or an argon gas atmosphere following the third step.

[0013] The inventive method for manufacturing the semiconductor device can also include, after the second step and before the third step, a fifth step of carrying out annealing in a nitrogen gas atmosphere, a nitrogen-containing mixed gas atmosphere, a vacuum atmosphere or an argon gas atmosphere.

[0014] In the inventive method for manufacturing the semiconductor device, the annealing temperature in the fifth step can be higher than the annealing temperature in the fourth step.

[0015] In the inventive method for manufacturing the semiconductor device, the annealing temperature in the fifth step can be higher than or equal to 350°C.

[0016] In the inventive method for manufacturing the semiconductor device, the annealing temperature in the fourth step can be higher than or equal to 150°C and lower than or equal to 450°C.

[0017] In the inventive method for manufacturing the semiconductor device, the annealing temperature in the fourth step can be higher than or equal to 300°C and lower than or equal to 420°C.

[0018] In the inventive method for manufacturing the semiconductor device, in the third step the metal film or the metal layer film can be formed such that it covers 60% to 90% of the surface of the front electrode.

[0019] A semiconductor device has the following characteristics. An insulating layer structure containing a gate insulating film and a gate electrode is formed on the front face of a silicon carbide substrate. A front-side electrode is provided over the front face of the silicon carbide substrate such that it is insulated from the gate electrode by an intermediate insulating film. The front-side electrode is made of aluminum or an aluminum alloy. A metal film consisting of nickel, a nickel alloy, copper, palladium, titanium, platinum, gold, or silver, or a metal layer film consisting of two or more metal films made of these materials, is provided on a surface of the front-side electrode such that it covers 60% or more of the surface of the front-side electrode.

[0020] In the semiconductor device according to the invention, the metal film or metal layer film can cover 90% or more of the surface of the front electrode. IMPACT OF THE INVENTION

[0021] According to the semiconductor device and the method for manufacturing the semiconductor device of the invention, the metal film is formed on the surface of the front electrode and annealing is carried out, for example, in a nitrogen atmosphere. Therefore, it is possible to suppress a drop in the gate threshold voltage when a negative voltage is applied to a gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a sectional view illustrating the structure of a semiconductor device according to embodiment 1. Fig. 2 is a flowchart which clearly illustrates a method according to embodiment 1 for manufacturing the semiconductor device; Fig. Figure 3 is a diagram illustrating a gate threshold voltage of the semiconductor device according to Example 1; Fig. Figure 4 is a diagram illustrating the relationship between the thickness of a first metal film and a decrease in the gate threshold voltage in a semiconductor device according to Example 2; Fig. Table 5 illustrates the conditions of a currentless NiP deposition process according to Example 3; Fig. Figure 6 is a diagram illustrating the relationship between a deposition pretreatment for a first metal film and a decrease in the gate threshold voltage in a semiconductor device according to Example 3; Fig. Table 7 illustrates the conditions of a currentless Cu deposition process according to Example 4; Fig. Figure 8 is a diagram illustrating the relationship between a material forming a first metal film and a gate threshold voltage in a semiconductor device according to Example 4; Fig. Figure 9 is a diagram illustrating the relationship between the area ratio of a first metal film and a decrease in the gate threshold voltage in semiconductor devices according to Examples 5 and 9; Fig. Figure 10 is a top view illustrating the arrangement of the first metal film in the semiconductor device according to Example 5; Fig. Figure 11 is a diagram illustrating the relationship between a tempering atmosphere and a decrease in the gate threshold voltage in a semiconductor device according to Example 6; Fig. Figure 12 is a diagram illustrating the relationship between annealing temperature and annealing time and a decrease in gate threshold voltage in a semiconductor device according to Example 7-1; Fig. Figure 13 is a diagram illustrating the relationship between annealing temperature and annealing time and a decrease in gate threshold voltage in a semiconductor device according to Example 7-2; Fig. 14 is a flowchart which clearly illustrates a method according to embodiment 2 for manufacturing the semiconductor device; Fig. Figure 15 is a graph illustrating a decrease in the gate threshold voltage of a semiconductor device according to Example 8; and Fig. Figure 16 is a sectional view illustrating the structure of a state-of-the-art SiC MOSFET. METHODS OF IMPLEMENTATION OF THE INVENTION

[0022] Preferred embodiments of a semiconductor device and a method according to the invention for manufacturing the semiconductor device are described in detail below with reference to the accompanying drawings. In the description and the accompanying drawings, an electron or a hole represents a majority carrier in the layers or regions marked with an appended "n" or "p". Furthermore, symbols "+" and "-" added to "n" or "p" indicate that the defect density is higher and lower, respectively, than that of the layer or region without the symbols. In the description of the following embodiments and the accompanying drawings, identical components are designated with the same reference numerals, and their descriptions are not repeated. (Version 1)

[0023] The construction of a semiconductor device according to embodiment 1 will now be described. Fig. Figure 1 is a sectional view illustrating the structure of the semiconductor device according to embodiment 1. As shown in Fig. As illustrated in 1, the semiconductor device according to embodiment 1 is a SiC MOSFET, which is produced using a process by depositing an n - -Epitaxial layer 2, which is an n - A drift layer will be produced on the front face of a SiC substrate 1, which will be an n-drain region, in an epitaxial substrate obtained by means of a p-base region 3. A p-base region 3 is selectively produced in a surface layer of the epitaxial substrate near the front face (n - -Epitaxial layer 2). In addition, a p-epitaxial layer 4 is deposited on the front of the epitaxial substrate such that it is separated from a portion of the n - -Epitaxial layer 2, which lies between adjacent p-basal regions 3, extends to the p-basal region 3.

[0024] A n ++ -Source area 5, a p+ A contact region 6 and an n-inversion region 7 are selectively provided in the p-epitaxial layer 4. The n ++ -Source area 5 and the p + The contact region 6 is located in a part of the p-epitaxial layer 4 that is opposite the p-basal region 3, extends in a depth direction through the p-epitaxial layer 4 and reaches to the p-basal region 3. The n-inversion region 7 is located in a part of the p-epitaxial layer 4 that is not opposite the p-basal region 3, extends in a depth direction through the p-epitaxial layer 4 and reaches to a part of the n - -Epitaxial layer 2, which lies between adjacent p-base regions 3. Furthermore, the n-inversion region 7 is on the side of the n. ++ -Source area 5, which belongs to the p + -Contact area 6 is arranged in the opposite direction, so that it is from n ++ -Source area 5 is separated.

[0025] A gate electrode 9, with an intervening gate insulating film 8, is positioned on the surface of a portion of the p-epitaxial layer 4, which lies between the n ++ The -source region 5 and the n-inversion region 7 are designed to extend to the surface of the n-inversion region 7. The gate insulating film 8 consists, for example, of silicon dioxide (SiO2) or nitrous oxide (N2O). The gate electrode 9 consists, for example, of polysilicon (poly-Si). The p-base region 3, the p-epitaxial layer 4, and the n- ++ -Source area 5, the p + The MOS gate structure, comprising a contact area 6, an n-inversion region 7, a gate insulating film 8, and a gate electrode 9, is provided on the front side of the epitaxial substrate. The gate electrode 9 is covered with an interlayer insulating film 10, such as a PSG film. The interlayer insulating film 10 has a source contact hole through which the n ++ -Source area 5 and the p+ -Contact area 6 are selectively exposed.

[0026] A titanium nitride (TiN) film 11 is provided on the surface of the interlayer insulating film 10. The end of the TiN film 11 extends to the surface of the n ++ -Source region 5, which is exposed through the source contact hole of the interlayer insulating film 10. A nickel (Ni) film 12 is on the surface of the n ++ -Source area 5 and the p +A contact area 6, exposed through the source contact hole of the interlayer insulating film 10, is provided. The end of the Ni film 12 extends onto the surface of a portion of the TiN film 11 covered by the interlayer insulating film 10. A front-side electrode 13, which is a source electrode, is provided on the surface of the TiN film 11 and the Ni film 12 such that it covers the entire front of the epitaxial substrate in an active region. The active region is a region in which a current flows when the semiconductor device is in a forward-biased state.

[0027] The front electrode 13 is designed to be buried in the source contact hole of the interlayer insulating film 10 and to be electrically connected to the n via the Ni film 12. ++ -Source area 5 and the p +-Contact area 6 is connected. In the active region, a gate connection spot (not shown) is selectively provided on the front face of the epitaxial substrate, and the front face electrode 13 is arranged such that it is separated from the gate connection spot and substantially covers a portion of the front face of the epitaxial substrate in the active region that is distinct from the gate connection spot. The front face electrode 13 is made, for example, of aluminum (Al) or an Al alloy such as aluminum containing 1% silicon (Al-1%Si) or aluminum containing 0.5% copper (Cu) (Al-0.5%Cu).

[0028] A first metal film 21 is provided on 10% or more of the surface of the front electrode 13. That is, the first metal film 21 covers 10% or more of the surface (hereinafter simply referred to as the surface) S1 of the side of the front electrode 13 opposite the SiC substrate. Therefore, it is possible to suppress a drop in a gate threshold voltage Vth and to maintain a state (hereinafter referred to as a blocking ground state) in which the source and drain are not connected when a positive voltage is applied to the gate electrode 9.As the ratio of the surface area (i.e., the contact area of ​​the first metal film 21 with the front electrode 13) S2 of the first metal film 21 to the surface area S1 of the front electrode 13 (= S2 / S1; hereinafter referred to as the area ratio of the first metal film 21) increases, the effect of suppressing a drop in the gate threshold voltage Vth is improved, which is preferable.

[0029] Specifically, the area ratio of the first metal film 21 is preferably, for example, greater than or equal to 60% and less than or equal to 90%. If the area ratio of the first metal film 21 is greater than or equal to 60%, it is possible to achieve a semiconductor device whose performance is within the permissible range and which, as a product, exhibits no functional problems. If the area ratio of the first metal film 21 is greater than 90%, a problem arises insofar as the first metal film 21 comes into contact with the gate terminal patch. However, if the area ratio of the first metal film 21 is less than or equal to 90%, the first metal film 21 does not come into contact with the gate terminal patch. Therefore, it is possible to prevent a short circuit between the gate terminal patch and the front electrode 13 via the first metal film 21.

[0030] The first metal film 21 can be a metal coating film formed by an electroplating process or an electroless deposition process, or a metal film formed by a sputtering process or an evaporation process. Specifically, the first metal film 21 can be, for example, a Ni film, a Ni alloy film (e.g., nickel-phosphorus (NiP) or nickel-boron (NiB)), a Cu film, a palladium (Pd) film, a titanium (Ti) film, a platinum (Pt) film, a gold (Au) film, a silver (Ag) film, or a metal layer film consisting of two or more of the metal films.

[0031] Preferably, the first metal film 21 is a nickel film, a nickel alloy film, a copper film, a titanium film, or a layered metal film consisting of two or more of these metal films. For example, the reason is as follows: When the semiconductor device is mounted in a package, a system carrier (not shown), whose base material is copper, is soldered to the first metal film 21. In this case, the first metal film 21 seeps into the molten solder (solder seepage), increasing its thickness or allowing the solder to come into contact with the front electrode 13. Consequently, a problem arises in that the adhesion of the first metal film 21 to the copper-based system carrier is reduced. Therefore, considering the occurrence of solder seepage, it is preferable to set the thickness of the first metal film 21 to a large value of approximately 2 µm or more.If the first metal film 21 is formed in this way with a large thickness, it is possible to form the first metal film 21 in a short time or at low cost. A second metal film 22, such as a gold (Au) film, can be formed on the surface of the first metal film 21.

[0032] A portion of the front face of the epitaxial substrate, distinct from the gate terminal patch and the first metal film 21 (or the second metal film 22 if the second metal film 22 is present), specifically a region between the gate terminal patch and the first metal film 21, or a breakdown voltage structure portion (not shown), is protected by a passivation film such as a polyimide film. The breakdown voltage structure portion is a region surrounding the active region that weakens the electric field of the active region and maintains a breakdown voltage. A contact metal film 14, obtained by successive layering of, for example, a Ni film and a Ti film, is placed on the back face of the epitaxial substrate, i.e., the back face of the SiC substrate 1, and a conductive connection is formed between the contact metal film 14 and the SiC substrate 1, which will be an n-drain region.A backside electrode 15 obtained by successive layering of, for example, a Ti film, a Ni film and an Au film is provided on the surface of the contact metal film 14.

[0033] An example is now described in which the first metal film 21 is formed by a deposition process in a method according to embodiment 1 for the manufacture of the semiconductor device. Fig. Figure 2 is a flowchart that clearly illustrates the procedure according to embodiment 1 for manufacturing the semiconductor device.

[0034] First, in the MOS gate structure or the SiC MOSFET, in which the films from the interlayer insulating film 10 to the contact metal film 14 are formed, an Al layer is patterned by photolithography in a predefined shape to form the front electrode 13 and the gate terminal spot (step S13). Then, the passivation film (not shown) is deposited (formed) on the front of the epitaxial substrate like a polyimide film (step S14). A source terminal spot contact hole, through which the surface of the front electrode 13 is selectively exposed, and a gate terminal spot contact hole, through which the gate terminal spot is exposed, are formed.For example, the surface area S1 of the front electrode 13, corresponding to the area ratio of the first metal film 21 (the ratio (= S2 / S1) of the surface S2 of the first metal film 21 to the surface S1 of the front electrode 13), which is formed in the subsequent process, is exposed through the source-connection spot contact hole. Then, a heat treatment (curing) to improve the strength of the passivation film is carried out at a temperature of, for example, 350°C for 1 hour (step S15).

[0035] Then, a Ti film, a Ni film, and an Au film are successively formed, for example, by a sputtering or vapor deposition process, on the surface of the contact metal film 14 to form the back electrode 15 (step S16). Then, for example, a Ni coating film is formed as the first metal film 21 on the surface of a portion of the front electrode 13 exposed through the source terminal spot contact hole of the passivation film by an electroless deposition process (step S17). Once the first metal film 21 has been formed by the electroless deposition process, a deposition pretreatment can be performed by a conventional method between steps S16 and S17 to improve the adhesion between the front electrode 13 and the first metal film 21.A process for forming the first metal film 21 is not limited to electroless deposition; the first metal film 21 can also be formed by electroplating, sputtering, or vapor deposition. The source terminal spot contact hole of the passivation film can be formed prior to step S17.

[0036] Tempering is then carried out, for example, in a nitrogen (N₂) gas atmosphere, a mixed gas atmosphere containing N₂ (for example, N₂ and argon (Ar) gas), a vacuum atmosphere, or an Ar gas atmosphere (step S18). Therefore, it is possible to suppress a decrease in the gate threshold voltage Vth when a negative voltage is applied to the gate electrode 9. The tempering temperature in step S18 can be low enough that the structure of the first metal film 21 is not altered. For example, the tempering temperature can be higher than or equal to 150°C and lower than or equal to 450°C. The tempering temperature in step S18 varies depending on the BT test conditions and is preferably higher than or equal to 300°C and lower than or equal to 420°C. The tempering time in step S18 can be, for example, longer than or equal to 0.5 hours and shorter than or equal to 6 hours.The annealing time in step S18 varies depending on the BT test conditions and is preferably longer than or equal to 1 hour and shorter than or equal to 3 hours. Setting the annealing temperature and time within the aforementioned ranges can improve the effectiveness of suppressing a drop in the gate threshold voltage Vth. The [missing information] Fig. The illustrated SiC MOSFET is completed through the processes mentioned above.

[0037] The process in steps S17 and S18 is performed on a standard SiC chip, which has the structure formed by the process in steps S13 to S16. In the standard SiC chip, the exposed area of ​​a portion of the front electrode 13, exposed through the source-terminal spot contact hole of the passivation film, comprises approximately 46% of the surface area S1 of the front electrode 13. Therefore, prior to step S17, the opening width of the source-terminal spot contact hole is adjusted to increase or decrease the exposed area of ​​the front electrode 13 in order to achieve the desired area ratio of the first metal film 21.Specifically, an insulating film can be selectively provided on the front electrode 13 to reduce the exposure area of ​​the front electrode 13, or the passivation film can be structured to increase the opening width of the source terminal spot contact hole, thereby increasing the exposure area of ​​the front electrode 13. (Example 1)

[0038] Now the gate threshold voltage Vth of a semiconductor device is described according to Example 1. Fig. Figure 3 is a diagram illustrating the gate threshold voltage of the semiconductor device according to Example 1. A SiC MOSFET was fabricated using the method according to embodiment 1 for the semiconductor device (hereinafter referred to as Example 1). In Example 1, in step S17, a NiP coating film is formed as the first metal film 21 by a currentless NiP deposition process and is annealed in an N2 atmosphere in step S18 (deposition and annealing are performed). The area ratio (= S2 / S1) of the first metal film 21 was 46%.

[0039] As a comparative example, a SiC MOSFET was fabricated without annealing after the formation of a first metal film (hereinafter referred to as Comparative Example 1). In Comparative Example 1, steps S13 to S17 of the method according to embodiment 1 are performed to fabricate the semiconductor device similarly to Example 1, and step S18 is omitted (deposition is performed, and annealing is not performed). Furthermore, a SiC MOSFET was fabricated without a first metal film (hereinafter referred to as Comparative Example 2). In Comparative Example 2, steps S13 to S16 of the method according to embodiment 1 are performed to fabricate the semiconductor device, and steps S17 and S18 are omitted (deposition and annealing are not performed).

[0040] In Example 1 and in comparison examples 1 and 2, the gate threshold voltage Vth was measured after a negative voltage was applied to the gate electrode using a base temperature stress test (BT test). The measurement results are shown in Fig. Figure 3 illustrates this. The BT test was performed under the following conditions: a base temperature (hereinafter referred to as the BT temperature) of 200°C; a voltage of -20 V was applied to the gate electrode; and a processing time of 10 minutes. The gate threshold voltage Vth was measured under the following conditions: room temperature; a drain current Id of 25 mA; and a voltage Vds of 10 V between the drain and the source. Fig. Figure 3 illustrates the gate threshold voltage Vth before the first metal film is formed in Example 1 and Comparative Example 1 (that is, the state in Comparative Example 2; hereinafter referred to as the initial state), the gate threshold voltage Vth after the first metal film has been formed in Example 1 and Comparative Example 1 (hereinafter referred to as "After Deposition"), and the gate threshold voltage Vth after annealing in Example 1 and after the negative voltage has been applied to the gate electrode in Example 1 and Comparative Examples 1 and 2 (after the BT test).

[0041] The in Fig. The results illustrated in Figure 3 showed that in Comparison Examples 1 and 2, after the negative voltage was applied to the gate electrode, the gate threshold voltage Vth decreased considerably, to -4 V or less, and the semiconductor device was in the forward ground state. In contrast, the results showed that in Example 1, after the negative voltage was applied to the gate electrode, the decrease in the gate threshold voltage Vth was smaller than in Comparison Examples 1 and 2, and the reverse ground state was maintained. Therefore, the results showed that if steps S17 and S18 were performed as in Example 1, it was possible to suppress the decrease in the gate threshold voltage Vth after the negative voltage was applied.Although not shown in the drawings, the inventors found that when steps S17 and S18 were carried out on the SiC MOSFET according to the prior art, the same effect as described above was achieved. (Example 2)

[0042] The following is the relationship between the thickness of a first metal film 21 and a decrease ΔVth of the gate threshold voltage. Fig. Figure 4 is a diagram illustrating the relationship between the thickness of a first metal film and the decrease in the gate threshold voltage in a semiconductor device according to Example 2. A plurality of first metal films 21 with SiC MOSFETs of varying thicknesses were fabricated using the method according to embodiment 1 for the semiconductor device (hereinafter referred to as Example 2). Specifically, three samples of first metal films 21 with thicknesses of 1 µm, 4.5 µm, and 10 µm were prepared as Example 2. Example 2 is identical to Example 1 except for the thickness of the first metal film 21.

[0043] In Example 2, a difference (hereinafter referred to as the drop in gate threshold voltage) ΔVth between the gate threshold voltage Vth before the BT test (before the negative voltage was applied to the gate electrode) and the gate threshold voltage Vth after the BT test (after the negative voltage was applied to the gate electrode) was calculated. The calculation result is shown in Fig. Figure 4 illustrates this. The BT test conditions and the measurement conditions of the gate threshold voltage Vth are the same as those in Example 1. Fig. Figure 4 illustrates, for comparison, a decrease ΔVth of the gate threshold voltage in comparison example 2 (deposition and annealing were not performed).

[0044] The in Fig. The results illustrated in Figure 4 showed that in Example 2, the decay ΔVth of the gate threshold voltage was essentially constant regardless of the thickness of the first metal film 21 and was smaller than the decay ΔVth of the gate threshold voltage in Comparative Example 2. Therefore, the results showed that a change (a decay) of the gate threshold voltage Vth of the semiconductor device according to the invention did not depend on the thickness of the first metal film 21. (Example 3)

[0045] Now the relationship between the deposition pretreatment and a decrease ΔVth of the gate threshold voltage is described. Fig. Table 5 illustrates the conditions of a currentless NiP deposition process according to Example 3. Fig. Figure 6 is a diagram illustrating the relationship between the deposition pretreatment and the decrease in the gate threshold voltage in a first metal film of a semiconductor device according to Example 3. A plurality of SiC MOSFETs were fabricated using the method of embodiment 1 for the semiconductor device, in which part of the deposition pretreatment process was omitted (hereinafter referred to as Example 3). Specifically, as Example 3, three test specimens were produced using a method in which, after the deposition pretreatment ended at different times, step S17 was not performed and step S18 was performed.

[0046] The time at which the deposition pretreatment ends will be described in detail when the electroless NiP deposition process, which includes the deposition pretreatment, is described. First, steps S13 to S16 were performed similarly to Example 1. Then, a degreasing process was carried out at a temperature of 50°C for 5 minutes to remove any greasy contaminants or foreign matter adhering to the surface of the front electrode 13, and the front electrode 13 was cleaned. Next, an etching process with an acid solution was carried out at room temperature (RT: for example, 20°C) for 2.5 minutes to remove a natural oxide film on the surface of the front electrode 13. For the first specimen, the deposition pretreatment ended at this stage (which in Fig. 5 is represented by an arrow A and in Fig. 6 is represented by “After Etching (A)” and was carried out in step S18, annealing. In this way, all processes ended.

[0047] Then, an acid cleaning (a residue removal process) was performed with a nitric acid (HNO3) solution at room temperature for 40 seconds to remove residues generated by the etching process. For the second sample, the deposition pretreatment ended at this stage (which in Fig. 5 is represented by an arrow B and in Fig. 6 is represented by “After acid cleaning (B)”) and was carried out in step S18, annealing. In this way, all processes ended. Then, a zincate treatment was carried out at room temperature for 40 seconds to replace Al in the surface of the front electrode 13 with zinc (Zn), forming a Zn film with a desired grain size on the surface of the front electrode 13. For the third specimen, all deposition pretreatments up to this stage (which is represented in Fig. 5 is represented by an arrow C and in Fig. 6 is represented by “After zincate treatment (C)” and was carried out in step S18, annealing. All processes end in this way.

[0048] Then, an electroless NiP deposition process was carried out at a temperature of 80°C for 27 minutes (step S17) to replace the Zn film with Ni, and Ni was continuously deposited on the surface of the front electrode 13, forming a NiP coating film as the first metal film 21. The second metal film 22 was then formed on the surface of the first metal film 21 by an electroless Au deposition process. As a comparative example, all processes up to this stage (which is described in Fig. 5 is represented by an arrow D and in Fig. 6 (represented by “After Deposition (D)”) was carried out and annealed in step S18 to produce a fourth specimen. Then, a decrease ΔVth of the gate threshold voltage in the four specimens was calculated. The calculation results are shown in Fig. Figure 6 illustrates this. The conditions in step S18, the BT test conditions, and the measurement conditions of the gate threshold voltage Vth are the same as those in Example 1. Fig. Figure 6 illustrates a decrease ΔVth of the gate threshold voltage in comparison example 2 (deposition and annealing were not performed).

[0049] The in Fig. The results illustrated in Figure 6 showed that the effect of suppressing a drop in the gate threshold voltage Vth in the specimen after deposition (D) was essentially the same as that in Example 1. The results showed that in the specimen after etching (A), the specimen after acid cleaning (B), and the specimen after zincate treatment (C), the drop ΔVth in the gate threshold voltage was as large as the drop ΔVth in the gate threshold voltage in Comparative Example 2, and the same effect as in the specimen after deposition (D) was not achieved. Therefore, the results showed that a change in the gate threshold voltage Vth of the semiconductor device according to the invention did not depend on the deposition pretreatment. (Example 4)

[0050] Now the relationship between the material forming the first metal film 21 and the decrease ΔVth of the gate threshold voltage is described. Fig. Figure 7 is a table illustrating the conditions of a currentless Cu deposition process according to Example 4. Fig. Figure 8 is a diagram illustrating the material forming the first metal film and the gate threshold voltage in a semiconductor device according to Example 4. A SiC MOSFET in which a Cu coating film was formed as the first metal film 21 was fabricated using the method according to embodiment 1 for the production of the semiconductor device (hereinafter referred to as Example 4).

[0051] Specifically, the process from step S13 to step S16 was first carried out, similar to Example 1. Then, similar to Example 3, cleaning, etching, acid cleaning, and a zincate treatment (hereinafter referred to as a first zincate treatment) were performed as a deposition pretreatment. In this case, etching was performed at a temperature of 50°C for 50 seconds, and acid cleaning was performed at a temperature of 21°C for 30 seconds. Furthermore, acid cleaning was repeated with a nitric acid solution at a temperature of 21°C for 60 seconds to remove a zinc film formed on the surface of the front electrode 13. Then, a second zincate treatment was performed at a temperature of 21°C for 45 seconds to re-form a zinc film on the surface of the front electrode 13.

[0052] Then, a currentless copper deposition process was performed at a temperature of 60°C for 60 minutes (step S17) to replace the zinc film with copper, and copper was continuously deposited onto the surface of the front electrode 13, forming a copper coating film as the first metal film 21. Then, in step S18, annealing was performed to fabricate Example 4. The gate threshold voltage Vth of Example 4 was then measured before and after the BT test (before and after the negative voltage was applied to the gate electrode). The measurement results are shown in Fig. Figure 8 illustrates this. The conditions of step S18, the BT test conditions, and the measurement conditions of the gate threshold voltage Vth are the same as those in Example 1. For comparison, Figure 8 illustrates this. Fig. 8 the gate threshold voltages Vth of Example 3 after deposition (D), in which the NiP coating film is formed as the first metal film 21, before and after the BT test and the gate threshold voltages Vth of Comparative Example 2 (deposition and annealing are not carried out) before and after the BT test.

[0053] The in Fig. The results illustrated in Figure 8 showed that in Example 4, the decrease ΔVth of the gate threshold voltage was smaller than that in Comparative Example 2, and the effect of suppressing a decrease in the gate threshold voltage Vth was achieved, similar to Example 3. Therefore, the results showed that a change in the gate threshold voltage Vth of the semiconductor device according to the invention did not depend on the material forming the first metal film 21. (Example 5)

[0054] Now the relationship between the area ratio of a first metal film 21 and a decrease ΔVth of the gate threshold voltage is described. Fig. Figure 9 is a diagram illustrating the relationship between the area ratio of the first metal film 21 and a decrease in the gate threshold voltage in the semiconductor devices according to Examples 5 and 9. Fig. Figure 10 is a top view illustrating the arrangement of the first metal film of the semiconductor device according to Example 5. A plurality of SiC MOSFETs, in which the area ratio of the first metal film 21 was greater than or equal to 10%, were manufactured using the method according to embodiment 1 for the semiconductor device (hereinafter referred to as Example 5). Specifically, as Example 5, test specimens containing the first metal films 21 with area ratios of 10%, 20%, 30%, 46%, 74%, and 90% were produced.

[0055] Now, a procedure for manufacturing the test pieces is described in detail. A large number of SiC chips with the structure formed by the process from step S13 to step S16 were produced. As in Fig. As illustrated in Figure 10(b), in the SiC chip, the exposed area of ​​a portion of a front-side electrode 13, which is exposed by a source-terminal spot contact hole 23a of a passivation film 23, comprises 46% of the surface area S1 of the front-side electrode 13. Reference numeral 24 denotes a gate-terminal spot, reference numeral 31 denotes an active region, and reference numeral 32 denotes a breakdown voltage structure portion. Therefore, in each SiC chip, the aperture of the source-terminal spot contact hole 23a was modified to obtain the aforementioned area ratio of the first metal film 21.

[0056] What was special, for example, was how in Fig. Figure 10(a) illustrates that if the area ratio of the first metal film 21 was less than 46%, for example, if the area ratio was 20%, an insulating film 25 was selectively provided on the portion of the front electrode 13 exposed by the source-terminal spot contact hole 23a, in order to reduce the exposed area of ​​the front electrode 13. As shown in the Fig. 10(c) and Fig. As illustrated in Figure 10(d), the passivation film 23 was structured, if the area ratio of the first metal film 21 was greater than 46%, for example, if the area ratio was 74% or 90%, such that the opening width of the source terminal spot contact hole 23a was increased. In Example 5, which was fabricated in this way, a reduction ΔVth of the gate threshold voltage was calculated. The calculation result is shown in Fig. Figure 9 illustrates this. The conditions of steps S17 and S18, the BT test conditions, and the measurement conditions of the gate threshold voltage Vth are the same as those in Example 1. For comparison, Figure 9 illustrates this. Fig. 9 the decrease ΔVth of the gate threshold voltage in comparative example 2 (deposition and annealing are not performed) when the area ratio of the first metal film is 21 0%.

[0057] The in Fig. The results illustrated in Figure 9 showed that the gate threshold voltage drop ΔVth in Example 5 was smaller than the gate threshold voltage drop in Comparative Example 2, and that it was possible to decrease the gate threshold voltage drop ΔVth with increasing area ratio of the first metal film 21. For example, if the area ratio of the first metal film 21 is x and the gate threshold voltage drop ΔVth is y, the relationship between the area ratio of the first metal film 21 and the gate threshold voltage drop ΔVth in Example 5 is given by the following expression (1) (a Fig. 9 (curve designated by reference numeral 41). y=1.25⋅In(x)−0.107 (Example 6)

[0058] Now the relationship between a tempering atmosphere in step S18 and a decrease ΔVth of the gate threshold voltage is described. Fig. Figure 11 is a diagram illustrating the relationship between the annealing atmosphere and a decrease in the gate threshold voltage in a semiconductor device according to Example 6. A plurality of SiC MOSFETs were fabricated using the method according to embodiment 1 for the semiconductor device, while the annealing atmosphere was varied in different ways in step S18 (hereinafter referred to as Example 6). Specifically, as Example 6, three test specimens were prepared, which were each annealed in an N2 gas atmosphere, a vacuum atmosphere, and an Ar atmosphere in step S18.

[0059] The structure of the sample tempered in the N2 gas atmosphere is the same as that in Example 1. Apart from the tempering atmosphere in step S18, the sample tempered in the vacuum atmosphere or the Ar atmosphere has the same structure as that in Example 1. Then, the decay ΔVth of the gate threshold voltage was calculated for each of the samples. The calculation results are shown in Fig. 11 illustrated. For comparison, illustrated Fig. 11 the decrease ΔVth of the gate threshold voltage of the sample annealed in a hydrogen (H2) atmosphere in step S18 (hereinafter referred to as comparison example 3) and the decrease ΔVth of the gate threshold voltage in comparison example 1 (deposition is carried out and annealing is not carried out).

[0060] The in Fig. The illustrated results showed that the drop ΔVth of the gate threshold voltage in Comparison Example 3 was as large as the drop ΔVth of the gate threshold voltage in Comparison Example 1. This showed that the effect of suppressing a drop in the gate threshold voltage Vth was not achieved in the H₂ atmosphere. In contrast, the results showed that the drop ΔVth of the gate threshold voltage in Example 6 was smaller than the drop ΔVth of the gate threshold voltage in Comparison Example 1. This showed that the effect of suppressing a drop in the gate threshold voltage Vth was achieved in the N₂ gas atmosphere, the vacuum atmosphere, and the Ar atmosphere.

[0061] The results showed that the sample tempered in the N₂ gas atmosphere exhibited the smallest decrease ΔVth of the gate threshold voltage. Therefore, tempering in an N₂ gas atmosphere or a mixed gas atmosphere containing N₂ is preferable in step S18. The decrease ΔVth of the gate threshold voltage in the sample tempered in the vacuum atmosphere or the Ar gas atmosphere was greater than the decrease ΔVth of the gate threshold voltage in the sample tempered in the N₂ gas atmosphere. However, tempering in a vacuum atmosphere allows for a reduction in the amount of impurities in a furnace and improves productivity compared to tempering in an Ar gas atmosphere. Therefore, tempering in step S18 can be performed in either a vacuum or an Ar gas atmosphere. (Example 7)

[0062] Now the relationship between annealing temperature and annealing time is described in step S18 and a decrease ΔVth of the gate threshold voltage. Fig. Figure 12 is a diagram illustrating the annealing temperature and time and a decrease in the gate threshold voltage in a semiconductor device according to Example 7-1. Fig. Figure 13 is a diagram illustrating the annealing temperature and time and a decrease in the gate threshold voltage in a semiconductor device according to Example 7-2. A plurality of SiC MOSFETs were fabricated using the method according to embodiment 1 for the semiconductor device, while the annealing temperature and time were varied in step S18 in different ways (hereinafter referred to as Example 7).

[0063] Specifically, as Example 7-1, a large number of test specimens were produced in step S18 at an annealing temperature of 280°C to 450°C for an annealing time of 0.5 hours to 6 hours, and the decay ΔVth of the gate threshold voltage was calculated for each specimen. The BT test conditions in Example 7-1 are the same as those in Example 1. The calculation results are presented in Fig. Figure 12 illustrates this. Furthermore, as Example 7-2, a large number of test specimens were produced in step S18 at an annealing temperature of 280°C to 330°C for an annealing time of 0.5 hours to 6 hours, and the decay ΔVth of the gate threshold voltage was calculated for each specimen. The BT test in Example 7-2 was performed under the following conditions: a BT temperature of 150°C; a voltage of -10 V applied to a gate electrode; and a processing time of 10 minutes. The calculation results are shown in Fig. 13 illustrated.

[0064] In the empty fields in the Fig. 12 and Fig. 13. The decay ΔVth of the gate threshold voltage is not calculated, since it is clear that the decay ΔVth of the gate threshold voltage, which is essentially the same as that for other combinations of annealing temperature and annealing time in the Fig. 12 and Fig. 13 is obtained based on the decrease ΔVth of the gate threshold voltage at the various combinations of annealing temperature and annealing time. Examples 7-1 and 7-2 have the same structure as Example 1, except for the annealing temperature and annealing time in step S18.

[0065] The in the Fig. 12 and Fig. The 13 illustrated results showed that, compared to the prior art, it was possible to suppress a drop in the gate threshold voltage Vth when the annealing temperature was higher than or equal to 150°C and lower than or equal to 450°C, and the annealing time was longer than or equal to 0.5 hours and shorter than or equal to 6 hours. Preferably, the drop ΔVth of the gate threshold voltage is smaller than, for example, a voltage value of -4 V, at which the semiconductor device in the Fig. The 12 illustrated results are normally enabled. In the Fig. As illustrated in the 13 results, the drop ΔVth of the gate threshold voltage can be smaller than, for example, -0.03 V. That is, as shown by a bold frame in the Fig. 12 and Fig. As indicated in section 13, it is preferable that the annealing temperature be higher than or equal to 300°C and lower than or equal to 420°C, and that the annealing time be longer than or equal to 1 hour and shorter than or equal to 3 hours. In this case, it is possible to suppress the decay ΔVth of the gate threshold voltage sufficiently to maintain the blocking ground state.

[0066] As described above, according to embodiment 1, after the MOSFET element structure has been formed on the SiC substrate, the first metal film is formed on the front electrode and annealing is carried out in a nitrogen atmosphere. Therefore, it is possible to suppress a drop in the gate threshold voltage when the negative voltage is applied to the gate electrode. Consequently, it is possible to keep the gate threshold voltage close to the desired setpoint and thus improve the reliability of the semiconductor device. Furthermore, according to embodiment 1, it is possible to improve the effect of suppressing the drop in the gate threshold voltage with increasing area ratio of the first metal film 21.

[0067] According to embodiment 1, after the MOSFET element structure has been formed on the SiC substrate, the first metal film is formed on the front electrode. Therefore, it is possible to suppress a drop in the gate threshold voltage. For example, if a SiC chip (SiC substrate) in which the MOSFET element structure is formed is obtained and the invention is applied to the SiC chip, it is possible to achieve the effect of suppressing a drop in the gate threshold voltage.

[0068] According to embodiment 1, the opening width of the source terminal spot contact hole or the surface of the front electrode is covered with the insulating film in such a way that the exposed area of ​​the front electrode is increased or decreased, thereby adjusting the area ratio of the first metal film. Therefore, for example, even when a SiC chip in which the element structure of the MOSFET is formed is reached, it is possible to easily adjust the area ratio of the first metal film to a desired value. (Version 2)

[0069] Now, a method according to embodiment 2 for manufacturing the semiconductor device is described. Fig. Figure 14 is a flowchart that clearly illustrates the process according to embodiment 2 for manufacturing the semiconductor device. The process according to embodiment 2 for manufacturing the semiconductor device differs from the process according to embodiment 1 in that a first annealing process is carried out (step S19) after a front electrode 13 has been formed (step S13) and before a passivation film is formed (step S14). The annealing temperature of the first annealing process can be higher than the annealing temperature of the annealing process in step S18 (hereinafter referred to as the second annealing process) and can be greater than or equal to, for example, 350°C. The conditions can be the same as those in the second annealing process, except for the annealing temperature of the first annealing process. (Example 8)

[0070] Now, a decrease ΔVth of the gate threshold voltage of a semiconductor device is described according to Example 8. Fig. Figure 15 is a diagram illustrating a decrease in the gate threshold voltage of the semiconductor device according to Example 8. A SiC MOSFET was fabricated using the method according to embodiment 2 for the fabrication of the semiconductor device (hereinafter referred to as Example 8). Example 8 is identical to Example 1, except that the first annealing process is carried out in step S19. That is, in Example 8, the first annealing process is carried out after the front electrode 13 has been formed, and the second annealing process is carried out after the first metal film 21 has been formed.

[0071] The decay ΔVth of the gate threshold voltage was calculated for Example 8. The calculation result is shown in Fig. 15 illustrated. Fig. Figure 15 illustrates the decrease ΔVth of the gate threshold voltage in Example 1, in which only the second annealing process is performed. The in Fig. The 15 illustrated results showed that when both the first and second annealing processes were performed, it is possible to further reduce the drop ΔVth of the gate threshold voltage after applying a negative voltage to a gate electrode. (Example 9)

[0072] The relationship between the area ratio of a first metal film 21 and a decrease ΔVth of the gate threshold voltage is now described. A number of examples 9-1 and 9-2, in which the area ratio of the first metal film 21 was greater than or equal to 46%, were produced using the method according to embodiment 2 for the fabrication of the semiconductor device. Specifically, as examples 9-1 and 9-2, samples containing first metal films 21 with area ratios of 46%, 74%, and 90% were prepared. The first annealing process was carried out at a temperature of 350°C for 1 hour. The second annealing process was carried out at a temperature of 300°C for 3 hours. A method for adjusting the area ratio of the first metal film 21 is the same as that in Example 5.

[0073] Then the decay ΔVth of the gate threshold voltage was calculated for examples 9-1 and 9-2. The calculation results are shown in Fig. Figure 9 illustrates this. The BT test in Example 9-1 was performed under the following conditions: a BT temperature of 200°C; and a voltage of -20 V was applied to the gate electrode. The BT test in Example 9-2 was performed under the following conditions: a BT temperature of 175°C; and a voltage of -10 V was applied to the gate electrode. The measurement conditions for the gate threshold voltage Vth are the same as those in Example 1.

[0074] The in Fig. The results illustrated in Figure 9 showed that, similar to Figure 5, it was possible in Examples 9-1 and 9-2 to decrease the decay ΔVth of the gate threshold voltage with increasing area ratio of the first metal film 21. For example, in Example 9-1, if the area ratio of the first metal film 21 is x and the decay ΔVth of the gate threshold voltage is y, the relationship between the area ratio of the first metal film 21 and the decay ΔVth of the gate threshold voltage is given by the following expression (2) (a Fig. 9 (curve designated by reference numeral 42). y=1.956⋅In(x)+0.0973

[0075] In Example 9-2, if the area ratio of the first metal film 21 is x and the decay ΔVth of the gate threshold voltage is y, the relationship between the area ratio of the first metal film 21 and the decay ΔVth of the gate threshold voltage is given by the following expression (3) (a in Fig.9 (curve designated by reference numeral 43). y=0.8007⋅In(x)+0.0634

[0076] As described above, according to embodiment 2 it is possible to achieve the same effect as in embodiment 1.

[0077] The invention is not limited to the embodiments described above, and various modifications and alterations of the invention can be made without departing from the scope and spirit of the invention. For example, in the embodiments described above, the MOSFET is formed using the SiC substrate, which will be the n-drain region. However, the MOSFET can also be formed using a SiC substrate that has an n -A drift layer will be formed. Furthermore, the SiC MOSFET in the embodiments described above is described as an example. However, the invention is not limited to the embodiments mentioned above. For example, the invention can be applied to a MOS semiconductor device with a MOS gate structure such as an IGBT. INDUSTRIAL APPLICATIONS

[0078] As described above, the semiconductor device and the method according to the invention for manufacturing the semiconductor device can be used for a MOS semiconductor device using a SiC semiconductor. REFERENCE MARK LIST 1 SiC substrate 2 n - -Epitaxial layer 3 p-base area 4 p-epitaxial layer 5 n ++ -Source area 6 p + -Contact area 7 n-inversion region 8 Gate insulating film 9 Gate electrode 10 Interlayer insulating film 11 TiN film 12 Ni-Film 13 Front electrode 14 Contact metal film 15 Backside electrode 21 first metal film 22 second metal film 23 Passivation film 23a Source connection spot contact hole 25 insulating film S1 surface of the front electrode S2 surface of the first metal film

Claims

[1] Method for manufacturing a semiconductor device comprising: a first step in forming an insulating layer structure containing a gate insulating film and a gate electrode on a front side of a silicon carbide substrate; a second step (S13) of forming a front-side electrode consisting of aluminium or an aluminium alloy over the front side of the silicon carbide substrate such that it is insulated from the gate electrode by an interlayer insulating film and that it covers the entire front side of the silicon carbide substrate in an active region, wherein the active region is a region in which a current flows when the semiconductor device is in a forward state; a third step (S17) of forming a metal film consisting of nickel, a nickel alloy, copper, palladium, titanium, platinum, gold or silver, or a metal layer film consisting of two or more metal films consisting of the metal materials, on a surface of the front-end electrode, wherein the metal film or metal layer film in the third step is formed such that it covers 60% to 90% of the surface of the front-end electrode; and a fourth step (S18) of carrying out annealing in a nitrogen gas atmosphere, a nitrogen-containing mixed gas atmosphere, a vacuum atmosphere or an argon gas atmosphere after the third step. [2] Method according to claim 1 for manufacturing the semiconductor device, further comprising: a fifth step (S19) of carrying out annealing in a nitrogen gas atmosphere, a nitrogen-containing mixed gas atmosphere, a vacuum atmosphere or an argon gas atmosphere after the second step and before the third step. [3] Method according to claim 2 for manufacturing the semiconductor device, wherein a annealing temperature in the fifth step is greater than a annealing temperature in the fourth step. [4] Method according to claim 2 for manufacturing the semiconductor device, wherein a annealing temperature in the fifth step is higher than or equal to 350 °C. [5] Method according to claim 1 for manufacturing the semiconductor device, wherein a annealing temperature in the fourth step is higher than or equal to 150°C and lower than or equal to 450°C. [6] Method according to claim 5 for manufacturing the semiconductor device, wherein the annealing temperature in the fourth step is higher than or equal to 300°C and lower than or equal to 420°C. [7] Method according to any one of claims 1 to 6 for manufacturing the semiconductor device, wherein the third step comprises: Formation (S14) of a passivation film on the front of the silicon carbide substrate; Forming a contact hole in the passivation film so that 60% or more and 90% or less of the front electrode is exposed; and Formation of the metal film or metal layer film by coating the entire surface of the front electrode, which is exposed through the contact hole of the passivation film. [8] Semiconductor device comprising: an insulating layer structure comprising a gate insulating film (8) and a gate electrode (9) which are formed on a front side of a silicon carbide substrate (1); a front-side electrode (13) made of aluminum or an aluminum alloy and provided over a front side of the silicon carbide substrate such that it is insulated from the gate electrode by an interlayer insulating film (10) and that it covers the entire front side of the silicon carbide substrate in an active region, wherein the active region is a region in which a current flows when the semiconductor device is in a forward state; and a metal film or a metal layer film of two or more metal films (21, 22) which is provided on a surface (S1) of the front electrode such that it covers 60% to 90% of the surface (S1) of the front electrode, wherein the metal film consists of nickel, a nickel alloy, copper, palladium, titanium, platinum, gold or silver.

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