Device, method and system for a rapid configuration mechanism

Abstract

Device (705) for device configuration, comprising the following: an interface logic (715, 716, 717) that is coupled with an element (725, 726, 727); a configuration store (712) containing a reference to a configuration context associated with the element (725, 726, 727); and a configuration control logic (711) coupled to the configuration memory (712) and a second interface, wherein the configuration control logic (711) configures at least part of the configuration context associated with the element (725, 726, 727) based on the reference to the configuration context contained in the configuration memory (712), wherein the device (705) includes a root controller and wherein the configuration memory (712) includes a cache memory for holding the reference to the configuration context and the configuration context.

Description

AREA

[0001] This disclosure relates to a computing system and, in particular (but not exclusively), to a configuration of devices for an intermediate interconnect architecture.

[0002] US 2011 / 0296255A1 discloses an I / O device comprising a host interface that can be configured to receive and process a variety of transaction packets sent by a number of processing units, each processing unit corresponding to a respective root complex.

[0003] US 2013 / 0 007 494 A1 shows the consumption and latencies for entering and exiting idle power states.

[0004] US 6 647 434 B1 shows a system for individually disabling a function of a multifunction device located on a computer bus of a computer system.

[0005] The problem stated is solved according to the invention by the features of claim 1. Further embodiments of the invention are described in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates an embodiment of a block diagram for a computing system that includes a multi-core processor. Fig. Figure 2 illustrates an embodiment of a computing system that incorporates a Peripheral Component Interconnect Express (PCIe) compliant architecture. Fig. Figure 3 shows an embodiment of a PCIe-compliant intermediate interconnect architecture with a 15-layer stack. Fig. Figure 4 illustrates an embodiment of a PCIe-compliant request or PCIe-compliant packet to be created or received within an intermediate link architecture. Fig.Figure 5 illustrates an embodiment of a transmitter and receiver pair for a PCIe-compliant interconnect architecture. Fig. Figure 6 illustrates embodiments of a logical view for a memory-mapped configuration space. Fig. Figure 7 illustrates an embodiment of a controller for configuring elements of an intermediate connection architecture. Fig. Figure 8 illustrates an embodiment of a protocol diagram for configuring an item using memory accesses from a host device. Fig. Figure 9 illustrates an embodiment of a configuration logic for fast device configuration. Fig. Figure 10 illustrates an embodiment of a protocol diagram for the rapid configuration of an element. Fig.Figure 11 illustrates an embodiment of a protocol diagram for a device for indicating a rapid configuration capability. Fig. Figure 12 illustrates an embodiment of a configuration space for an element in an intermediate connection architecture. Fig. Figure 13 illustrates an embodiment of a flowchart for a method for configuring a device. Fig. Figure 14 illustrates an embodiment of a low-energy computing platform. Fig. Figure 15 illustrates an embodiment of a processor with an on-chip interconnect. Fig. Figure 16 illustrates an embodiment of a computing system on a chip. Fig. Figure 17 illustrates an embodiment of a block diagram for a computer system. DETAILED DESCRIPTION

[0006] The following description provides numerous specific details, such as examples of specific processor types and system configurations, specific hardware structures, specific architectural and microarchitecture details, specific register configurations, specific instruction types, specific system components, specific configuration parameters, etc., to offer a basic understanding of the present invention. However, it will be clear to those skilled in the art that these specific details are not necessarily required to put the subject matter of this disclosure into practice.In other cases, a detailed description of known components or procedures, such as specific and alternative processor architectures, specific logic circuits / codes for described algorithms, specific firmware codes, specific interconnection operation, specific logic designs, specific manufacturing techniques and materials, specific compiler implementations, specific expressions of algorithms in code, specific shutdown and gate control techniques / logic, and other specific operational details of computing systems, has been omitted to avoid unnecessarily obscuring the present disclosure.

[0007] Although the following embodiments may be described with reference to energy saving and energy efficiency in specific integrated circuits, such as computing platforms or microprocessors, other embodiments can be applied to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein can be applied to other types of circuits or semiconductor devices that can also benefit from improved energy saving and energy efficiency. For example, the disclosed embodiments are not limited to server computing systems, desktop computing systems, or lightweight computing devices such as Ultrabooks™, but can also be used in other devices such as handheld devices, tablets, other thin notebooks, system-on-a-chip (SoC) devices, and embedded applications.Some examples of handheld devices include mobile phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include a microcontroller, a digital signal processor (DSP), a system-on-a-chip, a network PC, ancillary devices, network nodes, wide-area network switches (WAN switches), or any other system capable of performing the functions and operations taught below. Furthermore, the devices, methods, and systems described herein are not limited to physical computing devices but may also relate to software optimizations for energy conservation and efficiency.As can be readily seen from the description below, the embodiments of the methods, devices and systems described herein (whether referring to hardware, firmware, software or a combination thereof) can be considered essential for a future of “green technology” in balance with performance considerations.

[0008] As computer systems advance, their components become more complex. Consequently, the interconnect architecture used to couple and communicate between these components has also increased in complexity to ensure that bandwidth requirements are met for optimal component operation. Furthermore, different market segments require different aspects of interconnect architectures to meet their specific market needs. For example, servers require higher performance, while the mobile ecosystem may sometimes sacrifice overall performance for energy savings. Nevertheless, the primary purpose of most fabrics is to provide the highest possible performance with maximum energy savings. The following section describes a number of interconnects that might benefit from aspects of the invention described herein.

[0009] With reference to Fig.Figure 1 shows an embodiment of a block diagram for a computing system with a multi-core processor. The processor 100 comprises any processor or processing device 15, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a mobile processor, an application processor, a coprocessor, a system-on-a-chip (SoC), or any other code-executing device. In one embodiment, the processor 100 comprises at least two cores, cores 101 and 102, which may be asymmetric or symmetric cores (the embodiment shown). However, the processor 100 may comprise any number of processing elements 20, which may be symmetric or asymmetric.

[0010] In one embodiment, a processing element refers to hardware or logic for supporting a software thread. Examples of processing hardware elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logic processor, a hardware thread, a core, and / or any other element capable of maintaining state for a processor, such as an execution state or an architectural state. In other words, in one embodiment, a processing element refers to any hardware capable of being independently associated with code, such as software thread, operating system, application, or other code.A physical processor (or processor socket) typically refers to an integrated circuit that may contain any number of other processing elements, such as cores or hardware threads.

[0011] A core often refers to logic in an integrated circuit capable of maintaining independent architectural states, each associated with at least some dedicated execution resources. In contrast to cores, a hardware thread typically refers to any logic in an integrated circuit capable of maintaining independent architectural states, where the independently maintained architectural states share access to execution resources. As can be seen, the boundary between the terminology of a hardware thread and a core overlaps when certain resources are shared and others are dedicated to a single architectural state.However, often an operating system views a core and a hardware thread as individual logical processors, with the operating system being able to schedule operations on each logical processor individually.

[0012] The physical processor 100, as it is in Fig.As illustrated in Figure 1, it contains two cores—core 101 and 102. Here, cores 101 and 102 are considered symmetric cores, meaning cores with the same configurations, functional units, and / or logic. In another embodiment, core 101 contains an out-of-order processor core, while core 102 contains an in-order processor core. However, cores 101 and 102 can be individually selected from any type of core, such as a native core, a software-managed core, a core designed to run a native instruction set architecture (ISA), a core designed to run a translated instruction set architecture (ISA), a code-designed core, or any other known core. In a heterogeneous core environment (i.e.,(asymmetric cores) any form of translation, such as binary translation, can be used to schedule or execute code on one or both cores. To further the discussion: The functional units illustrated in core 101 are described in more detail below, while the units in core 102 operate in a similar manner in the embodiment shown.

[0013] As shown, the core 101 contains two hardware threads, 101a and 101b, which can also be referred to as hardware thread slots 101a and 101b. Consequently, software instances, such as an operating system, potentially view the processor 100 in one embodiment as four separate processors—that is, four logical processors or processing units capable of executing four software threads concurrently. As mentioned above, a first thread is associated with architecture state registers 101a, a second thread is associated with architecture state registers 101b, a third thread can be associated with architecture state registers 102a, and a fourth thread can be associated with architecture state registers 102b. Here, each of the architecture state registers (101a, 101b, 102a, and 102b) can be referred to as a processing unit, thread slot, or thread unit, as described above.As illustrated, the architecture state registers 101a are replicated in architecture state registers 101b, so that individual architecture states / contexts can be stored for both logical processor 101a and logical processor 101b. Within core 101, other, smaller resources, such as instruction pointers and rename logic in the assignment and rename block 130, can also be replicated for threads 101a and 101b. Some resources, such as reorder buffers in the reorder / termination unit 135, ILTB 120, load / store buffers, and queues, can be shared through partitioning. Other resources, such as internal general-purpose registers, page table base registers, low-level data caches and data TLB 115, execution unit(s) 140, and parts of the non-order unit 135, are potentially shared entirely.

[0014] The processor 100 often includes other resources that may be completely shared, shared through partitioning, or dedicated to processing elements. Fig.Figure 1 illustrates an embodiment of a purely exemplary processor with illustrative logical units / resources of a processor. It should be noted that a processor may include or omit any of these functional units, as well as any other known functional units, logic, or firmware not shown. As illustrated, core 101 comprises a simplified, representative pre-order processor core (000 processor core). However, a pre-order processor may be used in other embodiments. The OOO core includes a jump target buffer 120 for predicting jumps to be executed / taken and an instruction translation buffer (I-TLB) 120 for storing address translation entries for instructions.

[0015] The core 101 further includes the decode module 125, which is coupled to the retrieval unit 120 to decode retrieved elements. In one embodiment, the retrieval logic comprises individual sequencers linked to the thread slots 101a and 101b, respectively. Typically, the core 101 is linked to a first ISA that defines / specifies instructions executable on the processor 100. Often, machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode) that references / specifies an instruction or operation to be executed. The decode logic 125 comprises circuits that recognize these instructions based on their opcodes and forward the decoded instructions in the pipeline for processing, as defined by the first ISA.For example, in one embodiment, as discussed in more detail below, the decoders 125 include logic designed or adapted to recognize specific instructions, such as transaction instructions. As a result of recognition by the decoders 125, the architecture or core 101 performs specific, predefined actions to execute tasks associated with the governing instruction. It is important to note that any of the tasks, blocks, operations, and procedures described here can be executed in response to a single instruction or to multiple instructions, some of which may be new and some of which may be old. It should be noted that in one embodiment, the decoders 126 recognize the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, the decoders 126 recognize a second ISA (either a subset of the first ISA or an individual ISA).

[0016] In one example, allocation and renaming block 130 contains an assigner for reserving resources, such as register files for storing instruction processing results. However, threads 101a and 101b are potentially capable of out-of-order execution, with allocation and renaming block 130 also reserving other resources, such as reorder buffers for tracking instruction results.

[0017] Unit 130 may also contain a register renamer to rename program / instruction reference registers to other registers within processor 100. The reorder / termination unit 135 contains components such as the reorder buffers, load buffers, and memory buffers mentioned above to support out-of-order execution and subsequent in-order termination of instructions that were executed out of order.

[0018] In one embodiment, the scheduler and execution unit block 140 includes a scheduler unit for scheduling instructions / operations on execution units. For example, a floating-point instruction is scheduled on a port of an execution unit that has an available floating-point execution unit. Register files associated with the execution units are also included for storing the results of information instruction processing. Example execution units include a floating-point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a memory execution unit, and other known execution units.

[0019] The lower-level data cache and the data translation buffer (D-TLB) 150 are coupled to the execution unit(s) 140. The data cache is intended to store recently used / modified elements that are potentially maintained in memory coherence states, such as data operands. The D-TLB is intended to store new translations from virtual / linear to physical addresses. As a specific example, a processor might contain a page table structure to divide physical memory into multiple virtual pages.

[0020] Here, cores 101 and 102 share access to a higher-level cache or a more distant cache, such as a second-level cache linked to the on-chip interface 110. It should be noted that "higher-level" or "more distant" refers to the cache level that is higher or further away from the execution unit(s). In one embodiment, the higher-level cache is a last-level data cache—the last cache in the memory hierarchy on processor 100—such as a second- or third-level data cache. However, the higher-level cache is not restricted in this respect, so it can be linked to or contain an instruction cache. A track cache—a type of instruction cache—can instead be coupled behind decoder 125 to store recently decoded tracks. Here, an instruction potentially refers to a macro instruction (i.e., a command that executes a command).a general command that is recognized by the decoders), which can be decoded into a number of micro-commands (micro-operations).

[0021] In the configuration shown, the processor 100 also includes an on-chip interface module 110. Historically, a memory controller, described in more detail below, has been incorporated into a computing system outside the processor 100. In this scenario, the on-chip interface 11 is intended to communicate with devices outside the processor 100, such as system memory 175, a chipset (often including a memory controller hub for connecting to the memory 175 and an I / O controller hub for connecting to peripheral devices), a memory controller hub, a northbridge, or another integrated circuit. And in this scenario, the bus 105 can include any known intermediate connection, such as a multidrop bus, a point-to-point intermediate connection, a serial intermediate connection, a parallel bus, a coherent (e.g.,cache-coherent) bus, a layered protocol architecture, a differential bus and a GTL bus.

[0022] Memory 175 can be dedicated to the processor 100 or shared with other devices in a system. Common examples of memory types 175 include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. It should be noted that a device 180 may include a graphics accelerator, a processor or card coupled with a memory controller hub, a data storage device coupled with an I / O controller hub, a wireless transceiver, a flash device, an audio controller, a network controller, or any other known device.

[0023] However, more logic and devices are now being integrated onto a single chip, such as a SoC. Each of these devices can be integrated onto the processor 100. For example, in one embodiment, a memory controller hub is located in the same assembly and / or on the same chip as the processor 100. In this embodiment, part of the core 110 (an on-core portion) contains one or more controllers for coupling with other devices, such as the memory 175 or a graphics device 180. The configuration that includes an intermediary link and a controller for coupling with such devices is often referred to as an on-core (or un-core) configuration. For example, the on-chip interface 110 includes a ring intermediary link for on-chip communication and a serial point-to-point high-speed link 105 for off-chip communication.Nevertheless, in a SOC environment even more devices such as the network interface, coprocessors, memory 175, graphics processor 180 and any other known computer devices / interfaces can be integrated on a single chip or integrated circuit to provide a low form factor with high functionality and low power consumption.

[0024] In one embodiment, the processor 100 is capable of executing compiler, optimizer, and / or translator code 177 to compile, translate, and / or optimize the application code 176 to support or interact with the devices and procedures described herein. A compiler often contains a program or set of programs to translate source text / code into target text / code. Normally, compiling program / application code with a compiler involves multiple stages and passes to transform high-level programming language code into low-level machine or assembly language code. However, single-pass compilers can still be used for simple compilation.A compiler can use any known compilation techniques and perform any known compiler operations, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code transformation, and code optimization.

[0025] Larger compilers often include multiple passes, but these phases are most commonly contained in two general stages: (1) a front end, where syntactic processing, semantic processing, and some transformation / optimization generally occur, and (2) a back end, where analysis, transformations, optimizations, and code generation generally take place. Some compilers refer to a middle ground, illustrating the blurring of the boundaries between a compiler's front end and back end. As a result, a reference to an insertion, join, generation, or other compiler operation can occur in any of the aforementioned stages or passes, as well as in any other known stages or passes of a compiler. For example, a compiler potentially inserts operations, calls, functions, and so on.Dynamic compilation involves one or more phases of the compilation process, such as inserting calls / operations in a front-end phase and then transforming those calls / operations into lower-level code during a transformation phase. It's worth noting that during dynamic compilation, compiler code or dynamic optimization code can both insert such operations / calls and optimize the code for execution at runtime. As a specific, illustrative example, binary code (already compiled code) can be dynamically optimized at runtime. Here, the program code can contain the dynamic optimization code, the binary code, or a combination thereof.

[0026] Similar to a compiler, a translator, such as a binary translator, translates code either statically or dynamically to optimize and / or translate code.Therefore, a reference to the execution of code, application code, program code, or any other software environment may refer to: (1) the execution of one or more compiler programs, optimization code optimizers, or translators, either dynamically or statically, to compile program code, maintain software structures, perform other operations, optimize code, or translate code; (2) the execution of main program code that includes operations / calls, such as application code that has been optimized / compiled; (3) the execution of other program code, such as libraries, that is linked to the main program code to maintain software structures, to perform other operations with respect to software, or to optimize code; or (4) a combination thereof.

[0027] An interconnect fabric architecture designed to connect system components is the Peripheral Component Interconnect (PCI) Express architecture (PCIe architecture). The goal of PCIe is to enable components and devices from different manufacturers to work together in an open architecture that spans multiple market segments: clients (desktop and mobile devices), servers (standard and enterprise), and embedded and communications devices. PCI Express is often described as a load-storage I / O or load-storage I / O interconnect architecture defined for a wide variety of future computing and communications platforms. Some PCI characteristics, such as...The usage model, load-storage architecture, and software interfaces have been maintained through revisions, while previous parallel bus implementations have been replaced by a highly scalable, fully serial interface. Recent versions of PCI Express leverage advancements in point-to-point interconnects, switch-based technology, and the packetized protocol to deliver new levels of performance and features. Power management, quality of service (QoS), hot-swap support, data integrity, and fault handling are among some of the advanced features supported by PCI Express (PCIe). However, the protocols defined in the PCIe specifications can be deployed over any physical interface or topology, such as point-to-point, ring, mesh, cluster, etc.

[0028] With reference to Fig.Figure 2 shows an embodiment of a fabric consisting of point-to-point links that interconnect a set of components. The system 200 comprises a processor 205 and a system memory 210 coupled to a controller hub 215. The processor 205 comprises any processing element, such as a microprocessor, a host processor, an embedded processor, a coprocessor, or another processor. The processor 205 is coupled to the controller hub 215 by a front-end bus (FSB) 206. In one embodiment, the FSB 206 is a serial point-to-point link, as described below. In another embodiment, the link 206 comprises a serial differential link architecture compatible with a different link standard.

[0029] As more and more devices are integrated onto the same chip as the 205 processor, it is important to note that in some implementations the 215 controller hub is integrated with the 205 processor. In this case, the cores of the 205 processor connect to a memory controller hub 215 that is integrated on the chip. Furthermore, PCIe interfaces can be directly from the 205 processor, from the 215 controller hub, integrated onto the 205 processor, or provided in both forms.

[0030] System memory 210 comprises any storage device, such as random-access memory (RAM), non-volatile (NV) memory, or other memory accessible by devices in system 200. System memory 210 is coupled to the controller hub 215 by a memory interface 216. Examples of memory interfaces include a double data rate (DDR) memory interface, a dual-channel DDR memory interface, and a dynamic RAM (DRAM) memory interface.

[0031] In one embodiment, the controller hub 215 can comprise a root hub, root complex, or root controller, such as in a PCIe interconnect hierarchy. Examples of the controller hub 215 include a chipset, a memory controller hub (MCH), a northbridge, an interconnect controller hub (ICH), a southbridge, and a root controller / hub. Often, the term chipset refers to two physically separate controller hubs, such as a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). It should be noted that current systems often include the MCH integrated with the processor 205, while the controller 215 is provided separately, either within or outside the processor 205, to communicate with the I / O devices in a manner similar to that described below.In some embodiments, peer-to-peer routing is optionally supported by the root complex 215. In one embodiment, the root complex 215 comprises a logical collection of root ports, root complex register blocks, or integrated root complex endpoints.

[0032] Here, the controller hub 215 is coupled to the switch / bridge 220 via a serial connection 219. Input / output modules 217 and 221, which can also be referred to as interfaces / ports 217 and 221, can include / implement a layered protocol stack to establish communication between the controller hub 215 and the switch 220. In one embodiment, multiple devices are capable of being coupled to the switch 220.

[0033] The switch / bridge 220 directs packets / messages from the device 225 upstream, i.e., one hierarchy upwards towards a root complex, to the controller hub 215, and downstream, i.e., one hierarchy downwards away from a root controller, from the processor 205 or system memory 210 to the device 225. Upstream, as used in this example, refers to the relative position of an element closer to the root complex, or a direction of information flow towards the root complex, while downstream refers conversely to an element farther away from a root complex, or a direction of information flow away from the root complex. In one embodiment, the switch 220 is referred to as a logical array of multiple virtual PCI-to-PCI bridge devices.Here, switch 220 is illustrated as a system element intended to connect to two or more ports to allow packets to be routed from one port to another, appearing in some implementations as a collection of PCI-PCI bridges. A bridge, that is, a self-contained bridge, typically refers to a function that virtually or physically connects a PCI / PCI-X segment or PCIe port to an internal component intermediary or to another PCI / PCI-X bus segment or PCIe port.

[0034] Device 225 comprises any internal or external device or component intended to be coupled to an electronic system, such as an I / O device, a network interface controller (NIC), an add-in card, an audio processor, a network processor, a hard disk drive, a storage device, a CD / DVD-ROM drive, a monitor, a printer, a mouse, a keyboard, a router, a portable storage device, a FireWire device, a universal serial bus (USB) device, a scanner, and other input / output devices. In PCIe terminology, such a device is often referred to as an endpoint. Although not specifically shown, Device 225 may include a PCIe-to-PCI / PCI-X bridge to support legacy or other versions of PCI devices. Endpoint devices in PCIe are often classified as legacy, PCIe, or integrated root complex endpoints.In one embodiment, the device 225 comprises a physical or logical unit intended to perform a type of I / O, a component at one end of a link, or a reference to a function (or collection of functions in a multi-function device). In PCIe, a common usage for an element or unit on a PCIe link is often referred to as a function. Here, a function typically denotes an addressable unit in a configuration space to which a function number is assigned. In some embodiments, a function refers to a single functional device, while in others it refers to a multi-function device.

[0035] A graphics accelerator 230 is also coupled to the controller hub 215 via a serial connection 232. In one embodiment, the graphics accelerator 230 is coupled to an MCH, which is coupled to an ICH. The switch 220, and consequently the I / O device 225, is then coupled to the ICH. I / O modules 231 and 218 are also intended to implement a layered protocol stack for communication between the graphics accelerator 230 and the control unit node 215. Similar to the MCH discussion above, a graphics controller or the graphics accelerator 230 itself can be integrated into the processor 205.

[0036] With reference to Fig.Figure 3 shows an embodiment of a layered protocol stack. The layered protocol stack 300 comprises any form of layered communication stack, such as a Quick-Path Interconnect (QPI) stack, a PCIe stack, a next-generation High-Performance Computing Interconnect (HPI) stack, a Low-Performance Interface (LPI) stack, a Mobile Industrial Processor Interface (MIPI) stack, or any other layered stack. Although the immediately following discussion refers to Fig. While references 2-5 to a PCIe stack are relevant, the same concepts can apply to other intermediate interconnect stacks. In one embodiment, the protocol stack 300 is a PCIe protocol stack comprising a transaction layer 305, a data link layer 310, and a physical layer 320. An interface such as interfaces 217, 218, 221, 222, 226, and 231 in Fig.1 can be represented as a communication protocol stack of 300. The representation as a communication protocol stack can also be referred to as a module or interface that implements / includes a protocol stack.

[0037] PCI Express uses packets to transmit information between components. Packets can be formed at the transaction layer (305) and the data link layer (310) to transfer information from the sending component to the receiving component. As the transmitted packets pass through the other layers, they are augmented with additional information used to process packets at those layers. At the receiving end, the reverse process occurs: packets are transformed from their physical layer (320) representation to their data link layer (310) representation, and finally (for transaction layer packets) into a form that can be processed by the receiving device's transaction layer (305). Transaction layer

[0038] In one embodiment, the transaction layer 305 can provide an interface between the processing core of a device and the intermediate connection architecture, such as a data link layer 310 and a physical layer 320. In this respect, a primary responsibility of the transaction layer 305 can include the composition and decomposition of packets (i.e., transaction layer packets or TLPs). The translation layer 305 can also manage point-by-point flow control for TLPs. PCIe implements split transactions, i.e., transactions with a time-separated request and response, which, among other examples, allows one connection to carry other traffic while the destination device gathers data for the response.

[0039] Additionally, PCIe uses point-based flow control. In this scheme, a device announces an initial set of points for each of the receive buffers in transaction layer 305. An external device at the opposite end of the connection, such as the controller hub 115, then... Fig. Point 1 can count the number of points consumed by each TLP. A transaction can be transmitted if it does not exceed a point limit. Upon receiving a response, a set of points is restored. One example of the advantage of such a point scheme, among other potential benefits, is that the latency of point return does not affect performance, provided the point limit is not reached.

[0040] In one embodiment, four transaction address spaces comprise a configuration address space, a memory address space, an input / output address space, and a message address space. Memory space transactions comprise one or more read and write requests to transfer data to / from a location mapped to memory. In one embodiment, memory space transactions are capable of using two different address formats, such as a short address format like a 32-bit address or a long address format like a 64-bit address. Configuration space transactions are used to access the configuration space of various PCIe devices connected to the intermediate link. Transactions to the configuration space can include read and write requests.Message space transactions (or simply messages) are defined to support on-band communication between PCIe agents.

[0041] Therefore, in one embodiment, the transaction layer 305 combines packet header / payload information 306. A format for current packet header / payload information can be found in the PCIe specifications on the PCIe specification website.

[0042] With quick reference to Fig. Figure 4 shows an embodiment of a PCIe transaction layer packet descriptor. In one embodiment, the transaction descriptor 400 is a mechanism for transmitting transaction information. In this respect, the transaction descriptor 400 supports the identification of transactions in a system. Other potential uses include tracking modifications to a default transaction order and assigning transactions to channels.

[0043] The transaction descriptor 400, for example, comprises a global identifier field 402, an attribute field 404, and a channel identifier field 406. In the example shown, the global identifier field 402 is represented with a local transaction identifier field 408 and a source identifier field 410. In one embodiment, the global transaction identifier 402 is unique for all pending requirements.

[0044] According to one implementation, the local transaction identifier field 408 is a field generated by a request agent and can be unique for all pending requests that require completion by that request agent. In this example, the source identifier 410 further uniquely identifies the request agent within a PCIe hierarchy. Consequently, the local transaction identifier field 408, together with the source ID 410, creates a global identification of a transaction within a hierarchy domain.

[0045] Attribute field 404 defines properties and relationships of the transaction. In this respect, attribute field 404 is potentially used to provide additional information that allows modification of the standard handling of transactions. In one embodiment, attribute field 404 includes a priority field 412, a reserved field 414, an ordering field 416, and a no-spying field 418. Here, the priority subfield 412 can be modified by an initiator to assign a priority to the transaction. The reserved attribute field 414 is left reserved for future use or for manufacturer-defined usage. Possible usage models using priority and security attributes can be implemented using the reserved attribute field.

[0046] In this example, the order attribute field 416 is used to provide optional information that conveys the type of order that can modify default ordering rules. According to one example implementation, an order attribute of "0" indicates that default ordering rules should be applied, while an order attribute of "1" indicates relaxed ordering, where writes can overtake writes in the same direction and read completions can overtake writes in the same direction. The eavesdrop attribute field 418 is used to determine whether transactions are being intercepted. As shown, the channel ID field 406 identifies a channel to which a transaction is associated. Linkage layer

[0047] The data link layer 310, also known as data link layer 310, acts as an intermediate layer between the transaction layer 305 and the physical layer 320. In one embodiment, the data link layer 310 is responsible for providing a reliable mechanism for exchanging transaction layer packets (TLPs) between two components as a link. One side of the data link layer 310 accepts TLPs assembled by the transaction layer 305, applies a packet sequence identifier 311 (i.e., an identification number or packet number), calculates and applies an error detection code (CRC 312), and passes the modified TLPs to the physical layer 320 for transmission across a physical layer to an external device. Physical layer

[0048] In one example, physical layer 320 comprises a logical subblock 321 and an electrical subblock 322 to physically transmit a packet to an external device. Here, logical subblock 321 is responsible for the "digital" functions of physical layer 321. In this respect, the logical subblock may include a transmit section to prepare outgoing information for transmission by physical subblock 322, and a receive section to identify and prepare received information before passing it to data link layer 310.

[0049] The physical block 322 comprises a sender and a receiver. The sender receives symbols from the logical subblock 321, which the sender serializes and forwards to an external device. The receiver receives serialized symbols from an external device and transforms the received signals into a bitstream. The bitstream is deserialized and supplied to the logical subblock 321. In one embodiment, an 8b / 10b transmission code is used, with ten-bit symbols being sent / received. Special symbols are used to enclose a packet of frame 323. Furthermore, in one example, the receiver also supplies a symbol clock, which is recovered from the incoming serial stream.

[0050] As stated above, although the transaction layer (305), data link layer (310), and physical layer (320) have been discussed in relation to a specific implementation of a PCIe protocol stack, a layered protocol stack is not so restricted. In fact, any layered protocol may be included / implemented. For example, a port / interface represented as a layered protocol may include: (1) a first layer for assembling packets, i.e., a transaction layer; (2) a second layer for sequencing packets, i.e., a data link layer; and (3) a third layer for transmitting the packets, i.e., a physical layer. As a specific example, a layered protocol for a common standard interface (CSI layered protocol) is used.

[0051] With reference to Fig.Figure 5 next describes an embodiment of a serial PCIe point-to-point fabric. Although a serial PCIe point-to-point connection is shown, a serial point-to-point connection is not limited to this, as it can include any transmission path for transmitting serial data. In the embodiment shown, a PCIe connection can include two differentially driven low-voltage signal pairs: a transmit pair 506 / 511 and a receive pair 512 / 507. Consequently, the device 505 includes transmit logic 506 to send data to the device 510 and receive logic 507 to receive data from the device 510. In other words, two transmit paths, i.e., paths 516 and 517, and two receive paths, i.e., paths 518 and 519, are included in one PCIe connection.

[0052] A transmission path refers to any path used to transmit data, such as a transmission line, a copper wire, an optical line, a wireless communication channel, an infrared communication link, or any other communication path. A connection between two devices, such as Device 505 and Device 510, is called a link, such as Link 415. A link can support one lane—each lane representing a set of differential signal pairs (one pair for transmitting, one pair for receiving). To scale bandwidth, a link can combine multiple lanes, designated xN, where N is any supported link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider.

[0053] A differential pair can refer to two transmission paths, such as lines 416 and 417, used to transmit differential signals. For example, if line 416 switches from a low voltage level to a high voltage level (i.e., on a rising edge), line 417 switches from a high logic level to a low logic level (i.e., on a falling edge). Differential signals exhibit potentially better electrical characteristics, such as improved signal integrity (i.e., reduced cross-coupling, voltage overshoot / undershoot, callouts, etc.). This allows for a narrower timing window, enabling faster transmission frequencies.

[0054] With reference to Fig. Figure 6 presents embodiments of a logical view for a memory-mapped configuration space. Some of these examples of memory-mapped configuration spaces are shown immediately below with reference to Fig. Section 6 discusses this. Here, the PCI architecture defines and creates a configuration address space 626 in a memory 625, which is usually orthogonal to an I / O and memory address space 626.

[0055] In one embodiment, a mechanism for configuration read and write generation is provided using an I / O-mapped address data window 616, which is located at a fixed address, such as CFC / CF8, in the I / O space 615 of the processor 605. Here, the processor initiates a read or write operation to the address space 616, which is representative of a configuration address space (CAS) 626, and the read or write operation is then performed at the endpoint 622, which can be a device or function within the PCIe network.

[0056] In another embodiment, an Extended Configuration Access Mechanism (ECAM) is provided to enhance the configuration of a PCIe device or function. Here, a root complex 610 is mapped to a memory-mapped window 621 in a root complex memory space to represent a configuration access space 626 and to generate the semantic queries of the configuration read / write bus. Exemplary implementations of ECAM are discussed immediately below to provide a more detailed description of the inner workings of ECAM. However, the ECAM implementation is not limited to this. Furthermore, an FCAM, as discussed below, can use similar attributes to ECAM, so the following example can help in understanding an FCAM framework; however, an FCAM is also not limited to the detailed illustrative example.

[0057] In an ECAM implementation, PCI Express elements such as device 622 are often mapped to a PCI-compatible configuration space 626 to maintain compatibility with PCI software configuration mechanisms. Some examples are described below. A PCI Express connection originates from a PCI-PCI logical bridge and is mapped to configuration space 626 as the secondary bus of that bridge. The root port in root complex 610 is a PCI-PCI bridge structure that produces a PCI Express connection from a PCI Express root complex 610. A PCI Express switch is represented by several PCI-PCI bridge structures that connect PCI Express links to an internal PCI logical bus. The upstream switch port includes a PCI-PCI bridge; the secondary bus of this bridge represents the switch's internal forwarding logic.Downstream switch ports are PCI-PCI bridges that connect the internal bus to the buses representing the downstream PCI Express links from a PCI Express switch. These PCI-PCI bridges may appear on the internal bus. Endpoints 622, represented by Type 0 configuration space heads, may not appear on the internal bus in some implementations.

[0058] A PCI Express endpoint 622 can be mapped to configuration space 626 as a single function within a device that contains multiple functions, or simply as a single function. PCI Express endpoints and legacy endpoints often appear in one of the hierarchy domains spawned by root complex 610. For example, devices 622 appear in configuration space 626 in a tree that has a root port as its head. Integrated root complex endpoints and root complex event collectors may not appear in one of the hierarchy domains spawned by root complex 610. Instead, in some implementations, they appear in configuration space 626 as peers of the root ports.

[0059] In one embodiment, PCI Express extends the configuration space 626 to a larger size, such as 4096 bytes per function, compared to the 256 bytes allowed by a PCI local bus specification. In one embodiment, the PCI Express configuration space 626 is subdivided into a PCI 3.0-compatible portion, consisting of the initial set, such as the first 256 bytes of a configuration space for function 622, and an extended PCI Express configuration space, consisting of the remaining configuration space 626. The PCI 3.0-compatible portion of the configuration space 626 can be accessed either by the mechanism defined in the PCI local bus specification or the extended PCI Express configuration, the access mechanism (ECAM), or a quick configuration access mechanism (FCAM), as described later.

[0060] The extended PCI Express configuration space can be accessed via ECAM or FCAM. The PCI Express configuration mechanism, compatible with PCI 3.0 or later (e.g., 4.0, 5.0, and other future versions), supports the PCI configuration space programming model defined in the PCI Local Bus Specification. By adhering to this model, systems incorporating PCI Express interfaces remain compatible with conventional PCI bus enumeration and configuration software. Similar to PCI 3.0 device functions, PCI Express device functions provide a configuration space for software-driven initialization and configuration. The PCI Express configuration space headers are typically organized to conform to the format and behavior defined in the PCI Local Bus Specification.The 0-compatible configuration access mechanism can use the same request format as ECAM or FCAM. For PCI-compatible configuration requests, the extension register address field can be set to zero.

[0061] In one embodiment for systems implementing a processor architecture-specific firmware interface standard that enables access to configuration space 626, the operating system uses the standard firmware interface, and ECAM or FCAM access is optional. For example, for systems compliant with the Developer's Interface Guide for 64-bit Intel Architecture-based Servers (DIG64), version 2.1.93, the operating system uses the SAL firmware service to access the configuration space.

[0062] In one embodiment, the ECAM uses a flat memory-mapped address space to access the configuration registers of the Device 622. In this case, the memory address determines the configuration register being accessed, and the memory data updates (for a write) or returns the contents (for a read) of the addressed register. An exemplary mapping from memory address space to PCI Express configuration space addresses is defined in Table 1. Table 1: Implementation of the extended configuration address mapping Storage address 94 PCI Express configuration space A[(20+n-1):20] Bus number 1≤n≤8 A[19:15] Device number A[14:12] Function number A[11:8] Extension register number A[7:2] Registration number A[1:0] Along with the size of the access, used to create byte shares

[0063] The size and base address for the range of memory addresses mapped to the configuration space are determined by the design of the host bridge and the firmware. They can be reported to the operating system by the firmware in an implementation-specific manner. The size of the range is determined by the number of bits that the host bridge maps to the bus number field in the configuration address. In Table 1, this number of bits is represented as n, where 1 ≤ n ≤ 8. A host bridge that maps n memory address bits to the bus number field supports bus numbers from 0 to 2n-1 inclusive, and the base address of the range is aligned to a 2(n+20) byte memory address boundary. All bits in the bus number field mapped from the memory address bits can be cleared.

[0064] For example, if a system maps three memory address bits to the bus number field, the following may be true: n = 3; address bits A[63:23] are used for the base address, aligned to a 2^23 byte (8 MB) boundary; address bits A[22:20] are mapped to bits [2:0] in the bus number field; bits [7:3] in the bus number field are cleared; and the system is able to address bus numbers from 0 to 7 inclusive.

[0065] At least one memory address bit (n = 1) can be mapped to the bus number field. However, systems in other implementations map additional memory address bits to the bus number field as needed to support a larger number of buses. For example, systems that support more than 4 GB of memory addresses map at least eight bits of the memory address (n = 8) to the bus number field. It should be noted that in systems that include multiple host bridges, with each host bridge assigned different ranges of bus numbers, the highest bus number for the system may be limited by the number of bits mapped by the host bridge to which the highest bus number is assigned. In such a system, the highest bus number 5 assigned to a given host bridge would, in most cases, be greater than the number of buses assigned to that host bridge.In other words, for each host bridge, the number of bits n mapped to the bus number field should be large enough that the highest bus number assigned to any given bridge is less than or equal to 2n-1 for that bridge. In some processor architectures, it is possible to generate memory accesses that are not expressed in a single configuration request, for example, because a DW-aligned boundary is crossed or because a locked access is used. A root complex implementation cannot be used to assist in translating such accesses into configuration requests.

[0066] In addition, requirements can target extended functions in an ARI device, A[19:12] represents the (8-bit) function number that replaces the (5-bit) device number and (3-bit) function number fields.

[0067] In one embodiment, the system hardware provides a method for the system software to ensure that a write transaction using the ECAM is completed by the compiler before the system software continues execution.

[0068] In one implementation, ECAM converts memory transactions from the host CPU into configuration requests on the PCI Express fabric. This conversion may create order issues for the software, since writes to memory addresses are typically booked transactions, but writes to the configuration space may not be booked on the PCI Express fabric.

[0069] Generally, software does not know when a posted transaction has been completed by the compiler. In cases where the software needs to know that a posted transaction has been completed by the compiler, a technique commonly used is to read the location where a write operation is currently taking place. For systems that consistently follow PCI order rules, the read transaction will not be complete until the posted write operation is finished. However, since PCI order rules allow unposted write and read transactions to be reordered relative to each other, the CPU 605 should wait for an unposted write operation on the PCI Express fabric to complete to ensure that the transaction has been completed by the compiler.For example, software might wish to configure a base address register of a device function 622 by writing to the device 622 using the ECAM and then reading a location in the memory-mapped region described by that base address register. If the software outputs the memory-mapped read before the ECAM write is complete, it would be possible for the memory-mapped read to be reordered and arrive at the device before the configuration write request, leading to unpredictable results. To avoid this problem, implementations of the processor 605 and the host bridge 610 in one embodiment ensure that a method is available for the software to determine when the write operation using the ECAM has been completed by the completer.

[0070] This procedure can be as simple as the 605 processor itself recognizing a memory area dedicated to mapping ECAM accesses as unique and treating accesses to this area in the same way it would treat other accesses that generate unposted writes on the PCI Express fabric; that is, the transaction is unposted from the processor's point of view. An alternative mechanism is for the 610 host bridge (instead of the 605 processor) to recognize accesses to the memory-mapped configuration space 626 and not indicate to the 605 processor that this write operation has been accepted until the unposted configuration transaction on the PCI Express fabric is complete.A third alternative would be for the 605 processor and the 610 host bridge to book the memory-mapped write operation to the ECAM, with the 610 host bridge providing a separate register that the software can read to determine when the configuration write request to the PCI Express fabric is complete. Other alternatives are also possible. For example, a processor could provide a fetch instruction which, when executed, ensures that previous (earlier) memory access operations have completed.

[0071] Since root complex implementations are not required to support the generation of configuration requests from accesses that cross DW boundaries or use locked semantics, software should take care not to cause the generation of such accesses when using memory-mapped ECAM, unless it is known that the implementation of the 610 root complex used will support the translation. In systems implementing ECAM, the 610 PCI Express host bridge is intended to translate memory-mapped PCI Express configuration space accesses from the host processor into PCI Express configuration transactions.The use of the host bridge PCI class code may be reserved for backward compatibility; a host bridge configuration space may be implemented in an implementation-specific manner that is either compatible or incompatible with the PCI host bridge type 0 configuration space. A PCI Express host bridge may not need to signal errors through a root complex event collector. This support is optional for PCI Express host bridges. Device 622 can support an additional 4 bits for decoding a configuration register access, that is, decoding the extension register address field[3:0] of the configuration request header.

[0072] Device-specific registers for which there are valid reasons for placing them in the configuration space (e.g., they must be accessible before memory space is allocated) can be placed in a vendor-specific capability structure (in the PCI-compliant configuration space) or an extended vendor-specific capability structure (in the extended PCI Express configuration space). Device-specific registers accessed in the driver runtime environment can be placed in memory space allocated by one or more base address registers. Although the PCI-compliant or extended PCI Express configuration space may have sufficient space for device-specific runtime registers, placing them there is often discouraged.

[0073] A root port or integrated root complex endpoint can be associated with an optional block of memory-mapped registers, such as a 4096-byte block, referred to as the root complex register block (RCRB). These registers are used in one embodiment in a manner similar to configuration space 626 and can include extended PCI Express capabilities and other implementation-specific registers applicable to the root complex.

[0074] Multiple root ports or internal devices may be mapped to the same RCRB. In one implementation, the memory-mapped RCRB registers are not located in the same address space as the memory-mapped configuration space or memory space. In another implementation, they are located in the same address space but have different addresses.

[0075] As can be seen, an ECAM potentially enables faster completion of CPU-generated configuration requests, reducing CPU latency and configuration caching hidden from the system software, thus allowing faster entry and exit from power states. However, in some embodiments, these benefits do not extend to integrated devices.

[0076] As a result, one embodiment provides a Quick Configuration Access (FCAM) ​​mechanism. For example, an FCAM implementation appears transparently to host software as ECAM because the Root Complex 610 applies new FCAM principles to handling configuration requests. Furthermore, in some embodiments, the Root Complex 610 also generates new bus semantics using memory read / write commands and may provide a template for such commands.

[0077] In one embodiment, the root complex 610 includes a cache, such as an FCAM cache, mapped to a memory-mapped I / O window. Such cache utilization potentially enables one or more of the following: (1) host-initiated configuration writes that are cached and completed faster from the perspective of the host processor 205; (2) multiple host-initiated configuration writes that can be combined into a single bus transaction to the device 622, improving efficiency and reducing configuration time; (3) host-initiated reads from static and semi-static device configuration registers served from the cache, reducing latency, bus traffic, and power consumption.and (4) the device 622 can be powered off and then quickly restore the configuration context by keeping context in the cache, which is then quickly loaded into the device 622 when it is powered on again (this can be done in parallel if multiple devices are powered on) and this does not require direct host involvement, which reduces power consumption and latency.

[0078] In one embodiment, the FCAM cache is not cache-coherent with the 605 processor's cache. As a logical consequence, the ability to provide a non-coherent cache can enable the implementation of the caching mechanism behind a non-coherent I / O link, such as in a bridge, to support legacy PCI / PCIe hardware. However, in another embodiment, the FCAM cache is implemented cache-coherently with the 605 processor's cache.

[0079] In one embodiment, the FCAM cache implements a write-through preset to ensure that configuration updates are sent to the target function. However, the write-through preset can take various forms. For example, one implementation might use a lazy write-through preset, where writes are written through in a reasonably timely manner, i.e., delays due to overload, etc., occur.

[0080] However, in this scenario, write operations can be completed deterministically.

[0081] In one embodiment, when restoring the configuration context, such as reloading a configuration context into a configuration space for an endpoint device from the FCAM cache, write operations to the target function / device may be performed in large blocks. In this case, a configuration space itself could be written from the cache or from the processor using a block write operation instead of a smaller write operation such as a DW (or smaller).

[0082] An FCAM cache and restoring a configuration context from it are discussed in more detail below, for example with reference to Fig. 7 and Fig. 9.

[0083] In one embodiment, at least two types of configuration blocks are defined: legacy and pure. In an illustrative example, byte write masks are tracked and sent with write data to legacy block configuration areas, and successive writes are output individually. Additionally, in this example, legacy-compatible configuration registers are implemented within the legacy block. The pure block, on the other hand, may not be able to use byte write masks. Here, combining, merging, collapsing writes, or a combination thereof, is potentially allowed / enabled. Furthermore, implementers may include that some legacy-compatible configuration registers are accessible in both the pure and legacy blocks, provided they meet the requirements for pure block areas. Legacy blocks and pure blocks are further described below, such as in relation to... Fig.12 discussed in more detail.

[0084] In one embodiment, an FCAM-enabled device implements a mirror of the host FCAM cache at an offset address. The FCAM mirror cache can also implement a slow write-through specification that mirrors local updates back to the host.

[0085] In one embodiment, FCAM configuration traffic uses memory write semantics. As a result, some implementations utilize a translation of such memory semantics for legacy PCI / PCIe functions. As a specific illustrative example of the translation, writes function as described above, except that the configuration space for the legacy 622 device is treated as a legacy block, and the memory write semantics are translated into a configuration write operation, such as a legacy configuration write; and read operations are not served from the FCAM cache and passed through to the legacy 622 device.In one scenario, FCAM-enabled devices identify themselves by using a unique message such as a message mechanism in the form of a Device Ready Status (DRS) or Functional Ready Status (FRS) or a message mechanism in the form of a Configuration Base Address Register (CBAR).

[0086] As mentioned above, a fast configuration CAM (FAST CAM) mechanism can be implemented for conventional non-integrated functions / devices as well as for integrated functions / devices, such as those found in a system-on-a-chip (SoC). For the discrete implementation, i.e., when a function is not integrated, an exemplary protocol mechanism is now described. Here, the FCAM mechanisms operate using memory writes to specific addresses, such as a range allocated to the function by a Configuration Base Address Register (CBAR) and another range on the host / root-root complex 610, which can be located anywhere in memory. In one embodiment, the CBAR address range is determined using a message from the host 610 sent in response to a message sent by the device to self-identify as FCAM-enabled.When the exemplary write protocol is followed, the CBAR range is set sequentially and is not delayed for extended periods. Furthermore, updates from the device to the host range trigger a notification to the host software, such as a break, a trigger to return from a wait state (MWAIT), or another known mechanism. Additionally, some implementations provide a notification mechanism to trigger an action upon a CBAR update.

[0087] With reference to Fig.Figure 7 illustrates an embodiment of a controller for configuring elements of an intermediate interconnect architecture. In one embodiment, the controller 705 includes a root controller. Similarly, the controller 705 can be referred to as a root complex, a host, a host bridge, or by another name for a high-level hierarchical element that often acts as a collection point for root aspects of a PCIe architecture. As a specific illustrative example, the root controller 705 includes a memory controller, which may or may not be integrated into a processor or a system-on-a-chip (SoC). The controller 705 can also be an I / O controller intended to be coupled with I / O devices. Or, the controller 705 can be a logic block on an SoC for interacting with an integrated endpoint device 735.

[0088] Interface logic 715, 716, and 717 comprises logic for interacting with elements such as PCIe devices, bridges, functions, and endpoints. In its most basic form, interface logic 715 includes a physical layer interface for coupling with the aforementioned devices. However, as mentioned above, the 705 controller can include a layer stack for communicating with devices. It is important to note that each layer can be based on the same or different specifications. For example, a protocol layer, a data link layer, and the physical layer (PHY layer) can be based on one or more PCIe specifications. Alternatively, at least part of the PHY layer can be based on a MIPI PHY specification, such as the MPHY specification, while the remaining layers are based on PCIe.As a result, an intermediate interconnect architecture can be PCIe protocol-compatible, meaning it can be essentially compliant with one or more PCIe protocol definitions, even though these protocols are implemented over a physically differently defined interface. Some examples of physical interfaces include: a low-power PHY specification, a Mobile Industrial Peripheral Interface (MIPI) PHY specification, a PCIe PHY specification, and a higher-performance, high-power PHY specification. However, since one goal of the layers is to abstract their internal workings from each other, any known PHY interface can be used. Furthermore, the FCAM can be used in a different protocol or data link layer adaptation that is not PCIe, as described in more detail below.

[0089] Fig.Figure 7 also illustrates several elements that may include a device, a function, a switch, a bridge, a PCIe device capable of recognizing a variety of protocol communication defined by the PCIe specification, a non-PCIe device incapable of recognizing a variety of protocol communication defined by the PCIe specification, or any other known I / O device. As an example, it illustrates... Fig. 7. A Switch 725 with a legacy translator, as described herein. As a result, assuming a Device 735 is a legacy feature, the Switch 725 performs the legacy translation of memory write semantics to configuration writes and of memory read semantics to configuration reads to ensure backward compatibility. In this scenario, Devices 726 and 727 include FCAM support.

[0090] The controller 705 includes an FCAM block 710. In one embodiment, the FCAM block 710 includes hardware to support a rapid configuration mechanism for efficiently configuring the devices 725, 726, 727, and 735. It should be noted that in some embodiments, the FCAM block 710 may also include co-located code intended to be executed locally to perform certain operations to support rapid configuration.

[0091] In the illustrated embodiment, the FCAM block 710 comprises a configuration control logic 711 and a configuration memory 712. Although the configuration memory 712 is shown as a single logical block, it is not limited to this. In fact, it can consist of several separate memory elements that are not arranged together. As a specific illustrative example, the configuration memory 712 can include: a register to store a base address for a configuration space; a cache to temporarily store write operations and, in conjunction with the control logic 711, to implement the memory write semantics for the configuration; and a memory / cache for the configuration context information itself. It should be noted that one or a combination of these elements can be contained within the controller 705 as the configuration memory 712.However, to simplify the discussion, each of the aforementioned examples of configuration storage will be discussed separately below.

[0092] As a first example, configuration memory 712 includes a cache for serving host processor configuration requests. Instead of a host processor initiating a configuration write or other write operation and waiting for it to complete (update in the endpoint device and completion message), the processor can initiate a memory write and rely on FCAM block 710 to provide immediate completion. This allows the host processor to continue execution while FCAM block 710 serves the memory write as a write to a device configuration register / configuration space. In other words, the cache temporarily stores the host-initiated configuration write, resulting in faster completion from the host's perspective.In this embodiment, the configuration registers of the device 726 are mapped to a configuration space in memory, and a write operation to a specific configuration register in the device 726 addresses a memory address within the configuration space in memory that is to be assigned to the respective configuration register. When the write operation to the memory address is performed, the cache temporarily stores the write operation, provides a completion to the host, and then delivers the write operation to the respective configuration register that is mapped to the memory address of the write operation. Furthermore, the cache can provide other enhancements, such as combining, merging, and collapsing write operations.

[0093] As another example, let's say configuration memory 712 holds a reference to a configuration context. A reference to a configuration context, in this example, refers to a reference to where the configuration space is located. In this example, the reference can be a memory address, a pointer, or any other known reference to a location for a configuration space. Here, an address register, such as a base address register, can hold an address reference to a memory-mapped configuration space to be assigned to the element, such as address spaces 626 from... Fig.6. In another embodiment, a reference to a configuration context refers to a location where a cached copy of the configuration context is held, such as a memory location or other location. Or, in a further embodiment, a reference to a configuration context includes a reference that associates the configuration context with the device to which it is associated. For example, suppose that the configuration memory 712 holds a cache configuration context for the device 726 while the device 726 is in a low-power state; then, in this embodiment, a reference to the configuration context includes the configuration context itself in the memory 712 and the reference, such as a device ID, index, header, etc., that associates the context of the device 726 in the configuration memory 712.

[0094] As another example, the configuration memory is intended to maintain the configuration context. As described here, a configuration space potentially adheres to a defined template for information. And if a device, such as device 726, enters a low-power state, the configuration space information can be lost. As a result, in one embodiment, this configuration space information is cached so that it can be restored when device 726 returns to an active state. The context information stored in the cache can be located anywhere. Therefore, in one embodiment, configuration memory 712 maintains a reference to where the cached copy of the configuration space is stored. As another example, suppose device 726 is FCAM-enabled and switch 725 contains an FCAM cache.The FCAM cache in the Switch 725 can hold a cached copy of the configuration space of the Device 726. Upon a request to re-enter an active power state, the Controller 705 can provide this cached copy to recreate the configuration space for the Device 726.

[0095] In another embodiment, configuration memory 712 holds the configuration context for a device such as function 726. As a result, in this scenario, when device 726 enters a low-power state, the configuration space (or at least a portion of it) is stored in configuration memory 712. In other words, the configuration data for device 726 (either integrated or discrete) is written to configuration memory 712, and then device 726 enters a low-power state. Upon re-entry into an active state, the configuration context for device 726 is available without requiring a processor to rewrite configuration information using legacy configuration write operations.Consequently, the device 726 can be started up and shut down using the FCAM block 710 without direct intervention or access from a host processing device such as the processor 605. Fig. 6. This can happen very quickly.

[0096] As mentioned above, in one embodiment, a configuration context encompasses a state for several configuration space parameters for an element such as the device 726. As a result, the context can hold values ​​for the registers and parameters of the device 726; some of these are described herein, for example, in relation to the configuration space template with the legacy and rein blocks. In one embodiment, the configuration data includes data from configuration registers within the device 726.

[0097] As also mentioned above, in one embodiment, saving or restoring context (e.g., providing / writing context from a cache copy) is performed in response to a power event. A power event may involve an actual change in voltage or power. In other embodiments, however, a power event refers to a state change, a requested state change, or a transition phase between states, such as a change in a link state (e.g., a transition from one link state machine state to another, or into / out of a defined power state). In the case of saving or restoring context, the power event may involve entering (or indicating an entry, such as requesting an entry into) a low-power state, such as a sleep state (RTD3).To restore or deliver context from a cache copy, such as in cache 712, the cache control logic 711 can initialize or deliver the context in response to an entry (or indication of entry, such as a request for entry) into an active performance state. Other examples of a performance event include an indication that the element should enter an active performance state, an indication that the element should complete link training, an indication that the element should complete another phase of link initialization or operation, or an indication that the link should transition between link states.In one embodiment, an active power state with respect to a configuration context is one that is defined as having an active configuration space, and a sleep or low-power mode is one in which configuration space information is stored elsewhere due to a possible loss of data or power.

[0098] Although the blocks of Fig.Although the 7 blocks are depicted as logically separate and distinct, the actual implementation may not be so pronounced, and instead, the boundaries of the blocks may overlap or be integrated on the same device. As an illustrative example, all blocks (the 705 controller and the 725, 726, 727, and 735 devices) are integrated on a single chip as a system-on-a-chip (SoC). Here, the SoC may be contained within a system such as a mobile device with standardized voice communication capabilities or a non-mobile device that may or may not have voice communication capabilities. As another example, the 705 controller and the 726 and 727 devices are together on an integrated circuit, while the 725 switch and the 735 device are discretely coupled to the integrated circuit. Furthermore, all devices may be discretely separated.Furthermore, logic blocks, such as 711 and 712, can be nested with each other and with other blocks, such as the interface logic blocks 715, 716, and 717. In this example, the cache or the logic for performing FCAM operation can be contained within the layered stack logic of the interconnect architecture.

[0099] As a result, the FCAM block 710 potentially enables: the application of fast configuration to both integrated and discrete intermediate interconnect devices, reduced sleep resumption latencies by reducing host interventions and architectural constraints, concurrent and independent threads of non-block configuration activities, and complete virtualization of I / O devices including full support for feature extensions and legacy compatibility mechanisms for existing software and hardware.

[0100] Fig.Figure 8 illustrates an embodiment of a protocol diagram for configuring a memory element using memory accesses from a host device. Here, a host 805, such as a processing element, configures a device 815. The host 805 performs a write operation 821 targeting the device 815. As a first example, the write operation 821 includes a configuration write. Alternatively, the write operation 821 includes a memory write with memory write semantics. In the latter case, a memory write operation 821 can target a device 815 by using a memory write address that references a memory address which, as shown, is associated with a configuration space for the device 815 and possibly a specific configuration register within the device 815.

[0101] Controller 810 receives the write operation 821. This reception can occur over any connection. In one implementation, Controller 810 is a controller hub integrated onto Processor 805. As a result, message 821 is received via an intermediate connection on the chip. However, Controller 810 can also be located outside of Host 805, causing message 821 to be transmitted and received via an intermediate connection outside of Host 805.

[0102] In one embodiment, the controller 810 initiates and transmits a message 822 to the device 815. The example above continues, in which a write operation has an intended target of a configuration register within the device 815. The write operation 822 can take the form of a legacy configuration write operation or an ECAM-like write operation to a configuration space or the device register to update the register with a configuration value from the write operation 821.

[0103] In one scenario, terminations 823 and 824 are sent back to host 805 and controller 810, respectively. As can be seen here, there is a possible delay (hereinafter referred to as the host configuration termination delay) between the transmission of message 821 from host 805 and the receipt of termination 824 at host 805.

[0104] With reference to Fig.Figure 9 shows an embodiment of configuration logic for fast device configuration. In one embodiment, an FCAM block comprises 910 blocks for accelerating the configuration, such as potentially reducing the host configuration completion delay described above and reducing the latency for configuring functions, etc.

[0105] Similar to the discussion above, configuration storage can take many forms, such as storage for holding a reference to a configuration space for a function, storage for holding a reference to a configuration context, storage for holding configuration writes, or a combination thereof. At least two types of configuration storage are in Fig.Figure 9 is provided for illustration. The FCAM block 910 includes a base address register 911 for holding a base address for a configuration space to be assigned to a function.

[0106] As a second example, a Cache 913 is provided. The Cache 913 can hold a reference to a configuration context (a configuration space, a memory location for the configuration context, or the configuration context itself), or it can act as a cache or buffer to support read / write semantics for the device configuration.

[0107] As a specific example, let's say cache memory 913 holds a reference to a configuration context for a device. It's clear from the discussion above that this could be a reference to a location of a configuration space, a location of a configuration context for a configuration space, a reference to a device / function that has a cached configuration context associated with it, the configuration context itself, or a combination thereof.

[0108] Additionally, in one embodiment, the cache 913 is intended to support the memory access semantics for the configuration of devices / functions. Here, an access is made from a host device and buffered (or temporarily stored) in the cache 913. Furthermore, a control logic 912 is intended to handle the access, e.g., to provide access to the corresponding location in the correct form and potentially to deliver a completion to the host without a completion from the target device. This example is further described with quick reference to Fig. Figure 10 shows an embodiment of a protocol diagram for quick configuration of an element.

[0109] Here, a memory access 1021, such as a write operation to a memory address targeting a configuration register in device 1015, is transmitted to a controller 1010. Controller 1010 delivers the write operation to device 1015 in an acceptable format, for example, as a write operation recognizable by device 1015 to update the associated configuration register with a new value from access 1021. In this scenario, cache 913 can be used to buffer the write operation. Additionally, controller 1010 sends a completion message back to host 1005 in parallel (i.e., without a completion message from device 1015 referencing write operation 1022, or at least partially at the same time in transit or processing as message 1022).

[0110] How does it compare to Fig.As can be seen in Figure 8, the configuration of a register with the device 1015 is shown in Fig. From the perspective of host 1005, this is accelerated in that it quickly (and possibly immediately) receives a completion from controller 1010 without waiting for the delayed completion 824 in Fig. wait for 8, which occurs in response to the completion of the write operation 822.

[0111] With renewed reference to Fig.9. Read operations from the configuration space can also be accelerated. For example, a read access can be performed by a host device. And if a current copy is held in the cache 913, then the read operation can be performed by the controller without accessing the memory or the device to obtain the current data value. As a result, in one embodiment, the cache memory 913 is intended to be coherent with one or more processor caches. However, in another embodiment, the cache memory 913 is not coherent with one or more processor caches. Yet in some implementations, the cache 913 is consistent with the configuration state of the associated device. For example, in some implementations, the cache 913 is implemented behind a bridge, where it is consistent with a device configuration state but not coherent with a processor cache.

[0112] All other known buffering specifications or algorithms can be used for the controller 912 and the cache 913. For example, the controller 911 and the cache 913 can implement a write-through, a write-back, or any other known buffering algorithm.

[0113] In an example where a cache is used to hold configuration values ​​(either as a buffer for configuration accesses or to hold configuration context), a controller and the FCAM block 910 are able to map a memory address to a configuration register, receive an access to the memory address, hold / store a configuration value for the register in the cache 913, and translate the memory access from the host processing device to the memory address into a configuration request for the configuration register in a first configuration mode such as an extended configuration access mechanism mode.Furthermore, the controller, or a downstream component such as a switch or bridge, is able to deliver a configuration value held in Cache 913 to the configuration register in a second configuration mode, such as Fast Configuration Access (FCAM), without a memory access from the host processing device. It is important to note that in FCAM mode, a host processing device can perform a memory access, which the controller caches and delivers to the device while providing accelerated completion (as described above). However, in FCAM mode, the same memory access from the host processing device is not necessary to restore a configuration context stored either in Cache 913 or in another component.

[0114] With reference to Fig.Figure 11 shows an embodiment of a protocol diagram for a device to indicate quick configuration capability. For example, a device can identify itself as FCAM-capable. As shown, a link can perform training (120), such as link training or another phase / state transition. A device (1115) then sends a message (1125) to indicate that it is FCAM-capable. For example, message (1125) includes a DRS or DRS0-type message. Alternatively, message (1125) includes a Configuration Base Address Register (CBAR) message to indicate readiness for configuration, which can be in addition to or instead of a DRS message used to specify a CBAR location.Upon receiving message 1125, the controller 1110 is then able to configure the device 1115, sometimes without direct host intervention, using an FCAM or CBAR mechanism. In some cases, to support legacy compatibility, a root complex 1110 (or switch) may be prevented from issuing configuration requests for a period of time (e.g., a range of 1 ms to 500 ms, and a specific value such as 100 ms) following a performance event such as a reset. However, if a DRS or CBAR message indicating FCAM capability is received during this period, configuration 1130 can begin immediately without further waiting.

[0115] Next, with reference to Fig.Figure 12 illustrates an embodiment of a configuration space for an element in an intermediate interconnect architecture. As shown, a configuration space 1205, such as a configuration base address space or a data structure, therefore comprises a legacy block 1210 and a rein block 1215. Here, write operations to the legacy block 1210 potentially include read / write byte selections nested with data, as shown in the exemplary format for block 1210. As shown, a format of block 1210 includes a header 1211, masks 122, and the data 1213a-g, which, for example, contain double words. Furthermore, in one embodiment, write operations to the legacy block 1210 are performed in increasing order of addresses, ensuring that side effects are handled appropriately.

[0116] In one embodiment, the Rein block 1215 does not include read / write byte selections; although it can in an alternative embodiment. Bit definitions for the Rein block 1215 can be set in such a way that block-level side effects are safe. However, it may still be advantageous to perform writes in increasing address order. In one embodiment, the configuration logic in a controller and the logic in the device are able to support combining and merging writes to the Rein block 1215.

[0117] Fig.Figure 13 illustrates an embodiment of a flowchart for a procedure to configure a device. It should be noted from above that any of the protocol flows or operations performed by the logic described here can be represented as a procedure. As an example, although the discussion of Fig. Section 10 refers to a host, a controller, and a device for transmitting protocol messages; the message transmission (i.e., message 1021 and the termination 1023 in response to message 1021) can also be represented as a procedure. Conversely, any procedure described herein can be implemented in a similar manner in a device.

[0118] In the described procedure of Fig.In a flow 1305, a specific message is received from a device indicating Quick Configuration Compatibility (FCAM). As described above, the message may contain a DRS-like message or a CBAR message. A CBAR message can reference a location (i.e., a base address) used to update a CBAR in a controller. Then, in a flow 1310, a device is configured in response to receiving the message. In one embodiment, such device configuration involves restoring a configuration context. This involves receiving an FCAM-enabled message. Then, when the device enters sleep mode, it stores the configuration context in a structure such as a cache.Then, when the device enters an active power mode, a controller can directly configure it based on the configuration context stored in the cache and the device's FCAM capability. Alternatively, upon a reset or power-on, a controller can immediately configure the device in response to receiving an FCAM-enabled message. Either way, one or more configuration registers of an FCAM-enabled device can be updated or configured.

[0119] In one embodiment, configuring the device in sequence 1310 comprises a first memory write operation to the configuration address space and initiating a second memory write operation to a root complex memory space, which is said to be a controller to the configuration address space.

[0120] With reference to Fig.Figure 14 shows an embodiment of a low-power computing platform. In one embodiment, a low-power computing platform 1400 comprises a user device (UE) or a mobile terminal. In some embodiments, an UE refers to a device that can be used for communication, such as a device with voice communication capabilities. Examples of an UE include a telephone and a smartphone. However, a low-power computing platform can also refer to any other platform for achieving a low-power operating point, such as a tablet, a low-power notebook, an ultra-portable or ultra-thin notebook, a microserver, a low-power desktop computer, a transmitting device, a receiving device, or any other known or available computing platform that is not a mobile terminal.The platform presented represents a number of different interconnects for coupling several different devices. An exemplary discussion of these interconnects is provided below to offer options for implementing and integrating the devices and methods disclosed herein. For example, each of the interconnect protocols shown and discussed can implement a quick-configuration mechanism similar to the discussion above regarding the PCIe architecture, without necessarily implementing the PCIe architecture itself. However, a low-power computing platform 1400 need not include or implement the interconnects or devices shown. Furthermore, it may include other devices and interconnect structures not specifically shown.

[0121] Starting from the center of the diagram, Platform 1400 includes an Application Processor 1405. This often includes a low-power processor, which may be a version of a processor configuration described herein or known in the industry. For example, Processor 1400 may be implemented as a system-on-a-chip (SoC). As a specific illustrative example, Processor 1400 includes an Intel® Architecture Core™-based processor, such as an i3, i5, i7, or other such processor available from Intel Corporation, Santa Clara, California. However, it is understood that other low-power processors are also available, such as those from Advanced Micro Devices, Inc. (AMD), Sunnyvale, California, or a MIPS-based design from MIPS Technologies, Inc., Sunnyvale, California, or an ARM-based design from ARM Holdings, Ltd.The technology is licensed, or its customers, or their licensees or adopters, may instead be present in other embodiments such as an Apple A5 / A6 processor, a Qualcomm Snapdragon processor, or a TI OMAP processor. It should be noted that as the processor and SoC technologies of these companies continue to evolve, more components shown separately from the Host Processor 1400 may be integrated onto a single SoC. As a result, similar intermediate interconnections (and inventions therein) may be used "on the chip."

[0122] In one embodiment, the 1405 application processor runs an operating system, a user interface, and applications. Here, the 1405 application processor often recognizes or is associated with an instruction set architecture (ISA) that the operating system, user interface, and applications use to control the operation and execution of the 1405 processor. It also typically interacts with sensors, cameras, displays, microphones, and mass storage devices. Some implementations offload time-critical telecommunications-related processing to other components.

[0123] As shown, the host processor 1405 is paired with a wireless interface 1430 such as WLAN, WiGig, WirelessHD or another wireless interface. An intermediate connection compatible with LLI, SSiC or UniPort is used to pair the host processor 1405 and the wireless interface 1430.

[0124] LLI stands for Low Latency Interface. LLI typically enables shared memory between two devices. A bidirectional interface transports memory transactions between two devices and allows one device to access the local memory of another; often this is done without software intervention, as if it were a single device. In one embodiment, LLI allows three traffic classes to carry signals over the interface, reducing the GPIO number. For example, LLI defines a protocol stack for communication or a physical layer (PHY), such as an MPHY, which is described in more detail below.

[0125] SSIC stands for SuperSpeed ​​Inter-Chip. SSIC enables the design of high-speed USB devices using a low-power physical layer. For example, an MPHY layer is used, while USB 3.0-compatible protocols and software are used over the MPHY for improved performance.

[0126] UniPro describes a layered protocol stack with physical layer abstraction that provides a general-purpose, high-speed, error-handling solution for interfacing a wide range of devices and components: application processors, coprocessors, modems, and peripherals. It also supports various types of traffic, including control messages, bulk data transmission, and packetized streaming. UniPro can support the use of an MPHY or DPHY.

[0127] Other interfaces can also couple directly with the host processor 1405, such as a fault correction unit 1490, a network unit 1485, a display unit 1470, a camera unit 1475 and a memory unit 1480 through other interfaces that can utilize the facilities and procedures described here.

[0128] The error correction interface 1490 and the network 1485 communicate with the application processor 1405 through an error correction interface 1491, e.g. PTI, or a network connection, e.g. an error correction interface that operates via a functional network connection 1485.

[0129] The display 1470 comprises one or more displays. In one embodiment, the display 1470 comprises a display with one or more touch sensors capable of receiving / detecting touch inputs. In this embodiment, the display 1470 is coupled to the application processor 1405 via a Display Interface (DSI) 1471. The DSI 1471 defines protocols between the host processor and peripheral devices that can utilize a physical D-PHY interface. It typically accepts pixel formats and a defined instruction set for video formats and signaling, such as Display Pixel Interface 2 (DPI-2), and control display module parameters, such as those provided by a Display Command Set (DCS). As an example, the DSI 1471 operates at approximately 1.5 Gb / s per lane or at 6 Gb / s.

[0130] In one embodiment, the camera 1475 includes an image sensor used for still images, video recording, or both. Front- and rear-facing cameras are common in mobile devices. Stereo cameras can be used to provide stereoscopic support. As shown, the camera 1475 is coupled to the application processor 1405 via a peripheral interface, such as a CSI 1476. The CSI 1476 defines an interface between a peripheral device (e.g., camera, image signal processor) and a host processor (e.g., 1405, baseband, application engine). In one embodiment, image data transmissions are carried out via a DPHY, a unidirectional differential serial interface with data and clock signals. In one embodiment, the peripheral device is controlled via a separate return channel, such as the camera control.As an illustrative example, the speed of the CSI can range from 50 Mbps to 2 Gbps, or take any range / value within that range.

[0131] In one example, the 1480 memory comprises non-volatile memory used by the 1405 application processor to store large amounts of information. It can be based on flash technology or a magnetic storage medium such as a hard disk. Here, the 1480 is coupled to the 1405 processor via a Universal Flash Memory Intermediate (UFS Intermediate) 1481. In one embodiment, the UFS 1481 includes an intermediate tailored for low-power computing platforms such as mobile systems. For example, it offers transfer rates between 200 and 500 MB / s (e.g., 300 MB / s), using queuing functions to increase random read / write speeds. In one implementation, the UFS 1481 uses the MPHY physical layer and a protocol layer such as UniPro.

[0132] Modem 1410 typically stands for modulator / demodulator. The Modem 1410 usually provides the interface to the mobile network. It is capable of communicating with various network types and frequencies, depending on the communication standard used. In one embodiment, both voice and data connections are supported. The Modem 1410 is coupled to the Host 1405 using some known intermediary connection such as LLI, SSiC, UniPro, Mobile Express, and / or similar.

[0133] In one embodiment, a control bus is used to couple control or data interfaces, such as for wireless communication 1435, the loudspeaker 1440, and the microphone 1445. An example of such a bus is SLIMbus; a flexible, low-power, multi-drop interface capable of supporting a wide range of audio and control solutions. Other examples include PCM, I2S, I2C, SPI, and UART. Wireless communication 1435 comprises an interface such as a short-range communication standard between two devices (e.g., Bluetooth or NFC), a navigation system capable of triangulating position and / or time (e.g., GPS), a receiver for analog broadcasts or radio transmissions (e.g., FM radio), or another known wireless interface or standard.The one or more loudspeakers 1440 comprise any device for generating sound, such as an electromechanical device for producing ringtones or music. Multiple loudspeakers can be used for stereo or multi-channel sound. The microphone 1445 is often used for voice input, such as speaking during a call.

[0134] An integrated radio frequency integrated circuit (RFIC) 1415 is designed to perform analog processing such as amplification, mixing, filtering, and digital conversion of radio signals. As shown, the RFIC 1415 is coupled to the modem 1410 via the interface 1412. In one embodiment, the interface 1412 comprises a bidirectional high-speed interface (e.g., DigRF) that supports communication standards such as LTE, 3GPP, EGPRS, UMTS, HSPA+, and TD-SCDMA. As a specific example, DigRF uses a frame-oriented protocol based on an M-PHY physical layer. DigRF is typically described as an RF-friendly interface with low latency, low power consumption, and an optimized pin count, currently operating at between 1.5 or 3 Gbps per lane and configurable with multiple lanes, such as four lanes.

[0135] An interface 1461 (for example, an RF control interface) comprises a flexible bus for supporting simple to complex devices. As a specific example, the interface 1461 comprises a flexible two-wire serial bus designed for controlling RF front-end components. A bus master can write to and read from multiple devices, such as a power amplifier 1450 for amplifying the RF signal, sensors for receiving sensor inputs, switching modules 1460 for switching between RF signal paths depending on a network mode, and antenna tuners 1465 for compensating for poor antenna conditions or improving bandwidth. In one embodiment, the interface 1461 includes a group triggering function for time-critical events and low EMI.

[0136] An energy management unit 1420 is used to supply all the various components in the mobile device 1400 with managed voltage. For example, the voltage is reduced or increased to improve the efficiency of components in the mobile device. In one embodiment, it also controls and monitors the battery's state of charge and remaining energy. A battery interface can be used between the energy management unit 1420 and the battery. As a concrete example, the battery interface includes one-wire communication between a mobile device and smart / low-cost batteries.

[0137] With reference to Fig. Figure 15 shows a block diagram of an embodiment of a multi-core processor. As in the embodiment of Fig.The 1500 processor comprises several domains. Specifically, a 1530 core domain comprises multiple 1530A-1530N cores, a 1560 graphics domain comprises one or more graphics engines, including a 1565 media engine, and a 1510 system agent domain comprises several domains. A quick configuration mechanism, as disclosed herein, can be implemented to configure an integrated device / function such as the 1565 graphics engine or other agents. Note that in some implementations, the 1510 system agent can act as the root controller or complex, while the 1530 cores comprise a host processing device.

[0138] In various embodiments, the system agent domain 1510 handles power control events and energy management, allowing the individual units of domains 1530 and 1560 (e.g., cores and / or graphics engines) to be controlled independently. This enables them to dynamically operate in an appropriate power mode / level (e.g., active, turbo, sleep, idle, deep sleep, or other state according to the advanced configuration of the power interface) based on the activity (or inactivity) occurring in the given unit. Each of domains 1530 and 1560 can operate at a different voltage and / or power, and furthermore, the individual units within each domain can potentially operate at an independent frequency and voltage.It should be noted that, although only three domains are shown, it is obvious that the scope of protection of the present invention is not limited in this respect and that further domains may be present in other embodiments.

[0139] As shown, each core includes 1530 further low-level caches in addition to the various execution units and additional processing elements. The different cores are interconnected and linked to a shared cache memory formed from multiple units or sections of a last-level cache (LLC) 1540A-1540N; these LLCs often include memory and cache controller functionality and are shared among the cores and potentially with the graphics engine.

[0140] As can be seen, a ring connection 1550 couples the cores together and provides an intermediate connection between the core domain 1530, the graphics domain 1560, and the system agent circuit 1510 via several ring stations 1552A-1552N, each with a coupling between a core and an LLC section. As shown in Fig.As can be seen in Figure 15, the intermediate interconnect 1550 is used to carry various pieces of information, including address information, data information, acknowledgment information, and espionage / invalidation information. Although a ring interconnect is shown, any known on-chip intermediate interconnect or fabric can be used. As an illustrative example, some of the fabrics discussed above (e.g., another on-chip intermediate interconnect, an Intel On-Chip System Fabric (IOSF), an intermediate interconnect based on an Advanced Microcontroller Bus Architecture (AMBA), a multidimensional mesh fabric, or another known intermediate interconnect architecture) can be used similarly.

[0141] As further described, the system agent domain 1510 comprises a display engine 1512, which provides control for and an interface to an associated display. The system agent domain 1510 may include other units, such as an integrated memory controller 1520, which provides an interface to system memory (for example, DRAM implemented with multiple DIMMs); ​​and coherence logic 1522 for performing memory coherence operations. Multiple interfaces may be provided to enable an intermediary connection between the processor and other circuitry. For example, in one embodiment, at least one Direct Media Interface (DMI) 1516 and one or more PCIe interfaces 1514 are provided. The display engine and these interfaces typically couple to the memory via a PCIe bridge 1518.Furthermore, one or more other interfaces (e.g., an Intel® Quick Path Interconnect Fabric (QPI Fabric)) may be provided to enable communication between other agents such as additional processors or other circuits.

[0142] With reference to Fig.Figure 16 next presents an embodiment of a system-on-a-chip (SOC) design in accordance with the inventions. As a specific illustrative example, an SOC 1600 is included in a user device (UE) or mobile terminal. In one embodiment, the UE refers to any device used by an end user to communicate, such as a handset. Often, a UE connects to a base station or node, which in nature is potentially equivalent to a mobile station (MS) in a GSM network. However, the SoC presented can be used in other non-mobile terminals, such as a tablet, an ultrathin notebook, a notebook with a broadband adapter, or any other similar communication device.Within the SoC 1600, a quick configuration mechanism, as described herein, can be used to configure integrated devices such as a GPU 1615, Video 1620, Video 1625, a Flash Controller 1645, an SDRAM Controller 1640, a Boot ROM 1635, a SIM 1630, a Power Controller 1655, a PC 1650, or other logic block. In this context, a controller or other logic within block 1610 can act as a root complex. Furthermore, the quick configuration mechanism can be used to configure devices connected to the MIPI, HDMI, or other ports not shown.

[0143] Here, the SOC 1600 comprises two cores, 1606 and 1607. Similar to the discussion above, cores 1606 and 1607 can conform to an instruction set architecture such as that of an Intel® Core™ architecture-based processor, an Advanced Micro Devices, Inc. (AMD) processor, a MIPS-based processor, an ARM-based processor design, or a customer thereof, as well as their licensees or adopters. Cores 1606 and 1607 are coupled to a cache controller 1608, which is associated with a bus interface unit 1609 and an L2 cache 1610 for communication with other parts of the system 1600. An intermediate interconnect 1610 comprises an on-chip interconnect such as an IOSF, AMBA, or other interconnect discussed above, which potentially implements one or more aspects of the described invention.

[0144] The 1610 interface provides communication channels to other components such as a Subscriber Identification Module (SIM) 1630 for interacting with a SIM card, a Boot ROM 1635 for holding boot code for execution by the cores 1606 and 1607 to initialize and start the SOC 1600, an SDRAM controller 1640 for interacting with external memory (e.g., DRAM 1660), a Flash controller 1645 for interacting with non-volatile memory (e.g., Flash memory 1665), a Peripheral Controller Q1650 (e.g., serial peripheral interface) for interacting with peripheral devices, video codecs 1620 and a video interface 1625 for displaying and receiving input (e.g., touch input), a GPU 1615 for performing graphics-related calculations, etc. Each of these interfaces can incorporate aspects of the invention described herein.

[0145] Furthermore, the system illustrates peripheral communication devices such as a Bluetooth module 1670, a 3G modem 1675, a GPS 1685, and WiFi 1685. It should be noted that, as mentioned above, a UE includes radio for communication. Consequently, not all of these peripheral communication modules are required. However, a UE must include some type of radio for external communication.

[0146] It should be noted that the devices, methods, and systems described above can be implemented in any electronic device or system, as previously mentioned. As specific illustrations, the figures below provide exemplary systems for the use of the invention as described herein. As the systems are described in more detail below, a number of different interconnects are disclosed, described, and revisited from the discussion above. And, as is readily apparent, the advances described above can be applied to any of these interconnects, fabrics, or architectures.

[0147] With reference to Fig.Figure 17 illustrates a block diagram of components present in a computing system in accordance with an embodiment of the present invention. Similar to the discussion above, a quick configuration mechanism can be applied to or coupled with a processor 1710 to configure any of the blocks present in Fig. Figure 17 shows / describes. As shown, a System 1700 comprises any combination of components. These components can be implemented as ICs, parts thereof, discrete electronic devices or other modules, logic, hardware, software, firmware, or a combination thereof designed for a computing system, or as components installed anywhere else within a chassis of the computing system. It should also be noted that the block diagram of Fig.Figure 17 is intended to show a general overview of many components of the computing system. However, it should be understood that some of the components shown may be omitted, additional components may be present, and a different arrangement of the components shown may occur in other implementations. As a result, the invention described above may be implemented in any part of one or more of the intermediate connections illustrated or described below.

[0148] As in Fig.As can be seen in Figure 17, a Processor 1710 in one embodiment comprises a microprocessor, a multi-core processor, a multi-stranded processor, an ultra-low voltage processor, an embedded processor, or other known processing elements. In the illustrated implementation, the Processor 1710 acts as a main processing unit and a central hub for communication with many of the various components of the System 1700. As an example, the Processor 1700 is implemented as a system-on-a-chip (SoC). As a specific illustrative example, the Processor 1710 comprises an Intel® Architecture Core™-based processor, such as an i3, i5, i7, or any other such processor available from Intel Corporation, Santa Clara, California. However, it is understood that other low-power processors, such as those from Advanced Micro Devices, Inc., may also be included.(AMD), Sunnyvale, California, such as a MIPS-based design from MIPS Technologies, Inc. of Sunnyvale, California, an ARM-based design licensed from ARM Holdings, Ltd., or customers thereof or their licensees or adopters may instead be in other embodiments such as an Apple A5 / A6 processor, a Qualcomm Snapdragon processor, or a TI OMAP processor. It should be noted that many customer versions of such processors are modified and varied; however, they may support or recognize a specific instruction set that executes defined algorithms as provided by the processor licensor. In this case, the microarchitecture implementation may vary, but the processor's architectural function is generally constant.Certain details regarding the architecture and operation of the 1710 processor in one implementation are discussed below to provide an illustrative example.

[0149] In one embodiment, the 1710 processor communicates with a 1715 system memory. As an illustrative example, in one embodiment, this memory can be implemented using multiple memory devices to provide a given amount of system memory. For example, the memory can be a low-power, double-rate (LPDDR) design according to the Joint Electron Devices Engineering Council (JEDEC), such as the current LPDDR2 standard according to JEDEC JESD 209-2E (April 2009 edition), or a next-generation LPDDR standard, which will be designated LPDDR3 or LPDDR4, offering extensions to LPDDR2 to increase bandwidth. In different implementations, the individual memory devices can belong to different assembly types, such as a single-chip assembly (SDP), a dual-chip assembly (DDP), or a quad-chip assembly (Q17P).In some embodiments, these devices are soldered directly onto a motherboard to provide a lower-profile solution, while in other embodiments, the devices are configured as one or more memory modules that are coupled to the motherboard via a specific connector. Other memory implementations are also possible, such as other types of memory modules, for example, dual-row memory modules (DIMMs) of various types, including but not limited to microDIMMs and miniDIMMs. In one particular embodiment, the memory is specified between 2 GB and 16 GB and can be configured as a DDR3LM assembly or LPDDR2 or LPDDR3 memory soldered onto a motherboard via a ball grid array (BGA).

[0150] To ensure the persistent storage of information such as data, applications, one or more operating systems, and so on, a 1720 mass storage device can also be coupled with the 1710 processor. In various embodiments, this mass storage device can be implemented via an SSD to enable a thinner and lighter system design and to improve system responsiveness. However, in other embodiments, the mass storage device can be implemented primarily with a hard disk drive (HDD), with a smaller amount of SSD storage acting as an SSD cache to enable non-volatile storage of the context state and other such information during shutdown events, thus allowing for faster boot-up when system activities resume. As also in Fig.As shown in Figure 17, a flash device 1722 can be coupled to the processor 1710, for example, via a serial peripheral interface (SPI). This flash device can provide non-volatile storage of system software, including basic input / output software (BIOS) and other system firmware.

[0151] In various configurations, the system's mass storage is implemented using either an SSD or a disk, optical drive, or other type of drive with an SSD cache. In some configurations, the mass storage is implemented as an SSD or an HDD along with a recovery cache module (RST cache module). In different implementations, the HDD provides storage between 320 GB and 4 terabytes (TB) and more, while the RST cache is implemented using an SSD with a capacity of 24 GB to 256 GB. It should be noted that such an SSD cache can optionally be configured as a single-level cache (SLC) or multi-level cache (MLC) to provide an appropriate level of responsiveness. In an SSD-only option, the module can be located in various locations, such as an mSATA or NGFF slot. For example, an SSD might have a capacity ranging from 120 GB to 1 TB.

[0152] Various input / output devices (I / O devices) can be present within the System 1700. In particular, in the embodiment of Fig.Figure 17 shows a display 1724, which can be a high-definition LCD or an LED array formed in a cover section of the chassis. This display array can provide a touchscreen 1725, which is formed, for example, externally above the display array, so that user input can be supplied to the system via user interaction with this touchscreen to enable desired operations, for example, regarding the display of information, access to information, and so on. In one embodiment, the display 1724 can be coupled to the processor 1710 via a display interface, which can be implemented as a high-performance graphics interface. The touchscreen 1725 can be coupled to the processor 1710 via another interface, which in one embodiment is an I 2 It can be a C-intermediate connection. As further explained in Fig.In addition to the touchscreen 1725, user input can be made by touching a touch field 1730, which can be formed within the chassis, and also with the same I 2 A C-intermediate connection, such as the touchscreen 1725, can be used.

[0153] The display can operate in several modes. In one mode, the display can be in a transparent state, in which it is transparent to visible light. In various embodiments, most of the display, except for a front bezel around its perimeter, can be a display. When the system is operating in notebook mode and the display is in a transparent state, a user can view information displayed on the display while simultaneously seeing objects behind it. Furthermore, information displayed on the display can also be viewed by a user positioned behind it. Alternatively, the display can be in an opaque state, in which visible light is not allowed to pass through it.

[0154] In tablet mode, the system is folded so that the rear display surface of the display field rests in a position facing outwards towards the user when the base plate is resting on a surface or being held by the user. In tablet mode, the rear display surface serves as both a display and user interface, as it can incorporate touchscreen functionality and other familiar features of a conventional touchscreen device, such as a tablet. For this purpose, the display field can include a transparency adjustment layer positioned between a touchscreen layer and a display surface. In some embodiments, the transparency adjustment layer can be an electrochromic (EC) layer, an LCD layer, or a combination of both.

[0155] In various embodiments, the display can be of different sizes, for example an 11.6" or 13.3" screen and a 16:9 aspect ratio and at least 300 cd / m². 2 The display must have sufficient brightness. Additionally, it can have a high-definition resolution (HD resolution, at least 1920 x 1080p), be compatible with an embedded display port (eDP), and be a low-power field with field self-refresh.

[0156] Regarding touchscreen functionality, the system can offer a multi-touch display field capable of supporting multiple touches and at least five fingers. In some embodiments, the display can support up to ten fingers simultaneously. In one embodiment, the touchscreen is housed within a scratch- and impact-resistant combination of glass and a coating (such as Gorilla Glass™ or Gorilla Glass 2™) for low friction to reduce finger burns and prevent finger slippage. To provide an enhanced touch experience and responsiveness, the touch field in some implementations features multi-touch functionality, such as less than two frames (30 Hz) per static view during pinch zoom, and single-touch functionality of less than 1 cm per frame (30 Hz) with a 200 ms delay (finger-to-pointer latency).In some implementations, the display supports edge-to-edge glass with a minimal screen bezel that is also flush with the field surface, and minimal I / O interference when using multi-touch.

[0157] For perception calculations and other purposes, various sensors can be present within the system and can be coupled to the 1710 processor in different ways. Certain inertial and environmental sensors can be connected to the 1710 processor via a 1740 sensor hub, for example, using an I 2 C-intermediate connection, coupled. In the embodiment shown in Fig.As shown in Figure 17, these sensors can include an accelerometer 1741, an ambient light sensor (ALS) 1742, a compass 1743, and a gyroscope 1744. Other environmental sensors can include one or more thermal sensors 1746, which in some embodiments are coupled to the processor 1710 via a system management bus (SMBus).

[0158] The various inertial and environmental sensors integrated into the platform enable a wide range of applications. These applications allow for advanced computing operations, including perceptual calculations, and also enable improvements in energy management / battery life, safety, and system response speed.

[0159] For example, with regard to energy management and battery life issues, the ambient light conditions at a specific location on the platform will be determined, at least in part, based on information from an ambient light sensor, and the display intensity will be controlled accordingly. This will reduce energy consumption when operating the display under certain lighting conditions.

[0160] With regard to security measures, contextual information obtained from the sensors, such as location data, can be used to determine whether a user is authorized to access certain secure documents. For example, a user might be permitted to access these documents at work or at home. However, the user would be prevented from accessing such documents if the platform is located in a public place. In one embodiment, this determination is based on location information obtained, for example, via a GPS sensor or camera recognition of landmarks. Other security measures may include providing a pairing of devices within close proximity to each other, for example, between a portable platform as described herein and a user's desktop computer, mobile phone, or so on.Certain sharing can be achieved in some implementations via short-range communication when these devices are paired in this way. However, if the devices exceed a certain range, such sharing can be blocked. Furthermore, if a platform and a smartphone are paired as described herein, an alarm can be configured to trigger if the devices move beyond a predetermined distance from each other when they are in a public place. Conversely, when these paired devices are in a secure location, such as a workplace or home, the devices can cross this predetermined boundary without triggering such an alarm.

[0161] Responsiveness can also be improved through sensor information. For example, even when a platform is in a low-power state, its sensors can remain active, operating at a relatively low frequency. Accordingly, any changes in the platform's position, such as those detected by inertial sensors, GPS, or similar devices, are recorded. If no such changes are detected, a faster connection to a previous wireless hub, such as a Wi-Fi access point or similar wireless device, is established, as there is no need to search for available wireless network resources. This results in a higher level of responsiveness when waking from a low-power state.

[0162] It is understood that many other use cases may arise using sensor information obtained via the integrated sensors within a platform such as the one described herein, and the examples above are for illustrative purposes only. When using a system such as the one described herein, a perceptual computing system can allow the addition of alternative input types, including gesture recognition, and enable the system to capture user operations and intentions.

[0163] In some embodiments, one or more infrared or other heat detection elements, or any other element for detecting the presence or movement of a user, may be present. Such detection elements may comprise several different elements that work together, operate sequentially, or both. For example, detection elements may include elements that provide initial detection, such as a light or sound projection, followed by gesture recognition detection, for example, by an ultrasonic time-of-flight camera or a structured light camera.

[0164] Furthermore, in some embodiments, the system includes a light generator to produce an illuminated line. In some embodiments, this line provides a visual cue for a virtual boundary with respect to an imaginary or virtual location in space, where an action by the user to cross or break the virtual boundary or plane is interpreted as an intention to interact with the computing system. In some embodiments, the illuminated line can change color as the computing system transitions into different states with respect to the user. The illuminated line can be used to provide the user with a visual cue for a virtual boundary in space and can be used by the system to determine transitions in the computer's state with respect to the user, including determining when the user intends to interact with the computer.

[0165] In some embodiments, the computer detects a user's position and works to interpret the movement of a user's hand across the virtual boundary as a gesture indicating the user's intention to interact with the computer. In some embodiments, when the user crosses the virtual line or plane, the light generated by the light source may change to provide visual feedback to the user that they have entered a gesture-providing area to supply input to the computer.

[0166] Display screens can provide visual indications of state transitions of the computing system with respect to a user. In some embodiments, a first screen is provided in a first state in which the presence of a user is detected by the system, for example, by using one or more of the detection elements.

[0167] In some implementations, the system has the function of capturing the user's identity, for example, through facial recognition. This may involve a transition to a second screen in a second state, where the computer system has recognized the user's identity. In this second state, the screen provides visual feedback to the user that they have entered a new state. A transition to a third screen in a third state, where the user has confirmed their recognition, may also occur.

[0168] In some embodiments, the computing system can use a transition mechanism to determine the position of a virtual boundary for a user, the location of which can vary depending on the user and the context. The computing system can generate a light, such as an illuminated line, to indicate a virtual boundary for interaction with the system. In some embodiments, the computing system can be in a waiting state, and the light can be generated in a first color. The computing system can detect whether the user has crossed the virtual boundary, for example, by detecting the user's presence and movement using the detection elements.

[0169] In some embodiments, when it has been detected that the user has crossed the virtual boundary (such as when the user's hands are closer to the computing system than the virtual boundary), the computing system can transition to a state for receiving gesture input from the user, with a mechanism for indicating the transition potentially including the light indicating the virtual boundary changing to a second color.

[0170] In some embodiments, the computing system can then determine whether a gesture movement is detected. If a gesture movement is detected, the computing system can proceed with a gesture recognition process, which may involve the use of data from a gesture data library that may reside in memory within the computing device or be accessed by the computing device in some other way.

[0171] When a user gesture is recognized, the computing system can execute a function in response to the input and return to receiving additional gestures if the user is within the virtual boundary. In some embodiments, if the gesture is not recognized, the computing system can then enter an error state, with a mechanism for indicating the error state potentially including the light indicating the virtual boundary changing to a third color, and the system returning to receiving additional gestures if the user is within the virtual boundary to interact with the computing system.

[0172] As mentioned above, the system can be designed in other embodiments as a convertible tablet system that can be used in at least two different modes: a tablet mode and a notebook mode. The convertible system can have two panels, namely a display panel and a base panel, so that in tablet mode the two panels are stacked on top of each other. In tablet mode, the display panel faces outwards and can provide touchscreen functionality as found in conventional tablets. In notebook mode, the two panels can be arranged in an open, hinged configuration.

[0173] In various embodiments, the accelerometer can be a 3-axis accelerometer with data rates of at least 50 Hz. A gyroscope, which can also be a 3-axis gyroscope, can also be included. Additionally, an electronic compass / magnetometer may be present. One or more proximity sensors can also be provided (for example, to detect whether a person is near the system when the lid is open and to adjust power consumption or performance accordingly to extend battery life). For some operating systems, sensor data fusion, encompassing the accelerometer, gyroscope, and compass, can provide enhanced functionality. Furthermore, a sensor-activated wake-up mechanism can be implemented via a sensor hub with a real-time clock (RTC) to receive sensor input when the rest of the system is in a low-power state.

[0174] In some embodiments, an internal lid / display opening switch or sensor can be used to indicate whether the lid is open / closed and can be used to place the system into a connected standby state or to automatically wake it from a connected standby state. Other system sensors may include ACPI sensors for internal monitoring of processor, memory, and casing temperature to enable changes to processor and system operating states based on the detected parameters.

[0175] In one embodiment, the operating system can be Microsoft® Windows® 8, which implements a connected standby state (also referred to herein as Win8-CS). The connected standby state of Windows 8, or a similar state provided by another operating system, can, via a platform such as described herein, provide very low ultra-idle power to allow applications to remain connected to, for example, a cloud-based location while consuming very little power. The platform can support three power states: screen on (normal); connected standby (as the default "off" state); and off (zero watts power consumption). Thus, in the connected standby state, the platform is logically on (at minimal power levels) even when the screen is off.With such a platform, energy management for applications can be made transparent and constant connectivity can be maintained, partly due to sleep technology that allows the component with the lowest power consumption to perform an operation.

[0176] In Fig.Figure 17 also shows that various peripheral devices can connect to the processor 1710 via a low-pin-count (LPC) connection. In the embodiment shown, various components can be connected via an embedded controller 1735. Such components can include a keyboard 1736 (connected, for example, via a PS / 2 interface), a fan 1737, and a thermal sensor 1739. In some embodiments, the touch panel 1730 can also connect to the EC 1735 via a PS / 2 interface. Furthermore, a security processor, such as a Trusted Platform Module (TPM) 1738, in accordance with the Trusted Computing Group (TCG) TPM Specification Version 1.2 of October 2, 2003, can also connect to the processor 1710 via this LPC connection.However, it should be understood that the scope of the present invention is not limited in this respect and that secure processing and storage of secure information can take place in a protected location other than a static random access memory (SRAM) in a security coprocessor or as encrypted data blobs that can only be decrypted if protected by a security enclave processor mode (SE processor mode).

[0177] In a given implementation, peripheral ports may include a connector for a High-Definition Media Interface (HDMI) (which may have different form factors such as full-size, mini, or micro); one or more USB ports, such as full-size external ports conforming to the Universal Serial Bus Revision 3.0 (November 2008) specification, with at least one operating to charge USB devices (such as smartphones) when the system is in connected standby mode and plugged into an AC wall outlet. Additionally, one or more Thunderbolt™ ports may be provided. Other ports may include an externally accessible card reader, such as a full-size SDXC card reader and / or a SIM card reader for WWAN (e.g., an 8-pin card reader). For audio, a 3.5 mm jack with stereo sound and microphone capability may be provided.Combination functionality) with support for connection detection (for example, support only for headphones using the microphone in the cover or headphones with a microphone in the cable) may be present. In some embodiments, this jack may be convertible between stereo headphone and stereo microphone input. Additionally, a power connector for connection to an AC outlet may be provided.

[0178] The System 1700 can communicate with external devices in a variety of ways, including wirelessly. In the embodiment shown in Fig.As shown in Figure 17, various wireless modules are available, each of which can correspond to a radio device designed for a specific wireless communication protocol. One type of short-range wireless communication, such as in a near field, can be achieved via a near-field communication (NFC) unit 1745, which in one embodiment can communicate with the processor 1710 via an SMBus. It should be noted that devices in close proximity can communicate with each other via this NFC unit 1745. For example, a user can enable the system 1700 to communicate with another (e.g., a) portable device, such as the user's smartphone, by configuring the two devices to communicate in close proximity, thus facilitating the transmission of information such as identification information, payment information, data such as image data, or the like.Wireless energy transfer can also be carried out using an NFC system.

[0179] Using the NFC unit described herein, users can butt devices side-by-side and place devices for near-field coupling functions (such as near-field communication and wireless power transfer (WPT)) side by side by exploiting the coupling between the coils of one or more such devices. In particular, embodiments provide devices with strategically shaped and arranged ferrite materials to provide improved coupling of the coils. Each coil has an associated inductance that, in conjunction with the resistance, capacitance, and other characteristics of the system, can be selected to enable a common resonant frequency for the system.

[0180] What's next in Fig.As can be seen in Figure 17, additional wireless units can include other short-range wireless engines, including a WLAN unit 1750 and a Bluetooth unit 1752. The WLAN unit 1750 enables Wi-Fi™ communication in accordance with the Institute of Electrical and Electronics Engineers (IEEE) standard 802.11, while the Bluetooth unit 1752 enables short-range communication via a Bluetooth protocol. These units can communicate with the processor 1710 via, for example, a USB connection or a Universal Asynchronous Receiver Transmitter (UART) connection. Alternatively, these units can communicate with the processor 1710 via an intermediate connection according to a PCIe™ protocol, for example, in accordance with the PCI Express™ Base Specification Version 3.0 (published on 17.January 2007) or another such protocol, such as a serial data input / output standard (SDIO standard). Of course, the actual physical connection between these peripheral devices, which may be implemented on one or more expansion cards, can be made via the NGFF connectors adapted to a motherboard.

[0181] Additionally, wireless wide-area communication can be established, for example, according to a cellular or other wireless wide-area protocol via a WWAN unit 1756, which in turn can couple with a subscriber identity module (SIM) 1757. Furthermore, a GPS module 1755 can also be included to enable the reception and use of location information. It should be noted that in the embodiment described in Fig.Figure 17 shows the WWAN unit 1756 and an integrated recording device such as a camera module 1754 via a given USB protocol such as a USB 2.0 or 3.0 connection or a UART or I 2 They can communicate using the C protocol. Again, the actual physical connection of these units can be achieved by adapting an NGFF add-in card to an NGFF connector provided on the motherboard.

[0182] In a particular embodiment, wireless functionality can be provided modularly, for example, with a WiFi™ 802.11ac solution (e.g., an add-on card backward compatible with IEEE 802.11abgn) with support for Windows 8 CS. This card can be located in an internal slot (e.g., via an NGFF adapter). An additional module can provide Bluetooth capability (e.g., Bluetooth 4.0 with backward compatibility) as well as Intel® Wireless Display functionality. Additionally, NFC support can be provided via a separate device or a multifunction device, and can, for example, be located in a right front section of the chassis for easy access. Yet another module can be a WWAN device that can provide support for 3G / 4G / LTE and GPS. This module can be inserted in an internal (e.g., NGFF) slot.Integrated antenna support can be provided for WiFi™, Bluetooth, WWAN, NFC and GPS, enabling a seamless transition from WiFi™ to WWAN radio, Wireless Gigabit (WiGig) in accordance with the Wireless Gigabit Specification (July 2010) and vice versa.

[0183] As described above, an integrated camera can be incorporated into the lid. For example, this camera could be a high-resolution camera, e.g., with at least 2.0 megapixels (MP) and extending to a resolution of 6.0 MP and beyond.

[0184] To provide audio inputs and outputs, an audio processor can be implemented via a digital signal processor (DSP) 1760, which can couple to the processor 1710 via a high-definition audio (HDA) connection. Similarly, the DSP 1760 can communicate with an integrated encoder / decoder (CODEC) and an amplifier 1762, which in turn can couple to the output loudspeakers 1763, which can be implemented within the chassis. Likewise, the amplifier and the CODEC 1762 can be coupled to receive audio input from a microphone 1765, which in one embodiment can be implemented via dual-array microphones (such as a digital microphone array) to provide high-quality audio input for voice-activated control of various operations within the system.It should also be noted that the audio outputs from the amplifier / CODEC 1762 can be supplied to a headphone jack 1764. Although in the embodiment of . Fig. As shown in Figure 17 with these special components, it is obvious that the scope of the present invention is not limited in this respect.

[0185] In one particular embodiment, the digital audio codec and amplifier are capable of driving the stereo headphone jack, the stereo microphone jack, an internal microphone array, and stereo speakers. In various implementations, the codec can be integrated into an audio DSP or coupled to a peripheral controller hub (PCH) via an HD audio path. In some implementations, one or more subwoofers can be provided in addition to the integrated stereo speakers, and the speaker solution can support DTS audio.

[0186] In some embodiments, the 1710 processor can be powered by an external voltage regulator (VR) and several internal voltage regulators integrated within the processor chip, referred to as fully integrated voltage regulators (FIVRs). The use of multiple FIVRs within the processor allows components to be grouped into separate power levels, so that power is regulated and delivered by the FIVR only to the components in the group. During power management, a given power level of an FIVR can be shut down or turned off when the processor enters a specific low-power state, while another power level of a different FIVR remains active or fully powered on.

[0187] In one embodiment, a power maintenance layer can be used during some deep sleep states to supply the I / O pins for several I / O signals, such as the interface between the processor and a PCH, the interface with the external VR, and the interface with the EC1735. This power maintenance layer also supplies an on-chip voltage regulator that supports the onboard SRAM or other cache memory where the processor context is stored during sleep. The power maintenance layer is also used to further power the processor's wake-up logic, which monitors and processes the various wake-up source signals.

[0188] During power management, while other power levels are shut down or turned off when the processor enters certain deep sleep states, the power maintenance level remains on to support the aforementioned components. However, this can lead to unnecessary power consumption or loss when these components are not needed. To address this, embodiments can provide a connected standby sleep state to maintain processor context through a dedicated power level. In one embodiment, the connected standby sleep state facilitates waking the processor using resources from a PCH, which itself may be included in an assembly with the processor.In one embodiment, the connected standby sleep state facilitates the preservation of processor architecture functions in the PCH until the processor wakes up, enabling the shutdown of all unnecessary processor components that previously remained powered on during deep sleep states, including the shutdown of all clocks. In one embodiment, the PCH includes a timestamp counter (TSC) and connected standby logic to control the system during the connected standby state. The integrated voltage regulator for the power maintenance level may also be located on the PCH.

[0189] In one embodiment, during the connected standby state, an integrated voltage regulator can act as a dedicated power plane that remains powered on to support the dedicated cache memory, which stores the processor context, such as critical state variables, when the processor enters deep sleep and connected standby states. This critical state can include state variables related to the architecture, micro-architecture, error correction state, and / or similar state variables associated with the processor.

[0190] The wake-up source signals of the EC 1735 can be sent to the PCH instead of the processor during the connected standby state, so that the PCH manages the wake-up processing instead of the processor. Furthermore, the TSC is retained in the PCH to facilitate the retention of processor architecture functions. Although in the embodiment of Fig. As shown in Figure 17 with these special components, it is obvious that the scope of the present invention is not limited in this respect.

[0191] Power management in the processor can lead to improved energy savings. For example, power can be dynamically allocated between cores, with individual cores able to change frequency / voltage and multiple deep low-power states available to enable very low power consumption. Additionally, dynamic core control or independent core sections can offer reduced power consumption by switching off components when they are not in use.

[0192] Some implementations include a dedicated power management IC (PMIC) to control platform performance. With this solution, a system can experience very low battery degradation (e.g., less than 5%) over extended periods (e.g., 16 hours) when in a specific standby state, such as connected Windows 8 standby. In Windows 8 sleep mode, a battery life of, for example, more than 9 hours can be achieved (e.g., at 150 cd / m²). 2 Regarding video playback, a long battery life can be achieved; for example, full HD video playback can last for at least 6 hours. A platform implementation can have an energy capacity of, for example, 35 watt-hours (Whr) for Win8 CS using an SSD and (for example) 40-44 Whr for Win8 CS using an HDD with an RST cache configuration.

[0193] A specific implementation can support a nominal CPU thermal design power (TDP) of 15 W, with a configurable CPU TDP of up to approximately 25 W. The platform may include minimal openings due to the thermal characteristics described above. Furthermore, the platform is pillow-friendly (as no hot air is blown towards the user). Different maximum operating temperatures can be achieved depending on the chassis material. For a plastic chassis (with at least one plastic top or base section), the maximum operating temperature can be 52 degrees Celsius (C). For a metal chassis, the maximum operating temperature can be 46 °C.

[0194] In various implementations, a security module such as a TPM can be integrated into a processor or be a discrete device, such as a TPM 2.0 device. With an integrated security module, also known as Platform Trust Technology (PTT), the BIOS / firmware can expose certain hardware features for specific security functions, including secure commands, secure boot, Intel® Anti-Theft Technology, Intel® Identity Protection Technology, Intel® Trusted Execution Technology (TXT), and Intel® Manageability Engine Technology, along with secure user interfaces such as a secure keyboard and display.

[0195] Numerous examples are given below. It should be noted that these are merely illustrative. Furthermore, some refer to devices, methods, a computer-readable medium, means, etc. However, any of the examples can be provided or substituted. For instance, one of the representations provides a computer-readable medium containing code that, when executed, performs certain elements. These elements can be considered as elements of a method or logic within a device for performing these elements.

[0196] In one example, a device configuration setup includes: interface logic to be coupled to an element; a configuration store to hold a reference to a configuration context to be associated with the element; and configuration control logic coupled to the configuration store and the second interface, wherein the configuration control logic is to configure at least part of the configuration context to be associated with the element in response to a performance event based on the reference to the configuration context to be held in the configuration store.

[0197] In one example, the interface logic includes physical layer logic based on a physical layer specification (PHY specification) chosen from a group consisting of a low-power PHY specification, a Mobile Industrial Peripheral Interface (MIPI) specification, a Peripheral Component Interconnect Express (PCIe) specification, and a high-performance, high-power PHY specification.

[0198] In one example, the element includes a Peripheral Component Interconnect Express Device (PCIe Device) that is capable of recognizing several communication protocols defined by the PCIe specification.

[0199] In one example, the configuration context includes a state for several configuration space parameters for the element.

[0200] In one example, the configuration memory for holding a reference to a configuration context includes an address register for holding an address reference to a memory-mapped configuration space to be assigned to the element.

[0201] In one example, the device includes a root controller, and the configuration memory includes a cache memory for holding the reference to the configuration context and the configuration context.

[0202] In one example, the cache memory should be coherent with one or more processor caches, which should be contained in a processor that should be coupled with the root controller.

[0203] In one example, the cache memory is not intended to be coherent with one or more processor caches that are to be contained in a processor that is to be coupled with the root controller.

[0204] In one example, the cache memory should implement a write-through specification.

[0205] In one example, the configuration control logic should configure at least part of the configuration context in response to a performance event, if the element is to be further configured without intervention from a host device.

[0206] In one example, the performance event includes a statement that the element should enter an active performance state.

[0207] In one example, the performance event includes a statement that the element should complete a connection training.

[0208] In one example, the interface logic, configuration memory, and configuration control logic are integrated on a system-on-a-chip (SoC) coupled with the wireless interface logic, which is capable of voice communication.

[0209] In one example, the interface logic, configuration memory, and configuration control logic are integrated on an integrated circuit that is coupled into a non-mobile terminal system.

[0210] In one example, a device configuration device comprises: a host processing device; a memory; an integrated device for writing configuration data for the integrated device to memory and for entering a low-power state following the writing of configuration data to memory; and a controller coupled to the host processing device, the integrated device, and the memory, wherein the controller is to configure the integrated device, without direct intervention from the host processing device, at least partially, based on the configuration data to be held in memory in response to the integrated device initiating entry into an active power state.

[0211] In one example, the low power consumption state includes a sleep performance state.

[0212] In one example, the configuration data includes data from configuration registers within the integrated device.

[0213] In one example, the configuration registers are to be mapped to a configuration space in the memory, and a write operation to a specific configuration register within the integrated device is to address a memory address within the configuration space in the memory that is to be assigned to the specific configuration register.

[0214] In one example, a device configuration device comprises the following: a first port for coupling to a host processing device; a second port for downstream coupling to an element, wherein the element is said to comprise a configuration register; a cache for holding a configuration value for the configuration register; and a controller capable of mapping a memory address to the configuration register and translating a memory access from the host processing device to the memory address into a configuration request for the configuration register in a first configuration mode, and wherein the controller is further capable of delivering the configuration value for the configuration register to the configuration register in a second configuration mode without the memory access from the host processing device to the memory address.

[0215] In one example, the first configuration mode includes an Extended Configuration Access Mechanism (ECAM) mode, and the second configuration mode includes a Fast Configuration Access Mechanism (FCAM) ​​mode.

[0216] In one example, the controller is further capable of delivering the configuration value for the configuration register to the configuration register without the memory access from the host processing device to the memory address in a second configuration mode, which involves the controller caching the configuration value to be included in the memory access from the host processing device in the cache; providing a completion for the memory access to the host processing device; and delivering the configuration value from the cache to the configuration register in the element.

[0217] In one example, a device configuration procedure includes: receiving a specific message from a device indicating quick configuration compatibility; updating a configuration register with a reference to a configuration address space for the device in response to receiving the specific message; configuring the device, wherein configuring the device includes initiating a first memory write operation to the configuration address space; and initiating a second memory write operation to a root complex memory space that is said to be orthogonal to the configuration address space.

[0218] In one example, the specific message comprises a pure basic address register message.

[0219] In one example, the specific message includes a Device Readiness Status (DRS) message.

[0220] In one example, a fast device configuration device includes the following: configuration logic capable of supporting combining and merging write operations in a Rein block area comprising one or more Rein configuration registers; a port for coupling to an upstream device; and protocol logic associated with the port, the protocol logic being designed to generate a specific message to indicate fast configuration capability.

[0221] In one example, the specific message comprises a pure basic address register message.

[0222] In one example, the configuration logic is also used to support write operations in a legacy block.

[0223] In one example, the write operations to the legacy block should include read / write byte selections that are nested with data and are to be specified in ascending address order.

[0224] In one example, a non-volatile, computer-readable medium contains code which, when executed, causes the first device to: receive a specific message indicating a quick-configuration capability of a second device; receive a write message from a third device, the write message referencing an address associated with a configuration space of the first device; and initiate a write operation to the configuration space of the first device; and initiate a completion for the write message to the second device without receiving a response from the first device to the write operation to the configuration space of the first device.

[0225] In one example, the first device is an endpoint device and the second device is a host processing device.

[0226] In one example, the first, second, and third devices are contained on a single integrated circuit, along with a memory for holding the code.

[0227] Although the present invention has been described with respect to a limited number of embodiments, numerous modifications and variations thereof are apparent to those skilled in the art. The attached claims are intended to cover all such modifications and variations that fall within the basic concept and scope of the present invention.

[0228] A design can go through several stages, from creation to simulation to fabrication. Data representing a design can represent it in various ways. First, as is useful in simulations, the hardware can be represented using a hardware description language or another functional description language. Additionally, a circuit-level model with logic and / or transistor gates can be created at some stage of the design process. Furthermore, most designs reach a level of data at some stage that represents the physical placement of various devices within the hardware model.In the case where conventional semiconductor fabrication techniques are used, the data representing the hardware model can be data specifying the presence or absence of various features on different mask layers for masks used to create the integrated circuit. In any representation of the design, the data can be stored on any form of machine-readable medium. A memory or magnetic or optical storage medium, such as a disk, can be the machine-readable medium for storing information transmitted via optical or electrical waves, which are modulated or otherwise generated to transmit such information.When an electrical carrier wave is transmitted that displays or carries the code or design, a new copy is made to the extent that copying, buffering, or retransmission of the electrical signal is performed. In this way, a communications provider or network operator can store, at least temporarily, an item such as information encoded in a carrier wave on a tangible, machine-readable medium, embodying the techniques of embodiments of the present invention.

[0229] A module, as used here, refers to any combination of hardware, software, and / or firmware. For example, a module comprises hardware, such as a microcontroller, associated with a non-volatile medium to store code adapted for execution by the microcontroller. Therefore, in one embodiment, a reference to a module refers to the hardware specifically designed to recognize and / or execute the code to be held on a non-volatile medium. Furthermore, in another embodiment, the use of a module refers to the non-volatile medium that contains the code specifically adapted for execution by the microcontroller to perform predetermined operations.As can be deduced, in yet another embodiment the term module (in this example) can refer to the combination of the microcontroller and the non-volatile medium. Often, module boundaries, illustrated as separate, can typically vary and potentially overlap. For example, a first and a second module may share hardware, software, firmware, or combinations thereof, potentially retaining certain independent hardware, software, or firmware. In one embodiment, the use of the term logic includes hardware such as transistors, registers, or other hardware, such as programmable logic devices.

[0230] The use of the phrase "designed to" refers, in one embodiment, to arranging, assembling, manufacturing, offering for sale, introducing, and / or training a device, hardware, logic, or element to perform a designated or specific task. In this example, a device or element thereof that is not operating is still "designed" to perform a designated task if it is designated, coupled, and / or interconnected to perform the said designated task. As a purely illustrative example, a logic gate can output a 0 or a 1 during operation. But a logic gate that is "designed" to provide a enable signal for a clock does not include every potential logic gate that can output a 1 or a 0. Instead, the logic gate is one that is coupled in some way so that, during operation, the output 1 or 0 enables the clock to be enabled.It should be noted again that the use of the expression "designed to" does not require operation, but instead focuses on the latent state of a device, hardware and / or element, wherein in the latent state the device, hardware and / or element is configured to perform a specific task when the device, hardware and / or element is in operation.

[0231] Furthermore, in one embodiment, the use of the terms "capable of" and "operable to" refers to any device, logic, hardware, and / or element configured to enable the use of the device, logic, hardware, and / or element in a specific manner. It should be noted, as above, that in one embodiment, the use of "capable of" and "operable to" refers to the latent state of a device, logic, hardware, and / or element, wherein the device, logic, hardware, and / or element is not operational but is configured to enable the use of a device in a specific manner.

[0232] A value, as used here, encompasses any known representation of a number, a state, a logic state, or a binary logic state. Often, the use of logic levels, logic values, or logical values ​​is also referred to as 1 and 0, which simply represent binary logic states. For example, 1 refers to a high logic level, and 0 refers to a low logic level. In one embodiment, a memory cell, such as a transistor or a flash cell, may be capable of holding a single logic value or multiple logic values. However, other representations of values ​​have been used in computer systems. For example, the decimal number ten can also be represented as the binary value 1010 and the hexadecimal letter A. Therefore, a value encompasses any representation of information capable of being held in a computer system.

[0233] Furthermore, states can be represented by values ​​or parts of values. For example, a first value, such as a logical one, can represent a default or initial state, while a second value, such as a logical zero, can represent a non-default state. Additionally, in one embodiment, the terms reset and set refer to a default and an updated value or state, respectively. For instance, a default value potentially includes a high logic state, i.e., reset, while an updated value potentially includes a low logic state, i.e., set. It is important to note that any combination of values ​​can be used to represent any number of states.

[0234] The embodiments of methods, hardware, software, firmware, or code described above may be implemented by means of instructions or code stored on a machine-accessible, machine-readable, computer-accessible, or computer-readable medium that are executable by a processing element. A non-volatile, machine-accessible / machine-readable medium includes any mechanism that provides (i.e., stores and / or transmits) information in a form readable by a machine, such as a computer or electronic system.For example, a non-volatile machine-accessible medium includes random access memory (RAM) such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; a magnetic or optical storage medium; flash memory devices; electrical, optical, acoustic, or other forms of storage devices that store information from (propagated) volatile signals (for example, carrier waves, infrared signals, digital signals); etc., which must be distinguished from the non-volatile media that can receive information from them.

[0235] Instructions used to program logic for carrying out embodiments of the invention can be stored within a memory in the system, such as DRAM, cache, flash memory, or other storage. Furthermore, the instructions can be disseminated over a network or by means of other computer-readable media. Thus, a machine-readable medium can comprise any mechanism for storing or transmitting information in a form that can be interpreted by a machine (e.g., a computer).The term "computer-readable medium" encompasses, but is not limited to: floppy disks, optical discs, compact discs, read-only storage media (CD-ROMs) and magneto-optical disks, read-only storage media (ROMs), random-access memory (RAM), erasable programmable read-only storage media (EPROMs), electrically erasable programmable read-only storage media (EEPROMs), magnetic or optical cards, flash memory, or any tangible, machine-readable storage medium used in the transmission of information over the internet via electrical, optical, acoustic, or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). Accordingly, "computer-readable medium" includes any type of tangible, machine-readable medium suitable for storing or transmitting electronic instructions or information in a form that can be read by a machine (e.g., a computer).

Claims

[1] Device (705) for device configuration comprising the following: an interface logic (715, 716, 717) that is coupled with an element (725, 726, 727); a configuration store (712) containing a reference to a configuration context associated with the element (725, 726, 727); and a configuration control logic (711) coupled to the configuration memory (712) and a second interface, wherein the configuration control logic (711) configures at least part of the configuration context associated with the element (725, 726, 727) based on the reference to the configuration context contained in the configuration memory (712), wherein the device (705) includes a root controller and wherein the configuration memory (712) includes a cache memory for holding the reference to the configuration context and the configuration context. [2] Device (705) according to claim 1, wherein the interface logic (715, 716, 717) comprises a physical layer logic based on a physical layer specification (PHY specification) selected from a group consisting of a low-power PHY specification, a Mobile Industrial Peripheral Interface (MIPI) specification, a Peripheral Component Interconnect Express (PCIe) specification and a high-performance, high-power PHY specification. [3] Device (705) according to claim 1, wherein the element (725, 726, 727) comprises a peripheral component intermediate connection express device (PCIe device) capable of recognizing multiple communication protocols defined by the PCIe specification. [4] Device (705) according to claim 1, wherein the configuration context comprises a state for multiple configuration space parameters for the element (725, 726, 727). [5] Device (705) according to claim 1, wherein the configuration memory (712) for holding a reference to a configuration context comprises an address register for holding an address reference to a memory-mapped configuration space associated with the element (725, 726, 727). [6] Device (705) according to claim 1, wherein the cache memory is coherent with one or more processor caches which are to be contained in a processor coupled to the root controller. [7] Device (705) according to claim 1, wherein the cache memory is non-coherent with one or more processor caches contained in a processor coupled to the root controller. [8] Device (705) according to claim 1, wherein the cache memory implements a write-through specification. [9] Device (705) according to claim 1, wherein the configuration control logic (711) configures at least a part of the configuration context in response to a performance event. [10] Device (705) according to claim 9, wherein the performance event includes a statement that the element (725, 726, 727) enters an active performance state. [11] Device (705) according to claim 10, wherein the performance event includes a statement that the element (725, 726, 727) has completed a connection training. [12] Device (705) according to claim 1, wherein the interface logic (711), the configuration memory (712) and the configuration control logic (711) are integrated on a system-on-a-chip (SoC) coupled with the wireless interface logic capable of voice communication. [13] Device (705) according to claim 1, wherein the interface logic (715, 716, 717), the configuration memory (712) and the configuration control logic (711) are integrated on an integrated circuit which is coupled into a non-mobile terminal system.

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