REFERENCE ARCHITECTURE IN AN INTERSECTION WORK STORAGE FACILITY

Abstract

Device comprising: a memory controller (104) configured to select a target memory cell (107; 216) for a memory access operation, wherein the target memory cell (107; 216) is configured as a phase-change memory element in a cross-point memory arrangement (106), and the memory controller (104) comprising: a word line (WL) switch circuit arrangement (120; 222, 224) configured to select a global WL (GWL) and local WL (LWL) associated with the target memory cell (107; 216); a bit line (BL) switch circuit arrangement (124; 220) configured to select a global BL (GBL) and local BL (LBL) associated with the target memory cell (107; 216); and a sensing circuit arrangement (122;230), comprising a first sensing circuit assembly capacitor (234) and a second sensing circuit assembly capacitor (236), wherein the sensing circuit assembly is configured to precharge the selected GWL, the LWL and the first sensing circuit assembly capacitor (234) to a WL bias WLVDM, to generate a reference voltage (VREF) using the charge on the selected GWL and the charge on the first sensing circuit assembly capacitor (236) and to determine a state of the target working memory cell, based at least partially on VREF and a detected working memory cell voltage VLWL.;

Description

SPECIALIZATION

[0001] The present disclosure relates to a reference and sensing architecture in a cross-point working memory arrangement. BACKGROUND

[0002] A phase-change memory (WQM) is a working memory device that typically uses a chalcogenide material for its memory elements. A WQM is the unit that actually stores the information. In operation, the WQM stores information on the WQM by switching the WQM's phase between an amorphous and a crystalline phase. The chalcogenide material can have either a crystalline or an amorphous phase, exhibiting low or high conductivity, respectively. Generally, the amorphous phase has low conductivity (high impedance) and is associated with a reset state (logic zero), while the crystalline phase has high conductivity (low impedance) and is associated with a set state (logic one). The WQM can be contained within a WQM cell, which may also contain a selector, i.e., a selector.A selection device coupled to the memory element is included. The selection devices are configured to allow the combination of a large number of memory elements in a single array.

[0003] Phase-change memory elements can be arranged in a cross-point memory configuration, which includes row address lines and column address lines arranged in a grid. The row address lines and column address lines, called word lines (WLs) and bit lines (BLs) respectively, intersect in the formation of the grid, and each memory cell is sandwiched between a WL and a BL, with the WL and BL intersecting at a cross-point. It should be noted that row and column are convenient terms used to provide a qualitative description of the arrangement of WLs and BLs in a cross-point memory.

[0004] During a programming operation, the phase of the memory element can be changed by applying a first bias voltage to the WL and a second bias voltage to the BL, resulting in a differential bias voltage across the memory cell. This differential bias voltage can cause current to flow into the memory element. The differential bias voltage can be maintained across the memory cell for an initial duration sufficient to cause the memory element to "snap back," and then maintained for a second duration to transition the memory element from the amorphous state to the crystalline state, or vice versa. Snapping back is a characteristic of the composite memory element that results in an abrupt change in conductivity and a corresponding abrupt change in voltage across the memory element.

[0005] In a read operation, a target memory cell is selected by applying a first bias voltage to the WL and a second bias voltage to the BL, which intersect at the target memory cell for a time interval. A resulting differential bias voltage at the memory element is configured to be greater than a maximum setting voltage and less than a minimum reset voltage for the memory element. In response, the target memory element may snap back, depending on whether it is in the crystalline state (setting) or the amorphous state (resetting). A sensing circuitry coupled to the memory element is configured to detect the presence or absence of a snapback within a sensing time interval.The presence of a snapback can then be interpreted as a logical one, and the absence of a snapback as a logical zero. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Features and advantages of the claimed subject matter will become apparent from the following detailed description and consistent embodiments, the description being considered with reference to the accompanying drawings, wherein:

[0007] Fig. 1. A system block diagram is illustrated in accordance with several embodiments of the present disclosure;

[0008] Fig. 2A illustrates a part of an intersection point working memory system in accordance with several embodiments of the present disclosure;

[0009] Fig. 2B illustrates an exemplary binary weighted trimmer capacitor circuit arrangement in accordance with an embodiment of the present disclosure;

[0010] Fig. 2C is a simplified sketch illustrating inherent capacitances and a reference voltage adjustment capacitance in accordance with various embodiments of the present disclosure;

[0011] Fig. 3A is a timing diagram showing exemplary memory read operations of the intersection point memory system. Fig. 2A illustrates;

[0012] Fig. 3B is a timing diagram showing exemplary sensing and reference voltages and input voltages to a sensing amplifier for set and reset memory cells for memory read operations of the crosspoint memory system of Fig. 2A illustrates; and

[0013] Fig. 4 A flowchart of operations is illustrated to generate a reference voltage in a crossover working memory in accordance with various embodiments of the present disclosure.

[0014] Although the following detailed description contains references to illustrative embodiments, many alternatives, modifications and variants thereof will be obvious to those skilled in the art of invention. DETAILED DESCRIPTION

[0015] During a read operation, a sensing circuit is configured to detect whether a snapback has occurred, based at least in part on whether current is flowing in the memory cell. The current can be detected by a change in charge, which is detected as a change in voltage on a local word line (fiber optic). The voltage change can be relatively small and is usually determined relative to a reference voltage. Externally generated reference voltages require conductive paths from a reference supply voltage to the sensing circuit to provide the reference voltage. These conductive paths can increase the bare chip size associated with a memory array. Furthermore, generating the reference voltage increases the power consumption associated with the memory array.

[0016] In general, this disclosure describes a system and a method configured to locally generate a reference voltage for reading memory cells. The system and method are designed to use inherent capacitances associated with a local WL and a global WL, a first sensing circuit array capacitance (e.g., the capacitance of lines coupling the WL to the sensing circuit array), and a bias voltage applied as part of a memory access operation. The bias voltage charges the inherent capacitances. A resulting charge on the inherent capacitances can then be used to generate the reference voltage. A value of the reference voltage is based, as described here, at least partially on relative values ​​of the inherent capacitances, which include, for example, a second sensing circuit array capacitance.In one embodiment, as described herein, an unselected global WL can be coupled to the sensing circuitry from an unselected adjacent working memory portion, providing a tuning capacitance configured to adjust the reference voltage. In another embodiment, a trimmer capacitor circuitry can provide additional capacitance (i.e., tuning capacitance) configured to generate a desired reference voltage. For example, the trimmer capacitor circuitry can correspond to a binary-weighted trimmer capacitor configured to provide selectable capacitances that are multiples of a nominal capacitance. The multiple is determined by a binary select value applied to the binary-weighted capacitor. The reference voltage can be adjusted by changing the binary select value.For example, the reference voltage can be adjusted to optimize the sensing difference between a maximum set voltage and a minimum reset voltage for the memory cell.

[0017] The system and method may also include a sensing amplifier. The reference voltage is applied to a first input, and a sensing voltage associated with the reference voltage and an output from a selected memory cell (i.e., the detected memory cell voltage) are applied to a second input of the sensing amplifier. The first and second inputs of the sensing amplifier may be coupled before the sensing voltage is applied to generate the reference voltage. This coupling can enhance noise rejection by generating common-mode noise at the first and second inputs. The sensing amplifier can then provide noise immunity (i.e., common-mode noise rejection) when the first and second inputs are decoupled and the sensing voltage is applied to the second input.The sensing amplifier is configured to receive the sensing voltage and the reference voltage and to provide a logic level output, i.e., logic one or logic zero, which V. CC or V SS corresponds and is at least partially based on relative values ​​of the reference voltage and the sensing voltage. For example, V CC have a value of 1.2 volts and V SS can correspond to ground (i.e., zero volts).

[0018] The following describes methods for generating a local reference voltage and sensing memory cell outputs with respect to word lines. Similar methods can be applied to generate local reference voltages and memory cell sensing operations in a cross-point memory for bit lines, in accordance with the present disclosure.

[0019] Fig. Figure 1 illustrates a system block diagram 100in accordance with several embodiments of the present disclosure. The system 100 includes a processor 102 , a memory controller 104 and a memory arrangement 106 The processor 102 is via a bus 108 with the memory control 104 coupled. The processor 102 can send read and / or write requests that include (a) memory address(es) and / or associated data to the memory controller 104 provide and can read data from the memory controller 104 received. The memory control 104 It is configured to perform memory access operations, such as reading from and / or writing to a target memory cell. It is noted that the system 100 It has been simplified for the purpose of easier illustration and description.

[0020] The memory arrangement 106 corresponds at least to a part of a phase-change intersection point memory and includes a large number of word lines 115 , a multitude of bit lines 117 and a multitude of RAM cells, e.g. RAM cell 107 Each working memory cell is coupled between a word line (WL) and a bit line (BL) at a junction of the WL and BL. Each working memory cell comprises a memory element configured to store information and may include a memory cell selector device (i.e., selector) coupled to the memory element. Selectors may include ovonic threshold switches, diodes, bipolar transistors, field-effect transistors, etc. The working memory arrangement 106 It is configured to store binary data and data can be written to (i.e., programmed) or read from it.

[0021] The memory control 104 includes memory control logic 110 , a WL control circuit arrangement 114 and a BL control logic 116 The memory control logic 110 is configured to control the memory 104 to perform assigned operations. For example, the memory control logic can 110 communication with the processor 102 manage. The memory control logic 110 It can be configured to identify one or more target WLs that are associated with each received memory address. The memory control logic 110 can be configured to perform WL control logic operations 114 and the BL control logic 116 to manage at least partially based on the target WL identifiers.

[0022] The WL control logic 114includes a WL switch circuit arrangement 120 and a sensing circuit arrangement 122 The WL control logic 114 is configured to obtain (a) WL address(es) from the memory control logic 110 to receive and select one or more WLs for read and / or write operations. For example, the WL control logic can 114 It must be configured to select a target WL by coupling a WL selection bias to the target WL. The WL control logic 114 It can be configured to deselect a WL by decoupling the target WL from the WL selection bias and / or by coupling a WL deselection bias to the WL. The WL control logic 114 can be used with a variety of memory configurations 106 included WLs 115 Each WL can be coupled to a number of RAM cells, which in turn can be coupled to a number of BLs. 117corresponds to the WL switch circuit arrangement. 120 can include a variety of switches, with each switch configured to control a specific WL, e.g., WL 115a , to couple (or decouple) with the WL selection bias in order to determine the respective WL 115a To select, for example, the switch circuit arrangement. 120 include a large number of transistors.

[0023] The BL control logic 116 includes a BL switch circuit arrangement 124 In some embodiments, the BL control logic can 116 a sensing circuit arrangement, e.g. sensing circuit arrangement 122 , include. The BL control logic 116 is configured to select one or more BLs for read and / or write operations. The BL control logic 116 can be configured to select a target BL by applying a BL selection bias (V PP) with the target BL. For example, V can PP have a value of 5.0 volts. The BL control logic 116 It can be configured to deselect a BL by decoupling the target BL from the BL selection bias and / or coupling a BL deselection bias to the BL. The BL switch circuit arrangement 124 is the WL switch circuit arrangement 120 similar, except that the BL switch circuit arrangement 124 is configured to couple the BL selection bias with a target BL.

[0024] The sensing circuit arrangement 122 It is configured to detect the presence or absence of a snapback event during a probing interval, e.g., during a read operation. The probing circuit arrangement 122 is configured to output a logic level corresponding to the result of the read operation to, for example, the memory controller. 110to provide. For example, a logic level corresponding to a logical one can be output if a snapback is detected, and a logic level corresponding to a logical zero can be returned if a snapback is not detected.

[0025] For example, the WL control logic 114 and the BL control logic 116 in response to a signal from the main memory control logic 110 be configured to target a memory cell, e.g., memory cell 107 , to select for a readout process by selecting the WL 115a with the WL selection bias and BL 117a couple with the BL selection bias. The sensing circuit arrangement 126 It can then be configured to handle the WL 115a and / or the BL 117ato monitor for a sensing interval to determine if a snapback event occurs. If the sensing circuit arrangement 126 If a snapback event is detected, then the working memory cell can 107 are in the set state. If the sensing circuit arrangement 126 If no snapback event is detected within the sampling interval, then the working memory cell can 107 are in a reset state.

[0026] Thus, the WL control logic can be 114 and / or the BL control logic 116 It must be configured to select a target memory cell for a read operation, initiate the read operation, monitor the selected memory cell at a probing interval for a snapback event, and send the result of the probing, for example, to the memory control logic. 110 to provide.

[0027] Fig. 2A illustrates a part 200 of an intersection point memory system in accordance with various embodiments of the present disclosure. The part 200 includes a BL and a WL, which are located in a working memory cell. 216 cross. The part 200 It also includes a BL bias circuit arrangement. 210 , a BL switch circuit arrangement 220 , a local WL(LWL) switch circuit arrangement 222 , a global WL(GWL) switch circuit arrangement 224 and a sensing circuit arrangement 230 In some embodiments, the part 200 a GWLB switch 225 include a component configured to represent an adjacent part of the memory array. For example, the BL bias circuit array can include a component configured to represent an adjacent part of the memory array. 210 and the BL switch circuit arrangement 220 in the BL control logic 116includes its and the fiber optic switch circuit arrangement 222 , the GWL switch circuit arrangement 224 and the GWLB switch 225 can be used in the WL control logic 114 It includes the sensing circuit arrangement. 230 This is an example of the sensing circuit arrangement 122 out of Fig. 1.

[0028] The BL bias circuit arrangement 210 is equipped with a voltage supply V PP and the BL switch circuit arrangement 220 coupled. The BL switch circuit arrangement 220 is also via the local BL 214 with the working memory cell 216 coupled. The fiber optic switch circuit arrangement 222 is also via the LWL 212 with the working memory cell 216 and about the GWL 213 with the GWL switch circuit arrangement 224 coupled. The GWL switch circuit arrangement 224is also equipped with the sensing circuit arrangement 230 coupled. The fiber optic switch circuit arrangement 222 is configured to connect to an optical fiber, e.g., an optical fiber. 212 , to select and the selected fiber optic cable 212 with the GWL circuit arrangement 224 to couple. The GWL switch circuit arrangement 224 is configured to use a selected fiber optic cable, e.g., fiber optic cable 212 , and the GWL 213 with the sensing circuit arrangement 230 to couple during, for example, a memory cell readout process.

[0029] The part 200 It also includes a variety of control inputs. For example, VDM acts as a control signal input for the BL bias circuit arrangement. 210 For example, VDM can have a nominal value of 4.0 volts. If VDM is increased above a threshold, an output AXN of the BL bias circuit arrangement can be used. 210to become BLVDM, which is related to VDM as BLVDM ~ VDM – VTn, where VTn is a threshold voltage of a switch controlled by VDM and in the BL bias circuit arrangement 210 is included. In another example, GBLSEL is a GBL (global BL) selection signal. GBLSEL is an active low signal, meaning that it is connected to the BL switch circuit arrangement. 220 The coupled GBL is selected when the GBLSEL is low, and not selected when the GBLSEL is high. "Low" and "high" in this context refer to logic levels and can be relative to a voltage; for example, low can be ground (e.g., V). SS ) correspond and high can be a positive voltage that is not zero (e.g. V) CC = 1.2 volts). LBLSEL is an LBL (local BL) selection signal and is active low. When both GBLSEL and LBLSEL are low, the LBL is 214 coupled with AXN. LWLSEL (local fiber optic selection) is configured to handle the coupling from the fiber optic cable.212 with the GWL 213 to control, and GWLSEL is configured to manage the coupling of the GWL 213 with the sensing circuit arrangement 230 to control. In some embodiments, the GWL switch circuit arrangement can 224 and the fiber optic switch circuit arrangement 222 include a deselection circuit arrangement configured to disable the GWL 213 and / or the fiber optic cable 212 with V SS to couple if not selected. In these embodiments, GWLDES and LWLDES are configured to couple the GWL 213 or the fiber optic cable 212 with V SS to couple.

[0030] The part 200 includes an inherent fiber optic capacity 218 with a capacity value C LWL , which is connected to the LWL 212 is coupled, and has a GWL-inherent capacity 232 with a capacity value C GWL , who is with the GWL 213 is coupled. The inherent capacities218 , 232 correspond to the inherent capacities of the fiber optic cable 212 or the GWL 213 are assigned. As used here, an inherent capacitance is a capacitance that exists in the circuit arrangement (e.g., conductive path and / or switch), rather than a capacitance assigned to a capacitor (i.e., a discrete element) that can be added to a circuit. Thus, although the capacitances are 218 and 232 as with the LWL 212 or the GWL 213 shown coupled, the capacities 218 and 232 no discrete elements. The capacity 218 corresponds to the inherent capacity of the fiber optic cable 212 and the capacity 232 corresponds to the inherent capacity of the GWL 213 .

[0031] In the embodiments that include the GWLB switch 225 can include the part 200 including the GWLB's inherent capacity 233with the capacity value C GWLB include the capacity 233 is configured to represent a capacity allocated to a GWL contained in another part of the memory arrangement, which is the sensing circuit arrangement 230 can be shared (e.g., multiplexing). The capacity 233 can be done via the GWLB switch 225 can be selected. In these embodiments, the capacity can be 233 , as described here, can be used as a setting capacitor to establish a reference voltage for the sensing circuit arrangement 230 to adjust, which are at least partially based on the inherent capacities 232 , 234 , 236 based on using the capacity 233 As a setting capacity, noise suppression can be improved by providing a relatively better matching noise component, which can then be eliminated, for example, by a sensing amplifier.

[0032] The sensing circuit arrangement 230 includes a sensing amplifier 240 , an HNEQ switch 242 , a bank of counters 244A , ... 244n , collective counter 244 , an NLRU switch 246 and an NLRL switch 248 The sensing circuit arrangement 230 includes a first sensing circuit arrangement capacity 234 with a capacity C HNREG and a second sensing circuit arrangement capacity 236 with a capacity C HNREGB The capacities 234 , 236 represent the inherent capacity of the circuit arrangement between the GWL switch circuit arrangement 224 and an upper Unlimited Read (NLRU) switch 246 or between the GWLB-SW 225 and the lower Unlimited Read (NLRL) switch 248 . Here, upper and lower parts of the memory arrangement are referred to as , e.g., the memory arrangement. 106 out of Fig. 1.

[0033] In some embodiments, the sensing circuit arrangement 230 a trimmer capacitor circuit arrangement 250 and trimmer capacitor switch TC-SWA 288A and TC-SWB 288B include. The TC-SWA 288A is configured to use the trimmer capacitor circuit arrangement 250 to couple with a node HNREG. The TC-SWB 288B is configured to use the trimmer capacitor circuit arrangement 250 to couple with a node HNREGB. The switches 288A , 288B are configured to use the trimmer capacitor circuit arrangement 250 with more than part of the memory arrangement 106 to enable this. For example, as described here, the TC-SWA can 288A be open and the TC-SWB 288B can be closed to accommodate the trimmer capacitor circuit arrangement 250to couple with HNREGB to set the capacity coupled with HNREGB. In this first example, the memory cell can be 216 It may be selected for a memory access operation. In another example, the TC-SWA might be selected. 288A closed and the TC-SWB 288B can be opened to access the trimmer capacitor circuit arrangement 250 to couple with HNREG to set the capacitance coupled to HNREG. In this second example, a memory cell in an adjacent memory segment can be selected for a memory access operation. In other words, the trimmer capacitor circuit arrangement can 250 It can be coupled to node HNREGB or node HNREG, but not to both. The trimmer capacitor circuit arrangement 250 can then be used to, as described here, V REF to adjust. The shared use of the trimmer capacitor circuit arrangement. 250is configured to save bare chip area.

[0034] The sensing amplifier 240 It comprises two inputs: a first input SA1, which is coupled to the HNREGB node, and a second input SA2, which is coupled to the HNREG node. The HNEQ switch 242 is connected between nodes HNREGB and HNREG. The switchboard 244 includes a variety of switches 244A , ..., 244n , which are configured to individually select the nodes HNREG and / or HNREGB with V SS to couple or decouple them. The switches 244A , ... 244n are controlled by a control signal SMIN. SMIN is active low, therefore the switches are 244A , ... 244n Closed when SMIN is low, and open when SMIN is high. The NLRU switch 246 is connected between the supply voltage WLVDM and the node HNREG and the NLRL switch 248is connected between the supply voltage WLVDM and the node HNREGB. For example, WLVDM can have a nominal value of -3.6 volts. The first sensing circuit arrangement capacitance 234 is coupled to the node HNREG and the second sensing circuit arrangement capacity 236 is coupled to the HNREGB node. The GWL switch circuit arrangement 224 is coupled with the node HNREG and the GWL-SW 225 can be coupled to the HNREGB node. The trimmer capacitor circuit arrangement 250 can be done via the TC-SWA, as described here. 288A with the HNREG node or via the TC-SWB 288B be coupled to the node HNREGB.

[0035] The HNEQ switch 242 It has a control input HNEQ and is configured to couple or uncouple the HNREG node with / from the HNREGB node. The NLRU switch 246 and the NLRL switch 248They each have a control input: NLRU and NLRL. The NLRU switch 246 is configured to couple the HNREG node with WLVDM, and the NLRL switch 248 is configured to couple the HNREGB node with WLVDM.

[0036] The sensing amplifier 240 can have two switches 247 , 249 , comprising a first stage SA stage 1 and a second stage SA stage 2. The sensing amplifier 240 is equipped with at least one power supply, V CC (logic level supply) coupled and can be used with V SS , i.e., mass, be coupled. The sensing amplifier 240 It also includes two control inputs, LSENB and SAEN. The switch 247 is configured to couple node SA2, and thereby node HNREG, with SEN, an input to SA stage 1. The switch 249is configured to couple node SA1, and thereby node HNREGB, to REN, another input to SA stage 1. In some embodiments, nodes REN and SEN can also be coupled to inputs to SA stage 2. The switches 247 and 249 These are high-active switches controlled by LSENB, whereby when LSENB is high, HNREGB is coupled to REN and HNREG is coupled to SEN. LSENB is also coupled to SA Stage 1 and is a low-active signal configured to enable SA Stage 1. Thus, as described here, SA Stage 1 is enabled when LSENB is low and disabled when LSENB is high. SAEN is configured to enable SA Stage 2. In operation, when SA Stage 2 is enabled, a memory readout output can be provided to the sensing nodes.

[0037] The sensing amplifier 240may include any type of sensing amplifier configured to receive negative input voltages (e.g., reference voltage and sensing voltage) and generate a logic-level voltage output while passing a short-circuit current between the logic-level supplies (e.g., V1). CC and V SS) during transitions. Such a sensing amplifier can be configured to shift the negative input voltages to positively referenced intermediate voltages. The corresponding values ​​of the intermediate voltages can be based, at least partially, on relative values ​​of the negative input voltages. Such a sensing amplifier can also be configured to convert the intermediate voltages to a logic-level voltage output, based, at least partially, on relative values ​​of the negative input voltages. Such a sensing amplifier can have a relatively low input offset voltage and be configured to provide level shifting with relatively low power consumption and at relatively high speed to generate a logic-level output from a relatively low input.

[0038] Fig. Figure 2B illustrates an example circuit arrangement section. 260, which has a binary weighted trimmer capacitor 251 in accordance with one embodiment of the present disclosure, comprising a binary-weighted trimmer capacitor. 251 This is an example of the trimmer capacitor circuit arrangement 250 out of Fig. 2A. The binary weighted trimmer capacitor 251 includes a large number (e.g. four) of trimmer capacitors 282A , ... 282D Each trimmer capacitor 282A , ... 284D has a capacitance value that is a power of two multiplied by a nominal capacitance value, dC. In a non-restricting example, the capacitance value of dC can be on the order of 10 femtofarads (fF). For example, the first trimmer capacitor has 282A a capacity value of one (i.e., 2 0 ) times dC, the second trimmer capacitor 282B has a capacity value of two (i.e., 2 1 ) times dC, the third trimmer capacitor 282Chas a capacity value of four (i.e., 2 2 ) times dC and the fourth trimmer capacitor 282D has a capacity value of eight (i.e., 2 3 ) times dC. The binary weighted trimmer capacitor 251 It also includes a large number of switches. 284A , ... 282D The number of switches corresponds to the number of trimmer capacitors. 282A , ... 282D One state of each switch 284A , ... 284D is configured to be selected by a selector 286 to be controlled. If a respective switch 284A , ... 284D When closed, the associated trimmer capacitor 282A , ... 282D with the switches 288A , 288B and thus coupled with HNREG or HNREGB. Therefore, based on the selector value (four bits in this example), none, one, or more of the switches can be set. 284A , ... 284D It must be closed. The binary weighted trimmer capacitor251 can then select a trim capacitance value in the range of zero (i.e., all switches) 284A , ... 284D open) up to 15·dC (i.e., all switches) 284A , ... 284D closed) provide in gradations of dC. Thus, as described here, it is possible to rely at least partially on capacity values ​​of the inherent capacities. 218 , 232 , 234 and 236 and the selected capacitance value of the binary weighted trimmer capacitor 251 based on generating a selected reference voltage at one or more of the nodes HNREG and HNREGB.

[0039] Fig. 2C is a simplified sketch 270 , which, as described here, are the inherent capacitances and a reference voltage adjusting capacitor circuit arrangement associated with the local reference voltage production 252 Illustrated. The reference voltage adjusting capacitor circuit arrangement. 252includes an adjustment capacitor 253 and an adjustable capacitor switch 254 In one embodiment, the circuit arrangement can be 252 the trimmer capacitor circuit arrangement 250 correspond. In this example, C corresponds to xx SW 254 TC SWB 288B , where TC SWA 288A is open and the trimmer capacitor circuit arrangement 250 decoupled from the HNREG node, and C xx 253 corresponds to the capacitance of the trimmer capacitor circuit arrangement 250 In another embodiment, the circuit arrangement can be 252 GWLB SW 225 and the inherent capacity 233 correspond. In this embodiment, C corresponds to xx -Switch 254 the GWLB SW 225 and the capacity 253 corresponds to the capacity 233 Thus, in this embodiment, C corresponds to... xx C GWLB .

[0040] The inherent capacities 218 , 232 , 234 , 236 and the adjustment capacity 253 They can be configured to be essentially parallel. Coupling the capacities 218 , 232 , 234 , 236 , 253 can then be done via the HNEQ switch 242 , a fiber optic switch 223 , a GWL switch 225 and the C xx -Switch 254 can be controlled. The fiber optic switch 223 and the GWL switch 225 can then be used in the fiber optic switch circuit arrangement 222 or the GWL switch circuit arrangement 224 It may be included. In general, the capacities can 218 , 232 , 234 , 236 , 253 used in operation to assign a charge to a reference voltage for the sensing amplifier 240 to save. The HNEQ switch 242is configured to couple and uncouple the nodes HNREG and HNREGB as described herein. The coupling configuration capacity 253 is simultaneously with the inherent capacity 236 configured to provide a target reference voltage associated with WLVDM.

[0041] In general, a charge Q on a capacitive element with capacitance C is equal to the product of the capacitance and the potential difference (i.e., voltage) across the capacitive element (Q = C·V). As used herein, "capacitive element" includes, for example, a capacitor, an inherent capacitance, and / or a parallel combination of one or more of these. If a plurality of capacitive elements, one or more with an initial charge and a corresponding initial voltage, are then coupled in parallel, the initial voltages will equalize to a final voltage. Based on charge conservation, a total charge before equalization is equal to a total charge after equalization. For example, consider two capacitive elements with capacitances C1 and C2 and respective initial voltages V1 and V2. The initial charge is Q i = Q1 + Q2 = C1·V1 + C2·V2.

[0042] When the capacitors are then coupled in parallel, the final discharge Q f = V f ·(C1 + C2), where V f The final voltage across the parallel-coupled capacitive elements is given by Q. i = Q f , C1·V1 + C2·V2 = V f ·(C1 + C2). Thus,

[0043] Based on charge conservation and the use of inherent capacitances charged by bias voltages, a reference voltage, as described here, can be generated locally.

[0044] Fig. 3A is a time diagram 300 , the exemplary memory read operations of the intersection point memory system 200 illustrated. Fig. 3B is a time diagram 350, which is an example of voltages at nodes HNREG and HNREGB including sensing and reference voltages and input voltages (REN, SEN) to a sensing amplifier for set and reset working memory cells for working memory read operations of the cross-point working memory system 200 Illustrated. The time diagrams. 300 , 350 are best understood when they are also viewed with attention to the in Fig. 2A illustrated intersection point working memory section 200 and the one in Fig. 2C illustrated simplified part 270 be read.

[0045] The time diagram 300 includes a waveform 302 , which corresponds to the control input GWLSEL, a waveform 304 , which corresponds to the control input LBLSEL, a waveform 306 , which corresponds to the control input GBLSEL, a waveform 308A, which is a control input NLRU, a control input for the NLRU switch 246 , corresponds to, and a waveform 308B , which is connected to a control input NLRL, a control input for the NLRL switch 248 , corresponds to the time diagram 300 It also includes, as described here, a waveform 310 , which corresponds to the control input LWLSEL, a waveform 312 , which corresponds to the HNEQ control input, a waveform 314 , which corresponds to the output AXN of the BL bias circuit arrangement 210 corresponds to a waveform 316 , which corresponds to the control input LSENB, used to activate a first stage of the sensing amplifier 240 is configured, a waveform 318 , which corresponds to a control input SAEN, used to activate an output of the sensing amplifier 240 is configured, and a waveform 320 , which corresponds to the control input SMIN.

[0046] The time diagram350 includes a waveform 322A , which corresponds to a voltage detected at node HNREGB (and a reference voltage V) REF (can correspond), and a waveform 322B , which corresponds to a voltage detected at node HNREG (and a sensing voltage V) SENSE (can correspond). The waveforms 322A and 322B correspond to the voltages at HNREGB and HNREG for a working memory cell, e.g.: working memory cell 216 , in a set state. The time diagram 350 It also includes a waveform 324A , which are waveforms 322A similar, and a waveform 324B , which are waveforms 322B similar, except that the waveforms 324A and 324B a working memory cell, e.g., working memory cell 216 , in a reset state.

[0047] The time diagram 350As described here, it also includes a waveform 326A , which applies a first input voltage REN to a first stage of the sensing amplifier 240 corresponds to, and a waveform 326B , which connects a second input voltage SEN to a first stage of the sensing amplifier 240 corresponds to the waveforms. 326A and 326B REN and SEN correspond to a working memory cell, e.g., working memory cell 216 , in a set state. The time diagram 350 As described here, it also includes the waveform 328A , which applies a first input voltage REN to a first stage of the sensing amplifier 240 corresponds to, and a waveform 328B , which connects a second input voltage SEN to a first stage of the sensing amplifier 240 corresponds to the waveforms. 328A and 328B REN and SEN correspond to a working memory cell, e.g., working memory cell 216, in a reset state.

[0048] Initially, at time t0, GWLSEL and LWLSEL are low, and LBLSEL and GBLSEL are high, indicating that the corresponding GWL, LWL, GBL, and LBL are not selected. NLRU is low, indicating that the node HNREG is not coupled to WLVDM. Similarly, NLRL is low, indicating that HNREGB is not coupled to WLVDM. NLRL remains low for the duration t0 until at least t 11 low. NLRL can be used for memory read operations for an adjacent memory array part, similar to NLRU, thereby changing the waveform 308B the waveform 308Afor memory read operations of the adjacent memory segment. HNEQ is low, indicating that node HNREG is not coupled to node HNREGB. AXN is low, indicating that VDM is also low. LSENB is high, indicating that HNREGB is coupled to REN, HNREG is coupled to SEN, and SA stage 1 is not enabled. SAEN is low, indicating that the output of the sensing amplifier... 240 (i.e., SA level 2) is not activated. SMIN is low, indicating that HNREG and HNREGB are not enabled via the switches. 244A , ..., 244n with V SS is coupled. Thus, the charges are on the inherent capacities. 218 , 232 , 234 and 236 and the adjustment capacity 253 At time t0, the voltage at HNREGB, the voltage at nodes HNREG, REN and SEN, is also zero (i.e., V SS ).

[0049] At time t1, GWLSEL, LBLSEL, GBLSEL and LWLSEL change state, with GWL 213 , fiber optic cable 212 , LBL 214 and select the corresponding GBL and thus the working memory cell 216 with the BL bias circuit arrangement 210 and with the sensing circuit arrangement 230 coupling. SMIN switches to high, whereby the switches 244A and 244n opened and the nodes HNREG and HNREGB of V SS to be decoupled. Thus, at time t1, the fiber optic switch is decoupled. 223 and the GWL switch 225 closed, thereby utilizing the inherent capacities 218 and 232 The nodes HNREG and HNREG are coupled. The voltages at nodes HNREGB and HNREG, REN and SEN, remain zero.

[0050] The NLRU switch closes at time t2. 246 , which couples HNREG with WLVDM. Thus, at time t2, when the NLRU switch is closed, 246concludes, the inherent capacities 218 , 232 and 234 The nodes are coupled with WLVDM and begin loading WLVDM. The node HNREG begins transitioning to WLVDM, and the node HNREGB remains at V. SS .

[0051] The NLRU switch opens at time t3. 246 , thereby utilizing the inherent capacities 218 , 232 and 234 decoupled from WLVDM. The time period from t2 to t3 represents a pre-charging time. The inherent capacities 218 , 232 and 234 are charged to WLVDM during the pre-charging period. At time t3, HNREGB remains at V SS and HNREG (i.e., C HNREG ), GWL 213 (i.e. C GWL ) and fiber optic cable 212 (i.e. C LWL ) are at WLVDM. At time t4, the fiber optic switch circuit arrangement decouples. 222 in response to the changing state of LWLSEL LWL 212 from GWL 213 , which fiber optic cable 212It is potential-free. Fiber optic cable. 212 remains loaded on WLVDM.

[0052] The HNEQ switch closes at time t5. 242 , thereby coupling node HNREGB to HNREG and SA1 to SA2. VDM is also connected to the BL bias circuit arrangement at time t5. 210 created, thereby AXN from V SS The value is increased to BLVDM. Time t5 corresponds to the start of a sampling interval of the state of the working memory cell. 216 and also the generation of a reference voltage V REF for the sensing amplifier 240 Advantageously, the reference voltage V can be REF locally generated from the ground-source and fiber-source bias voltages and for a duration corresponding to the sensing interval. In other words, V can be REF as an accidental byproduct of loading the LWL 212This can be understood. Thus, the remote generation of the reference voltage and the transmission of the remotely generated reference voltage to the sensing amplifier can be understood. 240 This can be avoided and occur without extending the sensing interval duration. An additional advantage of coupling HNREGB and HNREG is that noise present on, for example, GWL, HNREG, HNREG and / or GWLB (if used for setting capacitance) can be converted to common-mode noise. Thus, the sensing amplifier can 240 reduce or eliminate common-mode noise, resulting in relatively improved noise immunity and robustness.

[0053] Just before the HNEQ switch closes 242 , i.e., shortly before time t5, the inherent capacity 236 (C HNREGB ) and the adjustment capacity 253 (C xx ) configured to have a zero charge, and the inherent capacities 232 and 234are configured to store a load: Q GWL = C GWL ·WLVDM or Q HNREG = C HNREG ·WLVDM to demonstrate.

[0054] Thus, the initial charge Q i shortly before the HNEQ switch closes 242 : Q i = Q xx + Q HNREGB + Q GWL + Q HNREG

[0055] If the capacities 236 and 253 if Q has zero charge i : Q i = (C xx ·0) + (C HNREGB ·0) + (C GWL ·WLVDM) + (C HNREG ·WLVDM) = (C GWL + C HNREG )·WLVDM.

[0056] After closing the HNEQ switch 242 Can the charge be transferred from the capacities? 232 and 234 to the capacities 236 and 253 be transmitted. It is in a permanent state, due to the capacities232 , 234 , 236 and 253 are coupled in parallel, Q f = (C GWL + C HNREG + C HNREGB + C xx )V f , where Q f the total discharge is and V f the final voltage at the capacitors 232 , 234 , 236 , 253 It is noted that the fiber optic capacity 218 This calculation does not include the fiber optic switch. 223 is open, so that the fiber optic cable 212 at least from the GWL 213 and the sensing circuit arrangement 230 is decoupled. Based on charge conservation (i.e., Q) i = Q f ) is (C GWL + C HNREG )·WLVDM = (C GWL + C HNREG + C HNREGB + C xx )·V f which can be written as: where V f the reference voltage V REFThis corresponds to what is described here. Advantageously, V can REF in accordance with the present disclosure, using the local bias WLVDM, and the charge in the inherent capacitances (i.e., the GWL capacitance C) GWL and the capacity of the first sensing circuit arrangement C HNREG ) are stored when the preload WLVDM is applied to the GWL via the HNREG node. 213 is created.

[0057] BLVDM is approximately equal to VDM minus a threshold voltage (e.g. VTn) of a switch that corresponds to the BL bias circuit arrangement. 210 is assigned. Thus, fiber optic cables represent 212 , which was loaded on WLVDM, and LBL 214 , which was now loaded onto BLVDM, a differential voltage at the working memory cell 216ready, which corresponds to BLVDM + |WLVDM|. In other words, since WLVDM is usually negative and BLVDM is usually positive, the adjusted potential difference at the working memory cell is 216 The sum of the absolute values ​​of BLVDM and WLVDM. Thus, the working memory cell 216 During the time interval t5 to t6, the memory cell either snaps back (set) or does not snap back (reset), depending on whether it stores a zero (reset) or a one (set). The charge on the optical fiber 212 This can then reflect the state of the working memory. For example, this occurs when the threshold voltage of the working memory cell 216 If the value is greater than BLVDM + |WLVDM|, there may be no snapback, which corresponds to logical zero in memory. If there is no snapback, V LWL on the LWL 212remain at or near WLVDM. In another example, if the threshold voltage of the working memory cell 216 If BLVDM + |WLVDM| is less than or equal to BLVDM + |WLVDM|, a snapback occurs, which logically corresponds to one in memory. When a snapback occurs, the voltage (V) LWL ) on fiber optic cable 212 on more than WLVDM, i.e. |V LWL |<|WLVDM|, increase as current flows through the working memory cell. In other words, V LWL WLVDM can be equivalent if no snapback occurs, and V LWL It can increase to near zero if a snapback occurs.

[0058] Simultaneously with the sensing, when the HNEQ switch is activated. 242 Once closed, node HNREG is coupled to node HNREGB. Shortly before the HNEQ switch closes (i.e., t 5minus ), is the node HNREGB at V SS and the node HNREG is at WLVDM. Thus, the inherent capacities are 234 and232 loaded onto WLVDM and the inherent capacity 236 and the adjustment capacity 253 are at V SS After closing the HNEQ switch 242 HNREGB and HNREG can settle on a value between V SS and compensate for WLVDM.

[0059] Thus, shortly before time t6, the voltages at HNREGB, HNREG and GWL can 213 at or near V REF be and LWL 212 can have a charge that corresponds to a voltage V LWL (i.e., a detected working memory cell voltage). At time t6, the HNEQ switch may be 242 open, thereby decoupling HNREGB and HNREG. Likewise, at time t6, the BL bias circuit arrangement can be opened. 210 by V PP be decoupled, thereby AXN becoming V SS can return. Both HNREGB and HNREG can be used at V REF stay and GWL 213 can also be the case with V REF be.

[0060] At time t7, the fiber optic cable can 212 be selected again and the fiber optic switch circuit arrangement 222 can the fiber optic cable 212 with the GWL 213 (i.e. C GWL ) and thus couple to the node HNREG. V LWL from the LWL 212 can then connect to node HNREG with V REF unite to create a voltage V SENSE to return to HNREG, which is configured to report the state of the memory cell 216 to display.

[0061] Before time t7, the HNEQ switch is open, thus decoupling HNREGB from the HNREG node. Due to the balancing that occurred between times t5 and t6, both the HNREGB and HNREG nodes are at V REF Thus, shortly before time t7, an initial charge coupled to the node HNREG is applied to the inherent capacities. 232 and 234 : Q i = (C HNREG + C GWL)·V REF .

[0062] Likewise, the LWL 212 assigned initial charge C LWL ·V LWL , where V LWL This corresponds to a detected working memory cell voltage, which may be at or near WLVDM, or a voltage associated with WLVDM and BLVDM, e.g., zero volts. Based again on charge conservation: (C HNREG + C GWL )·V REF + C LWL V LWL = (C HNREG + C GWL + C LWL )·V SENSE , where V SENSE a voltage at node HNREG, resulting from the re-coupling of the fiber optic cable 212 with the GWL 213 and the node HNREG is created after a sampling interval. Thus,

[0063] During the time interval t7 to t8, HNREGB can be used at V REF be and HNREG can at V SENSE be. Thus, the waveform corresponds to 322A V SENSEand the waveform 322B corresponds to V REF for a working memory cell in the set state and the waveform 324A corresponds to V SENSE and the waveform 324B corresponds to V REF for a working memory cell in its reset state during the time interval beginning at time t7. V REF is attached to input SA1 and V SENSE is connected to input SA2 of the sensing amplifier 240 Since LSENB remains high during the time interval t7 to t8, SA1 is coupled to REN and SA2 is coupled to SEN, causing REN to be high at V REF is and SEN at V SENSE is whether there is a difference between V REF and V SENSE is positive or negative (i.e., V) SENSE > V REF or V SENSE < V REF ) can then indicate whether a snapback occurred or not, and thus whether the memory cell 216 stores zero or one. If V SENSE is greater than V REF, is the sensing amplifier 240 It is configured to logically output one at the sensing node. If V SENSE is smaller than V REF , is the sensing amplifier 240 configured to output logical zero at the sensing node. A difference between V SENSE and V REF can be determined as which, after some algebraic manipulation, can be simplified to

[0064] Since V LWL In the absence of a snapback, WLVDM may be equal to or near zero; if there is a snapback, it may be desirable that V REF at or near WLVDM / 2. V REF may be at or near WLVDM / 2 if C GWL + C HNREG = C HNREG + C xx

[0065] Thus, the selection of C can xx at least partially based on the values ​​of C GWL, C HNREG and C HNREGB based.

[0066] In some embodiments, C xx be selected such that V REF is not the same as WLVDM / 2. For example, setting V REF It can be configured to be greater or less than WLVDM / 2 to account for fluctuations in the memory cell threshold voltage, thereby providing a more reliable sensing of the memory cell's state. In other words, setting V REF It should be configured to optimize the sensing of the working memory cell's state.

[0067] At time t8, LSENB is switched low, thus decoupling SA1 from REN and SA2 from SEN, and activating SA stage 1 to at least partially control REN (i.e., V). REF ) and SEN (i.e., V SENSE) to generate a positive intermediate reference voltage. The voltages at nodes SEN and REN (which were at or below zero before time t8) are configured to reference the intermediate voltages, V CC or V CC – |V TP |, to start up. Whether the SEN node is at V CC or V CC – |V TP | is, depends on whether V SENSE greater or less than V REF was. For example, if V SENSE greater than V REF is (i.e. V) SENSE is less negative than V REF ), the node SEN V CC reach (waveform) 326B ) and the node REN can V CC – |V TP | become (waveform 326A ), where V TP this corresponds to the threshold voltage of a transistor included in SA stage 1. In another example, if V SENSE is smaller than V REF is (i.e. V) SENSE is more negative than V REF ), the node REN VCC reach (waveform) 328A ) and the node SEN can then V CC – |V TP | become (waveform 328B The SA stage 1 can be configured to generate intermediate output voltages at nodes SEN and REN, which V CC and V CC – |V TP | correspond if SEN and REN are decoupled from SA1 and SA2, respectively. Negative input voltages can be reduced to V by SA stage 1, for example. CC -(e.g., positive, logic level voltage) referenced intermediate voltages are level-shifted. SA Stage 1 can be configured to provide level shifting with a relatively low input offset voltage, zero static current between the supplies, and relatively low power consumption.

[0068] At time t9, SAEN is switched high to activate SA stage 2. The time interval t8 to t9 is configured to allow the intermediate voltages to settle into a steady state. For example, during a time interval t8 to t9, a respective V CC and V CC – |V TP | reach a continuous state on SEN and REN. At time t9, SA stage 2 is configured to convert the intermediate voltages to a logic-level voltage output, based at least partially on relative values ​​of the intermediate voltages, and to provide the logic-level output to the sensing nodes. For example, SA stage 2 can be coupled to SEN and REN. Thus, SAEN switches high at time t9, providing an output from the sensing amplifier to the sensing nodes. If V SENSE is greater than V REF , then the output V CC correspond. If V SENSE is smaller than V REF, then the output V SS correspond. At time t 10 Data that corresponds to a state of the memory element will be stored. 216 Display, e.g., logic zero and / or logic one corresponding voltage(s) from the sensing amplifier 240 output to the sensing node. At time t 10 can the sensing amplifier 240 be deactivated. The readout process can be deactivated at time t. 11 end.

[0069] Thus, the sensing amplifier 240 configured to V SENSE and V REF to receive and provide a logic level output, at least partially based on whether V SENSE greater or less than V REF SA Level 1 is configured to V SENSE and V REF on corresponding intermediate voltages, which lead to V CC are referenced, to shift the level. SA stage 2 is configured to shift the intermediate voltages to a logic level (e.g., V).SS or V CC ) to convert the output, at least partially based on relative values ​​of the intermediate voltages, and to provide the output to a sensing node.

[0070] Thus, the time diagrams 300 , 350 and the memory arrangement part 200 It is configured to illustrate the operation of a system for locally generating a reference voltage using, for example, WL bias voltages and inherent capacitances. The reference voltage can be adjusted by a variable capacitance, for example, the one in the trimmer capacitor circuit arrangement. 250 included trimmer capacitors or the inherent capacitance associated with an adjacent GWLB 233 , will be hired.

[0071] Thus, the Fig. 2A, Fig. 2B and Fig. 2C, the generation of a reference voltage by a sensing circuit arrangement using inherent capacitances. In one embodiment, an adjacent working memory component (e.g., GWLB) can be used to provide additional inherent capacitance to generate a reference voltage at or near WLVDM / 2. In another embodiment, the trimmer capacitor circuit arrangement can provide the tuning capacitance. The tuning capacitance can be used to adjust V REF to adjust. V REF can be configured to take into account properties of the associated intersection point memory portion. For example, V REF to be set to more or less than WLVDM / 2 to optimize a sensing difference between a maximum set voltage and a minimum reset voltage for the memory cell.

[0072] Fig. 4 illustrates a flowchart 400of operations for a memory access operation, which includes generating a reference voltage in a crossover-point memory in accordance with various embodiments of the present disclosure. The operations can be performed, for example, by a memory controller, e.g., a memory controller. 104 , which uses the WL tax logic 114 and the BL control logic 116 The flowchart includes the following: 400 It depicts exemplary processes configured for performing a memory access operation, such as a read operation. In particular, the flowchart illustrates 400 Exemplary operations configured to read a memory cell, including generating a reference voltage using inherent capacitances and a bias voltage, as described here.

[0073] Processes of the flowchart 400can be used to decode a memory address during the process 402 begin. A GWL, an LWL, a GBL, and an LBL assigned to a target memory cell can be at least partially based on the decoded memory address during the process. 404 be selected. Process 406 The coupling of the selected GBL and LBL with the bias circuit arrangement and the GWL and LWL with a sensing circuit arrangement, e.g. sensing circuit arrangement, is possible. 230 out of Fig. 2A, include. Process 408 This includes precharging the selected GWL, LWL, and a first sensing circuit assembly capacitor. For example, the selected GWL, LWL, and first sensing circuit assembly capacitor can be precharged to the voltage WLVDM.

[0074] During the process 410The optical fiber can be decoupled from the sensing circuitry, and a BL bias voltage can be applied to the LBL. An applied voltage at the selected memory cell can then be equal to BLVDM minus WLVDM and is configured to be greater than a maximum set voltage and less than a minimum reset voltage for the memory cell. A snapback can increase the voltage on the optical fiber from WLVDM to a voltage at or near zero, and the absence of a snapback can have no effect on the voltage on the optical fiber; that is, the optical fiber voltage can remain at WLVDM. 412 includes generating a reference voltage, V REF, using charges on the capacitance associated with the GWL and the first sensing circuit arrangement capacitance. The reference voltage can, as described here, be based at least partially on an inherent capacitance based on the GWL, the first sensing circuit arrangement capacitance, a second sensing circuit arrangement capacitance, and a tuning capacitance. For example, the nodes HNREG and HNREGB of the sensing circuit arrangement can 230 They must be coupled to balance the stresses on the capacitors.

[0075] After a sensing interval, the fiber optic cable can be used in the process 414 to be coupled with the sensing circuit arrangement. As a result of the process 414 Can the node HNREG be placed on V? SENSE will be loaded. V SENSE is based at least partially on the state of the read memory cell. Process 416may include determining the working memory cell state, at least partially on V REF and the working memory cell voltage V LWL based. process 418 can provide a logic level output that corresponds to the memory cell state. For example, a sensing amplifier, e.g., a sensing amplifier, can 240 , be configured to V SENSE and V REF to receive and provide a logic level output that is at least partially based on whether V SENSE greater or less than V REF The program flow can then be interrupted during the process. 420 end.

[0076] Thus, the processes of the flowchart are 400 configured to provide a reference voltage V REF to generate using inherent capacitances and a WL bias, WLVDM. The processes of the flowchart 400They are also configured to apply a bias voltage to the memory cell and to detect a selected memory cell voltage. Whether a snapback occurs or not can then be determined, at least partially, based on the relative values ​​of one of the detected memory cell voltages V. LWL and V REF associated perceived tension V SENSE based on.

[0077] While Fig. Four different processes according to one embodiment are illustrated; it is understood that not all of the processes described in the illustration are shown. Fig. The processes shown in section 4 are necessary for other embodiments. In fact, it is fully taken into account here that in other embodiments of the present disclosure, the processes shown in Fig.The processes depicted in the drawings and / or other processes described herein can be combined in a manner not specifically shown in any of the drawings and yet still fully comply with the present disclosure. Therefore, patent claims relating to features and / or processes not exactly shown in a drawing are considered to be within the scope and content of the present disclosure.

[0078] As used in any embodiment herein, the term "logic" may refer to an application, software, firmware, and / or circuit arrangement configured to perform the operations mentioned above. Software may be implemented as a software package, code, instructions, instruction sets, and / or data recorded on a non-transistoric, computer-readable storage medium. Firmware may be implemented as code, instructions or instruction sets, and / or data permanently embedded (e.g., non-volatile) in working memory devices.

[0079] “Circuit arrangement,” as used herein in any embodiment, may, for example, individually or in any combination, include hard-wired circuit arrangements, programmable circuit arrangements such as computer processors comprising one or more individual instruction-executing cores, state machine circuit arrangements, and / or firmware that stores instructions executed by a programmable circuit arrangement. The logic may, collectively or individually, be implemented as a circuit arrangement that forms part of a larger system, such as an integrated circuit (IC), an application-specific integrated circuit (ASIC), a system-on-a-chip (SoC), desktop computers, laptop computers, tablet computers, servers, smartphones, etc.

[0080] In some embodiments, a hardware description language may be used to specify circuit and / or logic implementation(s) for the various logic and / or circuit types described herein. For example, in one embodiment, the hardware description language may be equivalent to or compatible with a high-speed integrated circuit (VHSIC) hardware description language (VHDL) that enables semiconductor fabrication of one or more of the circuits and / or logics described herein. The VHDL may be equivalent to or compatible with the IEEE 1076-1987 standard, IEEE 1076.2 standard, IEEE 1076.1, IEEE Draft 3.0 of VHDL-2006, IEEE Draft 4.0 of VHDL-2008, and / or other versions of the IEEE VHDL standards and / or other hardware description standards.

[0081] This disclosure thus describes a system and a method configured for the local generation of a reference voltage for reading memory cells. The system and method are configured to use inherent capacitances associated with a local WL, a global WL, and a first sensing circuit array capacitance. A bias applied as part of a memory read operation charges the inherent capacitances. A resulting charge on the inherent capacitances can then be used to generate the reference voltage. A value of the reference voltage is based at least partially on relative values ​​of the inherent capacitances. In one embodiment, a global WL from an unselected adjacent memory region can provide a tuning capacitance configured to tune the reference voltage as described herein.In another embodiment, a trimmer capacitor circuit arrangement can provide additional (i.e., tuning) capacitance configured to establish a target reference voltage.

[0082] The system and method can also include a two-stage sensing amplifier. A reference voltage is generated from the charges on the inherent capacitances by coupling the inputs of the sensing amplifier, which also causes any noise present in the sensing circuit to become common-mode. The reference voltage is applied to a first input, and a sensing voltage corresponding to the reference voltage and an output from the selected memory cell are applied to a second input of the sensing amplifier. A first stage is configured to convert negative input voltages to intermediate voltages that correspond to a supply voltage V. CCThe intermediate voltages are referenced and their levels shifted. The intermediate voltages are output by the first stage and input into a second stage. The second stage converts the intermediate voltages into a logic-level signal, i.e., logic one or logic zero, which is V CC or V SS The sensing amplifier is configured to provide a level shift with relatively low energy and relatively high speed, configured to produce a logic-level output from a relatively low input with relatively robust noise immunity. Examples

[0083] Examples of the disclosures presented here include, as discussed below, subjects such as a method, means for carrying out steps of the method, a device or apparatus or system belonging to a reference architecture in a cross-point memory. Example 1

[0084] According to this example, a device is provided that includes a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell. The memory controller also includes a bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and a sensing circuitry. The sensing circuitry includes a first sensing circuitry capacitor and a second sensing circuitry capacitor. The sensing circuitry is configured to preload the selected GWL, the LWL, and the first sensing circuitry capacitor to a WL bias WLVDM.The sensing circuit arrangement is also configured to provide a reference voltage (V. REF ) using a charge on the selected GWL and a charge on the first sensing circuit assembly capacitor. The sensing circuit assembly is also configured to at least partially access V REF and a detected working memory cell voltage V LWL based on determining the state of a working memory cell. Example 2

[0085] This example includes the elements from Example 1, with the BL switch circuit arrangement configured to apply a BL bias (BLVDM) to the selected LBL. Example 3

[0086] This example includes the elements from Example 1 and also includes an adjustment capacity, where V REF at least partially based on the adjustment capacity. Example 4

[0087] This example includes the elements from Example 3, wherein the adjustment capacitance includes at least one from a trimmer capacitor circuit arrangement and an unselected GWL. Example 5

[0088] This example includes the elements from Example 3 or 4, where the sum of the GWL capacitance and the first sensing circuit arrangement capacitance is equal to the sum of the second sensing circuit arrangement capacitance and the setting capacitance. Example 6

[0089] This example includes the elements from Example 4, where the trimmer capacitor circuit arrangement is a binary weighted trimmer capacitor. Example 7

[0090] This example includes the elements from one of examples 1 to 3, where the V REF is equal to half of WLVDM. Example 8

[0091] This example includes the elements from Example 3 or 4, with the adjustment capacity configured to V REF to adjust so that V REF greater than or less than half of WLVDM. Example 9

[0092] This example includes the elements from Example 4, with the trimmer capacitor circuit arrangement configured to be shared by an adjacent working memory section. Example 10

[0093] This example includes the elements from one of Examples 1 to 3 and additionally includes a sensing amplifier having a first input coupled to the second sensing circuit arrangement capacitor and a second input coupled to the first sensing circuit arrangement capacitor, wherein the sensing circuit arrangement is configured to couple the first input to the second input to provide V REF to produce. Example 11

[0094] This example includes the elements from Example 10, with the sensing amplifier configured to produce a V REF and V LWL associated perceived tension (V SENSE ) to receive, V SENSE and V REF to shift the levels of positively referenced intermediate voltages and to convert the intermediate voltages to a logic level output that corresponds to the state of the target working memory cell. Example 12

[0095] According to this example, a procedure is provided that includes: the selection of a target memory cell for a memory access operation by a memory controller; the selection of a global WL (GWL) and local WL (LWL) associated with the target memory cell by a word line (WL) switching circuit arrangement; the selection of a global BL (GBL) and local BL (LBL) associated with the target memory cell by a bit line (BL) switching circuit arrangement; the pre-charging of the selected GWL, LWL, and an initial sensing circuit arrangement capacitance to a WL bias WLVDM by a sensing circuit arrangement; and the generation of a reference voltage (V). REF) by the sensing circuit arrangement using a charge on the selected GWL and a charge on the first sensing circuit arrangement capacitor; and determining a state of the target working memory cell by the sensing circuit arrangement, at least partially on V REF and a detected working memory cell voltage V LWL based. Example 13

[0096] This example includes the elements from Example 12 and also includes the application of a BL bias (BLVDM) to the selected LBL by the BL switch circuit arrangement. Example 14

[0097] This example includes the elements from Example 12, where V REF at least partially based on an adjustment capacity. Example 15

[0098] This example includes the elements from Example 14, wherein the adjustment capacitance includes at least one from a trimmer capacitor circuit arrangement and an unselected GWL. Example 16

[0099] This example includes the elements from Example 14, where the sum of the GWL capacitance and the first sensing circuit arrangement capacitance is equal to the sum of the second sensing circuit arrangement capacitance and the setting capacitance. Example 17

[0100] This example includes the elements from Example 15, where the trimmer capacitor circuit arrangement is a binary weighted trimmer capacitor. Example 18

[0101] This example includes the elements from Example, where V REF is equal to half of WLVDM. Example 19

[0102] This example includes the elements from Example 14, with the setting capacity configured to VREF to adjust so that V REF greater than or less than half of WLVDM. Example 20

[0103] This example includes the elements from Example 15, with the trimmer capacitor circuit arrangement configured to be shared by an adjacent working memory section. Example 21

[0104] This example includes the elements from Example 12 and additionally includes coupling a first input of a sensing amplifier with a second input of the sensing amplifier through the sensing circuit arrangement to obtain V REF to generate, wherein the first input is coupled to a second sensing circuit arrangement capacitance and the second input is coupled to the first sensing circuit arrangement capacitance. Example 22

[0105] This example includes the elements from Example 21 and also includes receiving a sensed voltage (VSENSE ), the V REF and V LWL is assigned by the sensing amplifier; the level shift of V SENSE and V REF on positively referenced intermediate voltages by the sensing amplifier; and the conversion of the intermediate voltages to a logic level output corresponding to the state of the target working memory cell by the sensing amplifier. Example 23

[0106] According to this example, a system comprising a processor; a crosspoint memory array comprising a target memory cell, a target word line (WL), and a target bit line (BL) is provided. The target memory cell is sandwiched between the target WL and the target BL. The system also includes a memory controller coupled to the processor and the crosspoint memory array. The memory controller is configured to select a target memory cell for a memory cell access operation.The memory controller comprises a word line (WL) switch circuitry configured to select a global WL (GWL) and local WL (LWL) associated with the target memory cell; a bit line (BL) switch circuitry configured to select a global BL (GBL) and local BL (LBL) associated with the target memory cell; and a sensing circuitry. The sensing circuitry includes a first sensing capacitor and a second sensing capacitor. The sensing circuitry is configured to preload the selected GWL, the LWL, and the first sensing circuitry capacitor to a WL bias voltage (WLVDM). The sensing circuitry is also configured to apply a reference voltage (V). REF) using a charge on the selected GWL and a charge on the first sensing circuit arrangement capacitor, and to generate a state of the target working memory cell at least partially on the V REF and a detected working memory cell voltage V LWL to determine based on. Example 24

[0107] This example includes the elements from Example 23, with the BL switch circuit arrangement configured to apply a BL bias (BLVDM) to the selected LBL. Example 25

[0108] This example includes the elements from Example 23 and also includes an adjustment capacity, where V REF at least partially based on the adjustment capacity. Example 26

[0109] This example includes the elements from Example, where the adjustment capacitance includes at least one from a trimmer capacitor circuit arrangement and an unselected GWL. Example 27

[0110] This example comprises the elements of example claim 25 or 26, wherein a sum of the GWL capacity and the first sensing circuit arrangement capacity is equal to a sum of a second sensing circuit arrangement capacity and the setting capacity. Example 28

[0111] This example includes the elements from Example 26, where the trimmer capacitor circuit arrangement is a binary weighted trimmer capacitor. Example 29

[0112] This example includes the elements from Examples 23 to 25, where the V REF is equal to half of WLVDM. Example 30

[0113] This example includes the elements from Example 25 or 26, with the setting capacity configured to V REF to adjust so that V REF greater than or less than half of WLVDM. Example 31

[0114] This example includes the elements from Example 26, with the trimmer capacitor circuit arrangement configured to be shared by an adjacent working memory section. Example 32

[0115] This example includes the elements from Examples 23 to 25 and additionally includes a sensing amplifier having a first input coupled to the second sensing circuit arrangement capacitance and a second input coupled to the first sensing circuit arrangement capacitance, wherein the sensing circuit arrangement is configured to couple the first input to the second input to provide V REF to produce. Example 33

[0116] This example includes the elements from Example 32, with the sensing amplifier configured to produce a V REF and V LWL associated perceived tension (V SENSE ) to receive, V SENSE and V REF to shift the levels of positively referenced intermediate voltages and to convert the intermediate voltages to a logic level output that corresponds to the state of the target working memory cell. Example 34

[0117] Another example of the present disclosure is a system comprising at least one device arranged to carry out the method according to any one of claims 12 to 22. Example 35

[0118] Another example of the present disclosure is a device comprising means for carrying out the method according to any one of claims 12 to 22. Various features, aspects, and embodiments have been described herein. These features, aspects, and embodiments permit combinations, variations, and modifications, as those skilled in the art will understand. The present disclosure should therefore be understood as including such combinations, variations, and modifications.

Claims

[1] Device comprising: a memory controller configured to select a target memory cell for a memory access operation, wherein the memory controller includes: a word line (WL) switch circuit arrangement configured to select one global WL (GWL) and local WL (LWL) associated with the target working memory cell; a bit line (BL) switch circuit arrangement configured to select one global BL (GBL) and one local BL (LBL) associated with the target memory cell; and a sensing circuit arrangement comprising a first sensing circuit arrangement capacitor and a second sensing circuit arrangement capacitor, wherein the sensing circuit arrangement is configured to precharge the selected GWL, the LWL and the first sensing circuit arrangement capacitor to a WL bias WLVDM, a reference voltage (V REF) using the charge on the selected GWL and the charge on the first sensing circuit arrangement capacitor to generate a state of the target working memory cell, at least partially on V REF and a detected working memory cell voltage V LWL to determine based on. [2] Device according to claim 1, wherein the BL switch circuit arrangement is configured to apply a BL bias (BLVDM) to the selected LBL. [3] Device according to claim 1, which further comprises an adjustment capacity, wherein V REF at least partially based on the adjustment capacity. [4] Device according to claim 3, wherein the adjustment capacity comprises at least one consisting of a trimmer capacitor circuit arrangement and an unselected GWL. [5] Device according to claim 3 or 4, wherein the sum of the GWL capacity and the first sensing circuit arrangement capacity is equal to the sum of the second sensing circuit arrangement capacity and the setting capacity. [6] Device according to any one of claims 1 to 3, further comprising a sensing amplifier comprising a first input coupled to the second sensing circuit arrangement capacitor and a second input coupled to the first sensing circuit arrangement capacitor, wherein the sensing circuit arrangement is configured to couple the first input with the second input in order to V REF to produce. [7] Device according to claim 6, wherein the sensing amplifier is configured to detect a sensed voltage (V SENSE ), which lead to V REF and V LWL belonging to, to receive, V SENSE and V REFto shift the levels to positively referenced intermediate voltages and to convert the intermediate voltages to a logic level output corresponding to the state of the target working memory cell. [8] Procedure that includes: the selection of a target memory cell for a memory access operation by a memory controller; the selection of one of the global WL (GWL) and local WL (LWL) assigned to the target working memory cell by the word line (WL) switch circuit arrangement; the selection of one of the global BL (GBL) and local BL (LBL) assigned to the target memory cell by the bit line (BL) switch circuit arrangement; the pre-charging of the selected GWL, the LWL and a first sensing circuit arrangement capacity to a WL bias WLVDM by the sensing circuit arrangement; generating a reference voltage (V REF) using a charge on the selected GWL and a charge on the first sensing circuit arrangement capacitor through the sensing circuit arrangement; and Determining the state of the target working memory cell by the sensing circuit arrangement, at least partially based on V REF and a detected working memory cell voltage V LWL based. [9] The method of claim 8, further comprising: the application of a BL bias (BLVDM) to the selected LBL by the BL switch circuit arrangement. [10] Method according to claim 8, wherein V REF at least partially based on an adjustment capacity. [11] Method according to claim 10, wherein a sum of the GWL capacity and the first sensing circuit arrangement capacity is equal to a sum of a second sensing circuit arrangement capacity and the setting capacity. [12] Method according to claim 10, wherein the adjustment capacity comprises at least one consisting of a trimmer capacitor circuit arrangement and an unselected GWL. [13] The method of claim 8, further comprising: the coupling by the sensing circuit arrangement of a first input of a sensing amplifier with a second input of the sensing amplifier, in order to V REF to generate, wherein the first input is coupled to a second sensing circuit arrangement capacitance and the second input is coupled to the first sensing circuit arrangement capacitance. [14] The method of claim 13, further comprising: receiving a V REF and V LWL associated sensing voltage (V) SENSE ) through the sensing amplifier; the level shift of V SENSE and V REF on positively referenced intermediate voltages through the sensing amplifier; and the conversion of the intermediate voltages by the sensing amplifier to a logic level output that corresponds to the state of the target working memory cell. [15] System, encompassing: a processor; a crossover point memory arrangement comprising a target memory cell, a target word line (WL) and a target bit line (BL), wherein the target memory cell is connected between the target WL and the target BL; and a memory controller coupled to the processor and the intersection point memory array, wherein the memory controller is configured to select a target memory cell for a memory access operation, and wherein the memory controller comprises: a word line (WL) switch circuit arrangement configured to select one of the global WL (GWL) and local WL (LWL) associated with the target working memory cell; a bit line (BL) switch circuit arrangement configured to select one of the global BL (GBL) and local BL (LBL) associated with the target memory cell; and a sensing circuit arrangement comprising a first sensing circuit arrangement capacitor and a second sensing circuit arrangement capacitor, wherein the sensing circuit arrangement is configured to precharge the selected GWL, the LWL and the first sensing circuit arrangement capacitor to a WL bias WLVDM, a reference voltage (V REF ) using the charge on the selected GWL and the charge on the first sensing circuit arrangement capacitor to generate a state of a target working memory cell, at least partially on V REF and a detected target working memory cell voltage V LWL to determine based on. [16] System according to claim 15, wherein the BL switch circuit arrangement is configured to apply a BL bias (BLVDM) to the selected LBL. [17] System according to claim 15, which further comprises an adjustment capacity, wherein V REF at least partially based on the adjustment capacity. [18] System according to claim 17, wherein the adjustment capacity comprises at least one consisting of a trimmer capacitor circuit arrangement and an unselected GWL. [19] System according to claim 17 or 18, wherein the sum of the GWL capacity and the first sensing circuit arrangement capacity is equal to the sum of the second sensing circuit arrangement capacity and the setting capacity. [20] System according to any one of claims 14 to 16, further comprising a sensing amplifier comprising a first input coupled to the second sensing circuit arrangement capacitance and a second input coupled to the first sensing circuit arrangement capacitance, wherein the sensing amplifier is configured to couple the first input to the second input to V REF to produce. [21] System according to claim 20, wherein the sensing amplifier is configured to detect a V REF and V LWL associated perceived tension (V SENSE ) to receive, V SENSE and V REF to shift the levels to positively referenced intermediate voltages and to convert the intermediate voltages to a logic level output corresponding to the state of the target working memory cell. [22] System comprising at least one device arranged for carrying out the method according to any one of claims 8 to 14. [23] Device comprising the means for carrying out the method according to any one of claims 8 to 14.