Spin logic with magnetic insulators switched by spin-orbit coupling

Abstract

Device comprising: a non-magnetic conductor (201a, 201b); a first spin-orbit coupling layer, SOC layer (202), which is coupled to the first non-magnetic conductor (201a, 201b); a first ferromagnet, FM (204a), coupled to the first SOC layer (202); a second FM (204b); and a second layer (203) comprising a magnetic insulating material, wherein the second layer (203) is arranged between the first and second magnets (204a, 204b) such that magnetic insulating material is in direct contact with the first and second magnets (204a, 204b); where the first SOC layer (202) has: a third layer coupled to the first magnet (204a), wherein the first SOC layer comprises one or more of Bi and Ag, Bi and Cu, or Pb and Ag; and a fourth layer coupled to the third layer and another non-magnetic metal, wherein the fourth layer comprises one of Ag, Cu, or Au.

Description

BACKGROUND

[0001] Spintronics deals with the study of the intrinsic spins of the electron and the associated magnetic moment in solid-state devices. Spintronic logic involves integrated switching devices that use a physical variable of magnetization or spin as a computational variable. Such variables can be non-volatile (i.e., they retain a computational state when power to an integrated circuit is switched off). Non-volatile logic can improve performance and computational efficiency by allowing architects to put a processor into a powerless sleep state more frequently and with less energy. Existing spintronic logic generally suffers from high power consumption and relatively long switching times.

[0002] US 2014 / 0169088 A1 describes a neuron and synapse implementation comprising a circuit element containing a first and a second nanomagnet, as well as a first and a second fixed magnet. The first nanomagnet is inductively coupled to a first current-carrying element and configured to change its polarity depending on the current in the first current-carrying element. In one example, the first current-carrying element comprises a spin Hall-effect substrate. The second nanomagnet is magnetically coupled to the first nanomagnet and inductively coupled to a second current-carrying element. The first fixed magnet is positioned on top of the second nanomagnet and has a first fixed polarity, and the second fixed magnet is positioned on top of the second nanomagnet and has a second fixed polarity.

[0003] US 2014 / 0139265 A1 describes magnetic logic devices and architectures with high-speed, precision-switched operation. In a first example, a magnetic logic device comprises an input electrode with a first nanomagnet and an output electrode with a second nanomagnet. The spins of the second nanomagnet are non-collinear with the spins of the first nanomagnet. A channel region and a corresponding ground electrode are positioned between the input and output electrodes. In a second example, a magnetic logic device comprises an input electrode with an in-plane nanomagnet and an output electrode with a magnet exhibiting perpendicular magnetic anisotropy (PMA). A channel region and a corresponding ground electrode are positioned between the input and output electrodes.

[0004] DATTA, Supriyo; SALAHUDDIN, Sayeef; BEHIN-AEIN, Behtash: Nonvolatile spin switch for Boolean and non-Boolean logic. In: Applied Physics Letters, Vol. 101, No. 25, 2012, shows that the established physics of spin valves, together with the recently discovered giant spin Hall effect, could be used to construct read / write units that can be integrated into a single spin switch with input-output isolation, amplification, and fan-out similar to CMOS inverters, except that the information stored in nanomagnets is non-volatile. Such spin switches could be interconnected without external amplification, using only passive circuit elements, to perform logic operations. Since digitization and storage occur naturally in the magnets, the voltages can also be used to implement analog weighting for non-Boolean logic.

[0005] WO 2015 / 102739 A2 describes a device based on the spin Hall effect and the spin transfer torque (STT) effect, comprising: a magnetic tunnel junction element (MTJ) with a free magnetic layer structured so that its magnetization direction can be changed by spin transfer torque; an electrically conductive magnetic layer structure exhibiting a spin Hall effect (SHE) and generating, in response to an applied in-plane charge current, a spin-polarized current with a magnetic moment oriented in a predetermined direction and exhibiting both an in-plane magnetic moment component parallel to a surface of the electrically conductive magnetic layer structure and a perpendicular magnetic moment component perpendicular to the surface of the electrically conductive magnetic layer structure.The magnetization direction of the free magnetic layer can be switched by the spin-polarized current via a spin-transfer torque (STT) effect. This device can be configured in a 3-terminal configuration.

[0006] US 2015 / 0269478A1 describes a neuron and synapse implementation comprising a circuit element containing a first and second nanomagnet, as well as a first and second fixed magnet. The first nanomagnet is inductively coupled to a first current-carrying element and configured to change its polarity depending on the current in the first current-carrying element. In one example, the first current-carrying element comprises a spin Hall-effect substrate. The second nanomagnet is magnetically coupled to the first nanomagnet and inductively coupled to a second current-carrying element. The first fixed magnet is positioned on top of the second nanomagnet and has a first fixed polarity, and the second fixed magnet is positioned on top of the second nanomagnet and has a second fixed polarity. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The embodiments of the disclosure are more clearly evident from the following detailed description and the accompanying drawings of various embodiments of the disclosure, which, however, are not to be understood as limiting the disclosure to the specific embodiments, but merely serve for explanation and understanding. Fig. Figure 1 illustrates a cross-section of a charge-spin logic (CSL) with a slow switching speed due to weak magnetic dipole coupling between nanomagnets. Fig. Figure 2 illustrates a spin orbit coupling (SOC) receiver and a ferromagnet (FM) insulator coupled between FMs, according to some embodiments of the disclosure. Fig. Figure 3 illustrates a transmitter-receiver with the receiver made of Fig. 2 and a transmitter based on tunnel magnetoresistance (TMR), according to some embodiments of the disclosure. Fig. Figure 4 illustrates a transmitter-receiver with the receiver made of Fig. 2 and a transmitter based on Inverse SOC (ISOC), according to some embodiments of the disclosure. Fig. Figure 5 illustrates a flowchart of a procedure for operating the receiver from Fig. 2 according to some embodiments of the disclosure. Fig. Figure 6 illustrates a smart device, computer system, or SoC (System-on-Chip) with a receiver made of Fig. 2 and / or transmit / receive from Fig. 3-4 according to some embodiments. DETAILED DESCRIPTION

[0008] Fig. Figure 1 illustrates a cross-section of a charge-spin logic (CSL) circuit with slow switching speed and unreliable circuitry due to weak coupling between nanomagnets. Here, the section to the left of the vertical dotted line is the receiver (or write unit), and the section to the right of the vertical dotted line is the transmitter (or read unit). The receiver receives an input V in from a non-magnetic conductor (for example, Cu) coupled to a material exhibiting a spin Hall effect (SHE). If an input charging current of V in When the current is conducted from the non-magnetic conductor to the layer exhibiting a SHE (i.e., the SHE layer), the charging current causes a polarized spin current I' to be generated. s to the surface of the SHE layer. The surface of the SHE layer is coupled to an input ferromagnet (FM). The polarized spin current I' sIt applies a spin transfer torque (STT) to the input FM, which can switch the magnetization of the input FM. Accordingly, data associated with the input charging current (supplied by V) in ) are related to the input FM being “written” or “received”.

[0009] The incoming FM and the SHE layer from Fig. 1 are isolated from the transmitter (i.e., the right side of the vertical dotted line) by an insulator. The transmitter here consists of several layers—a non-magnetic layer and two magnetic tunnel junctions (MTJs), one of which is biased by the voltage -V, while the other MTJ is biased by the voltage +V. The MTJs are formed with two magnetic layers—one fixed and one free magnet—separated by a dielectric tunnel layer (e.g., MgO). Here, one of the two layers common to both MTJs is the output FM (i.e., the free magnet), which is coupled to the MgO layer and the non-magnetic conductor. The other side of the MgO tunnel dielectric is coupled to two fixed magnets separated by an insulator. The fixed magnets can have different coercive field values ​​H. c1 and H c2They exhibit and are initially set in opposite magnetization directions (indicated by the dot and cross on the FMs and positive (+M) and negative (-M) magnetizations). This is achieved by magnetic annealing, first in a stronger external magnetic field (i.e., greater than H). c2 ) in one direction and then in a weaker magnetic field (i.e. smaller than H) c2 , however larger than H c1 ) in the opposite direction.

[0010] The transmitter's output FM is switched across the input FM via magnetic dipole coupling. This coupling causes a current I to flow through the non-magnetic conductor via the tunneling magneto-resistance (TMR) effect: greater MTJ resistance if the magnetizations are antiparallel, and lower MTJ resistance if the magnetizations are parallel. The TMR uses a variable spin-in-charge conversion with limited conversion efficiency. Voltages of opposite polarities (i.e., +V and -V) are applied to the fixed magnetic layers of the two MTJs. Depending on the magnetization direction of the free output FM, its voltage is greater or less than zero. The sign of the resulting current I (which flows across V) out -connection is collected) is by V out , the voltage at the output FM, is determined.

[0011] Although the CSL from Fig. While functionally sound, this method has several disadvantages. For example, the magnetic dipole coupling between the input FM and the output FM via the insulator is too weak (e.g., 100 Oe), and therefore an input FM with a larger magnetic moment is required. Consequently, a stronger current I is drawn from the output FM. in A connection is required to switch the magnetization of the input FM across the SHE layer. This current applies spin transfer torque to the output FM and can disrupt its magnetization. Thus, such switching is unreliable and does not ensure input-output isolation. The higher current requirement directly contradicts the attenuation of read noise (i.e., there is a high probability of read noise being introduced by higher currents). The weak magnetic dipole coupling also causes slow switching of the output FM.

[0012] To remedy at least the aforementioned disadvantages of CSL from Fig. 1 Some embodiments of FMs with strong exchange coupling use switching times in relation to the long switching times of the CSL. Fig. 1 to reduce. In some embodiments, composite nanomagnets are provided comprising two FM metal layers separated by an insulating FM(IFM) layer. In some embodiments, a device or logic (or receiver) is provided comprising a first non-magnetic conductor; a first spin-orbit coupling layer (SOC layer) coupled to the first non-magnetic conductor; a first FM coupled to the SOC layer; a second FM; and an FM insulator sandwiched between the first and second FM.

[0013] There are many technical effects / advantages of the various embodiments of this disclosure. For example, the device in various embodiments exhibits a faster switching time than the CSL. Fig. 1. The device in various embodiments also has a smaller size than the CSL. Fig. 1, because it has fewer magnets than the CSL. Fig. 1. In some embodiments, there are no tunnel barriers (i.e., no MgO layer), and therefore the devices of some embodiments are more reliable than the CSL from Fig. 1. Because tunnel barriers often break under high tunnel currents, leading to equipment malfunctions. Other technical effects arise from the different designs and figures.

[0014] Numerous details are set forth in the following description to provide a more precise explanation of the embodiments of the present disclosure. However, it will be obvious to the person skilled in the art that the embodiments of the present disclosure can be implemented in practice without these specific details. In other cases, well-known structures and devices are shown in block diagram form and not in detail in order to avoid obscuring the embodiments of the present disclosure.

[0015] It should be noted that in the corresponding drawings of the embodiments, signals are represented by lines. Some lines may be thicker to indicate more constituent signal paths and / or have arrows at one or more ends to indicate the primary direction of information flow. Such indications are not intended to be restrictive. Rather, the lines are used in conjunction with one or more embodiments to facilitate a simpler understanding of a circuit or logic unit. Any signal shown, as dictated by design requirements or preferences, may actually comprise one or more signals capable of traveling in both directions and may be implemented using any suitable type of signal scheme.

[0016] Throughout this specification and in the claims, the term "connected" means a direct connection, such as an electrical, mechanical, or magnetic connection, between the things being connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things being connected, or an indirect connection through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and / or active components arranged to interact with each other to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal.The meaning of "ein", "eine", "einer" and "der", "die", "das" includes plural forms. The meaning of "in" includes "in", "auf", "an".

[0017] The terms "essentially", "close", "approximately", "nearly", and "about" generally refer to being within + / - 10% of a target value (unless specifically stated). Unless otherwise stated, the use of the ordinal adjectives "first", "second", and "third", etc., to describe a common object merely indicates that reference is being made to different instances of similar objects and does not imply that the objects so described must be in any particular order, whether temporal, spatial, sequential, or otherwise.

[0018] For the purposes of this disclosure, the expressions “A and / or B” and “A or B” mean (A), (B) or (A and B). For the purposes of this disclosure, the expression “A, B and / or C” means (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C).

[0019] For the purposes of these embodiments, the transistors in the various circuits and logic blocks described herein are metal-oxide-semiconductor (MOS) transistors or derivatives thereof, the MOS transistors including drain, source, gate, and bulk terminals. The transistors and / or MOS transistor derivatives also include tri-gate and FinFET transistors, gate all-around cylindrical transistors, tunneling FETs (TFETs), square-wire or rectangular-ribbon transistors, ferroelectric FETs (FeFETs), or other devices implementing transistor functionality, such as carbon nanotubes or spintronic devices. Symmetrical source and drain terminals of MOSFETs are therefore identical and are used interchangeably here. Conversely, a TFET device has asymmetrical source and drain terminals.Those skilled in the art will recognize that other transistors, for example bipolar junction transistors – BJT PNP / NPN, BiCMOS, CMOS, eFET, etc. – can be used without deviating from the scope of the disclosure. The term “MN” denotes an n-type transistor (e.g., NMOS, NPN, BJT, etc.) and the term “MP” denotes a p-type transistor (e.g., PMOS, PNP, BJT, etc.).

[0020] Fig. Figure 2 illustrates a receiver 200 with a SOC and an FM isolator coupled between FMs, according to some embodiments of the disclosure. In some embodiments, the receiver 200 comprises non-magnetic conductors (e.g., Cu) 201a and 201b, an SOC layer 202, a first FM 204a (i.e., FM1), a second FM 204b (i.e., FM2), and an FM isolator 203. In the following embodiments, the SOC layer 202 is any layer exhibiting a spin Hall effect. Accordingly, the SOC layer 202 is also referred to as the SHE layer 203. In some embodiments, a non-magnetic conductor 201a is coupled to the SHE layer 202 and provides the SHE layer 202 with an input charging current I. cIn some embodiments, at least one section of the lower surface of the SHE layer 202 is coupled to the non-magnetic conductor 201b, which is coupled to ground. In some embodiments, at least one section of the upper surface of the SHE layer 202 is coupled to the FM1 204a. In some embodiments, the FM1 204a is coupled to the FM insulator 203, which in turn is coupled to the FM2 204b.

[0021] In some embodiments, the SHE layer 202 (or the writing electrode) consists of one or more of β-tantalum (β-Ta), Ta, β-tungsten (β-W), W, Pt, copper (Cu), doped with elements such as iridium, bismuth, and any of the elements of period groups 3d, 4d, 5d and 4f, 5f in the periodic table, which may exhibit high spin-orbit coupling. The SHE layer 202 transitions into a non-magnetic layer of high-conductivity metal(s) (201a) to reduce the resistance of the connection with the SHE layer 202. The non-magnetic metal(s) is / are formed from one or more of the following: Cu, Co, α-Ta, Al, CuSi, or NiSi.

[0022] In some embodiments, the FM insulator 203, which is sandwiched between FM1 204a and FM2 204b, is formed from one or more of the following: yttrium iron garnet (YIG) Y3Fe5O 12 , magnetite Fe3O4, Fe2O3, NiO, Tb3Fe5O 12 or CrO2.

[0023] In some embodiments, the FMs 204a / b (collectively referred to here as FM 204) are free magnets formed from CFGG (i.e., cobalt (Co), iron (Fe), germanium (Ge), or gallium (Ga), or a combination thereof). In some embodiments, the FMs 204a / b are formed with materials of high spin polarization. Heusler alloys are an example of materials of high spin polarization. Heusler alloys are ferromagnetic due to a double exchange mechanism between adjacent magnetic ions. The FMs 204a / b are also referred to as the first and second magnetic contacts. FM1 204a is also referred to as the input magnet, while FM2 204b is also referred to as the output magnet. These designations are provided for the purpose of describing the different embodiments but do not change the structure of the receiver 200.

[0024] In some embodiments, the FMs 204a / b are equipped with a sufficiently high anisotropy (H k ) and a sufficiently low magnetic saturation (M s ) formed to increase the injection of spin currents. For example, Heusler alloys with high H k and lower M s used to form FMs 204a / b. In the following embodiments, the FMs 204a / b are described as Heusler alloys. However, in some embodiments, other magnetic materials with a high H can be used. k and a low M s exhibit, to be used to form the FMs 204a / b.

[0025] The magnetic saturation M s This is generally the state reached when an increase in the applied external magnetic field H cannot increase the magnetization of the material (i.e., the total magnetic flux density B essentially stabilizes). Here, a sufficiently low Ms , that M s less than 200 kA / m (kiloamperes per meter). The anisotropy H k This generally refers to a material property that is direction-dependent. Materials with H k These are materials with material properties that are strongly direction-dependent. A sufficiently high H is required here. k in connection with Heusler alloys considered to be greater than 2000 Oe (Oersted).

[0026] For example, a semimetal that has no band gap in spin-up states but a band gap in spin-down states (i.e., at energies within the band gap, the material has 100% spin-up electrons). If the material's Fermi level lies within the band gap, the injected electrons are nearly 100% spin-polarized. In this context, "spin-up" generally refers to the positive magnetization direction, and "spin-down" generally refers to the negative magnetization direction. Variations in the magnetization direction (e.g., due to thermal fluctuations) result in a mixture of spin polarizations.

[0027] In some embodiments, Heusler alloys such as Co2FeAl and Co2FeGeGa are used to form the FMs 204a / b. Other examples of Heusler alloys include: Cu2MnAl, Cu2MnIn, Cu2MnSn, Ni2MnAl, Ni2MnIn, Ni2MnSn, Ni2MnSb, Ni2MnGa, Co2MnAl, Co2MnSi, Co2MnGa, Co2MnGe, Pd2MnAl, Pd2MnIn, Pd2MnSn, Pd2MnSb, Co2FeSi, Fe2Val, Mn2VGa, Co2FeGe, etc. In some embodiments, the input nanomagnets FM1 204a are a Heusler alloy lattice compatible with Ag (i.e., the Heusler alloy is designed to have a lattice constant close to that of Ag (e.g., within 3%)).

[0028] In some embodiments, the applied current I c in the y-direction through the SHE layer 202 into the spin stream I s converted. In this example, the spin current I exerts sIn the z-direction, a spin transfer torque is applied to the nanomagnets of FM1 204a, reversing the magnetization direction of FM1 204a. The direction of magnetic writing to FM 204a is determined by the direction of the applied charging current I. c determined. Positive currents (i.e., currents flowing in the +y direction) generate a spin injection current with a transport direction (along the +z direction) and spins pointing in the +x direction. The injected spin current, in turn, generates a spin torque to align FM1 204a (coupled with the SHE layer 202) in the +x or -x direction. The injected spin current Is→, the one from a charging current Ic→ The value generated in FM1 204a is given by: Is→=PSHE(w,t,λsf,θSHE)(z^×Ic→) where the spin current vector Is→=I↑→−I↓→ the difference of the currents with spin along and opposite to the spin direction is, ẑ is the unit vector perpendicular to the interface, P SHE The spin Hall injection efficiency is the ratio of the magnitude of the transverse spin current to the lateral charging current, w is the width of the magnet, t is the thickness of the SHE layer 202, λ sf the spin-flip length in the SHE layer 202 is θ SHE The spin Hall angle for the SHE layer 202 to the free ferromagnetic layer interface is given by: The injected spin angular momentum, which is responsible for the spin torque, is given by: S→=h Is→ / 2e

[0029] In some embodiments, the FM layers exhibit parallel magnetizations (indicated by the parallel arrows) due to strong magnetic exchange between the FM layers (i.e., between FMs 204a / b via the FM insulator 203). Compared to the weak magnetic dipole coupling (e.g., 100 Oe) in Fig. In 1, the magnetic exchange between FMs 204a / b is much stronger (e.g., 10,000 Oe). In some embodiments, the FM insulator 203 provides electrical isolation between FM1 204a and FM2 204b, but allows the spin current I to s from the SHE layer 202 switches all free magnets - FM 204a / b and 203.

[0030] In some embodiments, several non-magnetic input conductors 201aa, 201bb, 201cc, etc. (not shown) are coupled to the SHE layer 202. For example, several input conductors 201aa, 201bb, 201cc are coupled to conductor 201a. Each of these multiple input conductors carries the input charging currents I ca , I cb , or I cc Subsequently, structure 200 performs the logical function of a majority gate (i.e., the magnetic state is set according to the sign of the majority of the input currents collected by conductor 201a). Alternatively, the structure performs the function of a minority gate (i.e., negation of the majority gate) if an inversion operation is applied to the magnetic state reading, as described below.

[0031] Fig. Figure 3 illustrates a 300 transmitter-receiver with the receiver made of Fig. 2 and a transmitter based on TMR, according to some embodiments of the disclosure. It should be noted that those elements from Fig. 3, which have the same reference numerals (or names) as the elements of any other figure, may operate or function in any manner similar to that described, but are not limited to doing so. In order not to complicate the understanding of the embodiments, differences between Fig. 3 and Fig. 2 described. In some embodiments, a transmitter section is combined with the receiver made of Fig. 2 coupled.

[0032] In some embodiments, the transmitter comprises two MTJ devices formed using the free FM 204b as the common free magnetic layer. In some embodiments, the first MTJ device is formed by a fixed FM 204c coupled to the free FM 204b via a dielectric tunnel MgO 301a. In some embodiments, the second MTJ device is formed by a fixed FM 204d coupled to the free FM 204b via a dielectric tunnel MgO 301b. In some embodiments, electrical contacts are coupled to the fixed FMs. For example, the non-magnetic conductor 201c is coupled to the FM 204c, wherein the non-magnetic conductor 201c is coupled to a positive supply (e.g., VDD). In some embodiments, the non-magnetic conductor 201d is coupled to the FM 204d, wherein the non-magnetic conductor 201d is coupled to a negative supply (e.g. -VDD).

[0033] In one case, the magnetization directions of the fixed FMs 204c / d are parallel to the magnetization direction of the free FM 204b (i.e., the magnetization directions of the free and fixed magnetic layers are parallel to each other). For example, the magnetization direction of the free FM 204b lies in the plane, while the magnetization directions of the fixed FMs 204c / d also lie in the plane. In another case, the magnetization directions of the fixed FMs 204c / d lie outside the plane, while the magnetization direction of the free FM 204b also lies outside the plane.

[0034] The thickness of a ferromagnetic layer (i.e., a solid or free magnetic layer) can determine its magnetization direction. For example, if the thickness of the ferromagnetic layer is above a certain threshold (depending on the magnet material, e.g., approximately 1.5 nm for CoFe), the ferromagnetic layer will have a magnetization direction that lies in the plane. Likewise, if the thickness of the ferromagnetic layer is below a certain threshold (depending on the magnet material), the ferromagnetic layer will have a magnetization direction that is perpendicular to the plane of the magnetic layer.

[0035] Other factors can also determine the magnetization direction. For example, factors such as surface anisotropy (depending on the adjacent layers or a multilayer composition of the ferromagnetic layer) and / or crystalline anisotropy (depending on the stress and the crystal lattice structure modification such as FCC, BCC, or L10 type of crystals, where L10 is a crystal class type that has perpendicular magnetizations) can also determine the magnetization direction.

[0036] In some embodiments, the transmitter further comprises a non-magnetic conductor 201e, one end of which is coupled to the FM 204b to collect the charging current, and the other end of which is coupled to another non-magnetic conductor 201f. In some embodiments, the non-magnetic conductor 201e behaves as a common node of a resistance divider, the resistances being the resistances of the two MTJs (one biased with VDD and the other with -VDD) coupled to the common node (i.e., non-magnetic conductor 201e).

[0037] The embodiment from Fig. 3 is more compact than the logic from Fig. 1, since the transmitter-receiver 300 has stacked all its magnets on top of each other, while the magnets in Fig. The FMs are arranged in two separate stacks (i.e., stacks on the receiver side and the transmitter side). Stacking all FMs (i.e., FM 204a / b, FM isolator 203, and FM 204c / d) together creates a more easily manufacturable logic. In some embodiments, the FMs can be formed in situ by stacking all FMs (i.e., FM 204a / b, FM isolator 203, and FM 204c / d) together (i.e., without breaking a vacuum). This creates a higher-quality device.

[0038] In some embodiments, the transceiver 300 is cascadeable. For example, the non-magnetic conductor 201e of the transceiver 300 can be coupled to a non-magnetic conductor 201a of another receiver (not shown). In this way, the logic elements can be cascaded in a VLSI (Very Large Scale Integrated) circuit.

[0039] In some embodiments, the output 201e of the transceiver 300 can be one of several inputs to a logic circuit. For example, the output 201ea of ​​the transceiver 300a (not shown), the output 201eb of the transceiver 300b (not shown), the output 201ec of the transceiver 300c (not shown), etc., are coupled to the input 201a of the transceiver 300. Each of these conductors 201ea, 201eb, and 201ec, for example, carries the charging currents I ca , I cb or I cc . Thereafter, the transmitter-receiver 300 performs the logical function of a majority gate (i.e., the sign of the output current in 201e is in accordance with the sign of the majority of the input charging currents I). ca , I cb and I ccset) according to some embodiments. Alternatively, the transmit-receiver 300 can perform the function of a minority gate (i.e., negation of the majority gate) when an inversion operation is applied to the readout (i.e., the opposite direction of the output current in 201e is set as positive).

[0040] Fig. Figure 4 illustrates a 400 transmitter-receiver with the receiver made of Fig. 2 and a transmitter based on Inverse SOC (ISOC), according to some embodiments of the disclosure. It should be noted that those elements from Fig. 4, which have the same reference numerals (or names) as the elements of any other figure, may operate or function in any manner similar to that described, but are not limited to doing so. In order not to complicate the understanding of the embodiments, differences between Fig. 4 and Fig. 2 described. In some embodiments, a transmitter section is combined with the receiver made of Fig. 2 coupled.

[0041] In some embodiments, the transmitter comprises a non-magnetic conductor 201g formed over a section of the FM 204b. In some embodiments, the transmitter further comprises a non-magnetic conductor 201h, provided such that one end of the non-magnetic conductor 201h is coupled to the FM 204b, while the other end of 201h is coupled to the SHE layer 202b (also part of the transmitter). In some embodiments, at least one section of the lower surface of the SHE layer 202b is coupled to ground via the non-magnetic conductor 201i. Here, the SHE layer 202a provides charge-to-spin conversion, while the SHE layer 202b provides spin-to-charge conversion.

[0042] In some embodiments, spin-in-charge conversion is achieved via spin-orbit interaction at metallic interfaces (i.e., using the inverse Rashba gem effect (IREE) and / or inverse SHE (ISHE), where a spin current injected by an input magnet generates a charge current). In some embodiments, the SHE layer 202a has an interface layer that converts a charge current into a spin current using the Rashba gem effect, while the bulk section of the SHE layer 202a converts a charge current into a spin current using SHE. In some embodiments, the SHE layer 202b has an interface layer that converts a spin current into a charge current using ISHE, while the bulk section of the SHE layer 202b converts a spin current into a charge current using SHE.

[0043] Table 1 summarizes transduction mechanisms for converting spin current into charging current and charging current into spin current for bulk materials and interfaces. Table 1: Transduction mechanisms for the conversion of spin to charge and charge to spin due to SOC Ladung → Spin Spin → Ladung Bulk Spin-Hall-Effekt Inverser Spin-Hall-Effekt Grenzfläche Rashba-Edelstein-Effekt Inverser Rashba-Edelstein-Effekt

[0044] In some embodiments, layers 202a / b are made of Fig. 4 (and the SHE layer 202 from Fig. 2) A superlattice stack that is functionally equivalent to a material providing a spin Hall effect. In some embodiments, the superlattice stack of the SHE layers 202a / b comprises layers of metals such as copper (Cu), silver (Ag), gold (Au), and layers of a surface alloy, e.g., bismuth (Bi) on Ag. In some embodiments, an FM layer is deposited on the superlattice 202b, the FM layer being made of CFGG (i.e., cobalt (Co), iron (Fe), germanium (Ge), or gallium (Ga), or a combination thereof). In some embodiments, 'N' number of layers of a surface alloy (e.g., interface layer) and of metal (e.g., bulk layer) are stacked alternately, 'N' being an integer to form a superlattice stack 202b. In one example, N = 10, which is sufficient to convert the input spin current into a corresponding charging current with an efficiency of one or higher.In other examples, a different number of layers can be used to compensate for the conversion efficiency versus the area of ​​the stack.

[0045] In some embodiments, the superlattice of the SHE layer 202a comprises an interface layer (i.e., a surface alloy) coupled to the FM layer 204a and a bulk layer (e.g., layer(s) of metal) coupled to the interface layer.

[0046] In some embodiments, the FM layer 204a is formed above the superlattice of the SHE layer 202a, composed of Co₂FeGeGa, Co₂FeAl, or other Heusler alloys, etc. In some embodiments, the surface alloy is one of the following: Bi-Ag, antimony-bismuth (Sb-Bi), Sb-Ag, or lead-nickel (Pb-Ni), etc. In some embodiments, the bulk layer metal is a noble metal (e.g., Ag, Cu, and Au) doped with other elements from group 4d and / or 5d of the periodic table. In some embodiments, one of the surface alloy metals is an alloy of heavy metal or materials with high SOC strength, the SOC strength being directly proportional to the fourth power of the atomic number of the metal.

[0047] In some embodiments, all metal layers in the stack of SHE layers 202a / b are of the same metal type. For example, all metal layers of the stack of SHE layers 202a / b are formed from Ag. In other embodiments, different metal layers can be used in the same stack for the metal portion of the layers. For example, some metal layers of the stack of SHE layers 202a / b are formed from Ag and others are formed from Cu.

[0048] In some embodiments, the atomic structure of the stack of SHE layers 202a / b exhibits non-uniform patterns of Ag and Bi atoms of the surface alloy, sandwiched between layers of Cu or other metals. Here, the Ag and Bi crystals exhibit a lattice mismatch (i.e., the distance between adjacent Ag and Bi atoms is different). In some embodiments, the surface alloy (i.e., the interface layer) is formed with a surface ribbing resulting from the lattice mismatch (i.e., the positions of the Bi atoms are offset by a varying distance from a plane parallel to a crystal plane of the underlying metal). The surface alloy is a structure that is not symmetrical with respect to the mirror inversion defined by a crystal plane.This inversion asymmetry leads to spin-orbit coupling in electrons near the surface (also known as the Rashba effect).

[0049] Here, sufficiently matching atomistic crystalline layers refer to a matching of the lattice constant "a" within a threshold above which atoms exhibit a dislocation that is detrimental to the device (i.e., the number and nature of dislocations lead to a significant (e.g., greater than 10%) probability of spin flipping while an electron traverses the interface layer). For example, the threshold lies within 5% (i.e., thresholds in the range of 0% to 5% of the relative difference of the lattice constants).

[0050] The direction of the second charging current I c2 depends on the direction of the second spin stream I s2 off. In some embodiments, the direction of the second spin stream I depends s2from the magnetizations of the FM layers 204a / b, which in turn depends on the direction of the torque induced by the first spin current I s1 is provided. In some embodiments, the direction of the first spin stream I depends s1 from the direction of the charging current I c1 away.

[0051] In some embodiments, the BiAg₂ / PbAg₂ interfacial surface alloy comprises a high-density, two-dimensional (2D) electron gas with a high Rashba state of charge (SOC). The spin-orbit mechanism responsible for the spin-to-charge conversion is described by the Rashba effect in 2D electron gases. In some embodiments, 2D electron gases are formed between Bi and Ag, and when current flows through the 2D electron gases, it becomes a 2D spin gas because electrons are polarized when a charge flows.

[0052] Hamiltonian energy H RThe number of SOC electrons in the 2D electron gas corresponding to the Rashba effect is expressed as: HR=αR(k×z^).σ' where α R where the Rashba coefficient is, “k” is the momentum operator of the electrons, and ẑ is a unit vector perpendicular to the 2D electron gas. σ' The operator of the electron spin is the spin polarizer. The spin-polarized electrons with polarization direction in the plane (in the xy-plane) experience an effective magnetic field that depends on the spin direction and is given by: B(k')=αRμB(k'×z^) where µ B that is the Bohr magneton.

[0053] This leads to the generation of a charging current in the SHE layer 202b, which is proportional to the spin current I. s2 The spin-orbit interaction at the Ag / Bi interface (i.e., the inverse Rashba gem effect (IREE)) generates a charging current I. c2 in the horizontal direction, which is expressed as: Ic2=λIREEISwm where w m the width of the magnet is and λ IREE the IREE constant (with length units) proportional to α R is.

[0054] The IREE effect generates a spin-in-charge-current conversion efficiency of approximately 0.1 with existing materials at a magnet width of 10 nm. For scaled nanomagnets (e.g., 5 nm width) and exploratory SHE materials such as Bi₂Se₃, the spin-in-charge conversion efficiency can range between 1 and 2.5 according to some embodiments. The net conversion of the driving charge current I d the magnetization-dependent charging current is: Ic2=±λIREEPidwm where P is the spin polarization.

[0055] In some embodiments, the transmitter-receiver 400 is cascadeable. For example, the SHE layer 202b can be coupled to a non-magnetic conductor of another receiver (e.g., 201a of another receiver (not shown)). In some embodiments, the output 202b of a transmitter-receiver 400 can be one of several inputs to a logic circuit. For example, the output 202ba of transmitter-receiver 400a (not shown), the output 202bb of transmitter-receiver 400b (not shown), the output 202bc of transmitter-receiver 400c (not shown), and so on, are coupled to the input 201a of transmitter-receiver 400. Each of these conductors carries the charging currents I ca , I eb , I cc etc. Thereafter, the transmitter-receiver 400 performs the logical function of a majority gate (i.e., the sign of the output current in 202b is in accordance with the sign of the majority of the input charging currents I). ca , I cb and I ccin conductors 202ba, 202bb and 202bc respectively). Alternatively, the transmit-receiver 400 performs the function of a minority gate (i.e., negation of the majority gate) when an inversion operation is applied to the reading, i.e., the opposite direction of the output current in 202b is set as positive.

[0056] Fig. Figure 5 illustrates a flowchart 500 of a procedure for operating the receiver from Fig. 2 (which is coupled with transmitters that refer to Fig. 3 and Fig. 4 are shown) according to some embodiments of the disclosure. It should be noted that those elements from Fig. 5, which have the same reference symbols (or names) as the elements of any other figure, can operate or function in any manner similar to that described, but are not limited to doing so.

[0057] Although the blocks in the flowchart refer to Fig. Although the 5 are shown in a specific order, the sequence of actions can be modified. Consequently, the illustrated embodiments can be executed in a different order, and some actions / blocks can be executed in parallel. Some of the in Fig. The five listed blocks and / or operations are optional according to certain embodiments. The numbering of the blocks shown is for clarity and does not dictate a sequence in which the various blocks must appear. Furthermore, operations from the different flows can be used in various combinations.

[0058] At block 501, a first charging current I c1 The power is supplied via the non-magnetic conductor 201a of the SHE layer 202a. The first charging current I is supplied at block 502. c1received by the SHE layer 202a. In some embodiments, the SHE layer 202a converts the first charging current I. c1 in the first spin stream I s1 um. The first spin stream I s1 exerts a torque on the FM 204a. At block 503, this is switched off by the first spin current I. s1 The applied torque affects the magnetization of FM 204a. At block 504, the nanomagnets of the FM insulator 203, which is coupled to FM 204a, also switch in the same direction as the magnetization of FM 204a. At block 505, FM 204b (i.e., the second FM) also switches due to the torque exerted by the first spin current I. s1 is exerted via a strong exchange coupling.

[0059] In some embodiments, the first spin stream I s1 from FM 204b to the SHE layer 202b via the non-magnetic conductor 201h as the second spin current I s2 transferred. In some embodiments, the second spin stream I s2from the SHE layer 202b via the ISHE (Inverse Spin Hall Effect) back into charging current (i.e. the second charging current I) c2 ) converted. In some embodiments, the direction of the second charging current I depends c2 from the magnetization direction of the FM 204b (which in turn depends on the magnetization directions of the FM 203a).

[0060] Fig. Figure 6 illustrates a smart device, computer system, or SoC (System-on-Chip) with a receiver made of Fig. 2 and / or transmit / receive from Fig. 3-4 according to some embodiments. It should be noted that those elements from Fig. 6, which have the same reference symbols (or names) as the elements of any other figure, can operate or function in any manner similar to that described, but are not limited to doing so.

[0061] Fig. Figure 6 shows a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, the computer device 1600 represents a mobile computing device such as a computer tablet, a mobile phone or smartphone, a wirelessly enabled e-reader, or other wireless mobile device. It is understood that certain components are shown in general terms and not all components of such a device are shown in the computer device 1600.

[0062] In some embodiments, the computer device 1600 includes a first processor 1610 with a receiver. Fig. 2 and / or transmit / receive from Fig. 3-4 according to some described embodiments. Other blocks of the 1600 computer device can also include a receiver from Fig. 2 and / or transmit / receive from Fig.3-4 according to some embodiments. The various embodiments of the present disclosure may also include a network interface within 1670 such as a wireless interface, so that a system embodiment can be integrated into a wireless device, for example a mobile phone or a personal digital assistant.

[0063] In some embodiments, the 1610 processor (and / or the 1690 processor) may include one or more physical devices such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by the 1610 processor include the execution of an operating platform or operating system on which applications and / or device functions are run. These processing operations include I / O (input / output) operations with a human user or other devices, power management operations, and / or operations related to connecting the 1600 computer device to another device. The processing operations may also include audio I / O and / or display I / O operations.

[0064] In some embodiments, the computer device 1600 includes an audio subsystem 1620, which comprises hardware (e.g., audio hardware and audio circuitry) and software (e.g., drivers, codecs) components related to providing audio functionality to the computer device. Audio functionality may include speaker and / or headphone output and microphone input. Provisions for such functionality may be integrated into or connected to the computer device 1600. In one embodiment, a user interacts with the computer device 1600 by providing audio commands, which are received and processed by the processor 1610.

[0065] In some embodiments, the computer device 1600 includes the display subsystem 1630. The display subsystem 1630 comprises hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and / or tactile display for a user to interact with the computer device 1600. The display subsystem 1630 has a display interface 1632, which includes the specific screen or hardware device used to provide a display to a user. In one embodiment, the display interface 1632 includes logic that is separate from the processor 1610 to perform at least some of the processing related to the display. In another embodiment, the display subsystem 1630 includes a touchscreen (or touch-panel) device that provides both output and input to a user.

[0066] In some embodiments, the computer unit 1600 includes the I / O controller 1640. The I / O controller 1640 represents hardware and software components related to user interaction. The I / O controller 1640 can be operated to manage hardware that is part of the audio subsystem 1620 and / or the display subsystem 1630. The I / O controller 1640 also illustrates a connection point for additional equipment that can be connected to the computer unit 1600 through which a user could interact with the system. For example, equipment that can be connected to the computer unit 1600 could include microphone equipment, speaker or stereo systems, video systems or other display equipment, keyboard or miniature keyboard equipment, or other I / O equipment for use with specific applications, such as card readers or other equipment.

[0067] As mentioned above, the I / O control 1640 can interact with the audio subsystem 1620 and / or the display subsystem 1630. For example, input via a microphone or other audio device can provide input or commands for one or more applications or functions of the computer device 1600. Additionally, audio output can be provided instead of, or in addition to, display output. In another example, if the display subsystem 1630 has a touchscreen, the display device also functions as an input device that can be managed, at least partially, by the I / O control 1640. There can also be additional buttons or switches on the computer device 1600 to provide I / O functions that are managed by the I / O control 1640.

[0068] In some embodiments, the I / O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that may be included in the computer unit 1600. Input can be part of direct user interaction as well as provide the system with environmental inputs to influence its operation (e.g., filtering for noise, setting displays for brightness detection, applying a flash to a camera, or other features).

[0069] In some embodiments, the computer device 1600 includes a power management system 1650 that manages battery power consumption, battery charging, and features related to power-saving operation. The memory subsystem 1660 includes storage devices for storing information in the computer device 1600. The memory may include non-volatile (the state does not change when the power supply to the storage device is interrupted) and / or volatile (the state is indeterminate when the power supply to the storage device is interrupted) storage devices. The memory subsystem 1660 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) relating to the execution of the applications and functions of the computer device 1600.

[0070] Elements of embodiments are also provided as a machine-readable medium (e.g., Memory 1660) for storing computer-executable instructions (e.g., instructions for implementing any other processes discussed herein). The machine-readable medium (e.g., Memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD-ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase-change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) that can be transmitted from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by means of data signals over a communication link (e.g., a modem or network connection).

[0071] In some embodiments, the computer device 1600 includes a connectivity 1670. The connectivity 1670 includes hardware devices (e.g., wireless and / or wired connectors and communication hardware) and software components (e.g., drivers, protocol stack) to enable the computer device 1600 to communicate with external devices. The computer device 1600 could be a separate device, such as other computer devices, wireless access points or base stations, and peripheral devices such as headsets, printers, or other equipment.

[0072] Connectivity 1670 can include several different types of connectivity. For generalization, the computer equipment 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 generally refers to cellular network connectivity provided by wireless carriers, such as GSM (Global System for Mobile Communications) or variations or derivatives, CDMA (Code Division Multiple Access) or variations or derivatives, TDM (Time Division Multiple Access) or variations or derivatives, or other mobile communication service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular and may include personal networks (such as Bluetooth, near field, etc.), local area networks (such as Wi-Fi), and / or wide area networks (such as WiMAX), or other wireless communication.

[0073] In some embodiments, the computer device 1600 includes peripheral connections 1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) for establishing peripheral connections. It is understood that the computer device 1600 can be a peripheral device (“up to” 1682) to other computer devices and can also have peripheral devices (“from” 1684) connected to it. The computer device 1600 typically has a “docking” port for connecting to other computer devices for managing (e.g., downloading and / or uploading, modifying, synchronizing) content on the computer device 1600.In addition, a docking port can allow the Computer Setup 1600 to connect to certain peripheral devices, enabling the Computer Setup 1600 to control content output, for example to audiovisual or other systems.

[0074] In addition to a proprietary docking connector or other proprietary connection hardware, the computer setup can establish 1600 peripheral connections via common or standards-based connectors. Common types include a USB (Universal Serial Bus) connector (which can have any number of different hardware interfaces), DisplayPort including Mini DisplayPort (MDP), High Definition Multimedia Interface (HDMI), FireWire, or other types.

[0075] References in the description to "one embodiment," "some embodiments," or "other embodiments" mean that a particular feature, structure, or property described in connection with the embodiments is included in at least some, but not necessarily all, embodiments. The various manifestations of "one embodiment" or "some embodiments" do not necessarily all refer to the same embodiments. If the specification states that a component, feature, structure, or property "may" or "could" be included, that particular component, feature, structure, or property is not necessarily included. If the specification or claim refers to "one" element, this does not mean that there is only one of the elements.If the specification or claims refer to "another" element, this does not preclude the existence of more than one other element.

[0076] Furthermore, the specific features, structures, functions, or properties can be combined in any suitable way in one or more embodiments. For example, a first embodiment can be combined with a second embodiment, provided that the specific features, structures, functions, or properties associated with the two embodiments are not mutually exclusive.

[0077] Although the disclosure has been described in connection with specific embodiments thereof, the person skilled in the art will, in view of the foregoing description, see many alternatives, modifications and variations of such embodiments.

[0078] Furthermore, well-known power / ground connections for integrated circuit (IC) chips and other components are shown, or omitted, in the presented figures to simplify the presentation and explanation, so as not to complicate the understanding of the disclosure. Arrangements may also be presented in block diagram form to avoid complicating the understanding of the disclosure, and also in view of the fact that details relating to the implementation of such block diagram arrangements depend heavily on the platform within which the present disclosure is to be implemented (i.e., such details should be well known to a person skilled in the art). If specific details (e.g., circuits) are presented to describe embodiments of the disclosure, it should be obvious to a person skilled in the art that the disclosure can be carried out without or with variations of these specific details.The description should therefore be viewed as descriptive and not as restrictive.

[0079] The following examples represent further embodiments. Details in the examples can be used arbitrarily in one or more embodiments. All optional features of the device described herein can also be implemented in relation to a method or process.

[0080] For example, a device is provided comprising: a first non-magnetic conductor; a first spin-orbit coupling layer (SOC layer) coupled to the first non-magnetic conductor; a first ferromagnet (FM) coupled to the SOC layer; a second FM; and an FM insulator sandwiched between the first and second FM. In some embodiments, the first and second FM are formed from one of the following: a Heusler alloy, Co, Fe, Ge, Ga, or a combination thereof.

[0081] In some embodiments, the FM insulator is formed from one of the following: yttrium iron garnet (YIG) Y3Fe5O 12 , magnetite Fe3O4, Fe2O3, NiO, Tb3Fe5O 12or CrO2. In some embodiments, the first SOC layer is formed from one or more of the following: β-Ta, β-W, W, Pt, iridium-doped Cu, bismuth-doped Cu, or Cu doped with an element from group 3d, 4d, 5d, 4f, or 5f of the periodic table. In some embodiments, the first SOC layer comprises: an interface layer coupled to the first FM; and a bulk layer coupled to the interface layer and another non-magnetic metal. In some embodiments, the interface layer is formed from at least one of the following: Bi and Ag; Bi and Cu; or Pb and Ag.

[0082] In some embodiments, the bulk layer is formed from at least one of the following: Ag, Cu, or Au. In some embodiments, the device includes a second non-magnetic conductor coupled to the first SOC layer, the second non-magnetic conductor being coupled to ground. In some embodiments, the device includes a third non-magnetic conductor coupled to a section of the second FM and to a power supply. In some embodiments, the device includes: a second SOC layer; a fourth non-magnetic conductor coupled to a section of the second FM and the second SOC layer; and a fifth non-magnetic conductor coupled to a section of the second SOC layer and to ground.

[0083] In some embodiments, at least one of the first, second, third, fourth, and fifth non-magnetic conductors is made of copper. In some embodiments, the device includes a non-magnetic connection coupled at one end to the second FM and at the other end to a ground node. In some embodiments, the device includes: a first stack of an insulator, a solid ferromagnet, and a non-magnetic conductor coupled to a positive power supply; and a second stack of an insulator, a solid ferromagnet, and a non-magnetic conductor coupled to a negative power supply, the first and second stacks being separated by a gap and coupled to sections of the second FM.

[0084] In some embodiments, the insulators of the first and second stacks are made of MgO. In some embodiments, the first and second FMs are free magnets. In some embodiments, the first SOC layer converts a charging current into a spin current that switches the first FM. In some embodiments, the first SOC layer exhibits a spin Hall effect when a charging current is received from the first non-magnetic conductor.

[0085] In another example, a system is provided that includes: a memory; a processor coupled to the memory, the processor having a device according to the device described above; and a wireless interface to enable the processor to communicate with another device. In some embodiments, the device is cascadeable with another device. In some embodiments, the other device is the same as the device described above. In some embodiments, the device is a majority gate. In some embodiments, the device is a minority gate.

[0086] In another example, a method is provided that includes: transmitting a first charging current through a first non-magnetic conductor; receiving the first charging current through a first spin-orbit coupling (SOC) layer, wherein the first SOC layer is to convert the first charging current into a first spin current; switching a first ferromagnet (FM) through the first spin current; switching an insulating FM coupled to the first ferromagnet; and switching a second FM through the first spin current, wherein the insulating FM is coupled to both the first and second FMs. In some embodiments, the method includes: receiving the first spin current through the second FM; providing the received first spin current to a second SOC layer; and converting the received first spin current into a second charging current through the second SOC layer.In some embodiments, the method includes applying a positive supply to a section of the second FM via a third non-conductive metal.

[0087] In another example, a device is provided comprising: means for transmitting a first charging current; means for receiving the first charging current and converting the first charging current into a first spin current; means for switching a first ferromagnet (FM) by the first spin current; means for switching an insulating FM coupled to the first ferromagnet; and means for switching a second FM by the first spin current, the insulating FM being coupled to both the first and the second FM. In some embodiments, the device comprises: means for receiving the first spin current via the second FM; and means for converting the first spin current into a second charging current. In some embodiments, the device comprises: means for applying a positive supply to a section of the second FM.

[0088] In another example, a system is provided that includes: a memory; a processor coupled to the memory, the processor having a device according to the device described above; and a wireless interface to enable the processor to communicate with another device. In some embodiments, the device is cascadeable with another device. In some embodiments, the other device is the same as the device described above. In some embodiments, the device is a majority gate. In some embodiments, the device is a minority gate.

Claims

[1] Device comprising: a non-magnetic conductor (201a, 201b); a first spin-orbit coupling layer, SOC layer (202), which is coupled to the first non-magnetic conductor (201a, 201b); a first ferromagnet, FM (204a), coupled to the first SOC layer (202); a second FM (204b); and a second layer (203) comprising a magnetic insulating material, wherein the second layer (203) is arranged between the first and second magnets (204a, 204b) such that magnetic insulating material is in direct contact with the first and second magnets (204a, 204b); where the first SOC layer (202) has: a third layer coupled to the first magnet (204a), wherein the first SOC layer comprises one or more of Bi and Ag, Bi and Cu, or Pb and Ag; and a fourth layer coupled to the third layer and another non-magnetic metal, wherein the fourth layer comprises one of Ag, Cu, or Au. [2] Device according to claim 1, wherein the first and the second FM (204a, 204b) comprise one or more of a Heusler alloy, Co, Fe, Ge, Ga or a combination thereof. [3] Device according to claim 1, wherein the magnetic insulating material comprises one of Y, Fe, Ni, Tb, or Cr. [4] Device according to claim 1, wherein the first SOC layer (202) comprises one or more of β-Ta, β-W, W, Pt, iridium-doped Cu, bismuth-doped Cu or Cu doped with an element from groups 3d, 4d, 5d, 4f or 5f of the periodic table. [5] Device according to claim 1, wherein the conductor is a first conductor (201a), wherein the device has a second non-magnetic conductor (201b) which has a non-magnetic material, the second conductor (201b) is coupled to the first SOC layer (202) conductor, and the second conductor (201b) is coupled to ground. [6] Device according to claim 5, which has a third non-magnetic conductor, wherein the third conductor is coupled to a section of the second FM and to a power supply. [7] Device according to claim 6, comprising: a fifth SOC layer; a fourth non-magnetic conductor coupled to a section of the second FM and the fifth SOC layer; and a fifth non-magnetic conductor coupled to a section of the fifth SOC layer and to ground. [8] Device according to claim 7, wherein at least one of the first, second, third, fourth and fifth non-magnetic conductors is made of Cu. [9] Device according to claim 1, comprising a non-magnetic connection coupled at one end to the second FM and at another end to a ground node. [10] Device according to claim 1, comprising: a first stack of an insulator, a fixed ferromagnet, and a non-magnetic conductor coupled to a positive power supply; and a second stack of an insulator, a fixed ferromagnet and a non-magnetic conductor coupled to a negative power supply, where the first and second stacks are separated by a distance and coupled to sections of the second FM. [11] Device according to claim 10, wherein the insulators of the first and second stack are made of MgO. [12] Device according to claim 1, wherein the first and the second FM (204a, 204b) are free magnets. [13] Device according to claim 12, wherein the first SOC layer (202) converts a charging current into a spin current which switches the first FM. [14] Device according to claim 1, wherein the first SOC layer (202) exhibits a spin Hall effect when a charging current is received from the first non-magnetic conductor (201b). [15] System comprising the following: a storage facility; a processor coupled to the memory, the processor comprising a device that includes the following: a first conductor (201a, 201b) comprising a spin-orbit coupling material, SOC material, and non-magnetic material; a first layer (202) which is coupled to the first conductor (201a, 201b); a first magnet (204a) coupled to the first layer (202); a second magnet (204b); and a second layer (203) comprising a magnetic insulating material, wherein the second layer (203) is arranged between the first and the second magnets (204a, 204b) such that magnetic insulating material is in direct contact with the first and the second magnets (204a, 204b); a second conductor comprising a non-magnetic material, wherein the second conductor is coupled to the first layer, and wherein the second conductor is coupled to a ground node; a third conductor comprising a non-magnetic material, wherein the third conductor is coupled to a section of the second magnet (204b) and to a power supply node; a fifth layer that includes a SOC material; a fourth conductor comprising a non-magnetic material, wherein the fourth conductor is coupled to a section of the second magnet (204b) and to the fifth layer; and a fifth conductor comprising a non-magnetic material, wherein the fifth conductor is coupled to a section of the fifth layer and to ground; and a wireless interface through which the processor can communicate with another device. [16] System according to claim 15, wherein the device can be cascaded with another device. [17] System according to claim 15, wherein the device is a majority gate or a minority gate. [18] Method comprising the following: Transfer of an initial charging current through a first non-magnetic conductor (201a); Receiving the first charging current through a first spin-orbit coupling layer, SOC layer (202), wherein the first SOC layer (202) is intended to convert the first charging current into a first spin current; Switching of a first ferromagnet, FM (204a), by the first spin current; Switching an isolating FM coupled to the first ferromagnet (204a); Switching a second FM by the first spin current, wherein the isolating FM is directly coupled to the first and the second FM; Receiving the first spin stream via the second FM; Providing the received first spin stream to a second SOC layer; and Converting the received first spin current into a second charging current through the second SOC layer.

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