Connection fault detection in multi-chip enclosures

Abstract

A device comprising the following: physical layer logic for: receiving initial data on multiple data lanes of a physical connection; receiving a current signal corresponding to the initial data on a current lane, wherein the current lane is another of the lanes of the physical connection, and wherein the current signal corresponding to the initial data serves to identify a type of initial data; identifying a first instance of a fault detection code of a specific type in the initial data; receiving second data on at least some of the multiple data lanes; receiving a current signal corresponding to the second data on the current lane, wherein the current signal corresponding to the second data serves to identify a type of second data, the type of second data being different from the type of first data;and identifying a second instance of the error detection code of the special type in the second data, and path error detection logic for: determining from a syndrome associated with the error detection code corresponding to the first data that a bit error is present in the first data; determining from the syndrome in which bit of the first data the error occurred; and assigning the bit with the error to one of the several paths.

Description

TECHNICAL FIELDThis disclosure relates to data processing systems and, more particularly (but not exclusively), to point-to-point connections.BACKGROUNDAdvances in semiconductor processing and logic design have enabled an increase in the amount of logic that may be present on integrated circuit devices. As a logical consequence, computer system configurations of single or multiple integrated circuits in a system have evolved into threads having multiple cores and multiple hardware and multiple logical processors present on single integrated circuits as well as other interfaces integrated into such processors. A processor or integrated circuit typically includes a single physical processor die, where the processor die may include any number of cores, hardware threads, logical processors, interfaces, memory, control nodes, etc.As a result of the greater ability to accommodate greater processing power in smaller enclosures, the popularity of smaller computing devices has increased. Smart phones, tablets, ultra-thin notebooks, and other user devices have grown exponentially. However, these smaller devices build servers for both data storage and complex processing exceeding the form factor. As a result, the demand in the high performance data processing market (i.e., server location) has also increased. For example, in modern servers, there is typically not only a single processor with multiple cores, but also multiple physical processors (also referred to as multiple sockets) to increase computing power. However, as processing power increases along with the number of devices in a data processing system, communication between sockets and other devices becomes increasingly critical.Indeed, connections from more traditional multi-drop buses handling primarily electrical communications have evolved to fully mature connection architectures that enable fast communication. Unfortunately, the demands of future processors to consume at even higher rates according to demand are placed on the capabilities of existing interconnect architectures.WO 2015 / 099719 A1 relates to a point-to-point interconnections with physical layer logic that serves to receive data on one or more data lanes of a physical connection, to receive a valid signal on another of the lanes of the physical connection that identifies that valid data will follow a assertion of the valid signal on the one or more data lanes, and to receive a stream signal on another of the lanes of the physical connection that identifies a type of the data on the one or more data lanes.US 2014 / 0025736 A1 relates to a method for controlling cluster connection aggregations in a network environment. The method comprises receiving a request message from a network element over an out-of-band control connection. The request message includes a request to bundle a port connected to the network element into a channel group connected to a cluster. The cluster comprises a plurality of clustered network elements. The method further comprises determining a status of the port with respect to the channel group and sending a response message to the network element over the out-of-band control link. The response message indicates the status of the port of the network element.SUMMARYThe present invention is defined by the subject matter of the main claim 1 and the subordinate claims 14, 17 to 20. The claims dependent thereon define further embodiments of the devices and methods according to the invention.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 illustrates an embodiment of a data processing system including an interconnect architecture. FIG. 2 illustrates an embodiment of a connection architecture comprising a layered stack. FIG. 3 illustrates an embodiment of a request or packet to be generated or received within a connection architecture. Figure 4 illustrates an embodiment of a transmitter and receiver pair for a link architecture. FIG. 5 illustrates an embodiment of a multichip package. FIG. 6 is a simplified block diagram of a multichip package link (MCPL). FIG. 7 is an illustration of example signaling on an example MCPL. Figure 8 is a simplified block diagram of an MCPL. FIG. 9 is a diagram of a portion of an example link state machine. FIG. 10 is an illustration of an example link state machine. FIG. 11 is an illustration of signaling to enter a low power state. FIG. 12 is a block diagram illustrating an example implementation of an MCPL. FIGS. 13A-13C are example bit assignments of data on lanes of an example MCPL. Figs. 14-1, 14-2, 14-3 illustrate an exemplary syndrome decoding table. Figs. 15-1, 15-2, 15-3 illustrate another exemplary syndrome decoding table. FIG. 16 is a block diagram illustrating an example implementation of an MCPL. FIGS. 17A-17B are diagrams illustrating examples of connection reconfiguration in accordance with at least some embodiments. FIGS. 18A-18B are simplified flow diagrams illustrating techniques for handling errors on an MCPL. FIG. 19 illustrates an embodiment of a block for a data processing system including multiple processors.Like reference numerals and labels in the various drawings indicate like elements.DETAILED DESCRIPTIONIn the following description, numerous specific details are set forth, such as examples of specific types of processors and system configurations, specific hardware structures, specific architectural and microarchitectural details, specific register configurations, specific instruction types, specific system components, specific dimensions / heights, specific processor pipeline stages and operation, etc., in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the present invention. In other instances, well-known components or methods, such as specific and alternative processor architectures, specific logic circuitry / code for described algorithms, specific firmware code, specific connection operation, specific logic configurations, specific fabrication techniques and materials, specific compiler implementations, specific expression of algorithms into code, specific shutdown and gating techniques / logic, and other specific operational details of the computer system have not been described in detail to prevent unnecessary obscuring of the present invention.Although the following embodiments may be described with respect to power savings and power efficiency in specific integrated circuits, such as in computing platforms or microprocessors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from better energy efficiency and energy saving. For example, the disclosed embodiments are not limited to desktop computer systems or Ultrabooks™ systems. And they may also be used in other devices such as handheld devices, tablets, other thin notebooks, systems-on-a-chip (SOC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include a microcontroller, a digital signal processor (DSP), a system on a chip, network computers (NetPC), set-top boxes, network nodes, wide area network switches (WAN), or any other system capable of performing the functions and operations taught below. Moreover, the apparatuses, methods, and systems described herein are not limited to physical computing devices, but may also relate to software optimizations for energy conservation and efficiency. As will become apparent in the following description, the embodiments of methods, apparatus, and systems described herein (whether in terms of hardware, firmware, software, or a combination thereof) are important for a "green technology" future in balance with performance considerations.As data processing systems continue to develop, the components therein become more and more complex. As a result, the complexity of the interconnect architecture for coupling and communicating between the components also increases to ensure that the bandwidth requirements are met for optimal component operation. Furthermore, different market segments demand tuning of different aspects of connection architectures to the needs of the market. For example, servers require higher power while the mobile ecosystem is sometimes able to sacrifice overall power for power savings. Nevertheless, it is a prominent purpose of most structures to provide maximum power with maximum energy saving. Discussed below is a number of connections that would potentially benefit from aspects of the invention described herein.One interconnect fabric architecture includes the Peripheral Component Interconnect (PCIe) Express (PCIe). A primary goal of PCIe is to enable components and devices from different vendors to operate together in an open architecture spanning multiple market segments; clients (desktop and mobile), servers (standard and enterprise), and embedded as well as communication devices. PCI Express is a high performance universal I / O link defined for a wide variety of future data processing and communication platforms. Some PCI attributes, such as their usage model, load-store architecture, and software interfaces, have been maintained in their revisions, whereas previous parallel bus implementations have been replaced with a highly scalable, fully serial interface. The more recent versions of PCI Express take advantage of the advances in point-to-point connections, soft-based technology, and packet-based protocols to provide new levels of performance and features. Performance management, Quality of Service (QoS), hot plug / hot swap support, data integrity, and error handling are some of the advanced features supported by PCI Express.Referring to FIG. 1, an embodiment of a structure consisting of point-to-point connections that connect a set of components together is illustrated. System 100 includes processor 105 and system memory 110 coupled to control nodes 115. Processor 105 includes any processing element, such as a microprocessor, a host processor, an embedded processor, a coprocessor, or other processor. Processor 105 is coupled to control node 115 via front side bus (FSB) 106. In one embodiment, FSB 106 is a serial point-to-point connection, as described below. In another embodiment, link 106 comprises a serial, differential link architecture conforming to a different link standard.System memory 110 includes any storage device, such as random access memory (RAM), nonvolatile memory (NV), or other memory that can be accessed by devices in system 100. System memory 110 is coupled to control node 115 via memory interface 116. Examples of a memory interface include a double data rate (DDR) memory interface, a dual channel DDR memory interface, and a dynamic RAM memory interface (DRAM).In one embodiment, control node 115 is a root node, root complex, or root controller in a Peripheral Component Interconnect Express (PCIe or PCIE) connection hierarchy. Examples of control nodes 115 include a chipset, memory controller hub (MCH), north bridge, interconnect controller hub (ICH), south bridge, and master / master node. Often, the term chipset refers to two physically separate control nodes, i.e., a storage control node (MCH) coupled to an interconnect control node (ICH). It should be noted that current systems often include the MCH integrated with processor 105, while controller 115 is to communicate with I / O devices in a similar manner as described below. In some embodiments, direct forwarding (peer-to-peer) is optionally supported by root complex 115.Here, control node 115 is coupled to switch / bridge 120 via serial link 119. Input / output modules 117 and 121, which may also be referred to as interfaces / ports 117 and 121, include / implement a layered protocol stack to provide communication between control node 115 and switch 120. In one embodiment, multiple devices are capable of being coupled to switch 120.Soft / bridge 120 routes packets / messages from device 125 upstream, i.e., up a hierarchy towards a root complex, to controller nodes 115 and downstream, i.e., down a hierarchy away from a root controller, from processor 105 or system memory 110 to device 125. Switch 120, in one embodiment, is referred to as a logical array of multiple PCI-to-PCI virtual bridge devices. Device 125 includes any internal or external device or component to be coupled to an electronic system, such as an I / O device, a network interface controller (NIC), an expansion card, an audio processor, a network processor, a hard disk, a storage device, a CD / DVD-ROM, a monitor, a printer, a mouse, a keyboard, a router, a portable storage device, a firewire device, a universal serial bus (USB) device, a scanner, and other input / output devices. In the PCIe art jargon, such a device is often referred to as an endpoint. Although not specifically shown, device 125 may include a PCIe-to-PCI / PCI-X bridge to support legacy devices or devices with a different PCI version. Endpoint devices in PCIe are often referred to as legacy, PCIe, or root complex integrated endpoints.Graphics accelerator 130 is also coupled to control node 115 via serial link 132. In one embodiment, graphics accelerator 130 is coupled to an MCH, which is coupled to an ICH. Switch 120, and corresponding I / O device 125, is then coupled to the ICH. I / O modules 131 and 118 also serve to implement a layered protocol stack to communicate between graphics accelerator 130 and control node 115. Similar to the MCH discussion above, a graphics controller or graphics accelerator 130 itself may be integrated into processor 105.Referring to FIG. 2, an embodiment of a layered protocol stack is illustrated. Layered protocol stack 200 includes any form of layered communication stack, such as a quick path interconnect (QPI) stack, a PCie stack, a next generation high performance data processing interconnect stack, or another layered stack. Although the discussion immediately below with reference to FIGS. 1-4 relates to a PCIe stack, the same concepts may be applied to other interconnect stacks. In one embodiment, protocol stack 200 is a PCIe protocol stack including transaction layer 205, link layer 210, and physical layer 220. An interface, such as interfaces 117, 118, 121, 122, 126, and 131 in FIG. 1, may be depicted as communication protocol stack 200. Representation as a communication protocol stack can also be referred to as a module or an interface converting / comprising a protocol stack.PCI Express uses packets to communicate information between components. Packets are formed in the transaction layer 205 and data link layer 210 to transport the information from the sending component to the receiving component. As the transmitted packets pass through the other layers, they are augmented by additional information necessary to handle packets at these layers. On the receiving side, the reverse process occurs and packets are transformed from their presentation on physical layer 220 to the presentation on data link layer 210 and finally (for transaction layer packets) to the form that can be processed by the transaction layer 205 of the receiving device.Transaction LayerIn one embodiment, transaction layer 205 serves to provide an interface between a processing core of a device and the connection architecture, such as data connection layer 210 and physical layer 220. In this regard, the primary task of transaction layer 205 is to assemble and disassemble packets (i.e., transaction layer packets or TLPs). The translation layer 205 typically manages credit-based flow control for TLPs. PCIe implements shared transactions, i.e., transactions in which the request and response are separated in time, enabling a link to carry other traffic while the target device collects data for the response.In addition, PCIe utilizes credit-based flow control. In this scheme, a device advertises an initial amount of credit for each of the receive buffers in transaction layer 205. An external device at the opposite end of the connection, such as control node 115 in Figure 1, counts the number of credits consumed by each TLP. A transaction may be sent when the transaction does not exceed a credit limit. Upon receiving a response, an amount of credit is recovered. An advantage of a credit scheme is that latency of credit return does not affect performance provided that the credit limit is not reached.In one embodiment, four transaction address spaces include a configuration address space, a memory address space, an input / output address space, and a message address space. Memory space transactions include one or more read requests and write requests for transferring data to / from a memory mapped location. In one embodiment, memory space transactions are capable of using two different address formats, e.g., a short address format such as a 32-bit address or a long address format such as a 64-bit address. Configuration space transactions are used to access configuration space of the PCIe devices. Transactions to the configuration space include read requests and write requests. Message space transactions (or simply messages) are defined to support in-band communication between PCIe agents.Thus, in one embodiment, transaction layer 205 assembles packet header / payload 206. The format for current packet header / payload may be found in the PCIe specification at the PCIe specification website.Referring now to FIG. 3, an embodiment of a PCIe transaction descriptor is illustrated. In one embodiment, transaction descriptor 300 is a mechanism for carrying transaction information. In this regard, transaction descriptor 300 supports identification of transactions in a system. Other potential uses include recording modifications of standard transaction order and linking of transaction to channels.Transaction descriptor 300 includes global tag field 302, attribute field 304, and channel tag field 306. In the illustrated example, global tag field 302 is shown to include local transaction tag field 308 and source tag field 310. In one embodiment, global transaction tag 302 is unique to all outstanding requests.According to one implementation, local transaction tag field 308 is a field generated by a request agent and is unique to all outstanding requests that require completion for that request agent. Further, in this example, source tag 310 uniquely identifies the request agent within a PCIe hierarchy. Accordingly, along with source tag 310, local transaction tag field 308 provides global tagging of a transaction within a hierarchy domain.Attribute field 304 indicates characteristics and relationships of the transaction. In this regard, attribute field 304 is potentially used to provide additional information that enables modification of the default handling of transactions. In one embodiment, attribute field 304 includes priority field 312, reserved field 314, ordering field 316, and table sniff field 318. Here, priority sub-field 312 may be modified by an initiator to assign a priority to the transaction. Reserved attribute field 314 is left reserved for future or vendor-specific use. Possible usage models using priority or security attributes may be implemented using the reserved attribute field.In this example, the ordering attribute field 316 is used to provide optional information that carries the type of ordering that can modify the default ordering rules. According to an example implementation, an order attribute of "0" denotes that default order rules are to be applied, whereas an order attribute of "1" denotes resolved order, wherein writes may pass writes in the same direction and read completes may pass writes in the same direction. Sniff attribute field 318 is used to determine whether transactions are being listened to. As shown, the channel identification field 306 identifies a channel to which a transaction is associated.Bonding LayerLink layer 210, also referred to as data link layer 210, acts as an intermediate between transaction layer 205 and physical layer 220. In one embodiment, it is an object of the data link layer 210 to provide a reliable mechanism for exchanging transaction layer packets (TLPs) between two components of a link. One side of the data link layer 210 accepts TLPs composed by the transaction layer 205, applies packet sequence identification 211, i.e., an identification number or packet number, calculates and applies an error detection code, i.e., CRC 212, and transmits the modified TLPs to the physical layer 220 for transmission over a physical device to an external device.Physical LayerIn one embodiment, physical layer 220 includes logical sub-block 221 and electrical sub-block 222 for physically transmitting a packet to an external device. Here, logical sub-block 221 is responsible for the "digital" functions of physical layer 221. In this regard, the logical sub-block includes a transmit section for preparing the outgoing information for transmission by physical sub-block 222 and a receiver section for identifying and preparing received information prior to passing it to link layer 210.Physical block 222 includes a transmitter and a receiver. The transmitter is supplied with symbols by logical sub-block 221 which the transmitter serializes and transmits to an external device. The receiver receives serialised symbols from an external device and transforms the received signals into a bit stream. The bitstream is deserialized and passed to logical sub-block 221. In one embodiment, an 8b / 10b transmit code is employed, wherein ten-bit symbols are transmitted / received. Here, special symbols are used to provide a packet with frames 223. Additionally, in one example, the receiver also provides a symbol clock that is recovered from the incoming serial stream.As noted above, although transaction layer 205, link layer 210, and physical layer 220 are discussed with reference to a specific embodiment of a PCIe protocol stack, a layered protocol stack is not so limited. Indeed, any layered protocol may be included / implemented. As an example, a port / interface, represented as a layered protocol, includes: (1) a first layer for assembling packets, i.e., a transaction layer; a second layer for sequencing packets, i.e., a link layer; and a third layer for sending the packets, i.e., a physical layer. As a specific example, a layered common standard interface (CSI) protocol is used.Referring next to FIG. 4, an embodiment of a serial point-to-point PCIe structure is illustrated. Although one embodiment of a point-to-point serial PCIe link is illustrated, a point-to-point serial link is not so limited as it includes any transmit path for transmitting serial data. In the embodiment shown, a basic PCIe link includes two differentially driven low voltage signal pairs: a transmit pair 406 / 411 and a receive pair 412 / 407. Accordingly, device 405 includes transmit logic 406 to transmit data to device 410 and receive logic 407 to receive data from device 410. In other words, two transmit paths, i.e., paths 416 and 417, and two receive paths, i.e., paths 418 and 419, are included in a PCIe link.A transmission path refers to any path for transmitting data, such as a transmission line, a copper line, an optical line, a wireless communication channel, an infrared communication link, or another communication path. A connection between two devices, such as device 405 and device 410, is referred to as a connection, such as connection 415. A link may support a path - each path representing a set of differential signal pairs (a pair for transmission, a pair for reception). To scale bandwidth, a link may coalesce multiple lanes denoted xN, where N is any supported link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or broader.A differential pair refers to two transmit paths, such as lines 416 and 417, for transmitting differential signals. As an example, when line 416 transitions from a low voltage level to a high voltage level, i.e., a rising edge, line 417 controls from a high logic level to a low logic level, i.e., a falling edge. Differential signals potentially exhibit better electrical characteristics, such as better signal integrity, i.e., cross coupling, voltage overdrive / underdrive, ringing, etc. This allows for a better timing window, allowing for faster transmission frequencies.FIG. 5 is a simplified block diagram 500 illustrating an example multichip package 505 that includes two or more chips or dies (e.g., 510, 515) communicatively connected using an example multichip package link (MCPL) 520. While FIG. 5 illustrates an example of two (or more) dies interconnected using an example MCPL 520, it should be appreciated that the principles and features described herein regarding implementations of an MCPL may be applied to any interconnect or connection connecting a die (e.g., 510) and other components, including connecting two or more dies (e.g., 510, 515), connecting a die (or chip) to another component external to the die, connecting a die to another device or die external to the package (e.g., 505), connecting a die to a BGA package, implementation of a patch on interposer (POINT), among potentially other examples.Generally, a multichip package (e.g., 505) may be an electronic package in which multiple integrated circuits (ICs), semiconductor dies, or other discrete components (e.g., 510, 515) are packaged on a interconnecting substrate (e.g., silicon or other semiconductor substrate) enabling the combined components to be used as a single component (e.g., such as a larger IC). In some cases, the larger components (e.g., dies 510, 515) may themselves be IC systems, such as system-on-a-chip (SoC), multiprocessor chips, or other components that include multiple components (e.g., 525- 530 and 540- 545) on the device, for example, on a single die (e.g., 510, 515). Multichip packages 505 can provide flexibility for building complex and versatile systems from potentially multiple discrete components and systems. For example, each of the dies 510, 515 may be manufactured or otherwise provided by two different entities, with the silicon substrate of the package 505 provided by yet a third entity, among many other examples. Further, dies and other components within a multichip package 505 may themselves include interconnect or other communication structures (e.g., 535, 550) providing infrastructure for communication between components (e.g., 525-530 and 540-545) within the device (e.g., 510, 515, respectively). The various components and connections (e.g., 535, 550) may potentially support or use multiple different protocols. Further, communication between dies (e.g., 510, 515) may potentially include transactions between the various components on the dies via multiple different protocols. Designing mechanisms for providing inter-chip (or die) communication on a multi-chip package may be challenging, wherein traditional solutions, employing highly specialized, expensive, and package specific solutions based on the specific combinations of components (and desired transactions), should be interconnected.The examples, systems, algorithms, devices, logics, and features described in this specification may address at least some of the problems identified above, including potentially many others not expressly mentioned herein. For example, in some implementations, a high bandwidth, low power, and low latency interface may be provided to connect a host device (e.g., a CPU) or other device to a companion chip located in the same package as the host. Such a multi-chip package interconnect (MCPL) may support multiple package options, multiple I / O protocols, as well as reliability, availability, and serviceability (RAS) features. Further, the physical layer (PHY) may include an electrical layer and logical layer and may support longer channel lengths, including channel lengths up to, and in some cases exceeding, about 45 mm. In some implementations, an example MCPL may operate at high data rates, including data rates above 8-10 Gb / s.In an exemplary implementation of an MCPL, an electrical PHY layer may improve conventional multi-channel connection solutions (e.g., multi-channel DRAM I / O), expanding data rate and channel design, for example, a number of features including, as examples, regulated mid-rail termination, low power active crosstalk cancellation, circuit redundancy, bit-by-bit duty cycle correction and equalization, line coding, and transmitter smoothing, among potentially other examples.In an example implementation of an MCPL, a logical PHY layer may be implemented that may further assist (e.g., electrical layer features) in extending data rate and channel design, simultaneously also enabling the link to route multiple protocols across the electrical layer. Such implementations may provide and define a modular general physical layer that is protocol agnostic and configured to operate with potentially any existing or future connection protocol.Referring to FIG. 6, a simplified block diagram 600 is shown illustrating at least a portion of a system, including an example implementation of a multi-chip package interconnect (MCPL). An MCPL may be implemented using physical electrical connections (e.g., wires mapped as traces) connecting a first device 605 (e.g., comprising a first die, one or more subcomponents) to a second device 610 (e.g., connecting a second die, comprising one or more other subcomponents). In the particular example shown in the higher level illustration of diagram 600, all signals (in channels 615, 620) may be unidirectional, and lanes may be provided for the data signals to have both upstream and downstream data transfer. While the block diagram 600 of FIG. 6 refers to the first component 605 as the upstream component and the second component 610 as the downstream components, and physical lanes of the MCPL used to send data as the downstream channel 615, and lanes used to receive data (component 610) as the upstream channel 620, it should be appreciated that the MCPL between devices 605, 610 may be used by each device to send and receive data between the devices.In an example implementation, an MCPL may provide a physical layer (PHY) comprising implementing the MCPL PHY 625a,b (or, together, 625) and executable logic, MCPL PHY 630a,b (or, together, 630). Electrical, or physical, PHY 625 may provide the physical connection over which data is communicated between devices 605, 610. Signal conditioning components and logic may be implemented in conjunction with physical PHY 625 to establish high data rate and channel design capabilities of the connection, which in some applications may include closely clustered physical connections at lengths of about 45 mm or more. The logical PHY 630 may include logic to enable timing, link state management (e.g., for link layers 635 a, 635 b), and protocol multiplexing between potentially multiple different protocols used for communications over the MCPL.In an example implementation, physical PHY 625 may include, for each channel (e.g., 615, 620), a set of data lanes over which intra-band data may be sent. In this particular example, 50 data lanes are provided in each of the upstream and downstream channels 615, 620, although any other number of lanes as permitted by the layout and performance constraints, desired applications, device constraints, etc., may be used. Each channel may further comprise one or more dedicated lanes for a sampling or clock signal for the channel, one or more dedicated lanes for a valid signal for the channel, one or more dedicated lanes for a stream signal, and one or more dedicated lanes for a link state machine management or sideband signal. The physical PHY may further include a sideband link 640, which, in some examples, may be a lower frequency bidirectional control signal link used to coordinate state transitions and other attributes of the MCPL connecting devices 605, 610, among other examples.As noted above, multiple protocols may be supported using a translation of MCPL. Indeed, multiple, independent, transaction layers 650a, 650b may be provided on each device 605, 610. For example, each device 605, 610 may support and utilize two or more protocols, such as PCI, PCIe, QPI, Intel In-Die Interconnect (IDI), among others. IDI is an on-die coherent protocol used for communicating between cores, Last Level Caches (LLCs), memory, graphics, and I / O controllers. Other protocols may also be supported, including Ethernet protocol, Infiniband protocols, and other PCIe structure-based protocols. The combination of logical PHY and physical PHY may also be used as a die-to-die link to connect a SerDes PHY (PCIe, Ethernet, Infiniband, or other high-speed SerDes) on one die to its upper layers implemented on the other die, among other examples.Logical PHY 630 may support multiplexing between these multiple protocols on an MCPL. For example, the particular stream path may be used to confirm an encoded stream signal identifying which protocol to apply to data transmitted substantially simultaneously on the data paths of the channel. Further, logical PHY 630 may be used to negotiate the various types of link state transitions that the various protocols may support or request. In some cases, LSM_SB signals transmitted over the particular LSM_SB path of the channel may be used, along with sideband link 640, to communicate and negotiate link state transitions between the devices 605, 610. Further, link training, error detection, distortion detection, equalization, and other functionality of conventional links may be replaced or controlled, in part using logical PHY 630. For example, validity signals transmitted over one or more particular validity signal lanes in each channel may be used to signal connection activity, detect distortion and connection errors, and implement other features, among other examples. In the specific example of FIG. 6, multiple validity lanes are provided per channel. For example, data lanes may be bundled or clustered (physical and / or logical) within a channel, and a valid lane may be provided for each cluster. Further, multiple scanlines may be provided, in some cases also to provide a particular scanline signal for each cluster in multiple data-lane clusters in a channel, among other examples.As noted above, logical PHY 630 may be used to negotiate and manage connection control signals sent between the devices connected by the MCPL. In some implementations, PHY 630 logic may include link layer packet (LLP) generation logic 660 that may be used to send link layer control messages over the MCPL (i.e., in-band). Such messages may be sent over data lanes of the channel, where the stream lane identifies that the data is link layer-to-link layer messages, such as link layer control data, among other examples. Link layer messages enabled using LLP module 660 may aid in negotiation and performance of link layer state transitions, power management, loop switching, disabling, re-centering, scrambling, among other link layer features, between link layers 635 a, 635 bof devices 605, 610, respectively.Referring to FIG. 7, a diagram 700 is shown depicting example signaling using a set of lanes (e.g., 615, 620) in a particular channel of an example MCPL. In the example of FIG. 7, two clusters of twenty five (25) data lanes are provided for a total of fifty (50) data lanes in the channel. A portion of the traces are shown, while others (e.g., DATA[4-46] and a second strobe trace (ABTST)) are omitted (e.g., as redundant signals) for convenience in illustrating the particular example. When the physical layer is in an active state (e.g., not powered off or in a low power mode (e.g., an L1 state)), sense traces (ABTST) may be supplied with a synchronous clock signal. In some implementations, data may be sent on both the rising and falling edges of the sample. Each edge (or half clock cycle) may delimit a unit interval (UI). Accordingly, in this example, a bit (e.g., 705) may be sent on each lane, allowing every 8 UIs to send a byte. A byte period 710 may be defined as 8 UI or the time to send a byte on a single one of the data lanes (e.g., DATA[0-49]).In some implementations, a valid signal sent on one or more particular valid signal channels (e.g., VALID0, VALID1) may serve as a leading indicator for the receiving device to identify, when asserted (high), to the receiving device, or sink, that data from the sending device, or source is sent on data lanes (e.g., DATA[0-49]) during the following time period, such as byte time 710. Alternatively, if the valid signal is low, the source of the sink indicates that the sink is not transmitting data on the data lanes during the following period. Accordingly, if the logical PHY of the sink detects that the valid signal is not asserted (e.g., on lanes VALID0 and VALID1), the sink may ignore any data detected on the data lanes (e.g., DATA[0-49]) during the following period. For example, cross-talk noise or other bits may appear on one or more of the data lanes when the source is not actually transmitting data. Based on a low, or unacknowledged, valid signal during the previous time period (e.g., the previous byte time period), the sink may determine that the data lanes are to be ignored during the following time period.Data sent on each of the lanes of the MCPL can be aligned strictly with the strobe signal. A period of time may be defined based on the sampling, such as a byte period of time, and each of these periods may correspond to a defined window in which signals are to be transmitted on the data lanes (e.g., DATA[0-49]), the valid lanes (e.g., VALID1, VALID2), and a stream lane (e.g., STREAM). Accordingly, alignment of these signals may allow identification that a valid signal in a previous time slot is applied to data in the following time slot and that a stream signal is applied to data in the same time slot. The stream signal may be an encoded signal (e.g., 1 byte of data for a byte period window) encoded to identify the protocol applied to data transmitted during the same period window.For purposes of illustration, a byte period window is defined in the specific example of FIG. 7. Validity is confirmed at time slot n (715) before any data is inserted into data lanes DATA[0-49]. At the following time period window n+1(720), data is sent on at least some of the data lanes. In this case, data is transmitted during n+1(720) on all fifty data lanes. Since validity has been confirmed for the duration of the previous time slot n (715), the sink device may validate the data received on data lanes DATA[0-49] during time slot n+1 (720). In addition, the advanced character of the valid signal during time period windows n (715) allows the receiving device to prepare for the incoming data. Continuing with the example of FIG. 7, the valid signal remains asserted (to VALID1 and VALID2) during the duration of time slot n+1(720), causing the sink device to expect the data sent over data lanes DATA[0-49] during time slot n+2(725). If the valid signal should remain asserted during time period window n+2(725), the sink device could further expect to receive (and process) additional data sent during an immediately following time period window n+3(730). In the example of FIG. 7, however, the assertion of the valid signal is deasserted during the duration of time slot n+2 (725), indicating to the sink device that no data is being sent during time slot n+3 (730), and that all bits detected on data lanes DATA[0-49] should be ignored during time slot n+3 (730).As noted above, multiple valid lanes and scan lanes may be maintained per channel. This may aid in maintaining circuit simplicity and synchronizing the clusters of relatively long physical lanes connecting two devices, among other advantages. In some implementations, a set of data lanes may be divided into clusters of data lanes. For example, in the example of FIG. 7, data lanes DATA[0-49] may be divided into two twenty-five lane clusters, and each cluster may have a particular valid and scan lane. For example, valid lane VALID1 may be associated with data lanes DATA[0-24], and valid lane VALID2 may be associated with data lanes DATA[25-49]. The signals on each "copy" of the valid and scan lanes for each cluster may be identical.As introduced above, data on stream lane STREAM may be used to indicate to the receiving logical PHY which protocol is to be applied to the corresponding data transmitted on data lanes DATA[0-49]. In the example of FIG. 7, a stream signal is sent on STREAM during the same time period window as data on data lanes DATA[0-49] to indicate the log of the data on the data lanes. In alternative implementations, the stream signal may be sent during a previous time period window, such as with associated validity signals, among other potential modifications. However, continuing with the example of FIG. 7, a stream signal 735 is sent during time period windows n+1 (720) encoded to indicate the protocol (e.g., PCIe, PCI, IDI, QPI, etc.) to be applied to the bits to be sent during time period windows n+1 (720) over data lanes DATA[0-49]. Similarly, another stream signal 740 may be sent during the following time period window n+2(725) to indicate the protocol applied to the bits sent during time period window n+2(725) over data lanes DATA[0-49], and so on. In some cases, such as in the example of FIG. 7 (where both stream signals 735, 740 have the same encoding, binary FF), data in successive time period windows (e.g., n+1(720) and n+2(725)) may belong to the same protocol. However, in other cases, data in successive time period windows (e.g., n+1(720) and n+2(725)) may be of different transactions for which different protocols are to be applied, and stream signals (e.g., 735, 740) may be encoded accordingly to identify the different protocols applied to the successive bytes of data on the data lanes (e.g., DATA[0-49]), among other examples.In some implementations, a low power or idle state may be defined for the MCPL. For example, if none of the devices on the MCPL are transmitting data, the physical layer (electrical and logic) of the MCPL may transition to an idle or low power state. For example, in the example of FIG. 7, at time slot n- 2 (745), the MCPL is in a sleep or idle state and sampling is disabled to conserve power. The MCPL may go out of low power or idle mode and enable sampling at time slot n-1 (e.g., 705). The scan may complete a transmission preamble (e.g., to assist in activating and synchronizing each of the channels of the channel as well as the sink device), with the scan signal beginning before any other signaling on the other non-scan lanes. Following this time slot n-1 (705), the valid signal may be asserted at time slot n (715) to notify the sink that data will arrive in the following time slot n+1 (720), as discussed above.The MCPL may re-enter a low power or idle state (e.g., an L1 state) following detection of idle conditions on the valid lanes, data lanes, and / or other lanes of the MCPL channel. For example, beginning at time slot n+3 (730), and continuing, signaling may not be detected. Logic on either the source or sink device may initiate a transition back to a low power state, again resulting (e.g., time slot n+5 (755) windows) in the sample transitioning to an idle power saving mode, among other examples and principles (including those discussed later herein).Electrical characteristics of the physical PHY may include one or more of asymmetric signal transmission, half rate forward timing, link channel tuning, and on-chip transport delay of transmitter (source) and receiver (sink), optimized electrostatic discharge (ESD), pad capacitance, among other features. Further, an MCPL may be implemented to achieve a higher data rate (e.g., approximately 16 Gb / s) and energy efficiency than with conventional package I / O solutions.Referring to FIG. 8, a simplified block diagram 800 is shown illustrating an example logical PHY of an example MCPL. A physical PHY 805 may be connected to a die that includes logical PHY 810 and additional logic supporting a link layer of the MCPL. The die may, in this example, further comprise logic to support multiple different protocols on the MCPL. For example, in the example of FIG. 8, PCIe logic 815 may also be provided as IDI logic 820, such that the dies may communicate using either PCIe or IDI over the same MCPL connecting two dies, among potentially many other examples, including examples where more than two protocols or protocols other than PCIe and IDI are supported over the MCPL. Different protocols supported between the dies may provide varying levels of service and features.Logical PHY 810 may include link state machine management logic 825 to negotiate link state transitions associated with requests from logic at upper layers of the die (e.g., received via PCIe or IDI). Logical PHY 810 may further include link test and debug logic (e.g., 830) in some implementations. As noted above, an example MCPL may support control signals sent between dies over the MCPL to enable protocol agnostic, high-performance, and power efficiency features (among other example features) of the MCPL. For example, logical PHY 810 may support the generation and transmission, as well as the reception and processing of valid signals, stream signals, and LSM sideband signals in conjunction with the transmission and reception of data over particular data lanes, as described in examples above.In some implementations, multiplexing (e.g., 835) and demultiplexing logic (e.g., 840) may be included in or otherwise accessible by logical PHY 810. For example, multiplexed logic (e.g., 835) may be used to identify data (e.g., embodied as packets, messages, etc.) to be sent to the MCPL. The multiplexing logic 835 may identify the protocol controlling the data and generate a stream signal encoded to identify the protocol. For example, in an example implementation, the stream signal may be encoded as a byte of two hexadecimal symbols (e.g., IDI: FFh; PCIe: F0h; LLP: AAh; sideband: 55h; etc.) and may be transmitted during the same window (e.g., a byte period window) of the data controlled by the identified protocol. Similarly, demultiplexing logic 840 may be used to interpret incoming stream signals to decode the stream signal and identify the protocol to apply to the data received simultaneously with the stream signal on the data lanes. Demultiplexing logic 840 may then apply (or ensure) protocol-specific link layer handling and cause the data to be handled by the corresponding protocol logic (e.g., PCIe logic 815 or IDI logic 820).Logical PHY 810 may further include link layer packet logic 850 that may be used to handle various link control functions, including power management tasks, loop switching, disabling, re-centering, scrambling, etc. LLP logic 850 may enable link layer-to-link layer messages via MCPL, among other functions. Data corresponding to LLP signaling may also be identified by a stream signal transmitted on a particular stream signal path encoded to identify that the data paths are LLP data. Multiplexing and demultiplexing logic (e.g., 835, 840) may also be used to generate and interpret stream signals corresponding to LLP traffic, as well as to cause such traffic to be handled by the appropriate die logic (e.g., LLP logic 850). Similarly, some implementations of an MCPL may include a dedicated sideband (e.g., sideband 855 and supporting logic), such as an asynchronous and / or lower frequency sideband channel, among other examples.PHY logic 810 may further include link state machine management logic that may generate and receive (and use) link state management messages over a particular LSM sideband path. For example, an LSM sideband trajectory may be used to perform handshaking to advance a connection learning state, leave power management states (e.g., an L1 state), among other potential examples. The LSM sideband signal may be an asynchronous signal in that it is not aligned with the data, validity, and stream signals of the connection, but instead corresponds to signaling state transitions and aligns the connection state machine between the two dies or chips connected by the connection, among other examples. Providing a particular LSM sideband path may, in some examples, enable eliminating conventional analog front end (AFE) noise blocking and reception detection circuits, among other example advantages.Referring to Figure 9, a simplified link state machine transition diagram 900 is shown along with sideband handshaking used between the state transitions. For example, a reset.idle state (e.g., wherein phase lock loop (PLL) calibration is performed) may transition to a reset.cal state (e.g., wherein the connection is further calibrated) by sideband handshaking. Reset.Cal may transition, by sideband handshaking, to a Reset.ClockDCC state (e.g., where duty cycle correction (DCC) and delay-locked looping (DLL) control may be performed). An additional handoff may be performed to transition from the Reset.ClockDC state to a Reset.Sleep state (e.g., to cancel the assertion of the valid signal). To aid in the alignment of signaling on the lanes of the MCPL, the lanes may be centered by a Center.Pattern state.In some implementations, as shown in the example of FIG. 16, the transmitter may center during the centering state. Generate patterns of learning or other data. The receiver may condition its receiver circuitry to receive such learning patterns, for example, by adjusting the phase interpolator position and vref position and adjusting the comparator. The receiver may continually compare the received patterns to expected patterns and store the result in a register. After a set of patterns is completed, the receiver may increment the phase interpolator setting, thereby leaving vref equal. The test pattern generation and comparison process may continue and new comparison results may be stored in the register, the procedure repeatedly traversing all phase interpolator values and all values of vref. Centering state. Sleep may be entered when the pattern generation and comparison process is complete. Subsequent to the centering of the webs by the connection states centering pattern and centering. Idle may enable sideband handshaking (e.g., using an LSM sideband signal over the particular LSM sideband path of the connection) to transition to a Connection.Init state to initialize the MCPL and enable data to be sent on the MCPL.Returning temporarily to the discussion of FIG. 15, as noted above, sideband hand blows may be used to enable link state machine transitions between dies or chips in a multichip package. For example, signals on the LSM sideband lanes of an MCPL may be used to synchronize the state machine transitions on the die. For example, if the conditions for exiting a state (e.g., reset.idle) are met, the page that met these conditions may acknowledge an LSM sideband signal on its outgoing LSM_SB lane, and wait for the other remote die to meet the same condition and acknowledge an LSM sideband signal on its LSM_SB lane. When both LSM_SB signals are asserted, the link state machine of each respective die may transition to the next state (e.g., a Reset.Cal state). A minimum overlap time may be defined during which both LSM_SB signals should be kept asserted before a state transition occurs. Further, a minimum idle time may be defined after cancelling an acknowledgement of LSM_SB to enable accurate reversal detection. In some implementations, each link state machine transition may be conditioned on and enabled by such LSM_SB handles.FIG. 10 is a more detailed link state machine diagram 1000 illustrating at least some of the additional link states and link state transitions that may be included in an example MCPL. In some implementations, an example link state machine may include, among the other states and state transitions illustrated in FIG. 10, a "directed loop transition" that may be provided to place the lanes of an MCPL into a digital loop. For example, the receiver lanes of an MCPL may be fed back to the transmitter lanes behind the clock recovery circuits. A state "LB_Neu" may also be provided in some cases, which may be used to align the data symbols. Additionally, as shown in FIG. 9, MCPL may support multiple link states, including an active L0 state and low power states such as an L1 idle state and an L2 idle state, among potentially other examples. As another example, configuration or centering states (e.g., CENTERING) may be extended or inherently assist in reconfiguration of a link upon power-up to allow lanes of the link to be remapped to route data around one or more lanes of the link determined to be faulty or marginal, among other examples.FIG. 11 is a simplified block diagram 1100 illustrating an example flow in a transition between an active state (e.g., L0) and a low power or idle state (e.g., L1). In this particular example, a first device 1105 and a second device 1110 are communicatively coupled using an MCPL. In the active state, data is sent over the lanes of the MCPL (e.g., DATA, VALID, STREAM, etc.). Link layer packets (LLPs) may be communicated over the lanes (e.g., data lanes, where the stream signal indicates that the data is LLP data) to support enabling link state transitions. For example, LLPs may be sent between the first and second devices 1105, 1110 to negotiate for L0 to enter L1. For example, upper layer protocols supported by the MCPL may communicate that entry into L1 (or other state) is desired, and the upper layer protocols may cause LLPs to be sent over the MCPL to allow link layer handshaking to cause entry of the physical layer into L1. For example, FIG. 11 shows at least a portion of transmitted LLPs including an LLP with "enter-in-L1" request transmitted from the second (upstream) device 1110 to the first (downstream) device 1105. In some implementations and upper layer protocols, the downstream port does not initiate entering L1. The receiving first device 1105 may in response send a change-to-L1" request LLP that the second device 1110 may acknowledge via a change-to-L1" acknowledgement (ACK) LLP, among other examples. Upon detecting the completion of the handoff, the logical PHY may cause a sideband signal on a particular sideband link to be acknowledged to acknowledge that the ACK has been received and that the device (e.g., 1105) is ready to enter and expect L1. For example, the first device 1105 may acknowledge a sideband signal 1115 sent to the second device 1110 to acknowledge receipt of the final ACK in the link layer handshake. In addition, the second device 1110 may also acknowledge a sideband signal in response to sideband signal 1115 to notify the first device 1105 of the sideband ACK of the first device 1105. When link layer control and sideband hand blows are complete, the MCPL PHY may transition to the L1 state causing all lanes of the MCPL to be placed in an idle power saving mode, including corresponding MCPL samples 1120, 1125 of devices 1105, 1110. The L1 may be exited when upper layer logic requests from the first or second device 1105, 1110 to reenter L0, for example, in response to detecting data to be sent to the other device via the MCPL.As noted above, in some implementations, an MCPL may enable communication between two devices, potentially supporting multiple different protocols, and the MCPL may enable communications corresponding potentially to any of the multiple protocols over the lanes of the MCPL. However, enabling multiple protocols can complicate entry and re-entry into at least some connection states. For example, while some conventional connections have a single upper layer protocol that takes the role of a master in state transitions, implementing an MCPL with multiple different protocols effectively includes multiple masters. As an example, as shown in FIG. 11, both PCIe and IDI may be supported between two devices 1105, 1110 via a translation of an MCPL. For example, placing the physical layer in an idle or low power state may be conditioned, with permission to be obtained first from each of the supported protocols (e.g., both PCIe and IDI).In some cases, entering L1 (or another state) may be requested by only one of the multiple supported protocols supported for translation of an MCPL. While there may be a probability that the other protocols may similarly request entering the same state (e.g., based on identifying similar conditions (e.g., little or no traffic) on the MCPL), the logical PHY may wait until permission or commands are received from each upper layer protocol before actually allowing state transition. The logical PHY may record which upper layer protocols requested the state change (e.g., made an associated handoff) and trigger the state transition upon identifying that each of the protocols requested the particular state change, such as a transition from L0 to L1 or another transition that would affect or interfere with communications with other protocols. In some implementations, protocols may be blinded in terms of their at least partial dependence on other protocols in the system. Further, in some cases, a protocol may expect a response (e.g., from the PHY) to a request to enter a particular state, such as a confirmation or a rejection of the requested state transition. Accordingly, in such cases, while waiting for permission from other supported protocols to enter an idle link state, the logical PHY may generate synthetic responses to a request to enter the idle state to "believe" the requesting upper layer protocol that a particular state has been entered (if the lanes are still actually active, at least until the other protocols also request entry into the idle state). Among other potential advantages, this may facilitate coordinating low power state entry between multiple protocols, among other examples.Implementations of a logical PHY may include error detection, error reporting, and error handling logic. In some implementations, a logical PHY of an example MCPL may include logic to detect PHY layer de-framing errors (e.g., on the valid and current lanes), sideband errors (e.g., associated with LSM state transitions), errors in LLPs (e.g., critical to LSM state transitions), among other examples. Some error detection / resolution may be delegated to upper layer logic, such as PCIe logic adapted to detect PCIe specific errors, or to system management software, among other examples. In some implementations, error detection and handling mechanisms may be provided, such as cyclic redundancy check (CRC), retry buffers, among other potential examples, to aid bit error detection on an MCPL. Further, error detection logic, whether implemented in management software or the logical PHY, may determine that specific lanes are faulty or marginal based on determining lane-specific bit errors on a link.An MCPL port may consist of a large number of lanes (e.g., 100 lanes or more) operating at very high speeds (e.g., 8 Gbs). For example, an MCPL port may comprise 80 or more lanes in each direction (e.g., a total of more than 160 lanes). In some cases, an MCPL connection(s) may transition to an active state (L0) even if some of the paths of the connection or port are faulty or "marginal.". This may occur once and for a limited time in a controlled noise and crosstalk environment after centering is complete. Webs may also become marginal over time, for example due to self-heating, electromigration, aging, packaging deficiencies, and other causes. Marginal pathways can cause the entire joint to fail. As a result, it is desirable to identify tracks that have become marginal and do so before failure of the connection occurs. Identification of a marginal trajectory may allow corrective action to be initiated, such as reconfiguration of the connection. In some cases, marginal lane discovery and correction may be performed dynamically without shutting down the link and associated systems. This may be advantageous, for example, in systems where continuous operation is desired, such as in server systems requiring operation around the clock. Identifying loaded tracks may also be helpful to tune the centering algorithms for process or package changes and improve manufacturing tests.Monitoring the analog quality of only a single operated web may be difficult at high speed. One conventional solution has been to provide an analog reference to enable a test device to access a problem path. However, this approach may not be satisfactory in a system with large numbers of lanes (e.g., 100 or more lanes). Further, identifying a specific one of the large number of lanes may be difficult. In addition, even if the specific marginal trajectory can be identified, dynamically reconfiguring the connection to account for the marginal trajectory can be expensive and annoying. For example, while QPI connections have functionality to identify hard faults after their occurrence and reconfigure around a poor path, such conventional solutions result in reduced bandwidth and other problems.In one implementation, MCPL logic can be provided that has the capability to identify specific marginal trajectories and, autonomously, initiates actions to replace the marginal trajectory before a hard fault results without causing the system to crash. Packets transmitted on a high speed link may be protected by checksum, parity and other values that allow detection of bit errors in the packet. In an example, at least some of the protocols transmitted on an MCPL connection may be protected with a CRC. For CRC, a particular associated packet is treated as a Galois field polynomial (e.g., GF(2)), which is divided by the CRC polynomial. The remainder, or checksum, may then be appended to the packet prior to transmission. At the receiving end, the receiver may attempt to perform the same calculation. If there are no bit errors in the packet, the same operation always yields a fixed remainder (or syndrome). Incorrect bits would, however, result in the syndrome differing from the fixed one.In a particular example, a common CRC may be used in each of the types of data transmitted over an MCPL. For example, a 16-bit CRC polynomial may be added to each of the flits, packets, or other data (from varying protocols) sent over an MCPL. In one example, the CRC polynomial may be selected such that a CRC syndrome generated from the CRC may be used to identify specific bit errors that may then be associated with specific lanes of a link. In one example, syndrome characteristics of a 16-bit polynomial calculation 0x1f053 may be used to identify bad lanes. Such a CRC polynomial may have capabilities that allow to identify all 1, 2, 3-bit errors and almost all 4-bit errors on an MCPL flit.Referring to FIG. 12, a simplified block diagram 1200 is shown illustrating components implemented in hardware and / or software that, in some cases, may be provided to identify problem lanes from CRC syndrome values identified during CRC error computations. For example, a first device 1205 may be coupled to a second device 1210 via an MCPL 1215. The first device 1205, in this example, may be a sending device in a particular transaction (or instance) and send data to the second, receiving device 1210 via the MCPL 1215. (It should be appreciated that in cases other than the transmitting device, device 1210 may transmit data to device 1205 via an MCPL, among other examples.) The first device 1205 may include logic 1220 to generate one or more flits for transmission over the MCPL 1215. A packet, message, or other formulation of data to be sent over the MCPL may comprise one or more flits. Each flit may include a CRC value calculated and encoded using a CRC generator 1225. The flits may be sent to the second receiving device 1210 via connection 1215. The second device 1210 may include logic to receive the flit and decode, or otherwise identify, the flit, including header values, slot values, and the CRC value (e.g., using CRC check logic 1230).A receiving device may use a CRC value in a received flit to identify bit errors in the flit. In some implementations, the receiving device may regenerate the CRC from the remaining bits of the received flits and compare the regenerated CRC value to the received CRC value (e.g., using CRC check logic 1230) to determine bit errors. An error checksum (or residue or "syndrome") may be generated during the comparison (e.g., using CRC check logic 1230) in response to an error in the flit (and a mismatch between the regenerated CRC value and the received CRC value). In some cases, a syndrome may be generated at the receiving device during regeneration of the CRC on the payload portion of the flit, and the regenerated CRC may be compared to the received CRC value, for example, by a bitwise XOR comparison, where the value resulting from the comparison represents the syndrome. In another example, a CRC may be performed at the receiving device on the entire flit (i.e., including the received CRC field), the result of this operation embodying the syndrome. The syndrome may be generated at the receiver using hardware or firmware, or alternatively, the syndrome may be generated by software, such as software for monitoring the operation of the receiver and the connection, among other potential implementations. In a specific implementation, a 16-bit syndrome value may be generated when errors are detected from a 16-bit CRC value. Other implementations may use other error residue values.A syndrome value (e.g., 1240) determined by the receiving device (e.g., by CRC check logic 1230) may be communicated or otherwise made available to a path monitoring module 1250 implemented in hardware and / or software (or even at the first or second device 1205, 1210). The trajectory monitor 1250 may include a bit error detection module 1255 including logic to associate a syndrome value with a particular bit (or multiple bits) in the flit. A CRC value may be generated from a CRC polynomial that is matched to the organization of the flit such that a unique syndrome value results from any given one of a set of errors (such as a set comprising each individual bit error on each of the bits of the flit, each individual two-bit error affecting any two consecutive bits of the flit, etc.). Accordingly, the bit error detection module 1255 may determine, from the syndrome 1240, one or more specific bits of the flit where the bit error occurred. The bit error detection module may also determine, from the syndrome, the type of error, such as a single bit error, a two bit error, etc.In some cases, the bits of a flit may be sent in the same corresponding lane in multiple different flits. Accordingly, an assignment may be obtained and determined (e.g., using bit-to-lane assignment module 1260) to assign an error affecting a given bit to its corresponding lane of the connection. In other cases, such as when the flit is sent during a partial width link state or during path reversal conditions, mapping the detected error affected bit to the path on which it was sent may be more complicated. In some implementations, the path error monitor 1250 may receive additional data from the receiving device 1210 (and / or transmitting device 1205) or from other resources (e.g., registers corresponding to the connection) indicating the conditions of the corresponding path when the flit was transmitted. Such additional information may include, for example, a flit rearranging phase number at the physical layer, a link width indicator at the physical layer, an indicator indicating whether or not path reversal is used, etc. Using such information, the bit-to-lane mapping module 1260 may determine the lanes used in transmitting a particular flit, and thereby determine the bit order used during transmission to determine the specific lane on which each flit bit was transmitted. In this way, the bit-to-lane mapping module 1260 may determine from the syndrome, at least for some bit errors, the lane on which the bit error occurred. The bit-to-lane allocation module 1260 may record or report this information for lane error monitoring 1265. The lane fault monitor 1265 may maintain records, a counter, or some other data indicative of, for each lane of a given connection (e.g., 1215), the number and frequency of faults detected on the lane (e.g., based on the reported connection faults determined using bit fault detection 1255 and bit-to-lane mapping module 1260).In one example, lane error monitor 1250 may maintain one or more tables to record particular bit errors lane by lane. A probabilistic decision algorithm may be utilized by the path error monitor 1265 to determine that a statistically significant number of bit errors are detected during a time period on a given path of a connection. The statistically significant value may be a threshold amount of errors determined over the period of time, may be a rate of errors that exceeds a defined threshold error rate for the web, among other examples. The algorithm may also take into account the amount of time the lane was active (e.g., remaining active in an L0 state or during a partial width state, etc.), the number of bits transmitted, among other factors, in determining when errors on the lane exceed a threshold or other acceptable value. Based on identifying a statistically significant amount of bit errors that appear on a given lane, a lane error monitor 1265 may determine that the lane is a marginal or faulty lane and do so before the problems with that lane result in an error in the MCPL as a whole.Upon determining that problems occur in one or more lanes of a connection, based on statistically significant numbers of bit errors determined for the lane from syndrome values 1240 and / or checksum comparison values 1280, a lane controller 1270 may be invoked to perform actions on the lane or lanes, or to instruct one or both of the devices 1205, 1210 to enter a reconfiguration state to address the problem. For example, a trajectory determined to be "bad" may cause the MCPL to be re-centered and reconfigured to repel the bad trajectory and re-associate logical trajectories with different physical trajectories of the connection.FIGS. 13A-13C illustrate representations of example bit assignments on data lanes of an example MCPL for various types of data. For example, an example MCPL may include fifty data lanes. Some forms of traffic sent on the MCPL may use less than the total number of lanes provided. FIG. 13A illustrates a first bit map of example 16-byte slots in a first protocol, such as IDI, that may be transmitted over the data lanes within an 8UI symbol, or window. For example, within the defined 8UI window, three 16-byte slots, including a header slot, may be sent. Two bytes of data remain, in this example, that may be transmitted on a fifty-lane link, and these remaining two bytes may be used for CRC bits (e.g., in lanes DATA[0] and DATA[1]), 16-bit CRC polynomial value 0x1f053 as discussed above.In another example, FIG. 13B illustrates a second example bit map for PCIe packet data sent over the fifty data lanes of an example MCPL. In the example of FIG. 13B, 16-byte packets (e.g., transaction layer (TLP) or data link layer (DLLP) PCIe packets) may be sent over the MCPL. Framing symbols can be included in these symbols and used to locate the start and end of each packet. In an example of PCIe, the framing used in the example of FIG. 13B may be the same as those characters mapped to PCIe at 8GT / s. In an 8UI window, three PCIe packets (e.g., data link layer packets (DLLPs) or transaction layer packets (TLPs)) may be sent with the remaining two bytes of bandwidth remaining unused within the window. As in the example of FIG. 13A, these two remaining bytes may be used for the same 16-bit CRC polynomial 0x1f053 used in other protocols (e.g., IDI) that enable bitwise identification of bit errors using CRC syndrome.In yet another example, shown in FIG. 13C, an example bit map of link-to-link packets (e.g., LLP packets) sent over an example MCPL is shown. LLPs may each be 4 bytes, and each LLP (e.g., LLP 0, LLP 1, LLP 2, etc.) may be transmitted four times in succession, in accordance with fault tolerance and fault detection within an example implementation. For example, failure to receive four consecutive identical LLPs may indicate a failure. Additionally, as with other types of data, failure to receive a VALID in a contiguous time slot, or symbol, may also indicate an error. In some cases, LLPs may have fixed slots. Additionally, in this example, unused or "spare" bits in the byte period may cause logical 0s to be sent over remaining lanes. These clear lanes may be extended to allow for the transmission of the 16-bit CRC polynomial 0x1f053, allowing for simultaneously detecting bit errors in the LLP packets, among other examples. Other example data types, or stream types, may be supported beyond these examples. In addition, alternative bit assignments for these and other types of data may be adopted and used in identifying bit errors on a per-lane basis. As an example, while some of the examples associate bits "right to left" starting with the lowest numbered lane (e.g., a cluster), other implementations (including other connections within the same system) may associate lanes from the highest numbered lane (or "left to right"), among other examples.In accordance with what has been said, in the event of flit errors, the current flit mapping may be stored or otherwise made identifiable to the bit-to-lane mapping logic. This state may be stored along with the syndrome to allow software (e.g., bit-to-lane allocation logic) to decode the lane position of the error. A set of possible flit assignments may be defined for use on a connection. Referring to FIGS. 14-1, 14-2, 14-3, there is shown a diagram of an assignment of syndrome values calculated from CRC values resulting from single bit errors in a flit. Such a mapping may be implemented in a syndrome decoding table which may be used to decode the lane on which a given bit error occurred. For example, the mapping shown in FIGS. 14-1, 14-2, 14-3 represents the mapping for single bit errors in a 400 bit (or smaller) flit. It should be appreciated that the illustration in FIGS. 14-1, 14-2, 14-3, in some implementations, may represent only a portion of the mapping, generating additional unique CRC syndrome values to map syndromes to single bit errors in flits and packets greater than 400 bits. For example, the use of CRC may be extended to generate unique syndrome values for packets, flits, or data packets of over 400 bits, such as for a 1-byte window of data sent over fifty lanes of an MCPL.A CRC polynomial can be selected such that a unique syndrome value can be present for each possible single bit error in the flit, as shown in Figures 14-1, 14-2, 14-3. As an example, a syndrome value of 0xcc48 may always result in this implementation when a single bit error affects bit 50 of the flit. As another representation, a syndrome value, in this example implementation, of 0xb8d3 may always result when a single bit error affects bit 229 of the flit, and so on. Achieving such an assignment can be accomplished by determining and using a particular CRC polynomial adapted to generate such unique values for the particular flit layout (and phit formats). For example, in the example of FIGS. 14-1 and 14-2, the CRC polynomial 0x1f053 may be selected to generate a 16-bit CRC that enables bit-specific error detection. Several other CRC polynomials may also be present for a given flit format that allows unique single bit CRC syndrome values for each single bit error in the flit. Software can be used to test a combination of bit errors that can arise for a given flit format, and further determine, for a series of different CRC polynomial candidates, which polynomials resulted in CRC syndrome values that were unique for each different bit error.Referring to FIGS. 15-1, 15-2, and 15-3, a second syndrome decoding table 1500 is shown corresponding to an example 400-bit flit and associated CRC generated from an example CRC polynomial (e.g., 0x1f053). Syndrome decoding table 1500, rather than being associated with single bit errors, allocates syndromes to the complete set of two bit errors (i.e., errors in consecutive bits) that may occur in a set of 400 consecutive bits. Accordingly, in some implementations, a CRC polynomial may be selected and used that results in unique CRC syndrome values not only for each possible single bit error on a flit, but also for all possible two bit errors, among other examples. As an example, a syndrome value of 0x1c93 may always result, in this implementation, when a double bit error affects the combination of bits 228 and 229 of the flit. As another representation, a syndrome value, in this example implementation, of 0xae58 may always result when a double bit error affects bits 99 and 100 of the flit, and so on. Of course, it should be appreciated that the examples shown in FIGS. 14-1, 14-2, 14-3, 15-1, 15-2, 15-3 are specific to an example implementation that serves to provide a 16-bit CRC value for a flit from any of the multiple protocols that may be transmitted over an MCPL. However, these same principles may be applied to other connection technologies. Further, it should be appreciated that some CRC polynomials may result in unique detection of other bit-specific errors in addition to (or as an alternative to) single-bit and two-bit errors, and other examples.An assignment of bit errors to one or more flit bits, such as implemented by a syndrome decoding table, may be used to assign the bit errors to one or more corresponding lanes used to transmit the associated flit affected by the bit error or errors. For example, a syndrome may be received in an associated transaction (e.g., from a particular device involved) in which an associated bit error was determined from the CRC value of a flit of the transaction. A lane monitor may determine whether the syndrome value is included in one of a set of syndrome decoding tables (e.g., 1400, 1500). If so, the correct syndrome decoding table can be used to identify the bit number within the flit that has the error (just as if multiple bits had errors). If the syndrome is not included in an available syndrome decoding table, the error may not be associated with particular bits or lanes (e.g., in cases where multiple non-contiguous bit errors affect the flit). In cases where a table containing the syndrome value is identified, one or more specific bits may be identified as being affected by the error, and a bit-to-lane allocation may then be determined for the identified bit or bits having an error to determine that the erroneous bit was transmitted on a given one of multiple lanes on a link of an interconnect. The lane number may be decoded, for example, by first determining the type of data in which the fault was detected (e.g., from the associated stream label). A corresponding bit-to-lane mapping (e.g., FIGS. 13A-13C ) corresponding to the data type may be determined and used. Further, the bit-to-lane mapping used may also be affected by determining whether any lanes have been (previously) withdrawn at a port (e.g., because the lane is marginal), the manner in which lanes within a cluster of lanes are mapped, which lanes of the corresponding cluster are idle, whether (and which) rearrangement phase was applied, and whether lane reversal was applied, among other example factors and considerations.Referring to FIG. 16, a simplified block diagram 1600 is shown, depicting at least a portion of a system including an example implementation of an MCPL including clusters 1605-1615 of data lanes used to implement the MCPL. The system may include logical PHY 630 of the MCPL and physical PHY 625 of the MCPL. Clusters of lanes, such as general cluster 1620 and phase-lock loop (PLL) 1625 may be used to provide lanes for timing and control, such as lanes used for the sideband, current, sample, and valid lanes of an MCPL, among other lanes. In an example, the control lane clusters 1605 may include one or more idle, or unused, lanes. These lanes may be used in the event one or more of the control lanes become marginal, where the marginal control lane is remapped into one of the unused lanes. Similarly, each of the clusters of data lanes 1605-1615 may be provided with a defined number of lanes. In some implementations, lanes may be associated with a given MCPL on a cluster basis. For example, in one example, each cluster of data lanes may include twenty physical lanes. If the MCPL is to include fifty lanes, three twenty lane clusters may be assigned to the MCPL to provide fifty (or indeed sixty) lanes. Since less than all of the associated clusters are allocated for use in the MCPL, additional unused lanes (e.g., 10 lanes) may be used when one of the associated lanes becomes marginal.As noted above, a CRC syndrome may be included in any flit of data sent on an MCPL, regardless of the data (or stream) type. Using the syndrome, individual bit errors can be identified and mapped to associated physical lanes allocated for use in the MCPL. After a threshold or statically significant amount of bit errors is identified for a particular physical path, the logical PHY, software management system, or other logic may determine that the particular path is marginal. To prevent a system fault caused by this marginal trajectory, the MCPL can be reconfigured without impacting the system. In one example, the logical mapping of lanes may be moved away from the marginal lane towards a block of unused lanes in a data lane cluster used in the MCPL. This reconfiguration of the lanes may cause redirection of the lanes used in the MCPL, and may include causing the MCPL to enter a connection state that enables reconfiguration.In one example, a modified link state and process for re-centering may be enabled, and a sideband path may be used to communicate with the transmitting and receiving devices to organize the reconfiguration. For example, the software or hardware based path controller may use the MCPL sideband to instruct the remote transmitter to reconfigure the connection to cause traffic on each path to be redirected left (or right) adjacent the marginal path away from the marginal path. The unused path accepted by the reconfigured MCPL may be ready for data transfer because it was involved in the original centering performed during MCPL initialization (e.g., transporting a scrambled "0" value during the L0 state), enabling data to be sent immediately following reconfiguration on the unused path. This may allow reconfiguration to precede the re-centering using a PRBS, among other efficiencies. In other cases, unused lanes may be kept idle during the L0 data transmit state to save power. In these cases reconfiguration may be performed (again without crashing the connection), but a PRBS is used in both the reconfiguration and recentration states.Reconfiguring a connection to account for an identified marginal lane by redirecting a portion of the lanes to adjacent lanes (and an unused lane) may minimize the overall forwarding overhead. A path multiplexer of the redirecting transmitting and / or receiving devices may perform the redirecting. In some implementations, the path multiplexer may be implemented in software or in the logical PHY 630, while in other implementations, the path multiplexer may be implemented in hardware of the physical PHY 625. In some examples, the path multiplexer may be opened up in other multiplexers, such as a loop slave (loopback slave) and path reversing multiplexers in the logical PHY 630. In some cases, the path multiplexer may be advantageously implemented in software or logical PHY 630 to prevent complications associated with other circuitry, as well as to control path clusters (e.g., general cluster) at some data path cluster boundaries, among other example considerations.Referring to FIGS. 17A-B, example implementations of reconfiguration of a connection are shown. For example, a cluster of n lanes is shown in Figure 17A. In this example, a total of y+2 lanes in the cluster are allocated following the configuration of the MCPL (at 1705). Accordingly, following the initial configuration, (logical) lanes numbered 0 through y+2 are mapped to physical lanes 0 through x+2. In this example, empty lanes in the MCPL are positioned on the most significant lanes of one of the clusters to form the MCPL, in this case lanes x+3-n. Continuing with this example, lane x may be determined to be marginal, for example, based on the detection of repeated bit errors associated with the lane using a CRC syndrome, as described above. To address the marginal lane x, both devices (e.g., 1710, 1710) on the link may enter a reconfiguration (and / or recentration) state and redirect traffic on a portion of the associated lanes to disable the marginal lane x and replace it with one of the unused lanes. For example, because the empty lanes "follow" the active lanes (and marginal lane x), reconfiguration may result in the lane assignments "following" the marginal lane being moved 1720 (as shown in 1725) to an adjacent physical lane towards the open lanes. Accordingly, the most significant assigned lane number y+2may be moved to the previously unused physical lane x+3, y+1may be moved to x+2, and lane number y originally assigned to marginal lane xmay be moved to physical lane x+1. Marginal trajectory x may be left unused following displacement 1720. In some cases, this reconfiguration change may be permanent, with trace x deemed permanent marginal and unusable.FIG. 17B illustrates another example of reconfiguration of an MCPL connecting devices 1730, 1735. In this example, lane numbers 0 through y+n are originally assigned (at 1740) to the phyic lanes x-3 through n. Additional unused physical lanes are also present in this example, such as lanes 0 through x-4. In this example, rather than occupying the most significant physical lanes of the connection, unused lanes occupy the least significant physical lanes of the connection (e.g., lanes 0 through x-4). Again, in this example, physical path x is determined to be marginal, triggering reconfiguration of the connection. However, assuming that the empty lanes in this example "precede" the marginal lane x, all lanes "preceding" the marginal lane are shifted 1745 in the opposite direction to the shift in Figure 17A, again toward the unused lanes. For example, lane number y is moved from marginal lane x to lane x-1, lane number y-1 is moved from physical lane x-1 to x-2, lane number y-3 is moved from lane x-3 to previously unused lane x-4, and so on (as shown at 1750). Accordingly, in determining how to move and re-associate lanes in a reconfiguration step, logic may identify the location of unused lanes in the lane clusters used to translate the data lanes of the connection (e.g., MCPL) and may move lanes from the marginal lane towards the empty lanes, as in the examples of FIGS. 17A-17B.For example, if one of the active data lanes is included in one of the associated clusters. Other cases may define an MCPL or data lane cluster with a different number of lanes, with corresponding numbers of clusters being assigned to a single MCPL, and a different number of unused lanes remaining in one of the assigned clusters. Regardless of the implementation, unused data lanes remaining in an associated cluster may be reserved to re-associate another data lane determined to be marginal.FIGS. 18A-18B show flowcharts 1800 a- brepresenting example techniques for detecting and remedying marginal lanes on an interconnect, such as an MCPL. For example, as shown in FIG. 18A, a flit may be received 1805, with an error code, such as a CRC, embedded in it 1805, or sent along with the flit of data on a link. Alternatively, errors may be detected by other mechanisms, such as by checking parity on the lane, among other examples. The connection may time multiplex transmission of data of several different types (or protocols) using the same connection. The error code may be used (e.g., by the receiving device) to detect 1810 one or more bit errors. For example, the error code may allow generation of an associated syndrome, which may indicate at which bits of the flit errors have occurred. The specific bit errors may be associated 1815 with the particular path of the link used to transmit the erroneous bit. Mapping bit errors to lanes may be based on which protocol is applied to the flit, where different protocols potentially map bits differently to lanes. The detected bit error may be associated 1820 with the particular lane and may be used to detect lanes that are marginal (e.g., based on a higher than average number of bit errors occurring on the particular lane).Referring to FIG. 18B, a particular path may be determined 1830 as marginal. The determination 1830 may be based on, for example, the detection of multiple bit errors occurring on the determined path, according to the technique described in the example of FIG. 18A. Determining 1830 that a trail is marginal may initiate reconfiguration of the connection to re-associate data with at least one empty, or unused, trail to disable the marginal trail. This can be accomplished, for example, by identifying 1835 an empty lane in a cluster of lanes used to form the link. A set of contiguous lanes may be present between the marginal lane and the empty lane. In some cases, the empty lane may be the first of a span of empty lanes in the cluster. Reconfiguration 1840 and re-mapping of the lanes may include moving the mapping of each lane in the set, including the marginal lane, to the empty and away from the marginal physical lane. Thus, data for each lane in the set, following reconfiguration 1840, is to be sent on the physical lane adjacent to its originally assigned physical lane (toward the empty lanes). One of the empty lanes is taken over as an associated lane in the link by means of the displacement, and the marginal lane is left unallocated. Lanes of the connection that are not included in the set remain as originally assigned. This reconfiguration 1840 may occur while the system is active, for example, by transitioning to a reconfiguration connect state, such as a centering state, and data transmission may automatically resume 1845 subsequent to reconfiguration 1840 on the newly allocated lanes.It should be noted that the above-described devices, methods, and systems may be implemented in any / any electronic device or system, as mentioned above. As specific illustrations, the following figures provide exemplary systems for utilizing the invention as described herein. As the following systems are described in more detail, a number of different compounds are disclosed, described and re-adopted from the above discussion. And as will be apparent, the advances described above may be applied to any of these connections, structures, or architectures.Referring now to FIG. 19, an example implementation of a system 1900 is shown, in accordance with an example embodiment. As shown in FIG. 19, multiprocessor system 1900 is a point-to-point interconnect system and includes a first processor 1970 and a second processor 1980 coupled via a point-to-point interconnect 1950. Each of the processors 1970 and 1980 may be some version of a processor. In one embodiment, 1952 and 1954 are part of a serial, coherent point-to-point interconnect structure, such as a high performance architecture. As a result, the invention can be implemented within the QPI architecture.While shown with only two processors 1970, 1980, it should be understood that the scope of the present invention is not so limited. In other embodiments, one or more additional processors may be present in a given processor.Processors 1970 and 1980 are shown to include integrated memory controller units 1972 and 1982, respectively. Processor 1970 also includes as part of its bus control units point-to-point (P-P) interfaces 1976 and 1978; similarly, second processor 1980 includes P-P interfaces 1986 and 1988. Processors 1970, 1980 may exchange information via a point-to-point (P-P) interface 1950 using P-P interface circuits 1978, 1988. As shown in FIG. 19, IMCs 1972 and 1982 couple the processors to respective memories, particularly a memory 1932 and a memory 1934 which may be portions of main memory locally connected to the respective processors.Processors 1970, 1980 each exchange information with a chipset 1990 via individual P-P interfaces 1952, 1954 using point-to-point interface circuits 1976, 1994, 1986, 1998. Chipset 1990 also exchanges information with a high performance graphics circuit 1938 via an interface circuit 1992 along a high performance graphics link 1939.A shared cache (not shown) may be included in each processor or outside both processors, and yet connected to the processors via a P-P connection, such that the local cache information of each processor or both processors may be stored in the shared cache when a processor is placed in a low power mode with low power.Chipset 1990 may be coupled to a first bus 1916 via an interface 1996. In one embodiment, the first bus 1916 may be a peripheral component interconnect (PCI) bus or a bus such as a PCI Express bus or another third generation I / O interconnect bus, although the scope of the present invention is not so limited.As shown in FIG. 19, various I / O devices 1914 are coupled to the first bus 1916, along with a bus bridge 1918 that couples the first bus 1916 to a second bus 1920. In one embodiment, the second bus 1920 includes a low pin count (LPC) bus. Various devices are coupled to the second bus 1920 including, for example, a keyboard and / or mouse 1922, communication devices 1927, and a storage unit 1928 such as a disk drive or other mass storage device, which, in one embodiment, often includes instructions / code and data 1930. Further, an audio I / O 1924 is shown coupled to the second bus 1920. It should be noted that other architectures are possible, with the components and interconnection architectures included varying. For example, instead of the point-to-point architecture of FIG. 19, a system may implement a multi-drop bus or other such architecture.While the present invention has been described in terms of a limited number of embodiments, numerous modifications and variations thereof will be apparent to those skilled in the art. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.A design may go through different phases, from creation via the simulation to fabrication. Data representing a design may represent the design in a variety of ways. First, since it is useful for simulations, the hardware can be represented using a hardware description language or another functional description language. Additionally, a circuit level model with logic and / or transistor gates may be produced at some stages of the design process. Further, at some stage, most designs achieve a level of data representing the physical positioning of various devices in the hardware model. In the case where conventional semiconductor manufacturing techniques are used, the data representing the hardware model may be the data indicating the presence or absence of various features on different mask layers for masks used to fabricate the integrated circuit. In any representation of the concept, the data may be stored in any form of machine readable medium. A memory or magnetic or optical storage, such as a disk, may be the machine readable medium for storing information transmitted via modulated or otherwise generated optical or electrical waves for transmitting such information. When an electrical carrier wave indicating or transporting the code or design is transmitted, a new copy is generated to the extent that copying, buffering, or retransmission of the electrical signal is performed. Thus, a communication provider or network operator may store an article, such as encoded information embodied in a carrier wave embodying techniques of embodiments of the present invention, on a tangible, machine-readable medium, at least temporarily.A module as used herein refers to any combination of hardware, software, and / or firmware. As an example, a module includes hardware, such as a microcontroller, associated with a non-transitory medium for storing code adapted to be executed by the microcontroller. Thus, reference to a module, in one embodiment, refers to the hardware specifically configured to recognize and / or execute code to be maintained on a non-transitory medium. Further, in another embodiment, using a module refers to the non-transitory medium including code specifically adapted to be executed by the microcontroller to perform predetermined operations. And as can be concluded, in yet another embodiment, the term module (in this example) may refer to the combination of the microcontroller and the non-volatile medium. Often, module boundaries represented as separate will usually vary or potentially overlap. For example, first and second modules may share hardware, software, firmware, or a combination thereof, potentially retaining somewhat independent hardware, software, or firmware. In one embodiment, using the term logic includes hardware such as transistors, registers, or other hardware such as programmable logic devices.Use of the phrase "configured to," in one embodiment, refers to arranging, composing, manufacturing, offering for sale, importing, and / or interpreting a device, hardware, logic, or element for performing a particular or particular task. In this example, a device or element thereof that is not operating is still "configured to" perform a particular task when designed, coupled, and / or connected to perform the particular task. As a purely illustrative example, a logic gate may provide a 0 or a 1 during operation. However, a logic gate "configured to" provide an enable signal to a clock does not include any potential logic gate that can provide a 1 or 0. Instead, the logic gate is one which is coupled in some way that during operation the output 1 or 0 serves to enable the clock. It is to be noted again that using the term "configured to" does not require operation, but instead focuses on the latent state of a device, hardware, and / or element, where in the latent state the device, hardware, and / or element is designed to perform a particular task when the device, hardware, and / or element is operating.Further, in one embodiment, using the phrases "to," "capable of," and / or "operable to" refers to a certain device, logic, hardware, and / or element designed in such a manner as to enable using the device, logic, hardware, and / or element in a specified manner. As noted above, in one embodiment, using "to", "capable of", or "operable" refers to the latent state of a device, logic, hardware, and / or element where the device, logic, hardware, and / or element is not operational, but is designed in such a manner as to enable using a device in a specified manner.A value as used herein includes any known representation of a number, state, logical state, or binary logical state. Often, using logic levels, logic values, or logic values is also referred to as 1s and 0s, which simply represents binary logic states. For example, a 1 refers to a high logic level and 0 refers to a low logic level. In one embodiment, a memory cell, such as a transistor or flash cell, may be capable of holding a single logical value or multiple logical values. However, other representations of values have been used in computer systems. For example, the decimal number ten may also be represented as a binary value of 1010 and a hexadecimal letter A. Thus, a value includes any representation of information capable of being maintained in a computer system.Moreover, states may be represented by values or by parts of values. As an example, a first value, such as a logical, a default, or initial state, while a second value, such as a logical zero, may represent a non-default state. Additionally, the terms "reset" and "set," in one embodiment, refer to a default or updated value or state, respectively. For example, a default value potentially includes a high logical value, i.e., reset, while an updated value potentially includes a low logical value, i.e., set. It should be noted that any combination of values may be used to represent any number of states.The embodiments of methods, hardware, software, firmware, or code set forth above may be implemented via instructions or code stored on a machine-accessible, machine-readable, computer-accessible, or computer-readable medium executable by a processing element. A non-transitory machine-accessible / readable medium includes any mechanism that provides (i.e., stores and / or sends) information in a form readable by a machine, such as a computer or electronic system. For example, a non-transitory machine-accessible medium includes random-access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage medium; flash memory devices; electrical storage devices; optical storage devices; acoustic storage devices; another form of storage devices for holding information received via volatile (propagated) signals (e.g., carrier waves, infrared signals, digital signals), etc., to be distinguished from the non-volatile media that can receive information therefrom.Instructions used to program logic to perform embodiments of the invention may be stored within a memory in the system, such as DRAM, cache, flash memory, or other memory. Further, the instructions may be distributed over a network or by other computer readable media. Thus, a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to floppy disks, optical disks, compact disk read-only memories (CDROMs), and magneto-optical disk read-only memories (ROMs), random access memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), Electrically erasable programmable read-only memory), magnetic or optical cards, flash memory, or a tangible, machine readable memory used in the transmission of information over the Internet via electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). Accordingly, the computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).The following examples are included in embodiments consistent with this specification. One or more embodiments may provide an apparatus, a system, a machine readable memory, a machine readable medium, and / or a method for receiving first data on a plurality of data lanes of a physical connection, receiving a stream signal corresponding to the first data on a stream lane identifying a type of the first data, identifying a first instance of an error detection code of a particular type in the first data, receiving second data on at least a portion of the plurality of data lanes, receiving a stream signal corresponding to the second data on the stream lane identifying a type of the second data, and identifying a second instance of the error detection code of the particular type in the second data. The power path is another one of the paths of the physical connection, and in some cases, the type of the second data is different from the type of the first data.In one example, the error detection code of the particular type is a cyclic redundancy check (CRC) code.In an example, the CRC code in the first data and the CRC code in the first data are based on a common CRC polynomial.In one example, the error detection code is transmitted on one or more particular lanes of the multiple lanes in the first data, and the error detection code is transmitted on one or more other lanes of the multiple lanes in the second data.In one example, fewer of the multiple lanes are used to send the second data than for the first data.In one example, lane error detection logic is provided (in hardware circuitry and / or software) to determine from a syndrome associated with the error detection code corresponding to the first data that a bit error is present in the first data, to determine from the syndrome in which bit of the first data the error occurred, and to assign the bit with errors to a particular one of the plurality of lanes.In one example, the bit error is associated with the particular path.In one example, the syndrome is generated from the error detection code corresponding to the first data.In one example, assigning the errored bit to a particular one of the plurality of lanes is based on the type of the first data.In one example, a particular one of the plurality of lanes is identified as marginal, and at least one of the plurality of lanes is unused. The connection may be reconfigured to interrupt forwarding of data on the particular lane and replace the particular lane with the at least one unused lane.In one example, reconfiguring the connection includes redirecting a group of lanes in the plurality of lanes to shift each lane in the group to an adjacent lane away from the particular lane and toward the at least one unused lane.In one example, each data type corresponds to a respective one of a plurality of different communication protocols.In one example, the physical layer logic is to receive a valid signal associated with at least the first data to indicate that the first data is valid.In one example, the physical layer logic is further to define a data window for data to be transmitted on the data lanes, and the data window corresponds to the valid signal.One or more embodiments may provide an apparatus, system, machine readable storage, machine readable medium, and / or method for determining a first error correction code for first data to be transmitted on multiple data lanes of a physical connection, transmitting the first data with the first error correction code on the multiple data lanes, determining a second error correction code for the second data to be transmitted on at least a portion of the data lanes of the physical connection, and transmitting the second data with the second error correction code on at least the portion of the data lanes. The first and second data may have different types or different protocols. The first error correction code and the second error correction code may each be instances of a same type of error correction code.In one example, the error correction code type includes a cyclic redundancy check (CRC) code, and the first error correction code and the second error correction code are each instances of a CRC generated by a particular CRC polynomial.In an example where the particular CRC polynomial is configured to enable generation of syndromes from CRC codes calculated according to the particular CRC polynomial, and the syndromes each correspond to a respective bit error on a specific associated bit in a flit.One or more embodiments may provide an apparatus, a system, a machine readable memory, a machine readable medium, and / or a method for identifying that a particular one of a plurality of lanes of a connection is marginal, where at least one of the plurality of lanes is unused. The link is then reconfigured to interrupt forwarding of data on the particular lane and replace the particular lane with the at least one unused lane, wherein reconfiguring the link comprises redirecting data of each lane in a subset of the plurality of lanes to an adjacent lane in the plurality of lanes.In one example, the particular lane is identified as marginal based on an assignment of a bit error to the particular lane, and the bit error is detected from a syndrome value generated by an error code included in the data transmitted over the link.In one example, the particular lane is identified as marginal based on a threshold amount of detected bit errors being associated with the particular lane.In one example, multiple flits from multiple different protocols are to be sent using the connection.One or more embodiments may provide a system comprising a link including a plurality of lanes, the plurality of lanes including a plurality of specific data lanes, at least one specific valid signal lane, and at least one stream signal lane, the stream lane identifying which of a plurality of different protocols is to be sent in an associated flit using the data lanes. The system may further include: a first device for transmitting data over the data lanes, the data including a cyclic redundancy check (CRC), and a second device communicatively coupled to the first device using the connection, the second device to receive data and determine an error affecting a particular one of the plurality of data lanes based on the CRC.In one example, the system further comprises a lane error controller to identify that a particular one of the plurality of data lanes is marginal, wherein at least one of the plurality of data lanes is unused, and redirect the data lanes to interrupt use of the particular lane and replace the particular lane with the at least one unused lane, wherein redirecting the data lanes comprises redirecting data of each lane in a subset of the plurality of data lanes to an adjacent lane in the plurality of lanes.Throughout this specification, reference to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Therefore, the phrase "in one embodiment" in various places throughout this specification does not necessarily always refer to the same embodiment. Further, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.In the foregoing specification, a detailed description has been given with reference to specific exemplary embodiments. It is, however, to be understood that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, not to be taken in a limiting sense. Further, the foregoing use of embodiment and example language does not necessarily refer to the same embodiment or example, but may refer to different and different embodiments, as well as potentially to the same embodiment.

Claims

An apparatus comprising: physical layer logic to: receive first data on a plurality of data lanes of a physical connection; receive a stream signal corresponding to the first data on a stream lane, wherein the stream lane is another one of the lanes of the physical connection, and wherein the stream signal corresponding to the first data is to identify a type of the first data; identify a first instance of an error detection code of a particular type in the first data; receive second data on at least a portion of the plurality of data lanes; receive a stream signal corresponding to the second data on the stream lane, wherein the stream signal corresponding to the second data is to identify a type of the second data, wherein the type of the second data is different than the type of the first data; identifying a second instance of the error detection code of the particular type in the second data, and lane error detection logic to: determine from a syndrome associated with the error detection code corresponding to the first data that a bit error is present in the first data; determine from the syndrome in which bit of the first data the error has occurred; and associate the bit with error with a particular one of the plurality of lanes.The apparatus of claim 1, wherein the error detection code of the particular type comprises a cyclic redundancy check (CRC) code.The apparatus of claim 2, wherein the CRC code in the first data and the CRC code in the second data are based on a common CRC polynomial.The apparatus of claim 1, wherein the error detection code is transmitted on one or more particular lanes of the plurality of lanes in the first data and the error detection code is transmitted on one or more other lanes of the plurality of lanes in the second data.The apparatus of claim 4, wherein fewer of the plurality of lanes are used to transmit the second data than for the first data.The apparatus of claim 1, wherein the bit error is to be associated with the particular path.The apparatus of claim 1, wherein the syndrome is generated from the error detection code corresponding to the first data.The apparatus of claim 1, wherein assigning the errored bit to a particular one of the plurality of lanes is based on the type of the first data.The apparatus of claim 1, wherein the physical layer logic is further to: identify that a particular one of the plurality of lanes is marginal, wherein at least one of the plurality of lanes is unused; and reconfigure the connection to interrupt forwarding of data on the particular lane and replace the particular lane with the at least one unused lane.The apparatus of claim 9, wherein reconfiguring the connection comprises redirecting a group of lanes in the plurality of lanes to shift each lane in the group to an adjacent lane away from the particular lane and toward the at least one unused lane.The apparatus of claim 1, wherein each data type corresponds to a respective one of a plurality of different communication protocols.The apparatus of claim 1, wherein the physical layer logic is further to receive a valid signal associated with at least the first data to indicate that the first data is valid.The apparatus of claim 12, wherein the physical layer logic is further to define a data window for data to be transmitted on the data lanes, and the data window corresponds to the valid signal.An apparatus comprising: error detection logic to: identify that a particular one of a plurality of lanes of a link is marginal, wherein at least one of the plurality of lanes is unused; and reconfigure the link to interrupt forwarding of data on the particular lane and replace the particular lane with the at least one unused lane, wherein reconfiguring the link comprises redirecting data of each lane in a subset of the plurality of lanes to a neighboring lane in the plurality of lanes, wherein the particular lane is identified as marginal based on an assignment of a bit error to the particular lane, and wherein the bit error is detected from a syndrome value generated by an error code included in data transmitted over the link.The apparatus of claim 14, wherein the particular lane is identified as marginal based on a threshold amount of detected bit errors being associated with the particular lane.The apparatus of claim 14, wherein multiple flits from multiple different protocols are to be sent using the connection.A method comprising: receiving first data on a plurality of data lanes of a physical connection; receiving a stream signal corresponding to the first data on a stream lane, wherein the stream lane is another one of the lanes of the physical connection, and wherein the stream signal corresponding to the first data is to identify a type of the first data; identifying a first instance of an error detection code of a particular type in the first data; receiving second data on at least a portion of the plurality of data lanes; receiving a stream signal corresponding to the second data on the stream lane, wherein the stream signal corresponding to the second data is to identify a type of the second data, wherein the type of the second data is different than the type of the first data; and identifying a second instance of the error detection code of the particular type in the second data, the method further comprising: determining from a syndrome associated with the error detection code corresponding to the first data that a bit error is present in the first data; determining from the syndrome in which bit of the first data the error occurred; and assigning the bit with error to a particular one of the plurality of lanes.A system comprising means for performing the method of claim 17.A method comprising: identifying that a particular one of a plurality of lanes of a link is marginal, wherein at least one of the plurality of lanes is unused; and reconfiguring the link to interrupt forwarding of data on the particular lane and replace the particular lane with the at least one unused lane, wherein reconfiguring the link comprises redirecting data of each lane in a subset of the plurality of lanes to a neighboring lane in the plurality of lanes, wherein the particular lane is identified as marginal based on an assignment of a bit error to the particular lane, and wherein the bit error is detected from a syndrome value generated by an error code included in data transmitted over the link.A system comprising means for performing the method of claim 19.

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