Microelectronic devices with efficient partitioning of high-frequency communication devices integrated on a housing fabric

Abstract

Microelectronic device (100, 200), comprising: a transceiver (122, 222) coupled to a first substrate (120, 220); an interposer substrate (130, 230); a second substrate (150, 250) coupled to the first substrate (120, 220) via the interposer substrate (130, 230), the interposer substrate (130, 230) providing electrical connections between components of the first substrate (120, 220) and components of the second substrate (150, 250), the second substrate (150, 250) comprising an antenna unit (152, 252) for transmitting and receiving communications at a frequency of approximately 4 GHz or higher; and at least one high-frequency circuit (124) formed with materials of group III-V, coupled to at least one of the first (120, 220) and second substrates (150, 250).

Description

AREA OF INVENTION

[0001] Embodiments of the present invention generally relate to the fabrication of semiconductor devices. In particular, embodiments of the present invention relate to efficient partitioning of microelectronic devices with high-frequency communication devices integrated on a housing fabric. BACKGROUND OF THE INVENTION

[0002] Future wireless products target operating frequencies much higher than the currently used lower GHz range. For example, 5G (5th generation mobile networks or 5th generation wireless systems) communication is expected to operate at a frequency of 15 GHz or higher. Furthermore, current WiGig (Wireless Gigabit Alliance) products operate at 60 GHz. Other applications, including automotive radar and medical imaging, use wireless communication technologies in millimeter-wave frequencies (e.g., 30 GHz to 300 GHz). For these wireless applications, the RF (radio frequency) circuitry being designed requires high-quality passive networks to accommodate the transmission of predefined frequency bands (where communication takes place), as well as the need for highly efficient power amplifiers and low-loss power combiners / switches.

[0003] Publication DE 60 2004 001 358 T2 refers to a module for an electronic component, and in particular to a module for an electronic component on which electronic components are operated in several frequency bands.

[0004] Publication US 2014 / 0 210 082 A1 refers to a semiconductor component with a first circuit board that is electrically connected to a second circuit board via an antenna.

[0005] Publication WO 2015 / 088 486 A1 refers to a chip package with a ceramic substrate located over a die and connected to an antenna.

[0006] Publication US 2012 / 0119932A1 proposes an integrated antenna housing architecture for radar modules.

[0007] Publication US 2014 / 0266 902 A1 refers to a common array module that includes antennas from two arrays on a substrate surface. SUMMARY

[0008] Examples refer to microelectronic devices. The microelectronic device comprises a transceiver coupled to a first substrate, an interposer substrate, and a second substrate coupled to the first substrate via the interposer substrate. The interposer substrate provides electrical connections between components of the first substrate and components of the second substrate. The second substrate comprises an antenna assembly for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. Furthermore, the microelectronic device comprises at least one high-frequency circuit formed with materials of Group III-V, coupled to at least one of the first and second substrates.

[0009] Another example relates to a microelectronic device comprising a first die coupled to a first side of a first substrate. The microelectronic device further comprises an interposer substrate and a second substrate coupled to a second side of the first substrate via the interposer substrate. The interposer substrate provides electrical connections between components of the first substrate and components of the second substrate. The second substrate includes an antenna assembly for transmitting and receiving communications at a frequency of approximately 15 GHz or higher. The microelectronic device includes an overmolded component coupled to the second side of the first substrate. The overmolded component includes an integrated passive die (IPD) coupled to the first substrate. The IPD includes passive elements for passive matching networks.The overmolded component comprises at least one die formed with materials of group III-V coupled to the first substrate.

[0010] Another example relates to a computing device comprising at least one processor for processing data. The computing device further comprises a communication module or chip coupled to the at least one processor. The communication module or chip comprises a first substrate supporting a first die, a second die coupled to the first die, an interposer substrate, and a second substrate coupled to the first substrate via the interposer substrate. The interposer substrate provides electrical connections between components of the first substrate and components of the second substrate. The second die has devices formed with compound semiconductor materials. The second substrate has an antenna assembly for transmitting and receiving communications at a frequency of approximately 15 GHz or higher. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates the joint integration of various components in a partitioned microelectronic device (e.g., a housing fabric architecture) according to one embodiment. Fig. Figure 2 illustrates the joint integration of various components in a partitioned microelectronic device (e.g., a housing fabric architecture) according to another embodiment. Fig. Figure 3 illustrates the joint integration of various components in a microelectronic device (e.g., a housing-fabric architecture) according to another embodiment. Fig. Figure 4 illustrates a top view of an interposer substrate (e.g., interposer substrate 340, interposer substrate 440) and a formed component (e.g., formed component 330, formed component 430) according to one embodiment. Fig. Figure 5 illustrates the joint integration of various components in a transformer within a microelectronic device (e.g., a housing fabric architecture) according to one embodiment. Fig. Figure 6 illustrates an expanded view of partitioned transformers according to one embodiment. Fig. Figure 7 illustrates a microelectronic device 700 with partitioned transformers according to one embodiment. Fig. Figure 8 illustrates a transformer with a plurality of loops according to one embodiment. Fig. Figure 9 illustrates a computing device 900 according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] This document describes microelectronic devices designed with efficient partitioning of high-frequency communication devices within a housing fabric. The following description details various aspects of the illustrative implementations using terms commonly employed by those skilled in the art to communicate the content of their work to others skilled in the art. However, it will be obvious to those skilled in the art that embodiments of the present invention can be implemented in practice with only some of the described aspects. For illustrative purposes, specific figures, materials, and configurations are provided to facilitate a thorough understanding of the illustrative implementations. However, it will be obvious to those skilled in the art that embodiments of the present invention can be implemented in practice without these specific details.In other cases, well-known features are omitted or simplified so as not to obscure the illustrative implementations.

[0012] Various processes are described as several discrete operations in a manner most helpful for understanding embodiments of the present invention; however, the order of the description should not be interpreted as implying that these operations are necessarily dependent on the order in which they are presented. In particular, these operations need not be performed in the order in which they are presented.

[0013] For wireless high-frequency applications (e.g., 5G, WiGig) of millimeter-wave communication systems (e.g., 1-10 mm, arbitrary mm waves), the designed RF circuits (e.g., low-noise amplifiers, mixers, power amplifiers, etc.) require high-quality passive matching networks to accommodate the transmission of predefined frequency bands where communication takes place, as well as the need for highly efficient power amplifiers and low-loss power combiners / switches, etc. While CMOS technology can be used for operation above 15 GHz, it suffers from reduced power amplifier efficiencies and inferior passive components, primarily due to the typically lossy silicon substrate. This results not only in lower system performance but also in increased thermal requirements due to the excess heat generated.In one example, the high heat dissipation is due to the fact that multiple power amplifiers must be used in a phased array arrangement to achieve the desired output power and transmission range. This will be even more critical for 5G systems, as the typical transmission range for a mobile network (e.g., 4G, LTE, LTE-Adv) is several times greater than that required for connectivity (e.g., WiFi, WiGig).

[0014] The present design efficiently partitions high-frequency components (e.g., 5G transceivers) and utilizes non-CMOS technologies (e.g., non-silicon substrates) for critical parts of a communication system (e.g., GaAs, GaN, passives-on-glass, etc.). With optimal system partitioning, critical parts requiring high efficiency and quality factors can be fabricated using a different technology (e.g., compound semiconductor materials, Group III-V materials). These parts can be located at either the device level (e.g., transistors on GaN / GaAs) or the circuit level (e.g., a Group III-V die integrating a power amplifier, a low-noise amplifier, etc.). The complete communication system is formed using a package-fabric approach, as described in embodiments of this invention.

[0015] The present design technology enables the integration of dies and / or devices manufactured on different technologies and / or substrates onto the same package to improve performance and reduce thermal requirements. The package can incorporate antenna units for communication with other wireless systems.

[0016] In one embodiment, the present design is a 5G (5th generation mobile network or 5th generation wireless system) architecture with non-CMOS-based transceiver components (such as Group III-V based devices or matrices) mounted on the same package with low-frequency circuitry and integrated passive devices (IPDs) to improve performance and reduce thermal requirements. In this arrangement, each component is directly assembled within the package. The package may have antennas integrated directly onto it. The 5G architecture operates at a high frequency (e.g., at least 20 GHz, at least 25 GHz, at least 28 GHz, at least 30 GHz, etc.) and can also provide endpoint connections of approximately 1-50 gigabits per second (Gbps). In another example, the present design operates at lower frequencies (e.g., at least 4 GHz, approximately 4 GHz).

[0017] In one example, the present design architecture features a 5G transceiver system-on-chip partitioning scheme with state matching between partitioned circuits. This enables system cost reduction, flexibility for performance optimization, and allows a design to be adapted to different types of products or design requirements (e.g., power levels). The partitioning facilitates the easy integration of components with antenna units.

[0018] This 5G architecture design provides optimized performance for RF receivers based on the use of compound semiconductor materials for certain components (e.g., switches, power amplifiers, mixers) and integrated passive devices or dies (IPDs) for higher-quality passive elements. The design also results in reduced costs, as it features a primary substrate designed for antenna or antenna components and a secondary substrate designed for higher-frequency components. For example, functional testing of receiver components, which can utilize in-mold circuitry, is decoupled from the need to first assemble them on the package. Furthermore, a 5G wireless module, including an RFIC with or without an integrated antenna, can be designed and marketed as a separate module.Functional blocks such as impedance matching circuits, harmonic filters, couplers, power combiners / dividers, etc., can be implemented using IPDs. IPDs are generally fabricated using wafer fab technologies (e.g., thin-film deposition, etching, photolithography).

[0019] Through efficient partitioning of the 5G transceiver, this architecture can reduce power consumption, lower thermal requirements, and achieve higher power amplifier efficiencies (e.g., using Group III-V technologies) with improved passive elements (e.g., using IPDs and more efficient power combiners or switches) due to the fabrication of passive elements on a non-CMOS substrate. The present architecture offers the possibility of integrating all these various discrete components, along with the antenna, onto a single package to create a complete 5G transceiver. These components can reside either at the device level (e.g., discrete transistors) or at the circuit level (e.g., a power amplifier, a low-noise amplifier).

[0020] Fig. Figure 1 illustrates the integration of various components in a partitioned microelectronic device (e.g., a package-fabric architecture) according to one embodiment. The partitioned microelectronic device 100 (e.g., a package-fabric architecture 100) comprises a printed circuit board (PCB) 110, a substrate 120, and an antenna substrate 150 with an antenna unit 152. The substrate 120 comprises a transceiver 122 and a component 124 (e.g., integrated passive devices or dies (IPDs), a combiner, a switch, a power amplifier, individual devices (e.g., transistors), any type of device or circuit formed in compound semiconductor materials, etc.). An interposer substrate 130 with a certain height (e.g. 50 to 500 micrometers) provides a distance 132 between the substrate 120 and the antenna substrate 150.The interposer substrate provides electrical connections between components of the antenna substrate and components of the substrate 120. The interposer substrate 120 can also embed potential passive elements for the transceiver 122 (or other structures, e.g., for shielding). In one example, the interposer can be formed with vias or pins. The antenna substrate can have different thickness, length, and width dimensions compared to the thickness, length, and width dimensions of the substrate 120.

[0021] In one example, antenna substrate components that primarily dominate a package area are partitioned in a separate, more cost-effective substrate 150 with a lower circuit density compared to substrate 120, which can include a high-density interconnect (HDI) and an impedance-controlled interconnect. An antenna substrate can be formed with fired low-temperature ceramic materials (LTCC), liquid crystal polymers, organic materials, glass, undoped silicon, etc. HDI PCB technologies can include blind and / or buried via processes and potentially microvias with a higher circuit density than conventional PCBs. In this way, an area of ​​substrate 120 without antenna components is reduced to lower costs compared to a planar structure that includes antenna components. The substrate 120 can be made of any materials (e.g.,organic materials, laminate substrates, materials for forming CPUs, etc.) are designed for high-frequency designs with desirable high-frequency characteristics (e.g., substrate loss, dielectric constant). The transceiver 122 can comprise a complementary metal-oxide-semiconductor (CMOS) circuit (e.g., a CMOS circuit with at least one baseband unit and at least one transceiver unit formed with a silicon-based substrate, CMOS die) or devices formed with compound semiconductor materials (e.g., Group III-V materials, gallium arsenide (GaAs), gallium nitride (GaN), compound semiconductor dies, etc.). The transceiver 122 can include one transceiver unit, while a separate die mounted on the substrate 120 comprises at least one baseband unit. The antenna unit 152 has one or more conductive layers.The solder balls or beads 142 couple the antenna substrate 150 to the interposer substrate 130, and the solder balls or beads 144 couple the interposer substrate to the substrate 120, while the solder balls or beads 112 couple the PCB 110 to the substrate 120. In some embodiments, connectors or pins may be used to electrically connect the lower substrate 120 to the PCB. Similarly, metal-to-metal beads may be used instead of solder balls 142. In some embodiments, other discrete components or dies may be attached to the back of the substrate 120. These components would lie in the same plane as the solder balls. Fig. 1 are shown.

[0022] The interposer substrate 130 can be replaced by metal columns or beads with or without cavities if a smaller distance (e.g. less than 100 micrometers) is required between the antenna substrate 150 and the substrate 120.

[0023] Additional components, such as conventional surface-mounted passive elements, can also be mounted on the substrate 120. Furthermore, the substrate 120 can be made of... Fig. 1. It must be molded and covered with an outer shield. The molding material can be a low-loss, non-conductive dielectric material, and the shield can be made of a conductive material.

[0024] In another embodiment, each of the devices or components can be coupled to one another. For example, component 124 can be coupled to at least one of the substrates 150, 130 and 120.

[0025] Fig. Figure 2 illustrates the integration of various components in a partitioned microelectronic device (e.g., a package-fabric architecture) according to another embodiment. The partitioned microelectronic device 200 (e.g., a package-fabric architecture 200) comprises a printed circuit board (PCB) 210, a substrate 220, and an antenna substrate 250 with an antenna unit 252. The substrate 220 includes a transceiver 222, a baseband unit 226, and optionally IPDs. An interposer substrate 230 of a specific height provides a distance 232 between the substrate 220 and the antenna substrate 250. The interposer substrate provides electrical connections between components of the antenna substrate and components of the substrate 220.

[0026] The interposer substrate 220 can also embed potential passive elements for the transceiver 222 (or other structures, e.g., for shielding). In one example, the interposer can be formed with vias or pins. The antenna substrate 250 can have a different thickness, length, and width dimensions compared to the thickness, length, and width dimensions of the substrate 220. The antenna substrate 250 includes a component 254 (e.g., switches, circuits formed in compound semiconductor materials, any type of device or circuit, etc.) and a component 256 (e.g., filters, combiners, etc.). These components can also be formed on or attached to a lower surface of the antenna substrate 250.

[0027] In one example, antenna substrate components that primarily dominate a housing area are partitioned in a separate, more cost-effective substrate 250 with a lower circuit density compared to substrate 220, which can feature a high-density interconnect (HDI) and an impedance-controlled interconnect. An antenna substrate can be formed from low-temperature ceramic materials, liquid crystal polymers, organic materials, glass, etc. Substrate 220 can be formed from any materials (e.g., organic materials, laminate substrates, materials for forming CPUs, etc.) designed for high-frequency designs with desired high-frequency characteristics (e.g., substrate loss, dielectric constant). A portion of substrate 220 is reduced to eliminate antenna components, thus lowering costs compared to a planar structure that includes antenna components.

[0028] The transceiver 222 can comprise a complementary metal oxide semiconductor (CMOS) circuit (e.g., a CMOS circuit with at least one baseband unit and at least one CMOS circuit formed with a silicon-based substrate, CMOS die) or devices formed with compound semiconductor materials (e.g., materials of group III-V, gallium arsenide (GaAs), gallium nitride (GaN), compound semiconductor dies, etc.). The antenna unit 252 comprises at least one antenna and one or more conductive layers. The solder balls or beads 242 couple the antenna substrate 250 to the interposer substrate 230, while the solder balls or beads 212 couple the PCB 210 to the substrate 220. The interposer substrate 230 can be replaced by metal columns or beads with or without cavities if a smaller distance (e.g. less than 100 micrometers) is required between the antenna substrate 250 and the substrate 220.

[0029] Fig. Figure 3 illustrates the integration of various components in a microelectronic device (e.g., a package-fabric architecture) according to another embodiment. The microelectronic device 300 (e.g., a package-fabric architecture 300) comprises a CMOS circuit of a die 310 (e.g., a CMOS circuit with at least one baseband unit and at least one transceiver unit formed with a silicon-based substrate, CMOS die), a circuit of a die 332 with devices formed with compound semiconductor materials (e.g., Group III-V materials, gallium arsenide (GaAs), or organic materials, gallium nitride (GaN), compound semiconductor dies, etc.), a circuit or devices of a die 336 formed with compound semiconductor materials (e.g., Group III-V materials, gallium arsenide (GaAs), gallium nitride (GaN), compound semiconductor dies, etc.).The IPD 330 and the antenna unit 350, which includes at least one antenna for transmitting and receiving high-frequency communications (e.g., 5G, WiGig, at least 4 GHz, at least 25 GHz, at least 28 GHz, at least 30 GHz), are formed from or organic materials. The antenna unit 350 has conductive layers 351 to 353. In this example, the vias 326 and 327 and the conductive layers 324 and 328 couple the circuit 332 of a compound semiconductor die to the CMOS circuit of the die 310 for electrical connections between these components. The substrates 320 and 350 have a plurality of dielectric layers 361 and 360, respectively, for isolation between conductive layers and components.

[0030] The compound semiconductor dies 332 and 336 (with circuitry or devices) and the IPD 334 are formed together in a separate overmolded component 330 (or overmolded module). If the overall height of the overmolded component 330 is greater than a certain height (e.g., greater than 100 micrometers), then an interposer substrate 340 or columns are required for assembling the antenna substrate above the interposer substrate 340. If the overall height of the overmolded component 330 is less than a certain height (e.g., 100 micrometers), solder beads can be used instead of the interposer substrate. In one example, the interposer substrate 340 has a useful function in providing shielding for the RF dies of the overmolded component 330. Peripheral rows of the shield 342 are inserted using grounded deep vias, as shown in Fig. 3 and Fig. 4 shown.

[0031] Fig. Figure 4 illustrates a top view of an interposer substrate (e.g., interposer substrate 340, interposer substrate 440) and an overmolded component (e.g., overmolded component 330, overmolded component 430) according to one embodiment. This shield 442, in combination with a lower ground plane (e.g., conductive layer 353) of the antenna substrate 350, can form an effective Faraday shield for RF dies. The interposer 440 and the shield 442 surround an overmolded component 430, which comprises compound semiconductor dies 432 and 436 (or circuits of these dies) and IPD 434. Matching networks formed from passive components, decoupling capacitors, power output networks, detection circuits or switches may also be integrated into (or embedded in) the overmolded component or on the substrate 320.

[0032] An in-mold circuit reduces costs because the circuitry can be tested separately from the rest of the substrate before assembly. The present design creates an independent 5G module that can be manufactured and sold separately.

[0033] In one embodiment, the CMOS die 310 is mounted on one side of the microelectronic device (e.g., a package-fabric architecture) via flip-chip assembly. In one example, the CMOS die 310 has a thickness of approximately 25–75 µm (e.g., approximately 50 µm) on a first side (e.g., bottom surface) of the microelectronic device, while high-performance, high-efficiency dies 332 and 336 of Group III–V are located on a second side (e.g., top surface) of the microelectronic device (e.g., a package-fabric architecture) embedded in the overmolded component 330. In one example, compound semiconductor materials (e.g., GaN, GaAs, etc.) exhibit significantly higher electron mobility compared to silicon materials, enabling faster operation.Compound semiconductor materials also have a wider bandgap, which allows power devices to operate at higher temperatures and results in lower thermal noise in low-power devices at room temperature compared to silicon materials. Compound semiconductor materials also exhibit a direct bandgap, which provides more favorable optoelectronic properties than an indirect bandgap from silicon. Passive elements required for passive matching networks are integrated into the IPD 334, or passive power combiners or splitters can be assembled on the microelectronic device (e.g., a package-fabric architecture). The components may be drawn approximately to scale, depending on the specific architecture, or they may not necessarily be drawn to scale.In one example, an antenna substrate 350 for a frequency of approximately 30 GHz has dimensions of approximately 2.5 mm by 2.5 mm.

[0034] In one example, high-frequency transceivers (e.g., 5G transceivers) use multiple transformers between two circuit components. In a partitioned system, one circuit component might be located on a different substrate than the other. By optimizing the connection between the two components, the present design can also partition the transformer. This means that the primary and secondary windings of the transformer (XFM) are located on at least two different substrates, enabling inductive coupling between the components without the need for a wired connection.

[0035] Fig. Figure 5 illustrates the joint integration of various components in a transformer within a microelectronic device (e.g., a housing fabric architecture) according to one embodiment. The microelectronic device 500 (e.g., a package-fabric architecture 500) comprises a CMOS circuit of a die 510 (e.g., a CMOS circuit with at least one baseband unit and at least one transceiver unit formed with a silicon-based substrate, CMOS die), a circuit or devices (e.g., individual transistors) of a die 532 formed with compound semiconductor materials (e.g., group III-V materials, gallium arsenide (GaAs), gallium nitride (GaN), compound semiconductor die, etc.), a circuit or devices of a die 536 formed with compound semiconductor materials (e.g., group III-V materials, gallium arsenide (GaAs), gallium nitride (GaN), compound semiconductor die, etc.).The IPD 534 and an antenna substrate 550 with an antenna unit 554, comprising at least one antenna for transmitting and receiving high-frequency communications (e.g., 5G, WiGig, at least 4 GHz, at least 25 GHz, at least 28 GHz, at least 30 GHz), are formed from a substrate or organic materials. The antenna unit 550 has conductive layers 551 to 553. In this example, vias 514 and 515 couple the antenna unit 554 to the CMOS circuit 510 for electrical connections between these components. The substrates 520, 522, and 550 have multiple dielectric layers 560 and 562, respectively, for insulation between conductive layers and components. The circuits or devices of the dies 532 and 536 and IPD 534 are directly coupled to the CMOS die 510 or coupled to a routing redistribution layer (RDL) 512.

[0036] In one example, a transformer is partitioned between the die 532 or die 536 and the CMOS die 510 with or without the routing layer 512. Fig. Figure 6 illustrates a disassembled view of partitioned transformers according to one embodiment. A CMOS circuit of a die 610 (e.g., CMOS circuit with a silicon-based substrate, CMOS die, die 510) includes a circuit or devices of a die 632 formed with compound semiconductor materials (e.g., Group III-V materials, gallium arsenide (GaAs), gallium nitride (GaN), compound semiconductor die, die 532, etc.) or organic materials), and a circuit or devices of a die 636 formed with compound semiconductor materials (e.g., Group III-V materials, gallium arsenide (GaAs)), gallium nitride (GaN), compound semiconductor die, die 536, etc.) or organic materials. In one example, the die 632 is coupled to the CMOS die 610 via a routing redistribution layer (RDL) 612. A transformer 622 has a loop 621 and a loop 620.Loop 621 is located on a lower region or surface of die 632, while loop 620 is located within the routing layer 612 near an upper surface of die 610. Loops 621 and 620 are separated by a small air gap or a thin dielectric layer to allow inductive coupling between these loops without requiring a wired electrical connection.

[0037] In another example, a transformer 642 has a loop 641 and a loop 640. Loop 641 is located on a lower region or surface of the die 636, while loop 640 is located near an upper surface of the die 610 or is embedded within the die. Loops 641 and 640 are separated by a small air gap or a thin dielectric layer to allow inductive coupling between these loops without requiring a wired electrical connection.

[0038] In another example, a first loop of a transformer can be implemented directly on a housing substrate and inductively coupled to a second loop of the transformer, which is integrated with an integrated circuit above the first loop.

[0039] Fig. Figure 7 illustrates a microelectronic device 700 with partitioned transformers according to one embodiment. The microelectronic device 700 (e.g., a housing-fabric architecture 700) comprises a printed circuit board (PCB) 710 and a substrate 714, which includes a transceiver 722 and a component 724 (e.g., integrated passive devices or dies (IPDs), a combiner, a switch, a power amplifier formed in compound semiconductor materials, etc.). The component 724 is coupled to the substrate 714. A transformer 730 has a loop 721 and a loop 720. The loop 721 is located on a lower region or surface of the component or die 724, while the loop 720 is arranged or embedded within an upper surface of the die 714.Loops 721 and 720 are separated by a small air gap or a thin dielectric layer to allow inductive coupling between them without requiring a wired electrical connection. In one example, the loops are separated by a distance of hundreds of nanometers to a few tens of micrometers. A larger distance reduces the inductive coupling between the loops.

[0040] Fig. Figure 8 illustrates a transformer with a plurality of loops according to one embodiment. A transformer is an electrical device that transfers electrical energy between two or more circuits by electromagnetic induction. A first loop 810 can be formed on a housing or a die. The first loop 810 (e.g., lower loop) is shown with three loops, but need not necessarily have a plurality of loops. A second loop 820 (e.g., upper loop) can be formed on a housing or a die. The loop 820 (e.g., lower loop) is shown with a single loop, but need not necessarily be a single loop. Rather, the loop 820 can have a plurality of loops. An area (e.g.,The area on a casing or die consumed by a transformer, the spacing between loops, the number of lower loops compared to the number of upper loops, and the loop thicknesses are design parameters that depend on an operating frequency, a coupling coefficient between the loops, and design rules imposed by a manufacturing technology. The loops can be formed in any configuration (e.g., horizontally, vertically, etc.) on a casing or die.

[0041] It is appreciated that in one embodiment of a system-on-a-chip, the die can contain a processor, memory, communication circuitry, and the like. Although depicted as a single die, there can be zero, one, or multiple dies contained in the same region of the wafer.

[0042] In one embodiment, the microelectronic device may be a crystalline substrate formed using a solid silicon or silicon-on-insulator substructure. In other implementations, the microelectronic device may be formed using alternative materials, which may or may not be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of materials of Groups III-V or IV. Although some examples of materials from which the substrate may be formed are described here, any material that can serve as a basis on which a semiconductor device may be built falls within the scope of protection of embodiments of the present invention.

[0043] Fig.Figure 9 illustrates a computing device 900 according to an embodiment of the invention. The computing device 900 accommodates a circuit board 902. The circuit board 902 can comprise a number of components, including, but not limited to, a processor 904 and at least one communication chip 906. The at least one processor 904 is physically and electrically coupled to the circuit board 902. In some implementations, the at least one communication chip 906 is physically and electrically coupled to the circuit board 902. In other implementations, the communication chip 906 is part of the processor 904. In one example, the communication chip 906 (e.g., microelectronic device 100, 200, 300, 400, 500, etc.) comprises an antenna unit 920 (e.g., antenna unit 152, 252, 352, 554, etc.).

[0044] Depending on its applications, the computing device 900 may include other components, which may or may not be physically and electrically coupled to the circuit board 902. These other components include, but are not limited to, volatile memory (e.g., DRAM 910, 911), non-volatile memory (e.g., ROM 912), flash memory, a graphics processor 916, a digital signal processor, a cryptoprocessor, a chipset 914, an antenna assembly 920, a display, a touchscreen display 930, a touchscreen control 922, a battery 932, an audio codec, a video codec, a power amplifier 915, a GPS (Global Positioning System) device 926, a compass 924, a gyroscope, a loudspeaker, a camera 950, and a mass storage device (such as a hard disk drive, a compact disc (CD), a digital versatile disc (DVD), and so on).

[0045] The 906 communication chip enables wireless communication for the transmission of data to and from the 900 computing device. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data through a non-solid medium by using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain wires, although this may be the case in some embodiments. The 906 communication chip can implement any number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), WiGig, and IEEE 802.20, Long Term Evolution (LTE) Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G and above. The Computing Device 900 can incorporate a plurality of Communication Chips 906. For example, a first Communication Chip 906 can be designated for shorter-range wireless communication such as Wi-Fi, WiGig, and Bluetooth, and a second Communication Chip 906 can be designated for longer-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, 5G, and others.

[0046] The at least one processor 904 of the computing device 900 comprises an integrated circuit die that is housed within the at least one processor 904. In some implementations of the invention, the integrated circuit die of the processor comprises one or more devices such as microelectronic devices (e.g., microelectronic device 100, 200, 300, 400, 500, etc.) in accordance with implementations of the invention. The term "processor" can refer to any device or section of a device that processes electronic data from registers and / or memory in order to convert this electronic data into other electronic data that may be stored in registers and / or memory.

[0047] The communication chip 906 also includes an integrated circuit die that is housed within the communication chip 906. According to another implementation of embodiments of the invention, the integrated circuit die of the communication chip includes one or more microelectronic devices (e.g., microelectronic device 100, 200, 300, 400, 500, etc.).

[0048] The following examples relate to further embodiments. Example 1 is a microelectronic device comprising a transceiver coupled to a first substrate and a second substrate coupled to the first substrate. The second substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher (e.g., at least 4 GHz, at least 15 GHz, at least 25 GHz). In one example, the transceiver comprises a transceiver unit and a baseband unit. In another example, the baseband unit is located on a separate substrate or die opposite the transceiver unit. In Example 2, the subject of Example 1 can optionally include an integrated passive die (IPD) coupled to at least one of the first and second substrates. The IPD has passive elements for passive matching networks. In Example 3, the subject of one of Examples 1 to 2 may optionally include that at least one high-frequency circuit (e.g., switch, low-noise amplifier, power amplifier, etc.) is formed with materials of Group III-V, which is coupled to at least one of the first and second substrates. In Example 4, the subject of one of Examples 1 to 3 can optionally include an interposer substrate that provides a distance between the first and the second substrate and electrically couples the first and the second substrate. In Example 5, the subject of Example 4 can optionally include the interposer substrate having a shield for shielding RF signals from the transmitter-receiver. In Example 6, the subject matter of one of Examples 1 to 5 may optionally include that the second substrate further comprises at least one switch formed in compound semiconductor materials and a component comprising filters or combiners formed with compound semiconductor materials. In Example 7, the subject of one of Examples 1 to 6 may optionally include the microelectronic device being a 5G package architecture for 5G communication. Example 8 is a microelectronic device comprising a first die coupled to a first substrate and a second substrate coupled to the first substrate. The second substrate includes an antenna assembly for transmitting and receiving communications at a frequency of approximately 15 GHz or higher (e.g., at least 15 GHz, at least 25 GHz). In Example 9, the subject matter of Example 8 can optionally include a microelectronic device with a molded component coupled to the second side of the first substrate. The molded component has an integrated passive die (IPD) coupled to the first substrate. The IPD includes passive elements for passive matching networks. In Example 10, the subject of one of Examples 8 to 9 may optionally include that the overmolded component has at least one die formed with materials of Group III-V and coupled to the second side of the first substrate. In Example 11, the subject matter of one of Examples 8 to 10 may optionally include the microelectronic device having an interposer substrate to provide a distance between the first and second substrates and to electrically couple the first and second substrates. In Example 12, the subject of Example 11 can optionally include the interposer substrate having a shield for shielding RF signals from devices of the overmolded component. In Example 13, the subject of one of Examples 8 to 12 may optionally include the first die having a complementary metal oxide semiconductor (CMOS) circuit formed with a silicon-based substrate. In Example 14, the subject of one of Examples 8 to 13 may optionally include the microelectronic device being a 5G package architecture for 5G communication. Example 15 is a computing device comprising at least one processor for processing data and a communication module or chip coupled to the at least one processor. The communication module or chip comprises a first substrate supporting a first die and a second die coupled to the first die. The second die may include devices formed with compound semiconductor materials. A second substrate is coupled to the first substrate. The second substrate includes an antenna assembly for transmitting and receiving communications at a frequency of approximately 15 GHz or higher. In Example 16, the subject of Example 15 can optionally include the fact that the computing device further comprises an integrated passive die (IPD) coupled to the first die. The IPD includes passive elements for passive matching networks. In Example 17, the subject of one of Examples 15 to 16 may optionally include the first die having a complementary metal oxide semiconductor (CMOS) baseband circuit. In Example 18, the subject matter of one of Examples 15 to 17 can optionally include the computing device further comprising a memory, a display module, and an input module. The memory, the display module, and the input module are located on a chip-chipset platform and are interconnected. Example 19 is a transformer comprising a first loop located on a first die or substrate and a second loop located on a second die or substrate. The first and second loops are inductively coupled. In another example, the first loop is located on a die and the second loop is located on a substrate, or vice versa. In Example 20, the subject of Example 19 can optionally include the second loop being formed in a routing layer that couples the first die or substrate to the second die or substrate. In Example 21, the subject of one of Examples 19 to 20 can optionally include the first loop being embedded in the first die or substrate and the second loop being arranged on the second die or substrate. In Example 22, the subject of one of Examples 19 to 21 can optionally include the second loop being embedded in the second die or substrate. In Example 23, the subject of one of Examples 19 to 22 may optionally include that the transformer further comprises an air gap or a dielectric material to separate the first loop from the second loop without a wiring connection between the first and the second loop.

Claims

[1] Microelectronic device (100, 200), comprising: a transceiver (122, 222) coupled to a first substrate (120, 220); an interposer substrate (130, 230); a second substrate (150, 250) coupled to the first substrate (120, 220) via the interposer substrate (130, 230), the interposer substrate (130, 230) providing electrical connections between components of the first substrate (120, 220) and components of the second substrate (150, 250), the second substrate (150, 250) comprising an antenna unit (152, 252) for transmitting and receiving communications at a frequency of approximately 4 GHz or higher; and at least one high-frequency circuit (124) formed with materials of group III-V, coupled to at least one of the first (120, 220) and second substrates (150, 250). [2] Microelectronic device (100, 200) according to claim 1, further comprising: an integrated passive die (IPD) (124) coupled to at least one of the first (120, 220) and second substrates (150, 250), wherein the IPD (124) has passive elements for passive matching networks. [3] Microelectronic device (100, 200) according to claim 1 or 2, wherein the interposer substrate (130, 230) comprises a shield for shielding RF signals from the transmit receiver (122, 222). [4] Microelectronic device (100, 200) according to claim 1, wherein the second substrate (150, 250) further comprises: at least one switch (124, 254) formed in compound semiconductor materials; and a component (124, 256) comprising filters or combining devices formed with compound semiconductor materials. [5] Microelectronic device (100, 200) according to claim 1, wherein the microelectronic device (100, 200) comprises a 5G housing architecture for 5G communications. [6] Microelectronic device (300), comprising: a first die (310) coupled to a first side of a first substrate (320); an interposer substrate (340); a second substrate (350) coupled to a second side of the first substrate (320) via the interposer substrate (340), wherein the interposer substrate (130, 230) provides electrical connections between components of the first substrate (120, 220) and components of the second substrate (150, 250), wherein the second substrate (350) has an antenna unit (354) for transmitting and receiving communications at a frequency of approximately 15 GHz or higher; and a formed component (330) coupled to the second side of the first substrate (320), wherein the formed component (330) has an integrated passive die (IPD) (334) coupled to the first substrate (320), the IPD (334) having passive elements for passive matching networks, wherein the formed component (330) comprises at least one die (332, 336) formed with materials of group III-V coupled to the first substrate (320). [7] Microelectronic device (300) according to claim 6, wherein the interposer substrate (340) comprises a shield for shielding RF signals of the superimposed component (330). [8] Microelectronic device (300) according to claim 6, wherein the first die (310) further comprises: a complementary metal oxide semiconductor (CMOS) circuit formed with a silicon-based substrate. [9] Microelectronic device (300) according to claim 6, wherein the microelectronic device (300) comprises a 5G housing architecture for 5G communications. [10] Computing device (900), comprising: at least one processor (904) for processing data; and a communication module or chip (906) coupled to the at least one processor (904), wherein the communication module or chip (904) comprises the following: a first substrate that supports a first die; a second die coupled to the first die, the second die having devices formed with compound semiconductor materials; an interposer substrate; and a second substrate coupled to the first substrate via the interposer substrate, wherein the interposer substrate (130, 230) provides electrical connections between components of the first substrate (120, 220) and components of the second substrate (150, 250), the second substrate having an antenna unit (920) for transmitting and receiving communications at a frequency of approximately 15 GHz or higher. [11] Computing device (900) according to claim 10, further comprising: an integrated passive die (IPD) coupled to the first die, wherein the IPD includes passive elements for passive matching networks. [12] Computing device (900) according to claim 10, wherein the first die comprises a complementary metal oxide semiconductor (CMOS) baseband circuit. [13] Computing device (900) according to claim 10, further comprising: a memory (910, 911, 912); a display module (930); and an input module (930), wherein the memory (910, 911, 912), the display module (930) and the input module (930) are on a chip-chipset platform and are interconnected.

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