System and procedure for direct writing to an MLC memory

Abstract

Method for programming a non-volatile memory (104) in a storage device (100), wherein a first part of the non-volatile memory (104) is configured as single-level cell (SLC) non-volatile memory and a second part of the non-volatile memory (104) is configured as multi-level cell (MLC) non-volatile memory, the method comprising: Receiving (502) data from a host device (252); Storing (504) the data in one or more volatile storage devices (116, 154, 156); Storing (508) some but not all of the data in the SLC non-volatile memory, wherein the data received by the host device (252) is the portion of the data that is stored in the SLC non-volatile memory and has a remainder; Storing (512), using the data stored in the one or more volatile memories (116, 154, 156), the data in the MLC non-volatile memory without transferring the portion of the data stored in the SLC non-volatile memory from the SLC non-volatile memory; Determine if there is an error in storing at least some of the data in the MLC non-volatile memory; in response to the determination that there is an error in storing at least some of the data in the MLC non-volatile memory: Request that the host device (252) resend the rest of the data; receive the rest of the data from the host device (252); and Using at least a section or portion of the part of the data stored in the SLC non-volatile memory and the remainder of the data received from the host device (252) to program the MLC non-volatile memory.

Description

Technical area

[0001] This application generally relates to memory devices. More specifically, this application relates to direct writing to a multi-level cell (MLC) memory without reading data from a single-level cell (SLC) memory. background

[0002] The background description provided herein is intended to generally present the context of the disclosure. Both the work of the present inventors to the extent described in the Background section, as well as aspects of the description that do not otherwise qualify as prior art at the time of filing, are not expressly or impliedly permitted as prior art against the present invention.

[0003] A memory device may include a memory device controller and a memory. The memory may consist of various types of memory, such as volatile memory (e.g., random access memory) and non-volatile memory (e.g., NAND flash memory). In particular, the non-volatile memory may consist of memory cells that can be programmed to store a single bit or a single level, referred to as a single-level cell (SLC), while other memory cells can be programmed to store multiple bits or multiple levels, referred to as multi-level cells.

[0004] When the memory device receives data from a host device, the memory device may first program the data into volatile memory (e.g., a portion of RAM allocated for use by the memory device controller). Then, the memory device controller may program the data from the volatile memory into SLC memory. Subsequently, the data stored in SLC memory may be moved or copied to MLC memory. For example, data stored in one or more SLC pages (or blocks) may be consolidated into one or more MLC pages (or blocks). As an example, where an MLC stores three bits per cell (e.g., X3), the data stored in three SLC pages may be copied into a single MLC page.In particular, an MLC can store data from three SLC pages, with the data stored in a top, middle, and bottom page of the MLC page. Therefore, copying data from the SLC memory to the MLC memory (or from one or more SLC pages (or blocks) to one or more MLC pages (or blocks)) can be referred to as a folding operation.

[0005] US 2015 / 0 012 684 A1 relates to a three-dimensional non-volatile memory in which copies of received data are stored in two different formats, one having a higher density and a higher error rate (e.g. an MLC format) and one having a lower density and a lower error rate (e.g. an SLC format). Short description of the drawings

[0006] The system can be better understood with reference to the following drawings and description. In the figures, like reference numerals designate corresponding parts throughout the different views. Fig. 1A is a block diagram of an exemplary non-volatile memory device. Fig. Figure 1B is a block diagram illustrating an example memory circuit. Fig. Figure 1C is a block diagram illustrating a hierarchical storage system. Fig. 2A is a block diagram illustrating example components of a controller of a non-volatile memory device. Fig. 2B is a block diagram illustrating example components of a non-volatile memory of a non-volatile memory system. Fig. 3A-B represent data transfer within different memory modules. Fig. 4 represents a data transfer within different memory chips. Fig. Figure 5 shows a first flowchart for direct writing to an MLC memory. Fig. Figure 6 shows a second flowchart for direct writing to an MLC memory. Detailed description

[0007] A storage device may include a storage device controller and a memory. In one embodiment, the memory may be in the form of one or more memory integrated circuit chips. The storage device may receive data from a host device instructing the storage device to store data in the memory. In response, the storage device controller may send one or more commands to the memory integrated circuit chip(s) to write the data to the memory.

[0008] As described in more detail below, the memory may include volatile memory and non-volatile memory. The non-volatile memory may include non-volatile memory cells in which the data may be stored. The non-volatile memory cells may take the form of solid-state (e.g., flash) memory cells and may be programmable once, a few times, or many times. Further, the non-volatile memory cells may be programmed to store a single level (e.g., a logical "0" or a logical "1"), referred to as single-level cells (SLC). Alternatively, the non-volatile memory cells may be programmed to store more than a single level (e.g., a logical "00," a logical "01," a logical "10," or a logical "11"), referred to as multi-level cells (MLC).Examples of MLC include double-level cells (DLC), triple-level cells (TLC), quadruple-level cells (QLC), etc.

[0009] When writing data to non-volatile memory, the data may first be stored in the SLC and then folded, or convolved, into the MLC. For example, the convolving process may involve performing an on-chip copy of data from three SLC blocks into a destination MLC block, thereby transferring data from the 1-bit (2-state) per cell arrangement of the SLC blocks to the higher-density 3-bit (8-state) per cell arrangement of the destination MLC block. As is generally understood, binary flash memory cells can have two possible states (0 or 1), representing 1 bit of information. For a given total operating voltage range available in a cell, the states of a binary cell can be represented by voltage levels above or below a reference voltage setting halfway between the maximum and minimum voltages of the range.MLC memory cells, which can have the same physical configuration as a binary cell, must partition their operating voltage range into finer step sizes to allow detectable peaks at each desired state. For a three-bit-per-cell MLC array, a distribution of eight detectable states (000, 001, 010, 011, 100, 101, 110, 111) fits within the same voltage range that the binary memory cell can use for only two states.

[0010] However, during a merge operation in which data stored in one or more source SLC blocks is to be copied to a destination MLC block, an error event may occur that results in only some of the data being successfully written to the destination MLC block. An example error event may include a power cycle (shutdown) or write abort event, which may cause the copying of the data to the destination MLC block to end prematurely or be aborted before all of the data has been copied. Another example error event may include a program failure, where, although all of the data may be copied to the destination MLC block, some of the data is incorrectly programmed into the destination MLC block. Other error events or combinations of error events that result in only some of the data being correctly written to the destination MLC block may be possible.

[0011] In one embodiment, instead of merging the data from the SLC to the MLC, the host data may be written to the MLC without merging or transferring the data from the SLC to the MLC. As discussed in more detail below, writing to the MLC is performed by writing (e.g., merging) the data from volatile memory to the MLC without transferring the data from the SLC to the MLC. Direct writing (e.g., without transferring data from the SLC to the MLC) may reduce write amplification and may be faster than merging the data from the SLC to the MLC. However, if an error event occurs (such as any error event disclosed above) when writing to the MLC, the host data may be lost. In particular, when the host data is received, the storage device may periodically acknowledge receipt of the host data.In the event that a power cycle error occurs before writing to the MLC is completed, the data that has already been acknowledged may be lost.

[0012] To perform a write operation to the MLC without merging or transferring data from the SLC to the MLC, in one embodiment, some or all of the host data written directly to the MLC may also be written to the SLC. In this way, if an error event occurs when writing to the MLC, the storage device can use the data written to the SLC to merge it into the MLC. Therefore, unless there is an error event, the MLC is written without merging from the SLC. Further, if an error occurs, the data from the SLC may be merged to the MLC.

[0013] In a more specific embodiment, less than all of the host data (but not all of the host data) that is written directly to the MLC is also written to the SLC. For example, the MLC may program a low page, a middle page, and a high page of data, as discussed in more detail below. Further, the SLC may be programmed with the low page and the middle page of data. In response to writing the data to the SLC (in the given example, the low page and middle page of data to the SLC), the storage device may send an acknowledgment to the host for the host data that is already written to the SLC. In this way, in response to an error event in the MLC program (e.g., programming the low page, middle page, and high page), the storage device may request that the host write the unacknowledged data (e.g., a remainder of the data that is unacknowledged, such asThe MLC can access the stored data (e.g., the stored lower and middle data pages) and retransmit the data (e.g., the stored lower and middle data pages). Therefore, even in the event of a fault, the data can be recovered and programmed to the MLC.

[0014] To program the MLC, one or more volatile memories may be used. In the TLC example, lower page latches, middle page latches, and upper page latches may be used. In practice, programming the MLC is done by writing the data from the lower / middle / upper page latches to the MLC lower / middle / upper pages. In one embodiment, programming the SLC may be performed at least partially concurrently with transferring the data to the volatile memory used to program the MLC. For example, in the TLC, the lower page of data is programmed into the SLC. Similarly, the lower page of data is latched or stored into the lower page latches. Programming the lower page of data into the SLC is performed at least partially concurrently with latching or storing the lower page of data into the lower page latches.Because of the simultaneous (or at least partially simultaneous) programming, programming the SLC does not delay (or delays less) the programming of the MLC.

[0015] In an alternating embodiment, the SLC may be programmed at a different time (e.g., either before or after) than when the data is programmed into the volatile memory used to program the MLC. For example, in the TLC, the middle page of data is programmed into the SLC. Likewise, the middle page of data is latched or stored into the middle page latches. Programming the lower page of data into the SLC is performed at a different time (e.g., before) than latching or storing the middle page of data into the middle page latches. In yet another alternating embodiment, a portion of the data programmed into the SLC is programmed at the same time as the data programmed into the volatile memory used to program the MLC, and another portion of the data programmed into the SLC is programmed at a different time (e.g.,either before or after) than the data is programmed into the volatile memory used to program the MLC.

[0016] Therefore, in one embodiment, the memory device may program the data (such as the lower / middle / upper page) from the volatile memory into the MLC memory without transferring the data from the SLC memory. In one embodiment, the memory device may also store only a portion of the data (such as the lower / middle page) into the SLC memory as a backup in the event of a failure. Specifically, if the data is not properly programmed into the MLC memory, the data in the SLC memory is used to program the data a second time into the MLC memory.

[0017] Referring to the figures, Fig. 1A is a block diagram illustrating a non-volatile memory device. The non-volatile memory device 100 includes a control unit 102 and a non-volatile memory, which may consist of one or more non-volatile memory chips 104. The non-volatile memory chips may comprise one or more memory integrated circuit chips. The control unit 102 and / or the non-volatile memory chips 104 may utilize a regulated voltage. As used herein, the term chip(s) refers to the set of non-volatile memory cells and the associated circuitry for managing the physical operation of those non-volatile memory cells formed on a single semiconductor substrate. The control unit 102 couples to a host device and transmits command sequences for read, program (e.g., write), and erase operations to the non-volatile memory chips 104.

[0018] The control unit 102 may take the form of a processing circuit, a microprocessor or processor, and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, an application-specific integrated circuit (ASIC), a programmable logic control unit, and an embedded microcontroller, for example. These examples of the control unit 102 are not exhaustive, and other forms for performing control unit functionality are contemplated. The control unit 102 may be configured with hardware and / or firmware to perform the various functions described below and shown in the flowcharts.For example, the hardware and / or firmware may be configured to analyze whether the value of the read counter should be stored in non-volatile memory, as discussed in more detail below. Also, some of the components shown as being internal to the control unit may be stored external to the control unit, and other components may be used. Additionally, the phrase "operatively in communication with" could mean directly in communication with or indirectly (wired or wirelessly) in communication with through one or more components, which may or may not be shown or described herein.

[0019] One type of controller 102 is a flash memory controller. As used herein, a flash memory controller is a device that manages data stored on flash memory and communicates with a host device, such as a computer or other electronic device. A flash memory controller may have a variety of functionality in addition to the specific functionality described herein. For example, the flash memory controller may format the flash memory to ensure that the memory is operating properly, measure bad flash memory cells, and allocate leftover cells to substitute for future failing cells. A portion of the leftover cells may be used to hold firmware to operate the flash memory controller and implement other features.In operation, when a host device needs to read or write data to the flash memory, it will communicate with the flash memory controller. If the host device provides a logical address from which data is read / written, the flash memory controller can convert the logical address received from the host device into a physical address in the flash memory (alternatively, the host device can provide the physical address). The flash memory controller can also perform various memory management functions, such as, but not limited to, wear leveling.Wear leveling (spreading out writes to avoid wearing out specific memory blocks that would otherwise be written to repeatedly) and automatic garbage collection (after a block is full, moving only the valid pages of data to a new block so that the full block can be erased and reused).

[0020] Non-volatile memory chips 104 may comprise any suitable non-volatile storage medium, including NAND flash memory cells and / or NOR flash memory cells. An example of non-volatile memory chips 104 may comprise a memory integrated circuit chip. The memory cells may take the form of solid-state (e.g., flash) memory cells and may be programmable once, a few times, or many times. As discussed above, the memory cells may also be single-level cells (SLC), double-level cells (DLC), triple-level cells (TLC), quadruple-level cells (QLC), or use other memory cell-level technologies now known or later developed. Therefore, any cell capable of storing more than a single level may be known as a multi-level cell (MLC). Also, the memory cells may be fabricated in a two-dimensional or three-dimensional manner.

[0021] The interface between the control unit 102 and the non-volatile memory chips 104 can be any suitable flash interface, such as Toggle Mode 200, 400, or 800. In one embodiment, the storage device 100 can be a card-based system, such as a Secure Digital (SC) or micro Secure Digital (micro SD) card. In an alternate embodiment, the storage device 100 can be part of an embedded storage system.

[0022] Although in the example shown in Fig. 1A, the non-volatile memory device 100 has a single channel between the control unit 102 and the non-volatile memory chips 104, the subject matter described herein is not limited to having a single memory channel. For example, in some NAND memory system architectures, such as those described in Fig. 1B-C, 2, 4, 8, or more NAND channels may exist between the control unit and the NAND memory system, depending on the capabilities of the control units. In any of the embodiments described herein, more than a single channel may exist between the control unit and the memory chips, even though a single channel is shown in the drawings.

[0023] Fig. 1B illustrates a memory circuit 200 including multiple non-volatile memory devices 100. As such, the memory circuit 200 may include a memory controller 202 that couples to a host device and to a memory system 204 including a plurality of non-volatile memory devices 100. The interface between the memory controller 202 and the non-volatile memory devices 100 may be a bus interface, such as a Serial Advanced Technology Attachment (SATA) or Peripheral Component Interface Express (PCIe) interface. The memory circuit 200, in one embodiment, may be a solid-state drive (SSD), as found in portable computing devices such as laptop computers and tablet computers.

[0024] Fig. 1C is a block diagram illustrating a hierarchical storage system. A hierarchical storage system 250 includes a plurality of storage controllers 202, each of which controls a respective storage system 204. The host systems 252 may access storage within the hierarchical storage system via a bus interface. In one embodiment, the bus interface may be a Non-Volatile Memory Express (MVMe) or a Fiber Channel over Ethernet (FCoE) interface. In one embodiment, the system illustrated in Fig. 1C may be a rack-mountable mass storage system that can be accessed by multiple host computers, such as one that would be found in a data center or other location where mass storage is needed.

[0025] Fig. Figure 2A is a block diagram illustrating exemplary components of control unit 102 in more detail. Control unit 102 includes front-end circuitry 108 that couples to a host device, back-end circuitry 110 that couples to the one or more non-volatile memory chips 104, and various other circuitry that performs functions that will now be described in detail.

[0026] The circuitry of the control unit 102 may include direct memory access (DMA) 112. In one embodiment, DMA 112 may be part of the control unit 102, as shown in Fig. 2A. In an alternate embodiment, DMA 112 may be separate from control unit 102. Independently, DMA 112 may be used to control the movement of data among various areas of memory. For example, DMA 112 may be used to control the movement of data between RAM (such as buffer RAM) and one or more latches (such as the main latch), which are discussed in more detail below. Further, in one embodiment, DMA 112 may include Flash DMA (FDMA), which is used to manage the movement of data within a flash memory device.

[0027] Referring again to the circuitry of control unit 102, a buffer manager / bus controller 114 manages buffers in random access memory (RAM) 116 and controls the internal bus arbitration of control unit 102. For example, one use of RAM 116 is buffer RAM, in which buffer manager / bus controller 114 may use RAM 116 to buffer host data received from the host device. As discussed in more detail below, DMA 112 may control the flow of data from RAM 116 to one or more portions of memory, such as main latch 158, which is discussed in more detail below. Read-only memory (ROM) 117 stores system boot code. Although in Fig. 2A is shown as being disposed separately from the control unit 102, in other embodiments, one or both of the RAM 116 and the ROM 118 may be disposed within the control unit. In still other embodiments, portions of the RAM and ROM may be disposed both within the control unit 102 and external to the control unit. Further, in some implementations, the control unit 102, the RAM 116, and the ROM 118 may be disposed on separate semiconductor chips.

[0028] The front-end circuit 108 includes a host interface 120 and a physical layer interface (PHY) 122, which provide the electrical interface with the host device or the next-level storage controller. The choice of the type of host interface 120 may depend on the type of storage used. Examples of host interfaces 120 include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, eMMC I / F, and NVMe. The host interface 120 typically facilitates the transfer of data, control signals, and timing signals.

[0029] The back-end circuitry 110 includes an error correction control (ECC) engine 124, which encodes the data bytes received from the host device and decodes and error-corrects the data bytes read from the non-volatile memory. An instruction sequencer 126 generates instruction sequences, such as program and erase command sequences, for transfer to the non-volatile memory chips 104. The RAID (Redundant Array of Independent Drives) circuitry 128 manages the generation of RAID parity and the recovery of failed data. RAID parity can be used as an additional level of integrity protection for the data written to the non-volatile memory device 100. In some cases, the RAID circuitry 128 may be part of the ECC engine 124.A memory interface 130 provides the command sequences to the non-volatile memory chips 104 and receives status information from the non-volatile memory chips 104. In one embodiment, the memory interface 130 may be a double data rate (DDR) interface, such as a toggle-mode 200, 400, or 800 interface. A flash control layer 132 controls the overall operation of the back-end circuitry 110.

[0030] Additional components of the system 100, which is Fig. 2A, include a media management layer 138 that performs wear leveling of memory cells of the non-volatile memory chips 104. The system 100 also includes other discrete components 104, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may couple to the control unit 102.

[0031] In alternative embodiments, one or more of the physical layer interface 122, the RAID circuitry 128, the media management layer 138, and the buffer management / bus controller 114 are optional components that are not necessarily provided in the controller 102.

[0032] Fig. 2B is a block diagram illustrating example components of non-volatile memory chips 104 in more detail. A non-volatile memory chip 104 includes peripheral circuitry 141 and a non-volatile memory array 142. The non-volatile memory array 142 includes non-volatile memory cells used to store data. The non-volatile memory cells may be any suitable non-volatile memory cells, including NAND flash memory cells and / or NOR flash memory cells in a two-dimensional and / or three-dimensional configuration. The peripheral circuitry 141 includes a state machine 160 that provides status information to the controller 102, a latch control circuitry 162, an SLC programming circuitry 164, and an MLC programming circuitry 166.

[0033] The non-volatile memory chip 104 further includes address decoders 148, 150 for addressing within the non-volatile memory array 142 and a data cache 152. The data cache 152 may include one or more sets of latches. Examples of latches include, but are not limited to, the main latch 154 and page latches 156. In one embodiment, one, some, or all of the latches in the data cache 154 may be a page wide. Further, a plurality of sets of data latches may be included in the data cache 152. For example, for a non-volatile memory array 142 arranged to store n bits per page, each set of data latches may include n data latches, where each data latch may store 1 data bit.

[0034] In one implementation, an individual data latch may be a circuit that has two stable states and can store one bit of data, such as a "set / reset" or SR, where the latch is constructed from NAND gates. The data latches 158 may function as a type of volatile memory that only retains data while powered on. Any of a number of known types of data latch circuits may be used for the data latches in each set of data latches. Each non-volatile memory chip 104 may have its own sets of data latches and a non-volatile memory array 142.

[0035] Latch control circuitry 162 is configured to control the flow of data to one or more of the latches. As discussed in more detail below, DMA 112 may be used to control the movement of data from RAM 116 (such as buffer RAM) to one or more latches, such as main latch 154. In one embodiment, latch control circuitry 162 may be used to control the movement of data from main latch 154 to one or more page latches 154. In the example of TLC, latch control circuitry 162 may be used to control the movement of data from main latch 154 to lower page latches, middle page latches, and upper page latches. In this regard, page latches 156 may include latches for different pages, such as lower page latches, middle page latches, and upper page latches for TLC. Furthermore, although the latch control circuit 162 in Fig. 2B is depicted as being located within the non-volatile memory 104, in an alternate embodiment, the latch control circuit 162 may be external to the non-volatile memory 104 and may be located within the control unit 102 or in another portion of the memory device. Likewise, although latches in the data cache 152 in Fig. 2B are shown as being located within the non-volatile memory 104, in an alternate embodiment, latches may be external to the non-volatile memory 104 and may be within the control unit 102 or in another portion of the memory device.

[0036] Peripheral circuitry 141 further includes an SLC programming circuitry 164 and an MLC programming circuitry 166. SLC programming circuitry 164 includes functionality for programming data into the SLC memory. For example, in one embodiment, data may be programmed from the main latch 156 to the SLC memory within the non-volatile memory array 142, as discussed in more detail below.

[0037] Likewise, MLC programming circuitry 166 includes functionality to program data into the MLC memory. As discussed in more detail below, MLC programming circuitry 166 may include an initial MLC programming circuitry and an MLC reprogramming circuitry (used in response to determining that there was an error programming the MLC). For example, in one embodiment, data may be programmed from page latches 160 to the MLC memory within non-volatile memory array 142.Furthermore, upon the occurrence of an error in programming the MLC (which is identified using the MLC programming error determination circuit configured to determine that there is an error in programming the MLC non-volatile memory), the MLC programming circuit 166 may access the SLC using the MLC reprogramming functionality to access the data lost due to the error event. Although the SLC programming circuit 164 and the MLC programming circuit 166 are shown in FIG. Fig. 2B as being located within the non-volatile memory 104, in an alternate embodiment, one or both of the SLC programming circuit 164 and the MLC programming circuit 166 may be external to the non-volatile memory 104 and located within the controller 102 or in another portion of the memory device.

[0038] As discussed above, the memory device may receive host data from the host device. In one embodiment, the memory device may couple to another electrical device via a physical layer, such as a physical layer interface (PHY) 122, which provides the electrical interface with the host device or the next level memory controller. Via the PHY 122, the memory device may receive data, such as host data, to write to the non-volatile memory. Upon receiving the data, the memory device may store the data in the RAM 116, such as the buffer RAM (BRAM). Thereafter, the DMA (or other control device) may initiate the transfer of the data stored in the BRAM to other memory, such as volatile memory (e.g., latches). Thereafter, data in the main latch may be transferred to the SLC memory for storage and to another memory (such aslower / middle / upper side latches) are transferred to the MLC memory for programming.

[0039] Fig. 3A-3B illustrate a transfer of data within various memory modules from BRAM to the main latch, from the main latch to the SLC memory, and from the lower / middle / upper page latches to the MLC memory. The transfer of data from the BRAM to the lower / middle / upper page latches is shown in Fig. 4. In one embodiment, the memory device may comprise multiple modules, such as module 0 to module N, as shown in Fig. 3A-B. Any number of modules is considered. Furthermore, in one embodiment, there may be a single chip within a module. For example, Fig. 3A-B represent 4 chips (Die0, Die1, Die2, Die3). However, a smaller or larger number of chips is considered within a module.

[0040] As in Fig. As shown in Figures 3A-B, the memory device can program the modules in parallel. Furthermore, in one embodiment, the chips within a module can be programmed serially. Fig. 3A-B illustrate the programming of a TLC memory, thereby programming a low page, a middle page, and a high page. Fig. 3A-B are mainly for illustration purposes, considering programming of other MLC memory such as DLC, QLC or the like.

[0041] Within module 0, at 300 for Die0, the DMA 112 controls the movement of the lower data page (LP) from the BRAM to the main latch 158. After the transfer at 300, at 302 the lower page from the main latch is programmed into the SLC memory in Die0. Further, after the transfer at 300, at 304 the DMA 112 controls the movement of the lower data page (LP) from the BRAM to the main latch 158 for Die1. In this regard, when the DMA 112 has completed the transfer of data from the BRAM to the main latch for one chip, the DMA 112 may begin the transfer of data from the BRAM to the main latch for another chip. Fig. 3A-B, at 300, 304, 308, and 312, illustrate the DMA transfer of the low page to the main latch of each of Die0, Die1, Die2, and Die3. Similarly, 302, 306, 310, and 314 illustrate the programming of the low page from the main latch into the SLC memory in each of Die0, Die1, Die2, and Die3.

[0042] The memory device may send the acknowledgment of the lower data page to the host device in response to one of several events. In one embodiment, the acknowledgment may be sent in response to programming the data into the non-volatile memory. For example, in response to an acknowledgment that the SLC memory has been programmed with the lower pages, the memory device may send an acknowledgment to the host device of the lower pages. In one embodiment, the memory device may send the acknowledgment after an acknowledgment that a single lower page in the SLC memory has been programmed. Alternatively, the memory device may send the acknowledgment after an acknowledgment that the lower pages have been programmed in multiple chips, such as Die0, Die1, Die2, and Die3.In an alternative embodiment, the memory device sends the acknowledgment to the host device in response to the data being transferred from the main latch to other volatile memory, such as the lower page latches, as described in more detail below. Fig. 3A-B do not represent the transfer of data from the main latch 158 to one of the side latches 160. Instead, Fig. 4 represents this transfer, as discussed in more detail below.

[0043] After the DMA 112 controls the transfer of the lower data page to the main latch in Die3 at 312, the DMA begins the transfer of the middle data pages (shown in the middle panel of Fig. 3A-B). Therefore, similar to the transfer for the lower page at 316, 320, 324, 328, the DMA serially controls the transfer from the BRAM to the main latch for the middle data pages. Likewise, after the transfer of the middle page from the BRAM to the main latch for a respective chip, the middle page in the main latch is programmed into the SLC memory, as shown at 318, 322, 326, 330.

[0044] Similar to the lower page, the memory device may send the middle data page acknowledgement to the host device in response to one of several events. In one embodiment, the acknowledgement may be sent in response to programming the data into the non-volatile memory (e.g., programming the middle page into the SLC memory). In an alternative embodiment, the memory device sends the acknowledgement to the host device in response to transferring the data from the main latch to the middle page latches, which is discussed in more detail below.

[0045] After the DMA 112 controls the transfer of the middle data page to the main latch in Die3 at 328, the DMA begins the transfer of the upper data pages (shown in the right panel of Fig. 3A-B). Therefore, similar to the transfer for the lower page and the middle page at 332, 336, 340, 344, the DMA serially controls the transfer from the BRAM to the main latch for the upper data pages. However, unlike the left and middle panels in Fig. 3A-B, the upper data page is not programmed into the SLC memory. Instead, the MLC is programmed at 334, 338, 342, and 346 using the lower / middle / upper page latches. Programming the MLC memory can take on the order of 1.8 to 2 milliseconds. This is in contrast to programming the SLC memory, which can take 400-500 microseconds.

[0046] The memory device may send the upper data page acknowledgement to the host device in response to one of several events. In one embodiment, the acknowledgement may be sent in response to programming the data in the non-volatile memory (e.g., completing programming of the MLC memory). However, during the time the MLC memory is being programmed (and before the upper data page acknowledgement has been sent to the host device), an error event may occur in which the MLC memory is not adequately or completely programmed. In this example, the program for the MLC memory may be restarted using the previously acknowledged data stored in the SLC memory (such as the lower page and middle page) and requesting that the host device resend the unacknowledged data (such as a remainder of the unacknowledged data (e.g.,the top side)), as described in more detail in . Fig. 5. In response to sending the request to retransmit the unacknowledged data, the host device retransmits the unacknowledged data (e.g., the top page). Further, in response to the memory device receiving the unacknowledged data again, the memory device may load the unacknowledged data into the page latches, load the acknowledged data (stored in the SLC memory) into the page latches, and then perform a second programming of the MLC memory (e.g., use a reprogramming circuit to perform the second programming of the MLC memory).

[0047] Fig. 4 represents a transfer of data within different memory chips. In particular, Fig. 4 shows the timing among the various circuit elements within a memory chip. Fig. Figure 4 illustrates the transfer of data within a single chip (Die0). However, in an alternative embodiment, multiple chips (as in Fig. 3A-B). Furthermore, Fig. 4 represents programming the TLC memory, which programs a lower page, a middle page and an upper page. Fig. Figure 4 is mainly for illustration purposes, considering programming from another MLC memory such as DLC, QLC or the like.

[0048] At time 0 (T0), the lower data page is sent from the BRAM to the main latch. In one embodiment, sending the lower data page from the BRAM to the main latch takes approximately 100-120 microseconds. At time 1 (T1), the lower data page is programmed into an SLC page, and the lower data page is transferred from the main latch to the lower page latch. In one embodiment, the lower data page is transferred from the main latch to the lower page latch in approximately 10 microseconds. Furthermore, programming the lower data page into the SLC memory may take approximately 400-500 microseconds. Therefore, as in Fig. 4, the programming of the lower data page into the SLC memory and the transfer of the lower data page to the lower page latch are performed at least partially concurrently. At T1' (after the transfer of the lower page from the main latch to the lower page latch), the middle data page is sent from the BRAM to the main latch. In one embodiment, the time to transfer the middle data page from the BRAM to the main latch is 100-120 microseconds, similar to the transfer time from the BRAM to the main latch for the lower data page. In this regard, the transfer of the middle data page from the BRAM to the main latch may be completed before the lower data page is programmed into the SLC.

[0049] At time 2 (T2), the middle data page is programmed into an SLC page. At time 3 (T3), the middle data page is transferred from the main latch to the middle page latch. Therefore, as shown in Fig. 4, the programming of the lower data page into the SLC memory and the transfer of the lower data page into the lower page latch are performed serially.

[0050] At time 4 (T4), the upper page of data is transferred from the BRAM to the main latch. At time 5 (T5), the upper page of data is transferred from the main latch to the middle page latch. Importantly, the upper page of data is not programmed into the SLC memory. At time 6 (T6), the data in the lower / middle / upper latch is programmed into the MLC lower / middle / upper page. In one embodiment, the time to program the data in the lower / middle / upper latch into the MLC lower / middle / upper page is 1.8-2 milliseconds. One type of programming the MLC is by using a "first-foggy-fine" method, such as shown in U.S. Patent No. 8,811,091, which is incorporated herein by reference in its entirety.

[0051] Fig. 5 illustrates a first flowchart 500 for direct writing to MLC memory. At 502, data is received from the host device. Examples of the data include low, middle, and high data pages. At 504, the data is stored in volatile memory such as RAM. The data may optionally be transferred to another volatile memory. For example, at 506, a DMA may be used to transfer the data from the volatile memory to one or more latches. As discussed above, the latches may include a main latch and one or more page latches (such as low / middle / high page latches). Further, the low / middle / high pages may be transferred from the BRAM to the main latch.

[0052] At 508, some, but less than all, of the data may be stored in non-volatile memory, such as SLC memory. For example, the lower and middle pages stored in the main latch may be saved in the SLC memory. Further, at 510, an acknowledgment of receipt of the data stored in the SLC memory may be sent to the host. For example, the memory device may send an acknowledgment to the host device indicating receipt of the data corresponding to the lower and middle pages stored in the SLC memory. At 512, the MLC memory is programmed using the data from the latches without accessing the data stored in the SLC memory. For example, the lower / middle / upper pages may be transferred from the main latch to the lower / middle / upper page latches.Furthermore, the lower / middle / upper side latches can be used to program the MLC lower / middle / upper side.

[0053] Fig. 6 illustrates a second flowchart 600 for direct writing to MLC memory. At 602, the memory device determines whether a write abort has occurred. For example, the memory device may determine that there was an error programming the MLC memory. In particular, when the memory device performs the power-on initialization sequence, the memory device may check the word line in the MLC memory to determine that the word line is not fully written. In response to this determination, the memory device may use the data in the MLC memory (such as the low and middle pages) and request the high page from the host device to program the MLC memory.

[0054] In response to determining that a write abort has occurred, at 606, the data stored in the SLC memory is accessed. For example, the lower and middle pages of the SLC memory are accessed. At 608, the DMA is used to load the data stored in the SLC into latches (such as lower / middle page latches). At 610, the memory device sends a communication to the host device requesting that the host device send the unacknowledged data. In response to the request, at 612, the memory device receives the unacknowledged data from the host device. In the example of TLC memory, the memory device receives the upper data page. At 614, the unacknowledged data is stored in volatile memory (such as BRAM). At 616, the DMA is used to load the unacknowledged data into one or more latches (such asinto the main latch and then into the upper side latches). At 618, the MLC memory is programmed with the data from the latches. In this regard, the MLC memory is programmed using the data transferred from the SLC memory. At 620, after confirming the programming of the MLC memory, the memory device sends an acknowledgment to the host device regarding the unacknowledged data.

[0055] In the present application, semiconductor memory devices such as those described in the present application may include volatile memory devices such as Dynamic Random Access Memory ("DRAM") or Static Random Access Memory ("SRAM") devices, non-volatile memory devices such as Resistive Random Access Memory ("ReRAM"), Electrically Erasable Programmable Read Only Memory ("EEPROM"), Flash memory (which may also be considered a subset of EEPROM), Ferroelectric Random Access Memory ("FRAM") and Magnetoresistive Random Access Memory ("MRAM"), and other semiconductor elements capable of storing information. Each type of memory device may have different configurations. For example, Flash memory devices may be configured in a NAND or a NOR configuration.

[0056] The memory devices can be formed from passive and / or active elements, in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistance-switching memory element, such as an anti-fuse, a phase-change material, etc., and optionally a guiding element such as a diode, etc. Further, as a non-limiting example, active semiconductor memory elements include EEPROM and Flash memory device elements, which in some embodiments include EEPROM and Flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.

[0057] Multiple storage elements can be configured to be connected in series or so that each element can be accessed individually. As a non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically include storage elements connected in series. A NAND memory array can be configured so that the array consists of multiple memory chains, in which a chain consists of multiple storage elements that share a single bit line and are accessed as a group. Alternatively, storage elements can be configured so that each element can be accessed individually, e.g., a NOR memory array. NAND and NOR memory configurations are exemplary, and memory elements can be configured in other ways.

[0058] The semiconductor memory elements arranged within and / or above a substrate can be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure.

[0059] In a two-dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, memory elements are arranged in a plane (e.g., an xz plane) that extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer over or in which the layer of memory elements is formed, or it may be a carrier substrate that is attached to the memory elements after they are formed. As a non-limiting example, the substrate may comprise a semiconductor such as silicon.

[0060] The memory elements can be arranged in an ordered array, such as a plurality of rows and / or columns, within the individual memory device level. However, the memory elements can be arranged in non-regular or non-orthogonal configurations. The memory elements can each have two or more electrodes or contact lines, such as bit lines and word lines.

[0061] A three-dimensional memory array is arranged so that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y, and z directions, with the y direction being substantially perpendicular and the x and z directions being substantially parallel to the main surface of the substrate).

[0062] As one non-limiting example, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), with each column having multiple memory elements in each column. The columns may be arranged in two-dimensional configurations, e.g., in an xz-plane, resulting in a three-dimensional array of memory elements with elements on multiple vertically stacked memory levels. Other configurations of memory elements in three dimensions may also constitute a three-dimensional memory array.

[0063] As a non-limiting example, in a three-dimensional NAND memory array, the storage elements can be coupled together to form a NAND chain within a single horizontal (e.g., xz) memory device level. Alternatively, the storage elements can be coupled together to form a vertical NAND chain spanning multiple horizontal memory device levels. Other three-dimensional configurations can be envisioned, with some NAND chains containing storage elements within a single memory level, while other chains containing storage elements spanning multiple memory levels. Three-dimensional memory arrays can also be designed in a NOR configuration and in a ReRAM configuration.

[0064] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed on a single substrate. Optionally, the monolithic three-dimensional memory array may also include one or more memory layers that are at least partially within the single substrate. As a non-limiting example, the substrate may comprise a semiconductor such as silicon. In a monolithic three-dimensional array, the layers constituting each memory device level of the array are typically formed on the layers of the underlying memory device levels of the array. However, layers of adjacent memory device levels of a monolithic three-dimensional memory array may be shared or have intervening layers between memory device levels.

[0065] On the other hand, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device with multiple memory layers. For example, non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrates can be thinned or removed from the memory device levels before stacking, but because the memory device levels are originally formed over separate substrates, the resulting memory arrays are non-monolithic three-dimensional memory arrays. Furthermore, multiple two-dimensional memory arrays or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked-chip memory device.

[0066] In one embodiment, a module may be used and may take the form of a packaged functional hardware unit designed for use with other components, a section of program code (e.g., software or firmware) executable by a (micro)processor or processing circuitry that normally performs a particular function of the functions concerned, or a self-contained hardware or software component that interfaces with a larger system, for example.

[0067] Furthermore, the methods, apparatus, processing, circuitry, and logic described herein may be implemented in many different ways and in many different combinations of hardware and software. For example, all or portions of the implementations may be a circuit including an instruction processor, such as a central processing unit (CPU), a microcontroller, or a microprocessor; or as an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a field-programmable gate array (FPGA); or as a circuit including discrete logic or other circuit components, including analog circuit components, digital circuit components, or both; or any combination thereof.The circuit may comprise discrete coupled hardware components or may be combined on a single integrated circuit chip, distributed among multiple integrated circuit chips, or implemented in a multiple-chip module (MCM) of multiple integrated circuit chips in a common package, as examples.

[0068] Accordingly, the circuit may store or access instructions for execution, or may implement its functionality solely in hardware. These instructions may be stored in a tangible storage medium other than a transient signal, such as flash memory, random access memory (RAM), read-only memory (ROM), or erasable programmable read-only memory (EPROM); or on a magnetic or optical disc, such as compact disc read-only memory (CD-ROM), a hard disk drive (HDD), or other magnetic or optical disc; or in another machine-readable medium. A product such asa computer program product, may comprise a storage medium and instructions stored in or on the medium, and the instructions, when executed by circuitry in a device, may cause the device to implement any of the processing described above or illustrated in the drawings.

[0069] Implementations can be distributed. For example, the circuit may have multiple distinct system components such as multiple processors and memories, and may span multiple distributed processing systems. Parameters, databases, and other data structures may be stored and managed separately, may be incorporated into a single memory or database, may be logically and physically organized in many different ways, and may be implemented in many different ways. Example implementations include linked lists, program variables, hash tables, arrays, records (e.g., database records), objects, and implicit storage mechanisms. Instructions may form parts (e.g., subroutines or other code sections) of a single program, may form multiple separate programs, may be distributed across multiple memories and processors, and may be implemented in many different ways.Example implementations include stand-alone programs, and as part of a library, such as a shared library such as a dynamic-link library (DLL). The library may, for example, contain shared data and one or more shared programs containing instructions that, when executed by the circuit, perform all of the processing described above or illustrated in the drawings.

[0070] Therefore, associated circuitry may be used for operating the memory elements and for communicating with the memory elements. As non-limiting examples, memory devices may include circuitry used for controlling and driving memory elements to achieve functions such as programming and reading. This associated circuitry may be on the same substrate as the memory elements and / or on a separate substrate. For example, a controller for memory read / write operations may be located on a separate controller chip and / or on the same substrate as the memory elements.

Claims

[1] A method for programming a non-volatile memory (104) in a memory device (100), wherein a first portion of the non-volatile memory (104) is configured as a single-level cell (SLC) non-volatile memory and a second portion of the non-volatile memory (104) is configured as a multi-level cell (MLC) non-volatile memory, the method comprising: Receiving (502) data from a host device (252); Storing (504) the data in one or more volatile memories (116, 154, 156); Storing (508) a portion but not all of the data in the SLC non-volatile memory, wherein the data received from the host device (252) comprises the portion of the data stored in the SLC non-volatile memory and a remainder; Storing (512), using the data stored in the one or more volatile memories (116, 154, 156), the data in the MLC non-volatile memory without transferring the portion of the data stored in the SLC non-volatile memory from the SLC non-volatile memory; Determining whether there is an error storing at least some of the data in the MLC non-volatile memory; in response to determining that there is an error storing at least some of the data in the MLC non-volatile memory: Requesting that the host device (252) resend the remainder of the data; receiving the remainder of the data from the host device (252); and Using at least a portion of the part of the data stored in the SLC non-volatile memory and the remainder of the data received from the host device (252) to program the MLC non-volatile memory. [2] The method of claim 1, wherein storing the data in one or more volatile memories (116, 154, 156) comprises storing the data in a buffer random access memory (BRAM). [3] The method of claim 1, wherein the memory device (100) further comprises one or more latches (154, 156); and wherein storing the data in one or more volatile memories (116, 154, 156) comprises storing the data in the one or more latches (154, 156). [4] The method of claim 3, wherein storing a portion of the data in the SLC non-volatile memory comprises programming the SLC non-volatile memory using the data stored in the one or more latches (154, 156); and wherein the portion of the data stored in the SLC non-volatile memory is used to program the MLC non-volatile memory only in response to determining the error in programming the MLC non-volatile memory. [5] The method of claim 1, wherein using at least a portion of the portion of the data stored in the SLC non-volatile memory comprises: Transferring the portion of the data in the SLC non-volatile memory to the one or more volatile memories (116, 154, 156); and Using the portion of the data transferred from the SLC non-volatile memory to the one or more volatile memories (116, 154, 156) to program the MLC non-volatile memory. [6] A method for programming a non-volatile memory (104) in a memory device (100), wherein a first portion of the non-volatile memory (104) is configured as a single-level cell (SLC) non-volatile memory and a second portion of the non-volatile memory (104) is configured as a multi-level cell (MLC) non-volatile memory, the method comprising: Receiving (502) data from a host device (252); Storing (504, 506) the data in one or more volatile memories (116, 154, 156); Storing (508) some or all of the data in the SLC non-volatile memory; Storing (512), using the data stored in the one or more volatile memories (116, 154, 156), the data in the MLC non-volatile memory without transferring some or all of the data stored in the SLC non-volatile memory from the SLC non-volatile memory; and sending (510) by the memory device (100) an acknowledgment of receipt of the portion of the data programmed in the SLC non-volatile memory, wherein the sending of the acknowledgment is performed before completion of programming of the data in the MLC non-volatile memory. [7] The method of claim 6, wherein storing some or all of the data in the SLC non-volatile memory comprises programming some, but less than all, of the data programmed in the MLC non-volatile memory into the SLC non-volatile memory; wherein the data received from the host device (252) comprises the portion of the data programmed in the SLC non-volatile memory and a remainder; and wherein the method, in response to determining that there is an error in storing the data in the MLC non-volatile memory, further comprises, by the storage device (100), sending a request to the host device (252) to resend the remainder of the data. [8] The method of claim 7, further comprising: in response to the request for the remainder of the data, receiving from the host device (252) the remainder of the data; and Storing the remainder of the data in the one or more volatile memories (116, 154, 156), wherein using some or all of the data transferred from the SLC non-volatile memory to the one or more volatile memories (116, 154, 156) to program the MLC non-volatile memory comprises: Using the portion of the data transferred from the SLC non-volatile memory to the one or more volatile memories (116, 154, 156) and the remainder of the data stored in the one or more volatile memories (116, 154, 156) to program the MLC non-volatile memory. [9] A storage device (100) comprising: one or more volatile memories (116, 154, 156); a non-volatile memory (104), wherein a first portion of the non-volatile memory (104) is configured as a single-level cell (SLC) non-volatile memory and a second portion of the non-volatile memory (104) is configured as a multi-level cell (MLC) non-volatile memory; a programming circuit (164) configured to program at least a portion of the data into the SLC non-volatile memory; a transfer circuit configured to transfer the data to the one or more volatile memories (116, 154, 156); a programming circuit (166) configured to transfer the data from the one or more volatile memories (116, 154, 156) to the MLC non-volatile memory without transferring at least a portion of the data stored in the SLC non-volatile memory from the SLC non-volatile memory; and an acknowledgment circuit configured to, in response to programming less than all of the data into the SLC non-volatile memory, send an acknowledgment to a host device (252) of receipt of the less than all of the data. [10] The memory device (100) of claim 9, wherein the one or more volatile memories (116, 154, 156) comprise buffer random access memory (BRAM) and one or more latches (154, 156); and wherein the transfer circuit comprises a direct memory access circuit configured to transfer the data from the BRAM to the one or more latches (154, 156). [11] The memory device (100) of claim 9, wherein the programming circuit is configured to program (508) less than all of the data into the SLC non-volatile memory. [12] The memory device (100) of claim 9, further comprising an MLC programming error determination circuit configured to determine that there is an error in programming the MLC non-volatile memory; and an MLC reprogramming circuit configured, in response to determining that there is an error in programming the MLC non-volatile memory, to use the at least a portion of the data stored in the MLC non-volatile memory to program the MLC non-volatile memory. [13] The storage device (100) of claim 12, wherein the data is received from the host device (252), the data comprising a plurality of pages; wherein less than all of the pages are stored in the SLC memory (508); wherein all of the pages are stored in the MLC memory (512). [14] The storage device (100) of claim 12, wherein the data comprises a first set of pages and a second set of pages; wherein the first set of pages is stored in the SLC non-volatile memory; wherein the second set of pages is not stored in the SLC non-volatile memory; and wherein both the first set of pages and the second set of pages are stored in the MLC non-volatile memory. [15] The memory device (100) of claim 14, wherein the acknowledgement circuit is configured to send the acknowledgement to the host device (252) of receipt of the first set of pages from memory in response to programming the first set of pages into the SLC non-volatile memory; and wherein the memory device (100) further comprises a request retransmission circuit configured to request retransmission of the second set of pages in response to there being an error in programming the MLC non-volatile memory. [16] The memory device (100) of claim 15, wherein the acknowledge circuit is further configured to send an acknowledgement of the second set of pages in response to programming the data into the MLC non-volatile memory. [17] A method for programming a non-volatile memory (104) in a memory device (100), wherein a first portion of the non-volatile memory (104) is configured as a single-level cell (SLC) non-volatile memory and a second portion of the non-volatile memory (104) is configured as a multi-level cell (MLC) non-volatile memory, the method comprising: Receiving (502) data from a host device (252); Storing (504, 506) the data in one or more volatile memories (116, 154, 156); Storing (508) some or all of the data in the single-level cell (SLC) non-volatile memory; performing a first programming (512) of the MLC non-volatile memory using the data stored in one or more volatile memories (116, 154, 156) without using the data stored in the SLC non-volatile memory; Determining whether there is an error in the initial programming of the MLC non-volatile memory; and in response to determining that there is an error in the first programming of the MLC non-volatile memory, performing a second programming of the MLC non-volatile memory using some or all of the data stored in the SLC non-volatile memory, wherein storing at least a portion of the data in the SLC non-volatile memory is performed at least partially concurrently with storing at least a portion of the data in the volatile memory (116, 154, 156). [18] The method of claim 17, wherein the one or more volatile memories (116, 154, 156) comprise a plurality of page latches (156); and wherein storing the data in the one or more volatile memories (116, 154, 156) comprises storing the data in the plurality of page latches (156). [19] The method of claim 18, wherein the data comprises a plurality of pages; wherein storing (508) some or all of the data in the SLC non-volatile memory comprises storing less than all of the plurality of pages; and wherein performing the first programming (512) of the MLC non-volatile memory comprises programming all of the plurality of pages. [20] The method of claim 19, wherein the data comprises a bottom page, a middle page, and a top page; wherein storing (508) some or all of the data in the SLC non-volatile memory comprises storing the lower page and the middle page in the SLC non-volatile memory, but not storing the upper page in the SLC non-volatile memory; and wherein performing the first programming (512) of the MLC non-volatile memory comprises programming the lower, middle, and upper pages into the MLC non-volatile memory. [21] The method of claim 20, wherein storing the lower page in the SLC non-volatile memory is performed at least partially concurrently with storing the lower page in the page latches (156); and wherein storing the middle page in the SLC non-volatile memory is not performed at least partially concurrently with storing the middle page in the page latches (156).

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