Non-volatile multibit random access memory cells

Abstract

A device that includes the following: a volatile storage element, wherein the volatile storage element includes a data true node (DT node) and a data complement node (DC node); and a non-volatile storage circuit, wherein the non-volatile storage circuit comprises at least a first pass transistor connected to the DT node of the volatile storage element, and comprising at least one second pass transistor connected to the DC node of the volatile storage element, wherein the non-volatile storage circuit further comprises a plurality of non-volatile storage elements, each non-volatile storage element of the plurality of non-volatile storage elements being configured to be selectively connectable to the DT node of the volatile storage element via the at least one first pass transistor and to be selectively connectable to the DC node of the volatile storage element via the at least one second pass transistor. wherein the plurality of non-volatile storage elements includes two non-volatile storage elements and the non-volatile storage circuit further includes the following: a bridge transistor connected to the two non-volatile storage elements, wherein the bridge transistor is configured to selectively connect one of the two non-volatile storage elements to the DT node of the volatile storage element via the at least one first pass transistor and to the DC node of the volatile storage element via the at least one second pass transistor.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS FIELD OF THE INVENTION

[0001] The present disclosure relates generally to the field of data storage devices, and more particularly to non-volatile static random access storage devices. STATE OF THE ART

[0002] A non-volatile static random-access memory (nvSRAM) is a type of non-volatile random-access memory. An nvSRAM typically includes multiple nvSRAM cells. An nvSRAM cell typically includes a static random-access memory (SRAM) configured to facilitate read and write operations and a non-volatile storage circuit configured to facilitate store and retrieve operations. For example, a store operation may store data from the SRAM of the nvSRAM cell to the non-volatile storage circuit of the nvSRAM cell. A retrieve operation, on the other hand, may retrieve data from the non-volatile storage circuit of the nvSRAM cell and load the retrieved data into the SRAM of the nvSRAM cell.

[0003] US 2015 / 0 269 989 A1 discloses a semiconductor structure and a memory device with this structure.

[0004] US 6 414 873 B1 relates to a non-volatile static random access memory (nvSRAM) in which each SRAM memory cell is assigned to at least two non-volatile memory cells. OVERVIEW

[0005] One embodiment of the present disclosure relates to a device according to claim 1. The device comprises a volatile storage element having a data true (DT) node and a data complement (DC) node. The device further comprises a non-volatile storage circuit. The non-volatile storage circuit comprises at least one first pass transistor connected to the DT node of the volatile storage element and at least one second pass transistor connected to the DC node of the volatile storage element. The non-volatile storage circuit further comprises a plurality of non-volatile storage elements.Each non-volatile storage element is configured to be selectively connectable to the DT node of the volatile storage element via the at least one first pass transistor and to be selectively connectable to the DC node of the volatile storage element via the at least one second pass transistor.

[0006] Another embodiment of the present disclosure relates to a system according to claim 9. The system comprises a processor and a non-volatile storage device configured to provide data storage for the processor. The non-volatile storage device comprises a plurality of non-volatile memory cells. Each non-volatile memory cell comprises a volatile storage element having a DT node and a DC node. Each non-volatile memory cell further comprises a non-volatile storage circuit. The non-volatile storage circuit comprises at least a first switching element connected to the DT node of the volatile storage element and at least one second switching element connected to the DC node of the volatile storage element. The non-volatile storage circuit further comprises a plurality of non-volatile storage elements.Each non-volatile storage element is configured to be selectively connectable to the DT node of the volatile storage element via the at least one first switching element and to be selectively connectable to the DC node of the volatile storage element via the at least one second switching element.

[0007] An additional embodiment of the present disclosure relates to a method according to claim 16. The method comprises: establishing a first data storage path between a first non-volatile storage element of a plurality of non-volatile storage elements and a DT node of a volatile storage element; programming the first non-volatile storage element based on data stored in the volatile storage element by using the first data storage path; establishing a second data storage path between a second non-volatile storage element of the plurality of non-volatile storage elements and the DT node of the volatile storage element; and programming the second non-volatile storage element based on the data stored in the volatile storage element by using the second data storage path.

[0008] It should be understood that both the foregoing general description and the following detailed description are exemplary and exemplary only and are not necessarily limiting of the present disclosure. The accompanying figures, which are incorporated in and constitute a part of the specification, illustrate the subject matter of the disclosure. The descriptions and figures together serve to explain the basic principles of the disclosure. BRIEF DESCRIPTION OF THE CHARACTERS

[0009] The numerous advantages of the disclosure may be better understood by those skilled in the art by reference to the accompanying figures, in which: Fig. 1 is a circuit diagram illustrating one embodiment of a non-volatile multi-bit random access memory cell; Fig. 2 is a time-based flowchart illustrating an example process performed during a storage operation; Fig. 3 is another time-based flowchart illustrating an example process performed during a storage operation; Fig. 4 is a circuit diagram illustrating an exemplary process performed during a fetch operation; Fig. 5 is a flowchart illustrating the exemplary process performed during the retrieval operation; Fig. 6 is a circuit diagram illustrating an embodiment of another non-volatile multi-bit random access memory cell; Fig. 7 is a circuit diagram illustrating an embodiment of another non-volatile multi-bit random access memory cell; and Fig. 8 is a block diagram illustrating a system using one embodiment of a non-volatile multi-bit random access memory. DETAILED DESCRIPTION

[0010] Reference will now be made in detail to the disclosed subject matter, which is illustrated in the accompanying figures.

[0011] Embodiments according to the present disclosure relate to non-volatile multi-bit random access memory cells. Non-volatile multi-bit random access memory cells are random access memory cells capable of storing / retrieving more than one bit of data per cell.

[0012] Generally referring to Fig. 1, a circuit diagram illustrating one embodiment of a non-volatile multi-bit random access memory cell 100 configured according to the present disclosure is shown. The non-volatile multi-bit random access memory cell 100 may include a volatile storage element 102 configured to facilitate read and write operations. The volatile storage element 102 may be configured using suitable volatile memory implementations. For example, as shown in Fig. 1, the volatile storage element 102 may implement a static random access memory (SRAM) comprising a first transistor 106 cross-coupled to a second transistor 108. The volatile storage element 102 may also include a data true (DT) node 110 and a data complement (DC) node 112 connected to the first and second transistors 106 and 108. It should be noted that because SRAMs are well understood by those skilled in the art, detailed operations of SRAMs will not be repeated in the present disclosure. It should also be noted that multi-bit non-volatile random access memory cells 100 employing SRAMs as the volatile storage elements 102 may be referred to as multi-bit nvSRAM cells 100 for illustrative purposes. However, it should be understood that the use of SRAMs as volatile storage cells is for illustrative purposes only.It is contemplated that other types of volatile storage elements may be used instead of (or in addition to) SRAMs without departing from the spirit and scope of the present disclosure.

[0013] The non-volatile multi-bit random access memory cell 100 may also include a non-volatile storage circuit 104 configured to facilitate storage and retrieval operations. The non-volatile storage circuit 104 of the non-volatile multi-bit random access memory cell 100 may be isolated from the volatile storage element 102 during read and write operations. The isolation may be achieved by turning off the storage elements (e.g., implemented as pass transistors) 124 and 126 that connect the non-volatile storage circuit 104 to the DT node 110 and the DC node 112. The isolation effectively allows the non-volatile multi-bit random access memory cell 100 to operate as a volatile storage element (e.g., an SRAM) for read and write operations.

[0014] The non-volatile memory switch 104 of the non-volatile multi-bit random access memory cell 100 can be used when data needs to be stored in the volatile storage element 102. This may be referred to as a store operation, which may be automatically triggered (may be referred to as an auto-save) when the main voltage source of the data is lost or drops below a threshold. Alternatively and / or additionally, store operations may be triggered based on certain preconfigured, hardware- and / or software-based actions. Regardless of the trigger event, after a store operation is initiated, a series of actions may be performed to execute the store operation.

[0015] In the Fig. 1, the non-volatile memory switch 104 of the non-volatile multi-bit random access memory cell 100 includes a first bulk programming transistor 114 and a second bulk programming transistor 116, each connected to a first non-volatile storage element 118 and a second non-volatile storage element 120. The first non-volatile storage element 118 and the second non-volatile storage element 120 each include a storage device capable of trapping charge (e.g., a silicon oxide nitride oxide silicon (SONOS) transistor, a floating gate, or the like). The first non-volatile storage element 118 and the second non-volatile storage element 120 are commonly bridged via a bridge transistor 122.The bridge transistor 122 is configured to selectively connect one of the first or second non-volatile storage elements 118 / 120 to one of a DT node pass transistor 124 or a DC node pass transistor 126 shared by the first and second non-volatile storage elements 118 and 120. The ability to selectively connect one of the first or second non-volatile storage elements 118 / 120 to one of the DT node pass transistor 124 or the DC node pass transistor 126 allows the non-volatile storage circuit 104 to selectively store (and retrieve) data to the two non-volatile storage elements 118 and 120, which in turn provides the non-volatile multi-bit random access memory cell 100 with the capabilities to store / retrieve two bits of data per cell.

[0016] Fig. 2 is a time-based flowchart illustrating an exemplary process performed during a storage operation 200 to establish a data storage path to a first non-volatile storage element 118 and to store data to the first non-volatile storage element 118 using the established storage path. Referring generally to Fig. 1 and Fig. 2, a bulk programming step 202 is performed by applying a voltage (VBP1) to the first bulk programming transistor 114 and applying a positive voltage (where VSE1 is positive) to the first non-volatile storage element 118 for a period of time. A subsequent step, referred to as the bulk erase step 204, may apply a negative voltage (where VSE1 is negative) to the first non-volatile storage element 118 for a period of time, thereby erasing data stored in the non-volatile storage element 118. A programming step 206 may begin after the bulk erase step 204. If DT-Data = 1, the passgate VSTR will be "off" and the first non-volatile storage element 118 will remain in the "erase" state after the programming step 206. If DT-Data = 0, the passgate VSTR will be "on" and the first non-volatile storage element 118 after the programming step 206 will go into the "program" state.

[0017] Fig. 3 is a time-based flowchart illustrating an exemplary process performed during a storage operation 300 to establish a data storage path to a second non-volatile storage element 120 and to store data to the second non-volatile storage element 120 using the established storage path. Referring generally to Fig. 1 and Fig. 3, a bulk programming step 302 is performed by applying a voltage (VBP2) to the second bulk programming transistor 116 and applying a positive voltage (where VSE2 is positive) to the second non-volatile storage element 120 for a period of time. A subsequent step, referred to as the bulk erase step 304, may apply a negative voltage (where VSE2 is negative) to the second non-volatile storage element 120 for a period of time, thereby erasing data stored in the non-volatile storage element 120. A programming step 306 may begin after the bulk erase step 304. By supplying power (VBR) to the bridge transistor 122, if DT-Data = 1, passgate VSTR will be "off" and the second non-volatile storage element 120 will remain in the "erase" state after the programming step 306.If DT-Data = 0, the passgate VSTR will be "on" and the second non-volatile storage element 120 will go into the "program" state after the programming step 306.

[0018] It is noted that the response times of the first and second non-volatile storage elements 118 and 120 to the voltage applied to VSE1 and VSE2, shown in Fig. 2 and Fig. 3, have been simplified for illustrative purposes. It is understood that the response times may not be instantaneous. It is therefore contemplated that in some implementations, precharge voltages may be used to help modify / improve the response times. It is understood that whether (and how) such precharge voltages are used may vary without departing from the spirit and scope of the present disclosure.

[0019] It should be noted that the non-volatile storage circuit 104 of the non-volatile multi-bit random access memory cell 100 configured according to the present disclosure also supports fetch operations from the two non-volatile storage elements 118 and 120. Fig. 4 and Fig. 5 are illustrations illustrating an exemplary process performed during a fetch operation 500 for fetching data stored in the first non-volatile storage element 118 into the volatile storage element 102 of the non-volatile multi-bit random access memory cell 100.

[0020] In particular, as in Fig. 4 and Fig. 5, a prewrite step 502 may be used to write "0"s to the volatile storage element 102 of the non-volatile multi-bit random access memory cell 100, effectively setting the DT node 110 to 0 and the DC node 112 to power. Step 504 may then set the volatile storage element 102 to a data hold mode by turning on the VCLAMP and applying a current limit to the volatile storage element 102 using the VSSIGATE. Thereafter, a fetch path may be established in a fetch step 506. To retrieve data from the first non-volatile storage element 118 (as shown in Fig. 4 for illustrative purposes), the fetch step 506 may turn on VRCL, VBP1, VBR and turn off VSTR and VBP2, effectively establishing the fetch path VCCT, VBP1, VSE1, VBR, VRCL, and the DC node 110 of the volatile storage element 102. To retrieve data from the second non-volatile storage element 120, the fetch step 506 may turn on VRCL, VBP2 and turn off VSTR and VBP1 and VBR, effectively establishing the fetch path VCCT, VBP2, VSE2, VRCL, and the DC node 110 of the volatile storage element 102.

[0021] After the appropriate fetch path is established, a charge step 508 may charge the volatile storage element 102 of the non-volatile multi-bit random access memory cell 100 so that the volatile storage element 102 can latch the data on the fetch path. For example, the charge step 508 may disconnect VCCI and VSSI and apply VSSI to the volatile storage element 102, allowing the volatile storage element 102 to latch the data on the fetch path and complete the fetch operation. In this way, when the non-volatile storage element 118 / 120 on the fetch path is in an erase state (stored data = 1), the DC node 112 of the volatile storage element 102 is grounded and the DT node 110 of the volatile storage element 102 is set to 1 upon completion of the fetch operation.On the other hand, if the non-volatile storage element 118 / 120 on the fetch path is in a programming state (stored data = 0), the DC node 112 of the volatile storage element 102 will not have a path to ground, and the DT node 110 of the volatile storage element 102 will therefore remain at the same prewrite value of 0, thereby performing the fetch operation as intended.

[0022] It should be noted that the non-volatile multi-bit random access memory cell 100 configured according to the present disclosure is not only capable of selectively storing data to the non-volatile storage elements 118 and / or 120, but is also capable of selectively retrieving data from the non-volatile storage elements 118 and / or 120. It should be noted that this capability may help provide several performance improvements over conventional nvSRAM cells, which are limited to storing / retrieving one bit of data per cell. For example, in certain implementations, the non-volatile storage elements 118 and 120 may be used alternately for data storage to help extend the lifetime of the non-volatile multi-bit random access memory cell 100.In another example, one of the non-volatile storage elements 118 or 120 may be dedicated as a non-volatile storage element for data storage when the power supply fails (e.g., providing auto-save when the main voltage source of the data drops below a threshold), while the other non-volatile storage element may be used to store data when the power supply is on, thereby enhancing the robustness of the data retention provided by the non-volatile random access memory cell 100.

[0023] Additionally and / or alternatively, non-volatile storage elements 118 and 120 may be used to provide redundancy, which may be appreciated under certain operating conditions. For example, one of non-volatile storage elements 118 or 120 may be used as a redundant element if non-volatile multi-bit random access memory cell 100 fails to retrieve from the other non-volatile storage element.It should further be noted that the non-volatile multi-bit random access memory cell 100 configured according to the present disclosure is capable of providing non-inverted fetches when, after fetching from the non-volatile storage circuit 104 of the non-volatile multi-bit random access memory cell 100, the data in the volatile storage element 102 of the non-volatile multi-bit random access memory cell 100 is the same as the data in the non-volatile storage circuit 104.

[0024] It is understood that the configuration of the non-volatile multi-bit random access memory cell 100 as described above is merely an example and is not intended to be limiting. It is contemplated that alternative configurations may be used to implement the non-volatile multi-bit random access memory cell and provide the aforementioned performance improvements without departing from the spirit and scope of the present disclosure. For example, Fig. 6 is a circuit diagram illustrating one embodiment of another non-volatile multi-bit random access memory cell 600 configured in accordance with the present disclosure.

[0025] As in Fig. 6, the non-volatile multi-bit random access memory cell 600 includes a volatile storage element (e.g., an SRAM) 602 configured to facilitate read and write operations, and a non-volatile storage circuit 604 configured to facilitate store and retrieve operations. It should be noted that the non-volatile storage circuit 604 of the non-volatile multi-bit random access memory cell 600 may be configured differently compared to the non-volatile storage circuit 104 as previously described. The non-volatile storage circuit 604 shown in Fig. 6 may be configured to support an n-number of non-volatile storage elements 606 (where n>2), thereby allowing the non-volatile multi-bit random access memory cell 600 to store / retrieve up to an n-number of data bits per cell.

[0026] In particular, the non-volatile storage circuit 604 may include a first group of serially connected switching elements (e.g., pass transistors) 608 connected to the DT node 610 of the volatile storage element 602. The non-volatile storage circuit 604 may also include a second group of serially connected switching elements (e.g., pass transistors) 614 connected to the DC node 612 of the volatile storage element 602. The first group of pass transistors 608 and the second group of pass transistors 614 may be connected together with the n-number of non-volatile storage elements 606 to form a chain of transistors, as shown in Fig. 6. This chain of transistors may provide the non-volatile multi-bit random access memory cell 600 with the ability to connect any of the n-number of non-volatile storage elements 606 to the DT node 610 or the DC node 612 of the volatile storage element 602, effectively allowing the non-volatile multi-bit random access memory cell 600 to store / retrieve up to an n-number of data bits per cell.

[0027] For example, to store data to a non-volatile storage element 606A (one of the n-number of non-volatile storage elements 606), the non-volatile multi-bit random access memory cell 600 may turn on VSTR(n+1) and VSTRn, turn off VSTR1, VRCL1, VRCLn, and perform the aforementioned bulk programming and bulk erasing steps on the non-volatile storage element 606A by applying a positive voltage and a negative voltage to VSE1, respectively. The non-volatile multi-bit random access memory cell 600 may then turn off VSTR(n+1) and VSTRn, turn on VSTR1, and perform the aforementioned programming step to enable data transfer from the DT node 610 to the non-volatile storage element 606A.

[0028] To retrieve data from non-volatile storage element 606A, non-volatile multi-bit random access memory cell 600 may turn on VSTR(n+1), VSTRn, and VRCL1, effectively establishing a retrieve path from non-volatile storage element 606A to DC node 612 of volatile storage element 602. Volatile storage element 602 may then be charged and latched to the data on the retrieve path (in this example, the data from non-volatile storage element 606A), thereby completing the retrieve operation as intended.

[0029] Similarly, to store data to the non-volatile storage element 606B, the non-volatile multi-bit random access memory cell 600 may turn on VSTR(n+1), turn off VSTR1 through VSTRn, VRCL1, VRCLn, and perform the aforementioned bulk programming and bulk erasing steps on the non-volatile storage element 606B. The non-volatile multi-bit random access memory cell 600 may then turn on VSTR(n+1), turn off VSTR1 through VSTRn, and perform the aforementioned programming step to enable data transfer from the DT node 610 to the non-volatile storage element 606B. To retrieve data from non-volatile storage element 606B, non-volatile multi-bit random access memory cell 600 may turn on VSTR(n+1) and VRCL1 through VRCLn, effectively establishing a retrieve path from non-volatile storage element 606B to DC node 612 of volatile storage element 602.

[0030] It is understood that while only two non-volatile storage elements 606 in Fig. 6, such a configuration is merely an example and is not intended to be limiting. It is contemplated that a non-volatile multi-bit random access memory cell 600 may include any number of non-volatile storage elements 606 without departing from the spirit and scope of the present disclosure, and data may be stored to and retrieved from the non-volatile storage elements 606 in a manner similar to that described above.

[0031] It is also understood that while the n-number of non-volatile storage elements 606 (and the chain of transistors in general) are shown positioned on one side of the volatile storage element 602, such a configuration is merely an example and is not intended to be limiting. It is contemplated that the n-number of non-volatile storage elements 606 (and the chain of transistors in general) may be distributed on more than one side of the volatile storage element 602 without departing from the spirit and scope of the present disclosure. In certain implementations, as in Fig. 7, when n is an even number, the non-volatile storage elements 706 (and the chain of transistors 704 in general) may be distributed on two opposite sides of the volatile storage element 702 to provide a balanced cell structure 700.

[0032] It should be understood that the various circuit diagrams presented above may not necessarily correspond to the physical configuration of the non-volatile multi-bit random access memory cells. In other words, the physical configuration of the non-volatile multi-bit random access memory cells may vary without departing from the spirit and scope of the present disclosure. In certain implementations, the size of the non-volatile multi-bit random access memory cells may be approximately 1.36 micrometers wide and 5.24 micrometers long. However, it is contemplated that the size of the non-volatile multi-bit random access memory cells may vary without departing from the spirit and scope of the present disclosure.

[0033] Fig.8 is a block diagram illustrating a system 800 employing a non-volatile multi-bit random access memory 802 configured in accordance with the present disclosure. The system 800 may include one or more microcontrollers (which may also be referred to as processors) 804 communicatively coupled to the non-volatile multi-bit random access memory 802. The non-volatile multi-bit random access memory 802 may include one or more non-volatile multi-bit random access memory cells configured in accordance with the present disclosure. The one or more non-volatile multi-bit random access memory cells in the non-volatile multi-bit random access memory 802 may be used to provide data acquisition and storage for the one or more processors 804.

[0034] It is understood that the present disclosure may be practically implemented in the form of a software, hardware, or firmware package. It is also understood that embodiments of the present disclosure are not limited to any fundamental implementation technology. Embodiments of the present disclosure may be implemented using any software and hardware technology, and using various technologies, without departing from the present disclosure or without losing all of its material advantages.

[0035] It is understood that the specific order or hierarchy of steps in the disclosed processes is merely exemplary. It is understood that the specific order or hierarchy of steps in the processes may be rearranged while maintaining the broad scope of the present disclosure. The appended method claims present elements of the various steps in an exemplary order and are not intended to be limited to the specific order or hierarchy presented.

[0036] It is believed that the systems and methods disclosed herein, and many of their attendant advantages, will be understood from the foregoing description, and it will be appreciated that various changes in the form, construction, and arrangement of components thereof may be made without departing from the broad scope of the present disclosure or without losing all of its material advantages. The form described hereinabove represents merely an exemplary embodiment thereof; it is the intent of the following claims to encompass and embrace such changes.

[0037] The above description is illustrative and not limiting. The embodiments described above (or one or more aspects thereof) may be used in combination with one another. Other embodiments will be apparent to those skilled in the art after reviewing the above description. Throughout this document, the terms "a," "an," or "another" are used, as is common in patent documents, to include one or more than one. Throughout this document, the term "or" is used to mean non-exclusive, or such that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise noted.In the event of inconsistent uses of this document and those documents incorporated by reference, the use in the incorporated references shall be considered supplementary to this document; in the event of irreconcilable inconsistencies, the use of this document shall supersede the use in the incorporated references.

[0038] Although the claimed subject matter has been described with reference to specific embodiments, it will be evident that various modifications and changes may be made to those embodiments without departing from the broader spirit and scope of what is claimed. Accordingly, the specification and drawings are to be regarded as illustrative and not restrictive. The scope of the claims should, therefore, be determined by reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. In the appended claims, the terms "comprising" and "in which" are used as simple equivalents of the respective terms "including" and "wherein."Furthermore, in the following claims, the terms "comprising" and "including" are open-ended; a system, device, article, or process that includes elements in addition to those listed after such a term in a claim is still intended to be within the scope of that claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc., are used only as labels and are not intended to impose numerical requirements on their objects.

Claims

[1] A device that includes: a volatile storage element, the volatile storage element including a data true node (DT node) and a data complement node (DC node); and a non-volatile storage circuit, wherein the non-volatile storage circuit comprises at least a first pass transistor connected to the DT node of the volatile storage element, and at least one second pass transistor connected to the DC node of the volatile storage element, wherein the non-volatile storage circuit further includes a plurality of non-volatile storage elements, wherein each non-volatile storage element of the plurality of non-volatile storage elements is configured to be selectively connectable to the DT node of the volatile storage element via the at least one first pass transistor and to be selectively connectable to the DC node of the volatile storage element via the at least one second pass transistor, wherein the plurality of non-volatile storage elements includes two non-volatile storage elements, and the non-volatile storage circuit further includes: a bridge transistor connected to the two non-volatile storage elements, the bridge transistor being configured to selectively connect one of the two non-volatile storage elements to the DT node of the volatile storage element via the at least one first pass transistor and to the DC node of the volatile storage element via the at least one second pass transistor. [2] The device of claim 1, wherein the at least one first pass transistor includes a first group of pass transistors connected in series to the DT node of the volatile storage element, the at least one second pass transistor includes a second group of pass transistors connected in series to the DC node of the volatile storage element, and the plurality of non-volatile storage elements includes at least two non-volatile storage elements connected to the first group of pass transistors and the second group of pass transistors to form a daisy chain of transistors. [3] The device of claim 2, wherein the volatile storage element includes a static random access memory (SRAM), and wherein the chain of transistors is distributed across at least two sides of the SRAM. [4] The device according to claim 3, wherein the chain of transistors is distributed symmetrically on two opposite sides of the SRAM. [5] The device of claim 1, wherein the plurality of storage elements includes a plurality of silicon oxide nitride oxide silicon (SONOS) transistors. [6] The device of claim 1, wherein the non-volatile storage circuit is configured to store a data bit from the volatile storage element in at least two of the plurality of non-volatile storage elements to provide data redundancy to the non-volatile storage circuit. [7] The device of claim 1, wherein the non-volatile storage circuit is configured to store a data bit from the volatile storage element in a first of the plurality of non-volatile storage elements when the device is supplied with power, and the non-volatile storage circuit is further configured to store the data bit from the volatile storage element in a second of the plurality of non-volatile storage elements when the device loses power. [8] The device of claim 1, wherein the non-volatile storage circuit is configured to alternate data storage among the plurality of non-volatile storage elements to increase the lifetime of the non-volatile circuit. [9] A system that includes: a processor; and a non-volatile memory device configured to provide data storage for the processor, the non-volatile memory device including a plurality of non-volatile memory cells, each non-volatile memory cell of the plurality of non-volatile memory cells including: a volatile storage element, the volatile storage element including a data true node (DT node) and a data complement node (DC node); and a non-volatile storage circuit, wherein the non-volatile storage circuit includes at least one first switching element connected to the DT node of the volatile storage element and at least one second switching element connected to the DC node of the volatile storage element, wherein the non-volatile storage circuit further includes a plurality of non-volatile storage elements, wherein each non-volatile storage element of the plurality of non-volatile storage elements is configured to be selectively connectable to the DT node of the volatile storage element via the at least one first switching element and to be selectively connectable to the DC node of the volatile storage element via the at least one second switching element, wherein the plurality of non-volatile storage elements includes two non-volatile storage elements, and the non-volatile storage circuit further includes: a bridge element connected to the two non-volatile storage elements, wherein the bridge element is configured to connect one of the two non-volatile storage elements to the DT node of the volatile storage element via the at least one first switching element and to selectively connect to the DC node of the volatile storage element via the at least one second switching element. [10] The system of claim 9, wherein the at least one first switching element includes a first group of switching elements connected in series to the DT node of the volatile storage element, the at least one second switching element includes a second group of switching elements connected in series to the DC node of the volatile storage element, and the plurality of non-volatile storage elements includes at least two non-volatile storage elements connected to the first group of switching elements and the second group of switching elements to form a daisy chain. [11] The system of claim 10, wherein the chain circuit is distributed across at least two sides of the volatile storage element. [12] The system of claim 9, wherein the volatile storage element includes a static random access memory (SRAM) and the plurality of non-volatile storage elements includes a plurality of silicon oxide nitride oxide silicon (SONOS) transistors. [13] The system of claim 9, wherein the non-volatile storage circuit is configured to store a data bit from the volatile storage element in at least two of the plurality of non-volatile storage elements to provide data redundancy for the particular non-volatile memory cell. [14] The system of claim 9, wherein the non-volatile storage circuit is configured to store a data bit from the volatile storage element in a first of the plurality of non-volatile storage elements when the particular non-volatile storage cell is supplied with power, and the non-volatile storage circuit is further configured to store the data bit from the volatile storage element in a second of the plurality of non-volatile storage elements when the particular non-volatile storage cell loses power. [15] The system of claim 9, wherein the non-volatile storage circuit is configured to alternate data storage among the plurality of non-volatile storage elements to increase the lifetime of the particular non-volatile storage element. [16] A procedure that includes: Establishing a first data storage path between a first non-volatile storage element of a plurality of non-volatile storage elements, wherein the plurality of non-volatile storage elements includes two non-volatile storage elements, and a data true node (DT node) of a volatile storage element; programming the first non-volatile storage element based on data stored in the volatile storage element by using the first data storage path; Establishing a second data storage path between a second non-volatile storage element of the plurality of non-volatile storage elements and the data true (DT) node of the volatile storage element; programming the second non-volatile storage element based on the data stored in the volatile storage element by using the second data storage path; and selectively connecting one of the two non-volatile storage elements via at least a first pass transistor to the DT node of the volatile storage element and via at least a second pass transistor to a DC node of the volatile storage element by means of a bridge transistor connected to the two non-volatile storage elements. [17] The method of claim 16, wherein the second data storage path and the first data storage path share at least one common pass transistor connected to the DT node of the volatile storage element. [18] A method according to claim 16, further comprising: Establishing a first retrieval path between the first non-volatile storage element of the plurality of non-volatile storage elements and a data complement (DC) node of the volatile storage element; retrieving data from the first non-volatile storage element to the volatile storage element using the first retrieval path; Establishing a second retrieval path between the second non-volatile storage element of the plurality of non-volatile storage elements and the data complement (DC) node of the volatile storage element; and Retrieving data from the second non-volatile storage element to the volatile storage element using the second data storage path.

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