Microelectronic structure, method for its manufacture and electronic system

Abstract

A microelectronic structure comprising an active channel (152) made of an indium-containing ternary or higher III-V compound, wherein the active channel (152) made of an indium-containing ternary or higher III-V compound has at least one side surface (1581, 1582) and a bottom surface (156), wherein the at least one side surface (1581, 1582) and the bottom surface (156) have an indium content that is higher than the average indium content of the active channel (152) made of an indium-containing ternary or higher III-V compound.

Description

TECHNICAL FIELD

[0001] Embodiments of the present description relate generally to the field of microelectronic devices, and more particularly to forming an active channel in a microelectronic transistor with indium-rich areas to enhance carrier mobility. background

[0002] Higher performance, lower costs, increased miniaturization of integrated circuit components, and higher packaging density of integrated circuits are current goals of the microelectronics industry for the manufacture of microelectronic devices. To achieve these goals, transistors within microelectronic devices must be downscaled, i.e., made smaller. Along with reducing the size of transistors, another goal has been to improve their efficiency through improvements in their designs, materials used, and / or manufacturing processes. Such design improvements include the development of unique structures, such as non-planar transistors, including tri-gate transistors, FinFETS, TFETS, Omega-FETs, and double-gate transistors.

[0003] US 2015 / 0 243 756 A1 discloses a method for fabricating a finFET. The method includes forming a fin-shaped channel region with indium on a substrate, forming a deep source / drain region adjacent to the channel region on the substrate, and forming a source / drain extension region between the channel region and the deep source / drain region.

[0004] US 2014 / 0 346 564 A1 discloses a field-effect transistor with multiple threshold voltages formed by strain technology. An integrated circuit device includes a first transistor having a first channel region over a first buffer, the first channel region formed of a III-V semiconductor material, and a second transistor having a second channel region over a second buffer, the second channel region formed of the III-V semiconductor material, and the second buffer and the first buffer having a lattice mismatch.

[0005] WO 2015 147 858 A1 discloses a III-V material-based device comprising: a first III-V material-based buffer layer on a silicon substrate; a second III-V material-based buffer layer on the first III-V material-based buffer layer, wherein the second III-V material includes aluminum; and a III-V material-based device channel layer on the second III-V material-based buffer layer.

[0006] WO 2014 209 390 A1 discloses a first buffer layer based on a III-V material that is applied to a silicon substrate. A second buffer layer based on a III-V material is applied to the first buffer layer. A channel layer made of a III-V material is applied to the second buffer layer made of a III-V material.

[0007] US 2015 / 0 093 868 A1 discloses an integrated circuit with fin field-effect transistors and methods for their fabrication. The methods may include forming a fin-shaped channel region comprising germanium on a substrate and forming a source / drain region adjacent to the channel region on the substrate. The methods may further include forming a barrier layer contacting the sidewalls of the channel region and the source / drain region. The barrier layer may contain SiGe1-x, where x may be in a range from about 0.05 to about 0.2.

[0008] EP 3 185 302 A1 discloses a gate all-around semiconductor device and a method for manufacturing a gate all-around semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1-16 are oblique sectional views, side cross-sectional views, and graphical illustrations of the fabrication of an indium-containing ternary or higher III-V compound active channel with a substructure for a non-planar transistor according to another embodiment of the present description. Fig. 17-24 are oblique sectional views and side cross-sectional views of the fabrication of an active channel insulating buffer from an indium-containing ternary or higher III-V compound non-planar transistor according to an embodiment of the present description. Fig. 25 illustrates a computing device according to an implementation of the present description. DESCRIPTION OF EMBODIMENTS

[0009] As used herein, the terms "over," "at," "between," and "on" can refer to a relative position of one layer with respect to other layers. A layer "over" or "on" another layer, or bonded "to" another layer, can be in direct contact with the other layer or can have one or more intermediate layers. A layer "between" layers can be in direct contact with the layers or can have one or more intermediate layers.

[0010] As is known to one skilled in the art, III-V group materials can exhibit higher electron mobility relative to conventional silicon materials commonly used in microelectronic transistor fabrication and therefore have potential for use in high-performance transistors in integrated circuit fabrication. Embodiments of the present description relating to indium-containing ternary or higher III-V compound active channels and processes for fabricating the same enable improved carrier mobility when fabricating ridge-shaped active channels, such as those used in tri-gate or gate-all-around (GAA) devices. In one embodiment, a substructure can be deposited in a narrow trench, and a top surface of the substructure can be reconstructed.An indium-containing ternary or higher III-V compound can then be deposited in narrow trenches to abut the top surface of the substructure, resulting in a fin having indium-rich side surfaces and an indium-rich bottom surface with a gallium-rich central portion. At least one of the indium-rich surfaces can abut a transistor gate oxide, resulting in high electron mobility and improved switching speed relative to conventional homogeneous compositions of indium-containing ternary or higher III-V active channels.

[0011] As in Fig. 1, at least one rib 112 may be formed on a substrate 102, wherein the ribs 112 may have opposite sidewalls 114 extending from a first surface 104 of the substrate 102 and terminating in a top surface 116. For clarity and brevity, Fig. 1 illustrates only two fins 112; however, it should be understood that any suitable number of fins 112 could be formed. In one embodiment, an etch mask (not shown) may be patterned on the substrate 102, followed by etching the substrate 102, wherein the portions of the substrate 102 protected by the etch mask (not shown) become the fins 112, and the etch mask (not shown) may thereafter be removed, as will be readily apparent to one of ordinary skill in the art. In one embodiment of the present disclosure, the substrate 102 and the fins 112 may be any suitable material, including, but not limited to, a silicon-containing material, such as monocrystalline silicon. However, the substrate 102 and the fins 112 do not necessarily have to be formed from silicon-containing materials and may be other types of materials known in the art.In another embodiment, the substrate 102 may comprise a silicon-on-insulator (SOI) substrate, a silicon-on-nothing (SON) substrate, a germanium substrate, a germanium-on-insulator (GeOI) substrate, or a germanium-on-nothing (GeON) substrate.

[0012] As in Fig. As shown in Figure 2, a dielectric material may be deposited over the substrate 102 and the fins 112 by any suitable deposition process, and the dielectric material may be flattened to expose the upper fin surface 116, forming isolation structures 122, known as shallow trench isolation structures, that abut the opposing fin sidewalls 114. The isolation structures 122 may be formed from any suitable dielectric material, including, but not limited to, silicon oxide (SiO2).

[0013] As in Fig. 3, the ridges 112 may be removed, forming a trench 124. The ridges 112 may be removed by any known etching techniques, including, but not limited to, dry etching, wet etching, or combinations thereof. In one embodiment, a portion of each trench 124 may be formed to extend into the substrate 102 either during or after the removal of the ridges 112. This portion of the trench 124 will be referred to as a nucleation trench 132. In one embodiment, the nucleation trench 132 may have a faceting (111), which may facilitate the growth of a III-V material, as will be explained. It is understood that alternative geometries of the nucleation trench 132 may be used. In one embodiment, the narrow trench 124 may have a height H in the range of approximately 50 to 500 nm and a width W in the range of approximately sub-10 nm to approximately 30 nm.

[0014] As in Fig. As shown in Figure 4, a nucleation layer 142 may be formed in the nucleation trench 132. The nucleation layer 142 may be formed by any formation process and may be any suitable material, such as a III-V epitaxial material, including, but not limited to, indium phosphide, gallium phosphide, gallium arsenide, and the like. The nucleation layer 142 may be doped or undoped and formed by epitaxial deposition.

[0015] As in Fig. 5, a partial structure 144 may be formed on the nucleation layer 142 within the trench 124 (see Fig. 4) and a top surface 146 opposite the nucleation layer 142. The substructure 144 may be formed by any known formation process. In one embodiment, the substructure 144 may have a depth D that is approximately 80% of the height H of the trench 124 (see Fig. 3).

[0016] In one embodiment of the present description, substructure 144 may be a III-V high bandgap material including, but not limited to, indium aluminum arsenide, indium phosphide, gallium phosphide, gallium arsenide, gallium arsenide antimonide, aluminum arsenide antimonide, indium aluminum gallium arsenide, indium aluminum gallium phosphide, aluminum gallium arsenide, and the like. For the purposes of the present description, a low bandgap material may be defined as a material having a bandgap less than silicon, and a high bandgap material may be defined as a material having a bandgap greater than silicon.

[0017] The high bandgap material used for substructure 144 can be selected to have the desired conduction band offset with a subsequently formed active channel of an indium-containing ternary or higher III-V compound, which will be effective in excluding electrons from substructure 144, thereby reducing leakage. The high bandgap material can be doped or undoped. In a doped embodiment, the high bandgap material can be doped with a dopant, such as a p-type dopant, including, but not limited to, magnesium, zinc, carbon, beryllium, and the like. In another doped embodiment, substructure 144 can be a channel material selected from the group consisting of indium gallium arsenide, indium arsenide, and indium antimonide.Such a combination of a high bandgap material and dopants may be more effective than a dopant alone in reducing leakage, as long as manufacturing processes result in an acceptably low crystalline concentration, which will be readily apparent to one skilled in the art.

[0018] In one embodiment, the doped substructure 144 may be the same material as the nucleation layer 142, so that few or no lattice defects occur. In other embodiments, the nucleation layer 142 may be graded into the substructure 144, or the material compositions thereof may be graded in concentration from one to another, as will be readily apparent to one skilled in the art.

[0019] In some exemplary embodiments, the substructure 144 may be deposited epitaxially. In some embodiments, a chemical vapor deposition (CVD) process or other suitable deposition technique may be used to deposit or otherwise form the substructure 144. For example, the deposition may be performed by CVD or rapid thermal CVD (RT-CVD), low pressure CVD (LP-CVD), ultra-high vacuum CVD (UHV-CVD), or gas source molecular beam epitaxy (GS-MBE) tools using III-V material compounds, such as combinations of indium, aluminum, arsenic, phosphorus, gallium, antimony, and / or precursors thereof. In one exemplary embodiment, the substructure 144 may be gallium arsenide doped with zinc to achieve zinc concentrations of up to approximately 1E19 atom / cm 3which can result in a resistivity of approximately 5E-3 Ohm-cm (or a corresponding conductivity of up to 200 Mho / cm). In any such embodiments, a precursor bubbler comprising a carrier gas, such as hydrogen, nitrogen, or a noble gas (e.g., the precursor can be diluted to a concentration of approximately 0.1-20%, with the carrier gas being the balance) can be present. In some exemplary cases, an arsenic precursor, such as arsine or tertiary butylarsine, a phosphorus precursor, such as tertiary butylphosphine, a gallium precursor, such as trimethylgallium, and / or an indium precursor, such as trimethylindium, can be present. An etching gas, such as a halogen-based gas, such as hydrogen chloride (HCl), chlorine (Cl), or hydrogen bromide (HBr), can also be present.The basic deposition of the substructure 144 may be possible over a wide range of conditions using a deposition temperature in the range, for example, of between approximately 300°C and 650°C, or in a more specific case, between approximately 400 and 500°C, and a reactor pressure, for example, in the range of approximately 1 Torr to 760 Torr. The carrier and the etchants may each have a flow in the range of between approximately 10 and 300 SCCM (typically, a flow of no more than 100 SCCM is necessary, however, some embodiments may benefit from higher flow rates). In a specific exemplary embodiment, the deposition of the substructure 144 may be carried out at a flow rate ranging between approximately 100 and 1000 SCCM. For in-situ doping with zinc, for example, a bubbler source using diethylzinc (DEZ) may be used (e.g.,Hydrogen gas bubbled through liquid DEC at a flow rate of between approximately 10 and 100 SCCM).

[0020] As in Fig. 6, the substructure 144 may be treated (generically illustrated with arrows 150) to reconstruct the top surface 146 thereof such that indium will migrate to the top surface 146 of the substructure during subsequent formation of an indium-containing active channel from a ternary or higher III-V compound, as will be explained.

[0021] In one embodiment, treatment 150 may be a heat or heating process, wherein substructure 144 may be exposed to a temperature of between approximately 500°C and 800°C for a period of between approximately 30 seconds and 25 minutes. In a specific embodiment, the temperature of the heating process may be approximately 750°C.

[0022] In another embodiment, treatment 150 may include exposing the top surface 146 of the substructure to an etchant. In one embodiment, the etchant may include tetramethylammonium hydroxide and similar chemicals.

[0023] Fig. 7 and Fig. 8 illustrate another embodiment of the treatment 150 (see Fig. 6). As in Fig. 7, the partial structural material 144 m be formed in such a way that it fills the trench 124 (see Fig. 4), wherein any portion of the substructure material 144 m which is not located within trench 124 (see Fig. 4), can be removed, such as with chemical-mechanical polishing. As in Fig. 8, the partial structural material 144 m (see Fig. 7) are etched down to the depth D to form the substructure 144. The etching of the substructure material 144 m (see Fig. 7) will form a reconstructed upper surface 146 of the substructure for the substructure 144.

[0024] In one embodiment, the treatment 150 of the upper surface 146 of the substructure may be based on a predominant <111> Lattice structure to a predominant <100> reconstruct. The term "predominantly" is defined to mean that the said lattice arrangement is more strongly present at the upper surface 146 of the substructure than any other lattice arrangement.

[0025] The present specification will hereinafter describe the formation of an indium gallium arsenide active channel (referred to as element 152); however, the active channel is not so limited, as it may be formed from any suitable indium-containing ternary or higher III-V compound. In one embodiment, the indium-containing ternary or higher III-V compound may comprise one of indium gallium arsenide, indium gallium antimonide, indium gallium arsenide antimonide, indium gallium phosphide, indium gallium arsenide phosphide, indium gallium antimonide phosphide, and indium gallium arsenide antimonide phosphide.

[0026] As in Fig. 9 and Fig. 10, an active indium gallium arsenide channel 152 may be formed on the substructure 144 within the trench 124 (see Fig. 4). In some embodiments, a chemical vapor deposition (CVD) process or other suitable deposition technique may be used to deposit or otherwise form the active channel 152. For example, the deposition may be performed by CVD or rapid thermal CVD (RT-CVD) or low pressure CVD (LP-CVD) or ultra-high vacuum CVD (UHV-CVD) or gas source molecular beam epitaxy (GS-MBE) tools using indium, gallium, and arsenic and / or precursors thereof. In a specific such exemplary embodiment, the active channel 152 may be undoped indium gallium arsenide, and the nucleation layer 142 and the doped substructure 144 may be gallium arsenide or indium phosphide. In any such embodiments, a precursor bubbler may be formed with a carrier gas, such as hydrogen, nitrogen, or a noble gas (e.g.,The precursor may be diluted to a concentration of approximately 0.1-20%, with the carrier gas being the balance. In some cases, an indium precursor, such as trimethylindium, a gallium precursor, such as trimethylgallium, and / or an arsenic precursor, such as arsine or tertiary butylarsine, may be present. An etching gas, such as a halogen-based gas such as hydrogen chloride (HCl), chlorine (Cl), or hydrogen bromide (HBr), may also be present. The basic deposition of the active indium gallium arsenide channel 152 may be possible over a wide range of conditions using a deposition temperature in the range, for example, of between approximately 300°C and 650°C, or in a more specific case, of between approximately 400 and 600°C, and a reactor pressure, for example, in the range of approximately 1 Torr to 760 Torr.The carrier and etchants may each have a flow rate ranging between approximately 10 and 300 SCCM (typically, a flow of no more than 100 SCCM is necessary, however, some embodiments may benefit from higher flow rates). In a specific exemplary embodiment, the deposition of the active channel 152 may be performed at a flow rate ranging between approximately 100 and 1000 SCCM.

[0027] The formation of the nucleation layer 142, the substructure 144 and the active indium gallium arsenide channel 152 may occur in a relatively narrow trench 124. In one embodiment, the doped substructure 144 may have a depth D (e.g., the distance between the substrate 102 and the active indium gallium arsenide channel 152 (see Fig. 3)) of more than about 50nm and a width of less than about 25nm (ie, the trench width W (see Fig. 3)). Furthermore, the formation of the nucleation layer 142, the substructure 144, and the active channel 152 takes place in a relatively narrow trench 124. The lattice imbalance between the substrate 102 and the nucleation layer 142 / substructure 144 may be greater than that which allows a substantially defect-free formation, so that the nucleation layer 142 / substructure 144 may be formed such that it has a sufficient depth D to accommodate defects, such as stacking faults, dislocations, and the like, away from the active indium gallium arsenide channel 152, which will be immediately apparent to one skilled in the art. Thus, it is possible that the electron mobility in the active channel 152 is not significantly impaired as a result.

[0028] How to continue in Fig. 9 and Fig. 10, a portion 154 of the active indium gallium arsenide channel 152 may extend out of the trench 124 (see Fig. 4), especially when epitaxial growth processes are used. With the deposition conditions explained above, the active indium gallium arsenide channel 152 can be grown in the narrow trench 124 (see Fig. 4) that the breeding area is self-assembled into a long “hut shape” with <111> upper lattice surfaces or "elongated hut-like growth" of section 154 is faceted. The described process conditions serve to create this faceted growth, which allows sufficient migration of adsorbed atoms, thereby achieving this low-energy surface shape, as one skilled in the art will understand. It has been found that the energetics of uptake of gallium differs from that of uptake of indium with regard to a natural tendency for preferential uptake of gallium along the central region, while indium is preferentially uptaken at the edges, for example, indium-rich side surfaces 1581 and 1582 of the active indium gallium arsenide channel 152. In particular, the temperature and precursor fluxes can be tuned to control the sharpness of the hut roof structure, i.e., of the portion 154 of the active indium gallium arsenide channel 152 extending out of the trench 124 (see . Fig. 4) and thus achieves the concentration profile that is Fig. 10. For weakly faceted growth conditions, such as those obtained with a lower temperature, e.g., approximately 580 °C, and high metal species precursor fluxes, the effect can be limited to wide trenches, such as with a width of approximately 30 nm. By increasing the process temperature to 580 °C, for example, and / or the metal species precursor fluxes, faceting can be improved and the effect can extend to narrower trenches with a width of, for example, 15 nm. It is believed that the effect can also be directed to trenches with a width of sub-10 nm.

[0029] As in Fig. 10, the process of the present description results in the migration of indium to opposite sidewall surfaces of the active indium gallium arsenide channel 152 adjacent to the isolation structures 122, thereby forming indium-rich side surfaces 1581 and 1582, and results in the reconstruction of the top surface 146 of the substructure (see Fig. 9) to the migration of indium to the upper surface 146 of the substructure (see Fig. 9) to form an indium-rich lower surface 156. The distribution of indium is in Fig. 10, where the indium has a darker hatching. The indium distribution of the active indium gallium arsenide channel 152 from one side to the other is shown in Fig. 11, where the X-axis is the distance from one indium-rich facet 1581 to the opposite indium-rich facet 1582 of the active indium gallium arsenide channel 152, and the Y-axis is the concentration in percent of indium (black dashed line) and gallium (white dashed line) over the X-axis distance (in nanometers). A central region 158 c may be located approximately at a midline between one indium-rich facet 1581 and the opposite indium-rich facet 1582. A line for arsenic is not shown for clarity and accuracy, but forms the remainder of the material within the active indium gallium arsenide channel 152.

[0030] The indium distribution of the active indium gallium channel 152 from top to bottom is shown in Fig. 12, where the X-axis is the distance from a top or apex region "A" of the indium gallium arsenide active channel 152, through the indium gallium active channel portion 154 (labeled "P"), through the remainder of the indium gallium arsenide active channel 152 (labeled "AC"), through the indium-rich bottom surface 156 near the interface "I," and into the substructure 144 (labeled "SS"), and the Y-axis is the concentration in percent of indium (black dashed line) and gallium (white dashed line) over the X-axis distance (in nanometers). A line for arsenic is not shown for clarity and accuracy, but constitutes the remainder of the material within the indium gallium active channel 152.

[0031] As in Fig. As can be seen in Figures 10-12, the term “indium-rich” refers to an indium content that is higher than an average amount of indium in the active indium gallium arsenide channel 152. A medium region 158 c , approximately at a centerline between one indium-rich side surface 1581 and the opposite indium-rich side surface 1582, may be "gallium-rich" with respect to the average amount of gallium in the active indium gallium arsenide channel 152.

[0032] When forming a doped substructure 144, the fabrication processes following the formation of the indium gallium arsenide active channel 152 should be carried out at relatively low temperatures (e.g., a low heat budget) to prevent the doped atoms from diffusing from the doped substructure 144 into the active channel 152 and impairing the electron mobility thereof. However, it is possible that easier diffusion (less than approximately 1E17 atoms / cm 3 ) of the p-type dopant from the doped substructure 144 into the active channel 152 is not a problem, since the deposited condition thereof may easily be an n-type, and thus may require a slight p-type counter-doping for compensation, which will be immediately apparent to one skilled in the art.

[0033] As in Fig. 13 and Fig. 14, section 154 (see Fig. 9) of the active indium gallium arsenide channel 152, such as by chemical-mechanical planarization.

[0034] As in Fig. 15, the isolation structures 122 may be recessed, such as through an etch process, such that the active indium gallium arsenide channel 152 extends above an upper level 126 of the isolation structures 122. In one embodiment, the isolation structures 122 may be recessed to slightly below the active indium gallium arsenide channel 152 such that a portion of the substructure 144 is exposed.

[0035] As in Fig. 16, at least one gate 160 may be formed over the portion of the indium gallium arsenide active channel 152 that extends above the isolation structures 122. The gate 160 may be formed by forming a gate dielectric layer 162 on or adjacent to the upper fin surface 116 and on or adjacent to the pair of laterally opposed fin sidewalls 114 and forming a gate electrode 164 on or adjacent to the gate dielectric layer 162, either by a gate-first or a gate-last process flow, as will be readily understood by one of ordinary skill in the art.

[0036] The gate dielectric layer 162 may be formed from any well-known gate dielectric material, including, but not limited to, silicon dioxide (SiO2), silicon oxynitride (SiO x N y), silicon nitride (Si3N4), and high-K dielectric materials such as hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The gate dielectric layer 162 may be formed by well-known techniques, such as depositing a gate electrode material, such as chemical vapor deposition (“CVD”), physical vapor deposition (“PVD”), or atomic layer deposition (“ALD”), and then patterning the gate electrode material using well-known photolithography and etching techniques, as will be readily understood by those skilled in the art.

[0037] The gate electrode 164 may be formed from any suitable gate electrode material. In one embodiment of the present disclosure, the gate electrode 164 may be formed from materials including, but not limited to, polysilicon, tungsten, ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, aluminum, titanium carbide, zirconium carbide, tantalum carbide, hafnium carbide, aluminum carbide, other metal carbides, metal nitrides, and metal oxides. The gate electrode 164 may be formed using well-known techniques, such as by depositing a gate electrode material over the entire surface and then patterning the gate electrode material using well-known photolithography and etching techniques, as will be readily apparent to those skilled in the art.

[0038] During operation of a microelectronic transistor, carriers shift in a surface area of the active channel that is closest to the gate oxide, which will be immediately apparent to one skilled in the art. Thus, with appropriate targeting, the active channel can be defined in the indium-rich regions of the active indium gallium arsenide channel 152. Furthermore, one skilled in the art understands that active indium gallium arsenide channels that are indium-rich have a smaller band gap and a higher mobility relative to active indium gallium arsenide channels that are gallium-rich. Thus, the fact that the indium-rich side surfaces 1581 and 1582 (see Fig. 14), which is connected to the gate oxide 162 ( Fig. 16) and the indium-rich lower surface 156 (see Fig. 14), which is close to the gate oxide 162 ( Fig. 16) lead to high electron mobility and improve the electrostatics with regard to the ability to turn a transistor on and off, i.e., lead to faster switching and less off-state leakage. The presence of an indium gallium arsenide active channel 152 with the indium-rich side surfaces 1581, 1582 and the indium-rich bottom surface 156 may be advantageous over an indium gallium arsenide active channel having a homogeneously high indium content, since the indium concentration has a strong expansion effect on a lattice constant. Thus, when indium is increased beyond a critical limit, the density of mismatched dislocations and other planar defects and point defects increases. As will be understood, these defects are incompatible with transistor requirements regarding carrier mobility or trapped and mobile charges.Thus, by having an indium content graded with the indium-rich regions located at the side surfaces 1581, 1582 and the bottom surface 156, the embodiments of the present description will result in lower defect densities than a device having an equivalent homogeneous concentration profile.

[0039] It is understood that a source region and a drain region (not shown) may be formed in the active indium gallium arsenide channel 152 on opposite sides of the gate 160, or a portion of the active indium gallium arsenide channel 152 on opposite sides of the gate 160 may be removed and the source and drain regions formed instead. The source and drain regions may be formed of the same conductivity type, such as n-type conductivity. In some implementations of an embodiment of the present disclosure, the source and drain regions may have substantially the same doping concentration and profile, while they may vary in other implementations. It is understood that only n-MOS regions are shown; p-MOS regions would be patterned and processed separately.

[0040] Fig. 17-24 illustrate additional embodiments of the present description. Starting with Fig. 16, a replacement gate process may be followed, wherein the gate dielectric 162 and the gate electrode 164 may be formed from sacrificial materials. A dielectric layer 172 may be deposited over the structure of Fig. 17 and planarized to expose the sacrificial gate electrode 164, as shown in Fig. 18. The sacrificial gate electrode 164 and the gate dielectric 162 may be removed to expose the active indium gallium arsenide channel 152 and a portion of the substructure 144 (for effective etching) between the remaining portions of the gate spacer 166 to form an exposed active channel region 152, as shown in Fig. 19 and Fig. 20 (cross-sectional view along line 20-20 of Fig. 19 (shown only with cross-sectional structures).

[0041] As in Fig. 21, the substructure 144 and the nucleation layer 142 may be removed, such as by a targeted etch (e.g., wet etching, dry etching, or a combination thereof). A dielectric material 176 may be deposited to fill the space left by the removal of the substructure 144 (see Fig. 20) and the nucleation layer 142 (see Fig. 20) was left as in Fig. 22, or to form an empty space 178, as shown in Fig. 23. Thereafter, the remaining components of a transistor can be formed following a known processing flow, such as a tri-gate processing flow, which will be readily apparent to those skilled in the art. In another embodiment, as shown in Fig. 24, a gate oxide layer 182 may be formed to surround the exposed active channel 152, and a gate electrode layer 184 may be formed to surround the gate oxide layer 182, and the remaining components of a transistor may follow a known gate-all-around processing flow in single or multiple wire configurations, which will also be readily apparent to one skilled in the art.

[0042] Fig. 25 illustrates a computing device 200 according to an implementation of the present description. Computing device 200 houses a circuit board 202. Circuit board 202 may include a number of components, including, but not limited to, a processor 204 and at least one communication chip 206A, 206B. Processor 204 is physically and electrically coupled to circuit board 202. In some implementations, the at least one communication chip 206A, 206B is also physically and electrically coupled to circuit board 202. In other implementations, communication chip 206A, 206B is part of processor 204.

[0043] Depending on its applications, computing device 200 may include other components that may or may not be physically and electrically coupled to circuit board 202. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a GPS device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard disk drive, a compact disk (CD), a digital versatile disk (DVD), and so on).

[0044] The communication chip 206A, 206B enables wireless communications for transferring data to and from the computing device 200. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although this may be the case in some embodiments. The communication chip 206 can implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designed as 3G, 4G, 5G, and beyond. Computing device 200 may include multiple communication chips 206A, 206B. For example, a first communication chip 206A may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip 206B may be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0045] The processor 204 of the computing device 200 may include microelectronic transistors, as previously described. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory. Furthermore, the communication chip 206A, 206B may include microelectronic transistors fabricated as previously described.

[0046] In various implementations, computing device 200 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device 200 may be any other electronic device that processes data.

[0047] It is understood that the subject matter of the present description is not necessarily limited to specific applications that are Fig.1-25. The subject invention may be applied to other microelectronic device and assembly applications, as well as any other suitable transistor applications, as will be readily apparent to one skilled in the art.

[0048] The following examples are further embodiments, wherein Example 1 is a microelectronic structure comprising an indium-containing ternary or higher III-V compound active channel, wherein the indium-containing ternary or higher III-V compound active channel has at least one side surface and a bottom surface, wherein the at least one side surface and the bottom surface have an indium content that is higher than the average indium content of the indium-containing ternary or higher III-V compound active channel.

[0049] In Example 2, the subject invention according to Example 1 can optionally comprise the active channel made of an indium-containing ternary or higher III-V compound comprising one of indium gallium arsenide, indium gallium antimonide, indium gallium arsenide antimonide, indium gallium phosphide, indium gallium arsenide phosphide, indium gallium antimonide phosphide and indium gallium arsenide antimonide phosphide.

[0050] In Example 3, the subject matter of the invention according to Example 1 can optionally comprise the active channel made of an indium-containing ternary or higher III-V compound comprising a rib.

[0051] In Example 4, the subject matter of the invention according to Example 1 may optionally comprise a substrate over which the active channel is formed from an indium-containing ternary or higher III-V compound.

[0052] In Example 5, the subject matter of Example 4 can optionally comprise the indium-containing ternary or higher III-V compound active channel comprising a rib having a pair of opposing surfaces, each of the surfaces having an indium content higher than the average indium content of the indium-containing ternary or higher III-V compound active channel, and the opposing surfaces of the rib being substantially perpendicular to a first surface of the substrate.

[0053] In Example 6, the subject matter of Example 4 may optionally comprise a substructure formed between the active channel of an indium-containing ternary or higher III-V compound and the substrate, wherein the substructure abuts the lower surface of the active channel of an indium-containing ternary or higher III-V compound.

[0054] In Example 7, the subject matter of Example 6 may optionally have the partial structure comprising a dopant and a channel material selected from the group consisting of indium gallium arsenide, indium arsenide, and indium antimonide.

[0055] In Example 8, the subject matter of Example 6 may optionally have the partial structure comprising a material selected from the group consisting of indium aluminum arsenide, indium phosphide, gallium phosphide, gallium arsenide, gallium arsenide antimonide, aluminum arsenide antimonide, indium aluminum gallium arsenide, indium aluminum gallium phosphide, and aluminum gallium arsenide.

[0056] In Example 9, the subject matter of the invention according to Example 8 may optionally comprise a dopant.

[0057] In Example 10, the subject matter of Example 7 or 9 may optionally comprise the dopant comprising a p-type dopant.

[0058] In Example 11, the subject matter of Example 10 may optionally comprise the dopant selected from the group consisting of magnesium, zinc, carbon, and beryllium.

[0059] In Example 12, the subject matter of Example 4 may optionally comprise an insulating buffer formed between the active channel of an indium-containing ternary or higher III-V compound and the substrate.

[0060] In Example 13, the subject matter of Example 12 may optionally include the insulating buffer comprising an insulating material.

[0061] In Example 14, the subject matter of Example 12 can optionally include the insulating buffer comprising an empty space.

[0062] In Example 15, the subject matter of Example 4 may optionally comprise a nucleation trench extending into the substrate and a nucleation layer abutting the nucleation trench.

[0063] In Example 16, the subject matter of Example 15 may optionally comprise the nucleation trench comprising a nucleation trench that <111> has a faceting.

[0064] In Example 17, the subject matter of Example 15 may optionally comprise the nucleation layer comprising a material selected from the group consisting of indium phosphide, gallium phosphide, and gallium arsenide.

[0065] The following examples are among further embodiments, with Example 18 being a method of fabricating a microelectronic structure comprising forming at least one fin on a substrate, the at least one fin comprising a pair of opposing sidewalls extending from the substrate; forming insulating structures abutting each of the fin sidewalls; forming a trench by removing the at least one fin; forming a substructure in the trench, the substructure having an exposed top surface; treating the substructure to reconstruct the top surface of the substructure;and forming an indium-containing ternary or higher III-V compound active channel within the trench, wherein side surfaces of the indium-containing ternary or higher III-V compound active channel abut the trench and have an indium content higher than the average indium content of the indium-containing ternary or higher III-V compound active channel, and wherein the indium-containing ternary or higher III-V compound active channel has a bottom surface abutting the top surface of the substructure, wherein the indium-containing ternary or higher III-V compound active channel has an indium content higher than the average indium content of the indium-containing ternary or higher III-V compound active channel;

[0066] In Example 19, the subject matter of Example 18 can optionally comprise forming the active channel from an indium-containing ternary or higher III-V compound comprising one of indium gallium arsenide, indium gallium antimonide, indium gallium arsenide antimonide, indium gallium phosphide, indium gallium arsenide phosphide, indium gallium antimonide phosphide, and indium gallium arsenide antimonide phosphide.

[0067] In Example 20, the subject matter of Example 18 can optionally comprise treating the substructure to reconstruct the top surface of the substructure, which comprises heating the substructure.

[0068] In Example 21, the subject matter of claim 20 may optionally comprise heating the substructure to a temperature of between about 500°C and 800°C for a time period of between about 30 seconds and 25 minutes.

[0069] In Example 22, the subject matter of Example 18 can optionally comprise treating the substructure to reconstruct the upper surface of the substructure, which comprises etching the upper surface of the substructure with an etchant.

[0070] In Example 23, the subject matter of Example 22 may optionally comprise etching the upper surface of the substructure with tetramethylammonium hydroxide.

[0071] In Example 24, the subject matter of Example 18 can optionally comprise forming the substructure in the trench comprising filling the trench with a substructure material and etching the substructure material to a predetermined depth in the trench forming a reconstructed upper surface of the substructure.

[0072] In Example 25, the subject matter of Example 24 may optionally comprise etching the partial structure material with tetramethylammonium hydroxide.

[0073] In Example 26, the subject matter of Example 18 can optionally comprise forming the substructure, which comprises forming the substructure including a dopant and a channel material selected from the group consisting of indium gallium arsenide, indium arsenide, and indium antimonide.

[0074] In Example 27, the subject matter of Example 18 can optionally comprise forming the substructure comprising forming the substructure from a material selected from the group consisting of indium aluminum arsenide, indium phosphide, gallium phosphide, gallium arsenide, gallium arsenide antimonide, aluminum arsenide antimonide, indium aluminum gallium arsenide, indium aluminum gallium phosphide, and aluminum gallium arsenide.

[0075] In Example 28, the subject matter of Example 27 may optionally comprise forming the partial structure with a dopant.

[0076] In Example 29, the subject matter of Example 26 or 28 may optionally comprise the dopant comprising a p-type dopant.

[0077] In Example 30, the subject matter of Example 29 can optionally comprise forming the partial structure with a p-type dopant selected from the group consisting of magnesium, zinc, carbon, and beryllium.

[0078] In Example 31, the subject matter of Example 18 may optionally comprise forming an insulating buffer between the active channel of an indium-containing ternary or higher III-V compound and the substrate.

[0079] In Example 32, the subject matter of Example 31 can optionally include forming the insulating buffer comprising an insulating material.

[0080] In Example 33, the subject matter of Example 31 can optionally include forming the insulating buffer comprising an empty space.

[0081] In Example 34, the subject matter of Example 18 can optionally comprise forming a nucleation trench extending into the substrate and forming a nucleation layer abutting the nucleation trench.

[0082] In Example 35, the subject matter of Example 34 may optionally comprise forming the nucleation trench, which comprises forming a nucleation trench that <111> includes faceting.

[0083] In Example 36, the subject matter of Example 34 can optionally comprise forming the nucleation layer from a material selected from the group consisting of indium phosphide, gallium phosphide, and gallium arsenide.

[0084] The following examples are further embodiments, with Example 37 being an electronic system comprising a circuit board; and a microelectronic device attached to the circuit board, the microelectronic device comprising at least one transistor comprising an indium-containing ternary or higher III-V compound active channel, the indium-containing ternary or higher III-V compound active channel having at least one side surface and a bottom surface, the at least one side surface and the bottom surface having an indium content that is higher than the average indium content of the indium-containing ternary or higher III-V compound active channel.

[0085] In Example 38, the subject matter of Example 37 can optionally comprise the active channel of an indium-containing ternary or higher III-V compound comprising one of indium gallium arsenide, indium gallium antimonide, indium gallium arsenide antimonide, indium gallium phosphide, indium gallium arsenide phosphide, indium gallium antimonide phosphide, and indium gallium arsenide antimonide phosphide.

[0086] In Example 39, the subject matter of Example 37 may optionally comprise a substrate over which the active channel is formed from an indium-containing ternary or higher III-V compound.

[0087] In Example 40, the subject matter of Example 39 may optionally comprise a substructure formed between the indium-containing ternary or higher III-V compound active channel and the substrate, wherein the substructure abuts the bottom surface of the indium-containing ternary or higher III-V compound active channel.

[0088] In Example 41, the subject matter of Example 40 may optionally have the partial structure comprising a dopant and a channel material selected from the group consisting of indium gallium arsenide, indium arsenide, and indium antimonide.

[0089] In Example 42, the subject matter of Example 40 can optionally have the partial structure comprising a material selected from the group consisting of indium aluminum arsenide, indium phosphide, gallium phosphide, gallium arsenide, gallium arsenide antimonide, aluminum arsenide antimonide, indium aluminum gallium arsenide, indium aluminum gallium phosphide, and aluminum gallium arsenide.

[0090] In Example 43, the subject matter of Example 42 may optionally comprise a dopant.

[0091] In Example 44, the subject matter of Example 41 or 43 may optionally comprise the dopant comprising a p-type dopant.

[0092] In Example 45, the subject matter of Example 44 may optionally comprise the dopant selected from the group consisting of magnesium, zinc, carbon, and beryllium.

Claims

[1] A microelectronic structure comprising an indium-containing ternary or higher III-V compound active channel (152), the indium-containing ternary or higher III-V compound active channel (152) having at least one side surface (1581, 1582) and a bottom surface (156), the at least one side surface (1581, 1582) and the bottom surface (156) having an indium content that is higher than the average indium content of the indium-containing ternary or higher III-V compound active channel (152). [2] The microelectronic structure of claim 1, wherein the indium-containing ternary or higher III-V compound active channel (152) comprises one of indium gallium arsenide, indium gallium antimonide, indium gallium arsenide antimonide, indium gallium phosphide, indium gallium arsenide phosphide, indium gallium antimonide phosphide, and indium gallium arsenide antimonide phosphide. [3] The microelectronic structure of claim 1, wherein the active channel (152) of an indium-containing ternary or higher III-V compound comprises a rib (122). [4] The microelectronic structure of claim 1, further comprising a substrate (102) over which the active channel (152) is formed from an indium-containing ternary or higher III-V compound. [5] The microelectronic structure of claim 4, wherein the indium-containing ternary or higher III-V compound active channel (152) comprises a rib (122) having a pair of opposed side surfaces (1581, 1582), and wherein each of the side surfaces (1581, 1582) has an indium content higher than the average indium content of the indium-containing ternary or higher III-V compound active channel (152), and wherein the opposed side surfaces (1581, 1582) of the rib (122) are substantially perpendicular to a first surface of the substrate (102). [6] The microelectronic structure of claim 4, further comprising a substructure (144) formed between the indium-containing ternary or higher III-V compound active channel (152) and the substrate (102), the substructure (144) abutting the bottom surface of the indium-containing ternary or higher III-V compound active channel (152). [7] The microelectronic structure of claim 6, wherein the substructure (144) comprises a dopant and a channel material selected from the group consisting of indium gallium arsenide, indium arsenide, and indium antimonide. [8] The microelectronic structure of claim 6, wherein the substructure (144) comprises a material selected from the group consisting of indium aluminum arsenide, indium phosphide, gallium phosphide, gallium arsenide, gallium arsenide antimonide, aluminum arsenide antimonide, indium aluminum gallium arsenide, indium aluminum gallium phosphide, and aluminum gallium arsenide. [9] The microelectronic structure of claim 8, further comprising a dopant. [10] A method of manufacturing a microelectronic structure, comprising: Forming at least one rib (112) on a substrate (102), the at least one rib (112) comprising a pair of opposing sidewalls extending from the substrate (102); forming insulating structures (122) abutting each of the rib side walls; Forming a trench (124) by removing the at least one rib (112); Forming a substructure in the trench (124), the substructure (144) having an exposed upper surface; Treating the substructure (144) to reconstruct the upper surface of the substructure (144); Forming an active channel (152) from an indium-containing ternary or higher III-V compound within the trench (124), wherein side surfaces (1581, 1582) of the active channel (152) from an indium-containing ternary or higher III-V compound abut the trench (124) and have an indium content that is higher than the average indium content of the active channel (152) from an indium-containing ternary or higher III-V compound, and wherein the active channel (152) from an indium-containing ternary or higher III-V compound has a lower surface that abuts the upper surface of the substructure (144), wherein the lower surface of the active channel (152) from an indium-containing ternary or higher III-V compound has an indium content that is higher than the average indium content of the active channel (152) from an indium-containing ternary or higher III-V compound. [11] The method of claim 10, wherein forming an active channel (152) from an indium-containing ternary or higher III-V compound comprises forming the active channel (152) from an indium-containing ternary or higher III-V compound of one of indium gallium arsenide, indium gallium antimonide, indium gallium arsenide antimonide, indium gallium phosphide, indium gallium arsenide phosphide, indium gallium antimonide phosphide, and indium gallium arsenide antimonide phosphide. [12] The method of claim 10, wherein treating the substructure (144) to reconstruct the upper surface of the substructure (144) comprises heating the substructure (144). [13] The method of claim 12, wherein heating the substructure (144) comprises heating the substructure (144) to a temperature of between about 500°C and 800°C for a period of time between about 30 seconds and 25 minutes. [14] The method of claim 10, wherein treating the substructure (144) to reconstruct the upper surface of the substructure (144) comprises etching the upper surface of the substructure (144) with an etchant. [15] The method of claim 14, wherein etching the upper surface of the substructure (144) with an etchant comprises etching the upper surface of the substructure (144) with tetramethylammonium hydroxide. [16] The method of claim 10, wherein forming the substructure (144) in the trench (124) comprises filling the trench (124) with a substructure material and etching the substructure material to a predetermined depth in the trench (124) forming a reconstructed upper surface of the substructure (144). [17] The method of claim 16, wherein etching the substructure material comprises etching the substructure material with tetramethylammonium hydroxide. [18] The method of claim 10, wherein forming the substructure (144) comprises forming the substructure (144) including a dopant and a channel material selected from the group consisting of indium gallium arsenide, indium arsenide, and indium antimonide. [19] The method of claim 10, wherein forming the substructure (144) comprises forming the substructure (144) from a material selected from the group consisting of indium aluminum arsenide, indium phosphide, gallium phosphide, gallium arsenide, gallium arsenide antimonide, aluminum arsenide antimonide, indium aluminum gallium arsenide, indium aluminum gallium phosphide, and aluminum gallium arsenide. [20] Electronic system comprising: a circuit board (202); and a microelectronic device attached to the board (202), the microelectronic device having at least one transistor (160) comprising an indium-containing ternary or higher III-V compound active channel (152), the indium-containing ternary or higher III-V compound active channel (152) having at least one side surface (1581, 1582) and a bottom surface, the at least one side surface (1581, 1582) and the bottom surface having an indium content that is higher than the average indium content of the indium-containing ternary or higher III-V compound active channel (152). [21] The electronic system of claim 20, wherein the indium-containing ternary or higher III-V compound active channel (152) comprises one of indium gallium arsenide, indium gallium antimonide, indium gallium arsenide antimonide, indium gallium phosphide, indium gallium arsenide phosphide, indium gallium antimonide phosphide, and indium gallium arsenide antimonide phosphide. [22] The electronic system of claim 20, further comprising a substrate (102) over which the active channel (152) is formed from an indium-containing ternary or higher III-V compound. [23] The electronic system of claim 22, further comprising a substructure (144) formed between the indium-containing ternary or higher III-V compound active channel (152) and the substrate, the substructure (144) abutting the bottom surface of the indium-containing ternary or higher III-V compound active channel (152). [24] The electronic system of claim 23, wherein the substructure (144) comprises a dopant and a channel material selected from the group consisting of indium gallium arsenide, indium arsenide, and indium antimonide. [25] The electronic system of claim 23, wherein the substructure (144) comprises a material selected from the group consisting of indium aluminum arsenide, indium phosphide, gallium phosphide, gallium arsenide, gallium arsenide antimonide, aluminum arsenide antimonide, indium aluminum gallium arsenide, indium aluminum gallium phosphide, and aluminum gallium arsenide.

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