Semiconductor structure

Abstract

Semiconductor structure including: a semiconductor fin section (14L, 14R) which has an end wall (15W) and extends upwards from a substrate (10, 12), a gate structure (16L, 16R) extending over a section of the semiconductor fin section, a first set of gate spacers (24P) located on opposite sidewall surfaces of the gate structure, and a second set of gate spacers (32P) located on outer side walls of the first gate spacers, wherein a gate spacer of the second set of gate spacers has an inner side wall surface with an upper section that directly contacts the outer side wall of one of the gate spacers of the first set of gate spacers, wherein in the second set of gate spacers only one gate spacer (32P) of the second set of gate spacers has a lower section that completely covers and directly contacts a side wall of the end wall (15W) of the semiconductor fin section (14L, 14R), and wherein another gate spacer (32P) of the second set of gate spacers extends over another section of the semiconductor fin section (14L, 14R).

Description

Technical field

[0001] The present application relates to a semiconductor structure comprising semiconductor fins and methods for forming them. Embodiments of the present invention relate to a semiconductor structure comprising semiconductor fin tips (for example, ends) positioned in a self-aligned manner within a gate structure. background

[0002] For more than three decades, the progressive miniaturization of metal-oxide-semiconductor field-effect transistors (MOSFETs) has defined the global semiconductor industry. Various breakthroughs in advanced scaling have been predicted for decades, yet a history of innovation has upheld Moore's Law despite numerous challenges. Nevertheless, there are now increasing indications that metal-oxide-semiconductor transistors are reaching their traditional scaling limits. As it becomes increasingly difficult to improve MOSFET, and consequently metal-oxide-semiconductor (CMOS), performance through progressive scaling, other methods for improving performance beyond scaling have become important.

[0003] The use of non-planar semiconductors, such as semiconductor fin field-effect transistors (FinFETs), is the next step in the evolution of CMOS devices. FinFETs are non-planar semiconductor devices that include at least one semiconductor fin protruding from the surface of the substrate. FinFETs can increase the current per unit area compared to a planar field-effect transistor.

[0004] In the prior art, semiconductor fins are first prepared and then cut using a structuring process. Gate structures are then formed that span each of the cut semiconductor fins, and subsequently, gate spacers are formed. In such processing, the semiconductor fin tips (e.g., the ends of cut semiconductor fins) are positioned under one of the gate structures, and there is typically a gate spacer that does not physically cover the semiconductor fin tip. Any error in the relative positioning of the gate with respect to the fin tip can result in a gate spacer that does not physically cover the semiconductor fin tip. During this process, and during the formation of source and drain regions by epitaxial growth, a rogue epitaxial semiconductor material fraction can form from the uncovered semiconductor fin tip.This problem becomes more pronounced as the critical dimensions (CDs) of the gate structures and gate distances become smaller and smaller.

[0005] In addition to the above, processing according to the state of the art when positioning the semiconductor fins under a gate structure can produce free surfaces that relax prestressed substrates and thus reduce mobility improvements.

[0006] Document US 2015 / 0076610A1 discloses a transistor comprising: a first fin arranged on a first region of a substrate, a second fin arranged on a second region of the substrate and spaced apart from the first fin, a gate structure arranged on the first fin, a first source / drain (S / D) terminal on the first fin adjacent to a first vertical side of the first gate structure, and a second S / D terminal on the second fin, wherein the first region of the substrate comprises a first subregion doped with a first concentration of dopant atoms of a first conductivity type, a second subregion doped with a second concentration of dopant atoms of a second conductivity type, and the second region of the substrate comprises a third subregion doped with the second concentration of dopant atoms of the second conductivity type.

[0007] Document WO 2015 / 047 281 A1 discloses a semiconductor device comprising: a semiconductor rib arranged over a substrate and having a recessed and a top section, a source region arranged in the recessed area of ​​the semiconductor rib, a drain region in the top section of the semiconductor rib, and a gate electrode arranged over the top section of the semiconductor rib between the source and drain regions.

[0008] Document US 2007 / 0145451A1 describes a semiconductor device comprising: an active region comprising a surface region and a first recess formed below the surface region, the active region extending in a first direction; a device insulation structure provided at an edge of the active region; a gate line traversing the surface region of the active region in a second direction orthogonal to the first direction; a second recess in the device's insulation structure to accommodate a certain portion of the gate line into the second recess; and a first interconnection region formed in the active region below the first recess and on a first side of the gate line.and a second connection area formed on a second side of the goal line and above the first connection area, the first and second connection regions forming a vertical channel extending in a lateral and vertical direction.

[0009] In view of the problem described above with the state of the art of processes for covering semiconductor fin tips with gate structures, there is a need to provide a new method that is able to position semiconductor fins under the gate structure, avoiding or reducing the problems associated with processing according to the state of the art. Summary

[0010] The above tasks and problems are solved by a semiconductor structure according to claim 1, wherein more advantageous embodiments are defined in dependent claims 2 to 12.

[0011] In one aspect of the present invention, a semiconductor structure is provided. In one embodiment of the present invention, the semiconductor structure comprises a semiconductor fin section having an end wall and extending upwards from the substrate. A gate structure spans a portion of the semiconductor fin section. A first set of gate spacers (in particular, inner gate spacers) is located on opposite side wall surfaces of the gate structure, and a second set of gate spacers (in particular, outer gate spacers) is located on the side walls of the first gate spacers. One of the gate spacers of the second set of gate spacers has a lower section that directly contacts the end wall of the semiconductor fin section.

[0012] In a further aspect of the present invention, a method for fabricating a semiconductor structure is provided. In one embodiment, the method may include forming a gate structure spanning a semiconductor fin. Next, a dielectric material is applied to the semiconductor fin and at least one of the sidewalls of the gate structure, and then a structured material stack with an opening over the dielectric material is formed. The semiconductor fin is then cut, the structured material stack and a portion of the dielectric material within the opening being used as an etching mask to provide a semiconductor fin section that includes the gate structure and has an exposed endwall. Gate spacers are then formed, one of the gate spacers comprising a lower section that is in direct contact with the exposed endwall of the semiconductor fin section.

[0013] In a further embodiment, the method can include forming a gate structure spanning a portion of a semiconductor fin. Next, a first set of gate spacers is formed onto opposing sidewalls of the gate structure, the first set of gate spacers spanning a further portion of the semiconductor fin. Subsequently, a sacrificial dielectric sheath is formed over the first set of gate spacers and the gate structure, the sacrificial dielectric sheath extending over the remaining portion of the semiconductor fin. A structured stack of material with an opening is formed over the sacrificial dielectric sheath.The semiconductor fin is then cut, using the structured material stack, a portion of the sacrificial dielectric cladding within the aperture, and one gate spacer from the first set of gate spacers as an etching mask to provide a semiconductor fin section that includes the gate structure and has an end wall. Lateral etching is then performed to retract the end wall of the semiconductor fin section downward or align it vertically with one gate spacer from the first set of gate spacers within the aperture. Next, a second set of gate spacers is formed, with one gate spacer from the second set having a lower section that directly contacts the exposed end wall of the semiconductor fin section. General description of the drawings

[0014] Embodiments of the invention are described below only by way of example, with reference to the following figures, in which: Fig. Figure 1A shows a top view of an exemplary semiconductor structure after forming a semiconductor fin on the surface of a substrate in accordance with an embodiment of the present invention. Fig. 1B a vertical cross-sectional view of the exemplary semiconductor structure along the vertical plane BB of Fig. It's 1A. Fig. 2A A top view of the exemplary semiconductor structure of Fig. 1A after the formation of the gate structures, which extend over sections of the semiconductor fin. Fig. 2B a vertical cross-sectional view of the exemplary semiconductor structure along the vertical plane BB of Fig. 2A is. Fig. 3 a cross-sectional view of the exemplary semiconductor structure of the Fig. 2A to 2B after the formation of a dielectric material sheath. Fig. 4 A cross-sectional view of the exemplary semiconductor structure of Fig. 3 after forming a structured stack of material. Fig. 5 a cross-sectional view of the exemplary semiconductor structure from Fig. 4 after cutting the semiconductor fin using the structured material stack and part of the dielectric material cladding as an etching mask. Fig. 6 A cross-sectional view of the exemplary semiconductor structure of Fig. 5 after removing the structured material stack. Fig. 7 a cross-sectional view of the exemplary semiconductor structure from Fig. 6 after the deposition of gate spacers and etching. Fig. 8 a cross-sectional view of the exemplary semiconductor structure of Fig. 2B after forming a first set of gate spacers, etching and depositing a sacrificial dielectric sheath in accordance with another embodiment of the present invention. Fig. 9 a cross-sectional view of the exemplary semiconductor structure of Fig. 8 after forming a structured material stack and after performing a breakdown etching of the sacrificial dielectric sheath. Fig. 10 a cross-sectional view of the exemplary semiconductor structure of Fig. 9 after cutting the semiconductor fin using the structured material stack, a gate spacer from the first set of gate spacers and a remaining section of the sacrificial dielectric sheath as an etching mask. Fig. 11 A cross-sectional view of the exemplary semiconductor structure of Fig. 10 after performing a lateral etching to retract an end wall from each trimmed semiconductor fin. Fig. 12 a cross-sectional view of the exemplary semiconductor structure of Fig. 11 after the removal of the structured material stack and the remaining section of the sacrificial dielectric sheath. Fig. 13 a cross-sectional view of the exemplary semiconductor structure of Fig. 12 after forming a second set of gate spacers. Detailed description

[0015] The following description should note that the drawings serve only illustrative purposes and therefore do not represent the actual size. It should also be noted that identical or related elements are marked with the same reference symbols.

[0016] The following description details numerous aspects, such as specific structures, components, materials, dimensions, processing steps, and processing techniques, to provide an understanding of the various embodiments of the present invention. However, a person skilled in the art will recognize that various embodiments of the present invention can be carried out without these specific details. Elsewhere, well-known structures and processing steps are not described in detail to prevent obscuring the present invention.

[0017] In the Fig. Figures 1A to 1B show different views of an exemplary semiconductor structure after a semiconductor fin 14P has been formed on the surface of a substrate in accordance with an embodiment of the present invention. Although only a single semiconductor fin 14P is described and shown, the present invention encompasses embodiments in which a plurality of semiconductor fins 14P can be formed on different sections of the substrate. In such an embodiment, all semiconductor fins are oriented parallel to one another.

[0018] In one embodiment of the present invention, and as shown, the substrate comprises, from bottom to top, a support substrate 10 and an insulating layer 12. In another embodiment (not shown), the substrate comprises a remaining section of a semiconductor mass substrate. The term "mass" in combination with the phrase "semiconductor substrate" means that the entire substrate consists of at least one semiconductor material.

[0019] The exemplary semiconductor structure found in the Fig. The semiconductor mass substrate shown in Figures 1A to 1B can be formed by first providing a semiconductor mass substrate or a semiconductor-on-insulator (SOI) substrate. When a semiconductor mass substrate is used in the present invention, the at least one semiconductor material providing the semiconductor mass substrate can, but is not limited to, comprise Si, Ge, SiGe, SiC, SiGeC, IIIN compound semiconductors such as InAs, INP, InAsP, and GaAs, and II / VI compound semiconductor materials. In such an embodiment, the uppermost semiconductor material layer portion of the semiconductor mass substrate can be used as each semiconductor fin 14P, with the remaining portion of the semiconductor mass substrate being used as the substrate. In some embodiments of the present invention, the semiconductor mass substrate can be a single crystalline semiconductor material.In other embodiments of the present invention, the semiconductor mass substrate can be a polycrystalline semiconductor material or an amorphous semiconductor material. The crystal orientation of the semiconductor mass substrate can be {100}, {110}, or {111}. Other crystallographic orientations besides those specifically mentioned can also be used in the present invention.

[0020] When an SOI substrate is used, the SOI substrate comprises, from bottom to top, a support substrate 10, an insulating layer 12, and an uppermost semiconductor layer. The uppermost semiconductor layer of the SOI substrate represents the semiconductor fin 14P of the structures shown in the Fig. 1A to 1B, ready. In some embodiments of the present invention, the support substrate 10 and the top semiconductor layer of the SOI substrate comprise the same semiconductor material. In other embodiments of the present invention, the support substrate 10 and the top semiconductor layer of the SOI substrate can comprise different semiconductor materials. The semiconductor material(s) that can be used as the support substrate 10 and the top semiconductor layer include, for the semiconductor bulk substrate, one of the semiconductor materials mentioned above. In one embodiment, the support substrate 10 and the top semiconductor layer of the SOI substrate both comprise silicon. In some embodiments, the support substrate 10 is a non-semiconductor material, such as a dielectric material and / or a conductive material.

[0021] The support substrate 10 and the top semiconductor layer of the SOI substrate can have the same or different crystal orientations, including those mentioned above for the semiconductor bulk substrate. The support substrate 10 and / or the top semiconductor layer of the SOI substrate can comprise a single-crystalline semiconductor material, a polycrystalline material, or an amorphous material. Typically, at least the top semiconductor layer of the SOI substrate is a single-crystalline semiconductor material.

[0022] The insulating layer 12 of the SOI substrate can be a crystalline or non-crystalline oxide or nitride. In one embodiment, the insulating layer 12 is an oxide such as silicon oxide.

[0023] The SOI substrate can be formed using standardized processes, including SIMOX (Separation by Ion Implantation of Oxygen) or layer transfer. If a layer transfer process is used, an optional thinning step can follow the joining of two semiconductor wafers. This optional thinning step reduces the thickness of a semiconductor layer to a more desirable thickness.

[0024] The thickness of the top semiconductor layer of the SOI substrate is typically between 10 nm and 100 nm, although other thicknesses below or above this range are also possible. The insulating layer 12 of the SOI substrate typically has a thickness between 1 nm and 200 nm, although other thicknesses below or above this range are also possible. The thickness of the support substrate 10 of the SOI substrate is irrelevant for the present invention.

[0025] In some embodiments of the present invention, a hard mask layer (not shown) can be formed on the top surface of either the semiconductor bulk substrate or the SOI substrate. The hard mask layer that can be used is a continuous layer that completely covers the top surface of the semiconductor bulk substrate or the SOI substrate. The hard mask layer used in the present invention can comprise a semiconductor oxide, a semiconductor nitride, and / or a semiconductor oxynitride. In one embodiment, the hard mask material that can be used to provide the hard mask layer can comprise silicon dioxide. In another embodiment, the hard mask material that can be used to provide the hard mask layer can comprise silicon nitride.In a further embodiment, the hard mask material that can be used to provide the hard mask layer can comprise a stack of silicon dioxide and silicon nitride in any order.

[0026] In some embodiments of the present invention, the hard mask material that can be used to provide the hard mask layer can be formed by a deposition process, such as chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD). In other embodiments, the hard mask material that can be used to form the hard mask layer can be formed by a thermal process, such as thermal oxidation and / or thermal nitritation. In still further embodiments, the hard mask material that can be used to provide the hard mask layer can be formed by a combination of a deposition process and a thermal processor.The thickness of the hard mask material that can be used to provide the hard mask layer can be in the range between 50 nm and 50 nm, with other thicknesses that are less or greater than the previously mentioned thickness ranges also being suitable for the hard mask layer.

[0027] Next, the semiconductor bulk substrate or SOI substrate, with or without the hard mask layer, can be structured to form the semiconductor fin 14P, as shown in the Fig. 1A to 1B. In one embodiment, the structuring process used to define the semiconductor fin 14P may include a sidewall image transfer (SIT) process. The SIT process involves forming a continuous mandrel material layer (not shown) on the top surface of the hard mask layer of the semiconductor bulk substrate or the SOI substrate. The continuous mandrel material layer (not shown) may comprise any material (semiconductor, insulator, conductive, or organic) that can be selectively removed from the structure during a subsequent etching process. In one embodiment, the continuous mandrel material layer (not shown) may consist of amorphous silicon, amorphous carbon, or polysilicon. In another embodiment, the continuous mandrel material layer (not shown) may consist of a metal, such as Al, W, or Cu.The continuous mandrel material layer (not shown) can be formed, for example, by chemical vapor deposition or plasma-enhanced chemical vapor deposition. The thickness of the continuous mandrel material layer (not shown) can be in the range of 50 nm to 300 nm, although thinner or thicker layers are also possible. Upon deposition of the continuous mandrel material layer (not shown), it can be patterned by lithography and etching to form a variety of mandrel structures (also not shown).

[0028] The SIT process continues by forming a dielectric spacer on each sidewall of each mandrel structure. The dielectric spacer can be formed by depositing dielectric spacer material and subsequently etching the deposited material. The dielectric spacer material can include any dielectric spacer material, such as silicon dioxide, silicon nitride, or a dielectric metal oxide. Examples of deposition processes that can be used to provide the dielectric spacer material include chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD).Examples of etching processes that can be used to provide the dielectric spacers include any etching process, such as reactive ion etching. Since the dielectric spacers are used as the etching mask in the SIT process, the width of each dielectric spacer can be used to determine the width of each semiconductor fin 14P.

[0029] After determining the dielectric spacers, the SIT process continues by removing each mandrel structure. Each mandrel structure can be removed by an etching process that is selective for removing the mandrel material. Following mandrel removal, the SIT process continues by transferring the structure provided by the dielectric spacers into the semiconductor material provided by the semiconductor fin 14P. Structure transfer can be achieved through an etching process. Examples of etching processes that can be used for structure transfer include dry etching (e.g., reactive ion etching, plasma etching, ion beam etching, or laser ablation) and / or chemical wet etching processes. In one example, the etching process used to transfer the structure includes one or more reactive ion etching steps.Upon completion of the structure transfer, the SIT process is terminated by removing the dielectric spacers from the structure. Each dielectric spacer can be removed by etching or a planarization process.

[0030] In some embodiments, lithography and etching can be used to define the semiconductor fin. Lithography involves depositing a photoresistive material (not shown) onto the semiconductor bulk substrate or the SOI substrate, structuring the photoresistive material by exposing it to a desired structure of radiation, and developing the exposed photoresistive material using a conventional resistive developer. Etching may include, for example, dry etching (particularly reactive ion etching, ion beam etching, plasma etching, or laser ablation) or a wet chemical etching process. Following the formation of the semiconductor fin 14P, the structured photoresistive material may be removed using a resistive removal process, such as ashing.

[0031] As used herein, the term “semiconductor fin” refers to a continuous semiconductor structure extending upward from the surface of a substrate. In one embodiment, the substrate comprises an insulating layer 12 and a support substrate 10. In another embodiment, the substrate is a remaining portion of a semiconductor bulk substrate. Each fin structure formed comprises a pair of vertically extending sidewalls that are parallel to each other. As used herein, a “vertical” surface is a surface that extends along a vertical plane and does not deviate from the vertical plane by more than three times the square of the surface roughness.

[0032] In the Fig. Figures 2A to 2B are different views of the exemplary semiconductor structure from the Fig. Figures 1A to 1B show the formation of gate structures 16L, 16R spanning different sections of the semiconductor fin 14P. The term "spanning" means that each gate structure 16L, 16R is formed over a semiconductor fin 14P, such that a first section of each gate structure 16L, 16R is on one side of the semiconductor fin 14P and a second section of each gate structure 16L, 16R is on the other side of the semiconductor fin 14P. Sections of each gate structure 16L, 16R are also placed on an exposed section of the substrate (in the illustrated embodiment, the gate structures 16L, 16R include sections positioned on the insulating layer 12).

[0033] In some embodiments of the present invention, and as shown, the gate structures 16L, 16R are functional gate structures. "Functional gate structures" refers to permanent gate structures used to control output currents (for example, the flow of charge carriers in a conductor) of a semiconductor device by electric or magnetic fields. Each functional gate structure 16L, 16R formed comprises a gate material stack consisting, from bottom to top, of a dielectric gate section 18L, 18R, a conductive gate section 20L, 20R, and a gate cap section (not shown). In some embodiments, the gate cap section may be omitted.

[0034] Each dielectric gate section 18L, 18R comprises a dielectric gate material. The dielectric gate material providing each dielectric gate section 18L, 18R can be an oxide, a nitride, and / or an oxynitride. For example, the dielectric gate material providing each dielectric gate section 18L, 18R can be a high-k material with a dielectric constant greater than that of silicon dioxide. Examples of high-k dielectrics include, but are not limited to, HfO₂, CrO₂, La₂O₃, Al₂O₃, TiO₂, SrTiO₃, LaAlO₃, Y₂O₃, and HfO₂. x , N y , ZrO x N y , LA2 ZrO x N y , Al2 ZrO x N y , Ti ZrO x N y , SrTi ZrO x N y , LaAl ZrO x N y , Y2 ZrO x N y , SiON, SiN x, silicates thereof or alloys thereof. Each value of x is independent between 0.5 and 3 and each value of y is independent between 0 and 2. In some embodiments, a multilayer dielectric gate structure comprising several dielectric gate materials, such as silicon dioxide and high-k gate dielectrics, can be formed and used as each dielectric gate section 18L, 18R.

[0035] The dielectric gate material used to provide each dielectric gate section 18L, 18R can be produced by any deposition process, including, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition. In some embodiments, a thermal process, including, for example, thermal oxidation and / or thermal nitritation, is used to form the dielectric gate materials of each dielectric gate section 18L, 18R. In some embodiments, each dielectric gate section 18L, 18R comprises the same dielectric gate material.In other embodiments, the dielectric gate section 18L can comprise a first dielectric gate material, and the second dielectric gate section 18R can comprise a second dielectric gate material that differs in composition from the first dielectric gate material. When different dielectric gate materials are used for the dielectric gate sections 18L and 18R, a block mask technology can be employed. In one embodiment of the present invention, the dielectric gate material used to provide the dielectric gate sections 18L and 18R can have a thickness in the range of 1 nm to 10 nm. Other thicknesses, less or more than the aforementioned thickness ranges, can also be used for the dielectric gate material.

[0036] Each conductive gate section 20L, 20R comprises a conductive gate material. The conductive gate material used to provide the conductive gate sections 20L, 20R can comprise any conductive material, including, for example, doped polysilicon, an elemental metal (e.g., tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium, and platinum), an alloy of at least two elemental metals, an elemental metal nitride (e.g., tungsten nitride, aluminum nitride, and titanium nitride), an elemental metal silicate (e.g., tungsten silicate, nickel silicate, and titanium silicate), or multilayer combinations thereof. In some embodiments, each conductive gate section 20L, 20R can comprise an NFET gate metal. In other embodiments, each conductive gate section 20L, 20R can comprise a PFET gate metal.In a further embodiment, the conductive gate section 20L comprises an NFET gate metal, wherein the conductive gate section 20R comprises a PFET gate metal. In a still further embodiment, the conductive gate section 20L comprises a PFET gate metal, wherein the conductive gate section 20R comprises an NFET gate metal.

[0037] The conductive gate material used to provide the conductive gate sections 20L, 20R can be produced using a deposition process, including, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD), or other similar deposition processes. If a metal silicate is formed, a conventional silicide process can be used. If a different conductive gate material is used for the conductive gate sections 20L, 20R, block mask technology can be employed. In one embodiment, the conductive gate material used to provide each conductive gate section 20L, 20R can have a thickness between 1 nm and 100 nm.Other thicknesses, which are below or above the aforementioned thickness range, can also be used for the conductive gate material used to provide the conductive gate sections 20L, 20R.

[0038] Each gate cap section comprises a gate cap material. The gate cap material providing each gate cap section can comprise one of the dielectric materials mentioned above as the hard mask material. In one embodiment, each gate cap section comprises silicon dioxide, silicon nitride, and / or silicon oxynitride. The dielectric material providing each gate cap section can be formed using conventional deposition processes, such as chemical vapor deposition or plasma-enhanced chemical vapor deposition. The dielectric material providing each gate cap section can have a thickness between 5 nm and 20 nm. Other thicknesses, lower or higher than the aforementioned thickness range, can also be used as the thickness for the dielectric material representing each gate cap section.

[0039] Any functional gate structure can be formed by providing a functional gate material stack consisting, from bottom to top, of the dielectric gate material, the conductive gate material, and, if present, the gate cap material. The functional gate material stack can then be structured. In one embodiment of the present invention, the structuring of the functional gate material stack can be carried out by using lithography and etching.

[0040] In other embodiments of the present invention, the gate structures 16L, 16R are sacrificial gate structures. A "sacrificial gate structure" is a material or stack of materials that serves as a placeholder for subsequently formed functional gate structures. In such a process, the functional gate structure is formed after semiconductor fin cutting by replacing the sacrificial gate structure with a functional gate structure as defined above. In such an embodiment, the dielectric gate section of a functional gate structure can be U-shaped. "U-shaped" means a material comprising a lower horizontal surface and a sidewall surface extending upward from the lower horizontal surface. The sacrificial gate structure, when used, can comprise a sacrificial dielectric gate section, a sacrificial gate material section, and a sacrificial gate cap section.In some embodiments, the sacrificial dielectric gate section and / or the sacrificial gate cap section can be omitted. The sacrificial dielectric gate section comprises one of the dielectric materials mentioned above for dielectric gate sections 18L, 18R. The sacrificial gate material section comprises one of the conductive gate materials mentioned above for conductive gate sections 20L, 20R. The sacrificial gate cap section comprises one of the gate cap materials mentioned above for gate cap sections. The sacrificial gate structures can be formed by depositing different material layers and subsequently structuring the resulting sacrificial material stack by, for example, lithography and etching.

[0041] The following drawings show only vertical cross-sections of the exemplary semiconductor structure along the vertical plane BB. The vertical plane BB is a plane that passes through the semiconductor fin 14P. Fig. Figure 3 is an example of the semiconductor structure of the Fig. Figures 2A to 2B show the formation of a dielectric material cladding. As shown, the dielectric material cladding 24 is a conformal layer covering the exposed surfaces of the semiconductor fin 14P and each gate structure 16L, 16R. The dielectric material cladding 24 can comprise any dielectric material, including, for example, a dielectric material oxide, a dielectric material nitride, and / or a dielectric material oxynitride. In one embodiment, the dielectric material cladding 24 can comprise silicon dioxide. In another embodiment, the dielectric material cladding 24 can consist of silicon nitride. In a further embodiment, the dielectric material cladding 24 can comprise a stack of silicon dioxide and silicon nitride in any order. In yet another embodiment, the dielectric material cladding 24 can comprise a SiBCN or a SiOCN material.

[0042] In some embodiments of the present invention, the dielectric material coating 24 can be formed by a deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or plasma-enhanced chemical vapor deposition (PECVD). The thickness of the dielectric material coating 24 can vary between 2 nm and 10 nm, and other thicknesses, smaller or larger than the aforementioned range, can also be used for the dielectric material coating 24.

[0043] In some embodiments (not shown), the dielectric material cladding 24 can be etched at this point of the present invention to form gate spacers (for example, a first set of gate spacers as described below) on the vertical sidewalls of each gate structure 16L, 16R. In one embodiment, the etching used to provide the first set of gate spacers can include reactive ion etching. In such an embodiment, the dielectric material cladding 24 is removed from the top surface of each gate structure 16L, 16R, as well as from the top horizontal surface of the semiconductor fin 16P.

[0044] Fig. Figure 4 shows an example semiconductor structure of Fig. 3. After forming a structured material stack. The structured material stack comprises an opening 30 positioned between the gate structure 16L and the gate structure 16R. The opening 30 defines a region in which the semiconductor fin 14P is subsequently cut. In accordance with the present invention, a portion of the opening 30 extends onto the gate structures 16L and 16R.

[0045] In one embodiment of the present invention, the structured material stack comprises, from bottom to top, an optical planarization layer section 26P and an antireflective coating section 28P. A section of photoresistive material (not shown) may be present on each antireflective coating section 28P.

[0046] The optical planarization layer (OPL) section 26P of the structured material stack that can be used in the present invention comprises a self-planarizing material. In one example, the optical planarization layer section 26P can be an organic material, including C, O, and H, and optionally comprising Si and / or F. In another example, the optical planarization layer section 26P can be an amorphous carbon. The self-planarizing material providing the optical planarization layer section 26P can be formed by spin coating, chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, or chemical solution deposition. The thickness of the optical planarization layer section 26P can be between 10 nm and 300 nm, with greater or smaller thicknesses also being possible.

[0047] The antireflective coating section 28P of the structured material stack comprises any antireflective coating material that reduces image distortions attributed to reflections from the surface of the underlying structure. In one example, the antireflective coating section 28P of the structured material stack comprises a silicon-containing antireflective coating material. The antireflective coating material providing the antireflective coating section 28P can be formed by spin coating, chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, or chemical solution deposition. The thickness of the antireflective coating section 28P can range from 10 nm to 150 nm, although smaller and larger thicknesses are also possible.

[0048] The in Fig. The exemplary semiconductor structure shown in Figure 4 can be formed by first providing a stack of materials from the bottom up: a top layer of self-planarizing material (as defined above), a top layer of antireflective coating material (as defined above), and a top layer of photoresistive material. The self-planarizing material and the top layer of antireflective coating material can be formed using any of the deposition processes mentioned above. The photoresistive material providing the top layer can be a positive photoresist, a negative photoresist, or a hybrid photoresistive material. The photoresistive material can be deposited using any of the deposition processes mentioned above for providing the antireflective coating material.After providing such a material stack, the material stack is structured by lithography or etching, both of which are described above in the section on structuring the semiconductor material to provide the semiconductor fin 14P. The etching process is followed by the removal of the remaining photoresistive material segment using a resist removal process, such as asching.

[0049] Fig. Figure 5 shows the exemplary semiconductor structure of Fig. 4 after cutting the semiconductor fin 14P using the structured material stack (26P, 28P) and a section of the dielectric material cladding 24, which is positioned in the opening 30 as an etching mask. The cut sections of the semiconductor fin 14P are henceforth referred to as semiconductor fin sections 14L, 14R.

[0050] In accordance with embodiments of the present invention, the exemplary semiconductor structures described in Fig. Figure 5 shows how gates are formed using one or more anisotropic etching processes. In one example, one or more reactive ion etching processes can be used. Typically, the anisotropic etching first breaks through the exposed portions of the dielectric material cladding 24 that are not protected by the structured material stack (26P, 28P), thus exposing a horizontal top surface of each gate structure 16L, 16R. Etching then continues (or a separate etching process is used) to cut the semiconductor fin 14P. The “breakthrough” etching forms a gate spacer of the first set of gate spacers 24P along one of the sidewall surfaces of each gate structure 16L, 16R. The one gate spacer from the first set of gate spacers 24P, which is formed inside the opening, is vertically aligned at the end wall 15W of each semiconductor fin section 14L, 14R.In some embodiments where the dielectric material cladding has been previously formed into gate spacers, the breakthrough etching can be omitted. As in . Fig. Figure 5 shows an end wall 15W of each semiconductor fin section 14L, 14R, exposed between the first gate spacer of the first set of gate spacers 24P formed within the opening 30. In accordance with the present invention, the end wall 15W of the semiconductor fin section 14L is aligned with the end wall 15W of the semiconductor fin section 14R.

[0051] Fig. Figure 6 shows an example semiconductor structure of Fig. 5. After removing the structured material stack (26P, 28P). The structured material stack (26P, 28P) can first be removed by removing the antireflective coating section 28P using a planarization process (such as a chemical-mechanical planarization process and / or grinding) or etching. The exposed OPL section 26P can then be removed using a back-etching process or a removal process that selectively removes the self-planarizing material that provides the OPL section 26P.

[0052] After removing the structured material stack, the remaining sections of the dielectric material sheath 24 can be etched to form another gate spacer of the first set of gate spacers 24P on one side of each gate structure 16L, 16R, opposite the area where the fin cutting takes place. This step is now shown in detail.

[0053] Fig. Figure 7 shows an exemplary semiconductor structure of Fig. 6 after forming a second set of gate spacers 32P. As shown, each gate spacer of the second set of gate spacers 32P is located on a side wall of a gate spacer of the first set of gate spacers 24P. It is further shown that a gate spacer of the second set of gate spacers 32P covers the exposed end wall 15W of each semiconductor fin section 14L, 14R. A gate spacer of the first set of gate spacers 24P and a gate spacer of the second set of gate spacers 32P, which are placed on the side of the gate structure 16L, 16R opposite the position where the fin cutting takes place, span the surface of each semiconductor fin section 14L, 14R.In the area where fin cutting takes place, the gate spacer of the first set of gate spacers 24P spans the surface of the semiconductor fin section 14L, 14R, while the gate spacer of the second set of gate spacers 32P covers the exposed end wall 15W of the semiconductor fin section 14L, 14R.

[0054] The second set of gate spacers 32P is first formed by forming a layer of dielectric material and subsequently etching the spacers. During the etching process, and if not already formed beforehand, another gate spacer of the first set of gate spacers 24P is formed. The dielectric material used to provide the second set of gate spacers 32P can comprise any of the dielectric materials mentioned above for the dielectric material sheath 24. In one embodiment, the dielectric material providing the second set of gate spacers 32P can comprise the same dielectric material used to provide the dielectric material sheath 24.In one embodiment, the dielectric material used to provide the second set of gate spacers 32 and the dielectric material used to provide the dielectric material cladding 24 both comprise silicon dioxide. In another embodiment, the dielectric material providing the second set of gate spacers 32P comprises a different dielectric material than the one used to provide the dielectric material cladding 24. In one example, the dielectric material used to provide the second set of gate spacers 32 comprises silicon nitride, while the dielectric material providing the dielectric material cladding 24 comprises both SiBCN and / or SiCON material.The dielectric material providing the second set of gate spacers 32P can be formed using one of the deposition processes described above for forming the dielectric material cladding 24. Spacer etching includes anisotropic etching, such as reactive ion etching.

[0055] Source / drain regions (not shown) are formed on exposed portions of the semiconductor fin section 14L, 14R that are not covered by gate structures 16L / 16R. The source / drain regions can be formed using conventional methods, such as epitaxial growth, which are known from the prior art. As is known, the source region would be located on one side of the functional gate structure and the drain region on the other side. In some embodiments, the source / drain regions can be unconnected. In still other embodiments, the source / drain regions can be connected. The source / drain regions comprise a semiconductor material and n- or d-doping. In some embodiments, the source / drain regions comprise the same semiconductor material used for the semiconductor fin sections 14L, 14R.In some embodiments, the source / drain regions can comprise a different semiconductor material than that used for the semiconductor fin sections 14L, 14R. In some embodiments where a sacrificial gate structure is formed, the sacrificial gate structure can now be replaced with a functional gate structure.

[0056] Fig. Figure 8 shows an exemplary semiconductor structure of Fig. 2B after forming a first set of gate spacers 50P and a sacrificial dielectric sheath 52 in accordance with another embodiment of the present invention.

[0057] Each gate spacer of the first set of gate spacers 50P is formed on a side wall of each gate structure 16L, 16R. Furthermore, the first set of gate spacers 50P is formed such that it spans a portion of the semiconductor 14P. The first set of gate spacers 50P can be formed by depositing a dielectric material and subsequently performing a spacer etching process. The dielectric material that can be used to provide the first set of gate spacers 50P can be one of the dielectric materials mentioned above for providing the dielectric material sheath 24. In an example, the dielectric material providing the first set of gate spacers 50P can be a SiBCN or a SiOCN dielectric material.The deposition process of the dielectric material providing the first set of 50P gate spacers can include chemical vapor deposition, plasma-enhanced chemical vapor deposition, or atomic layer deposition. Spacer etching can involve isotropic etching, such as reactive ion etching.

[0058] The sacrificial dielectric cladding 52 can comprise any of the dielectric materials mentioned above for providing the dielectric cladding 24, provided that the selected dielectric material used to provide the sacrificial dielectric cladding 52 has a different etch rate than the dielectric material used to provide the first set of gate spacers 50P. In an example where the first gate spacers comprise a SiBCN material, the sacrificial dielectric cladding 52 can comprise silicon dioxide and / or silicon nitride. The sacrificial dielectric cladding 52 would cover all exposed surfaces of the first gate spacer 50P, the top surface of each gate structure 16L, 16R, and all exposed surfaces of the semiconductor fin 14P (not specifically shown in the cross-sectional view).The sacrificial semiconductor cladding 52 can be formed using a deposition process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or atomic layer deposition. The sacrificial dielectric cladding 52 can have a thickness between 1 nm and 20 nm. Other thicknesses, both below and above the aforementioned range, can also be used for the sacrificial dielectric cladding 52.

[0059] Fig. Figure 9 shows an exemplary semiconductor structure of Fig. 8 after forming a structured material stack (26P, 28P) and after performing breakdown etching of the sacrificial dielectric cladding 52. After the breakdown etching has been performed, as shown, a section of the top surface layer of each gate structure 16L, 16R is exposed, as well as all surfaces of the semiconductor fin 14P positioned between the gate structures 16L, 16R. The sacrificial dielectric cladding 52 remaining after the breakdown etching can be referred to herein as the sacrificial dielectric cladding section 52P.

[0060] The structured material stack (26P, 28P) used in this embodiment of the present invention is the same as the structured material stack mentioned in previous embodiments of the present invention. Therefore, the structured material stack (26P, 28P) of this embodiment of the present invention comprises materials as described above in previous embodiments of the present invention and can be formed in the same way. Element 30 represents an opening that is formed within the structured material stack (26P, 28P) during its formation. The breakthrough etching comprises an anisotropic etching process that selectively removes the dielectric material that provides the sacrificial dielectric sheath 52.

[0061] Fig. Figure 10 shows the exemplary semiconductor structure of Fig. 9. After cutting the semiconductor fin 14P using the structured material stack (26P, 28P), one of the first gate spacers 50P (with opening 30) and a remaining section of the sacrificial dielectric cladding (for example, sacrificial dielectric cladding section 52P) as an etching mask. The cutting of the semiconductor fin 14P, which provides the semiconductor fin sections 14L, 14R, can be performed using anisotropic etching, which selectively removes the semiconductor material that provides the semiconductor fin 14P. The cutting of the semiconductor fin 14P exposes an end wall 15W of each remaining semiconductor fin section 14L, 14R. In some embodiments, each end wall 15W is positioned vertically on a side wall of the sacrificial dielectric cladding sections 52P within the opening 30.In accordance with the present invention, the end wall 50W of the semiconductor fin section 14L is aligned with the end wall 15W of the semiconductor fin section 14R.

[0062] Fig. Figure 11 shows the exemplary semiconductor structure of Fig. 10 after performing lateral etching to retract the end wall of each semiconductor fin section 14L, 14R. The lateral etching provides an undercut region beneath one of the sacrificial dielectric sheath sections 52P such that the end wall 15W is either beneath one of the first gate spacers 50P or is oriented perpendicular to the side wall of a gate spacer of the first set of gate spacers 50P positioned within the opening 30. The lateral etching comprises wet or dry isotropic chemical etching.

[0063] Fig. Figure 12 shows the exemplary semiconductor structure of Fig. 11 after removal of the structured material stack (26P, 28P) and the remaining sections of the sacrificial dielectric sheath (for example, the sacrificial dielectric sheath sections 52P). The structured material stack (26P, 28P) can be removed as described above in previous embodiments of the present invention. Each sacrificial dielectric sheath section 52P can be removed by etching, which selectively removes the dielectric material that provides the sacrificial dielectric sheath sections 52P.

[0064] Fig. Figure 13 shows the exemplary semiconductor structure of Fig.12 after forming a second set of gate spacers 32P. The second set of gate spacers 32P used in this embodiment of the present invention comprises one or more dielectric materials mentioned above for providing the second set of gate spacers 32P in the previous embodiment of the present invention. The second set of gate spacers 32P can be formed by deposition followed by spacer etching. The second set of gate spacers 32P is formed on the exposed sidewalls of the first set of gate spacers 50P and a portion of the semiconductor fin sections 14L, 14R. As shown, one of the gate spacers of the second set of gate spacers 32P, which is positioned at the end of the semiconductor fin sections 14L, 14R, covers the exposed sidewalls of the semiconductor fin sections 14L, 14R.The other gate spacer of the second set of gate spacers 32P, which is located on the side of the gate structure 16L, 16R opposite the side into which the semiconductor fin was cut, spans the semiconductor fin section 14L, 14R.

[0065] Source / drain regions (not shown) are formed on exposed portions of the semiconductor fin sections 14L, 14R that are not covered by gate structures 16L, 16R. The source / drain regions can be formed using conventional methods such as epitaxial growth, which are known from the prior art. As is known, the source region would be positioned on one side of the functional gate structure and the drain region on the other side of the functional gate structure. In some embodiments, the source / drain regions can be unconnected. In another embodiment, the source / drain regions can be connected. The source / drain regions comprise a semiconductor material and n- or p-doping. In some embodiments, the source / drain regions comprise the same semiconductor material as that of the semiconductor fin sections 14L, 14R.In some embodiments, the source / drain regions can comprise a different semiconductor material than that of the semiconductor fin sections 14L, 14R. In some embodiments where a sacrificial gate structure is formed, the sacrificial gate structure can now be replaced by a functional gate structure.

Claims

[1] Semiconductor structure encompassing: a semiconductor fin section (14L, 14R) which has an end wall (15W) and extends upwards from a substrate (10, 12), a gate structure (16L, 16R) extending over a section of the semiconductor fin section, a first set of gate spacers (24P) located on opposite sidewall surfaces of the gate structure, and a second set of gate spacers (32P) located on outer side walls of the first gate spacers, wherein a gate spacer of the second set of gate spacers has an inner side wall surface with an upper section that directly contacts the outer side wall of one of the gate spacers of the first set of gate spacers, wherein in the second set of gate spacers only one gate spacer (32P) of the second set of gate spacers has a lower section that completely covers and directly contacts a side wall of the end wall (15W) of the semiconductor fin section (14L, 14R), and wherein another gate spacer (32P) of the second set of gate spacers extends over another section of the semiconductor fin section (14L, 14R). [2] Semiconductor structure according to claim 1, wherein the gate structure (16L, 16R) is a functional gate structure. [3] Semiconductor structure according to claim 2, wherein a gate spacer of the first set of gate spacers (24P) has an outer surface that is vertically oriented to the side wall of the end wall (15W) of the semiconductor fin section (14L, 14R). [4] Semiconductor structure according to claim 2, wherein each gate spacer of the first set of gate spacers (24P) spans the semiconductor fin section (14L, 14R). [5] Semiconductor structure according to claim 1, wherein the substrate (10, 12) is a semiconductor-on-insulator substrate. [6] Semiconductor structure according to claim 1, wherein the first set of gate spacers (24P) comprises the same dielectric material as the second set of gate spacers (32P). [7] Semiconductor structure according to claim 1, wherein the first set of gate spacers (24P) comprises a different dielectric material than the second set of gate spacers (32P). [8] Semiconductor structure according to claim 1, wherein at least one gate spacer of the first set of gate spacers (24P) or of the second set of gate spacers (32P) comprises a SiBCN material. [9] Semiconductor structure according to claim 1, wherein at least one gate spacer of the first set of gate spacers (24P) or of the second set of gate spacers (32P) comprises a SiOCN material. [10] Semiconductor structure according to claim 1, wherein a gate spacer of the first set of gate spacers (24P) has an outer surface that is vertically oriented to the side wall surface of the end wall (15W) of the semiconductor fin section (14L, 14R). [11] Semiconductor structure according to claim 1, wherein one gate spacer of the second set of gate spacers (32P) is coplanar to a bottom surface of the semiconductor fin section (14L, 14R). [12] Semiconductor structure according to claim 1, wherein at least one gate spacer of the first set of gate spacers (24P) has a maximum thickness of approximately 10 nm.

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