Semiconductor power module

Abstract

Semiconductor power module (1), comprising: an insulating substrate (41) having one surface (43) and another surface (42); a support substrate (44) which is arranged at a distance from one surface (43) of the insulating substrate (41) and which has a front surface (46) which is opposite one surface (43) of the insulating substrate (41); a first power supply terminal (3) which is arranged on the side of one surface (43) of the insulating substrate (41); a second power supply terminal (4) to which a voltage of a magnitude different from a voltage applied to the first power supply terminal (3) is to be applied, wherein the second power supply terminal (4) is arranged on one side of the further surface (42) of the insulating substrate (41) such that it is opposite the first power supply terminal (3) via the insulating substrate (41); a first switching component (5) which is arranged on the side of the front surface (46) of the carrier substrate (44); a second switching component (6) which is arranged on the side of the front surface (46) of the carrier substrate (44) so ​​that it is electrically connected to the first switching component (5); an output terminal (2) located on the side of the front surface (46) of the support substrate (44); and a bond wire (104) which is electrically connected to the second switching component (6) and to the first power supply terminal (3) or the second power supply terminal (4) and which provides the second switching component (6) with at least a part of a terminal voltage between the first and the second power supply terminal (3,4), wherein the insulating substrate (41) has a first and a second recess region (76, 77) through which heat generated by the first switching element (5) and the second switching element (6) is dissipated from the side of one surface (43) to the side of the other surface (42) of the insulating substrate (41), and wherein the first recess region (76) has an opening which has a square shape in plan view and exposes the first switching component (5).

Description

Technical field

[0001] The present invention relates to a semiconductor power module. background

[0002] An inverter module, or inverter module, is disclosed in patent document 1 as an example of a semiconductor power module that includes switching components. This inverter module includes a first semiconductor component (first switching component), a second semiconductor component (second switching component), and a resin housing that encloses the semiconductor components.

[0003] In this inverter module, a positive terminal (power supply terminal) connected to the first semiconductor device and a negative terminal (power supply terminal) connected to the second semiconductor device are arranged at one end of the resin housing, separated by an interval. A pair of output terminals, connected to both the first and second semiconductor devices, are arranged at another end of the resin housing. List of citations from patent literature

[0004] Patent literature 1: Japanese patent application publication no. JP 2013 - 222 885 A

[0005] Further semiconductor power modules are known from documents DE 11 2013 003 222 T5, JP H09 - 102 578 A and DE 10 2008 049 193 A1. Overview of the invention Technical problem

[0006] A semiconductor power module containing switching components generally has the problem that a surge voltage is likely to be generated during a switching operation. The magnitude of this surge voltage is proportional to the inductance component of a current path, such as wiring, through which current flows, and one challenge therefore lies in removing this inductance component from the current path.

[0007] In the semiconductor power module disclosed in patent document 1, the two power supply terminals, to which different voltages are applied alternately, are arranged at an interval or at a distance from each other on an end section of the resin housing.

[0008] The distance between the two power supply terminals is relatively large, as it is determined by the shape of the resin housing. A magnetic field generated at one power supply terminal and a magnetic field generated at the other cannot therefore be satisfactorily canceled out, and a mutual inductance component between the terminals is likely to increase due to a reciprocal induction effect.

[0009] The present invention therefore provides a semiconductor power module in which an inductance component can be reduced. Solution to the problem

[0010] The present invention provides a semiconductor power module with the features of claim 1, comprising: an insulating substrate having one surface and another surface; an output terminal arranged on one surface side of the insulating substrate; a first power supply terminal arranged on one surface side of the insulating substrate; a second power supply terminal to which a voltage of a magnitude different from a voltage applied to the first power supply terminal is to be applied, wherein the second power supply terminal is arranged on another surface side of the insulating substrate such that it faces the first power supply terminal across the insulating substrate;a first switching component arranged on one surface side of the insulating substrate and electrically connected to the output terminal and the first power supply terminal; and a second switching component arranged on one surface side of the insulating substrate and electrically connected to the output terminal and the second power supply terminal.

[0011] With the present semiconductor power module, the distance between the first and second power supply terminals can be adjusted based on the thickness of the insulating substrate on which the first and second power supply terminals are positioned opposite each other or facing each other. The first and second power supply terminals can therefore be arranged in close proximity while maintaining isolation.

[0012] A magnetic field generated at the first power supply terminal and a magnetic field generated at the second power supply terminal can therefore be satisfactorily canceled out, and consequently, the mutual inductance component between the first and second power supply terminals can be reduced. A semiconductor power module in which this inductance component can be reduced can therefore be provided.

[0013] Preferred embodiments are claimed in the dependent claims.

[0014] The aforementioned and further tasks, features and effects of the present invention will become clearer through the following description of preferred embodiments with reference to the accompanying drawing. Brief description of the drawing Fig. Figure 1 is an electrical circuit diagram of the electrical structure of a semiconductor power module according to a preferred embodiment of the present invention. Fig. Figure 2 is a perspective view of the semiconductor power module of the Fig. 1 from a view from an upper side. Fig. Figure 3 is a perspective view of the semiconductor power module of the Fig. 2 from a view from a bottom side. Fig. Figure 4 is a perspective exploded view of the internal structure of the semiconductor power module. Fig. 1. Fig. Figure 5 is a top view of the internal structure of the semiconductor power module of the Fig. 1. Fig. Figure 6 is a side view of the internal structure of the semiconductor power module of the Fig. 1. Fig. 7 is an enlarged view of Region VII of the Fig. 5. Fig. 8 is a sectional view along line VIII-VIII of the Fig. 7. Fig. Figure 9 is an electrical circuit diagram of an electrical structure according to a first modification example of the semiconductor power module of the Fig. 1. Fig. Figure 10 is an electrical circuit diagram of an electrical structure according to a second modification example of the semiconductor power module of the Fig. 1. Description of embodiments

[0015] Fig. Figure 1 is an electrical circuit diagram of the electrical structure of a semiconductor power module 1 according to a preferred embodiment of the present invention.

[0016] With reference to Fig. 1 The semiconductor power module 1 according to the preferred embodiment includes an output-side terminal 2, a high-voltage-side terminal 3 (first power supply terminal), a low-voltage-side terminal 4 (second power supply terminal) to which a voltage is applied that is lower than a voltage applied to the high-voltage-side terminal 3.

[0017] The semiconductor power module 1 includes a plurality (five in the present preferred embodiment) of first switching components 5 connected between the output-side terminal 2 and the high-voltage-side terminal 3, and a plurality (five in the present preferred embodiment) of second switching components 6 connected between the output-side terminal 2 and the low-voltage-side terminal 4.

[0018] A half-bridge circuit 7 is formed by the output-side terminal 2, the high-voltage-side terminal 3, the low-voltage-side terminal 4, the plurality of first switching components 5 and the plurality of second switching components 6. The high-voltage-side terminal 3 and the low-voltage-side terminal 4 are arranged close to or adjacent to each other.

[0019] The multitude of first switching components 5 form a high-voltage upper arm 8, and the multitude of second switching components 6 form a low-voltage lower arm 9, namely in the half-bridge circuit 7.

[0020] Each first switching component 5 includes a MISFET (field-effect transistor with insulated gate) formed in a Si substrate, in a SiC substrate or in a semiconductor substrate of a wide or wide bandgap type, and has a first source electrode 10, a first drain electrode 11 and a first gate electrode 12, in the present preferred embodiment.

[0021] The first source electrode 10 and the first drain electrode 11 form a pair of first main electrodes, and the first gate electrode 12 forms a first control electrode by means of which a current flowing between the pair of first main electrodes is controlled in each first switching element 5. Each first switching element 5 includes a first diode 13, which is connected with reverse bias between the first drain electrode 11 and the first source electrode 10.

[0022] Each first switching element 5 is connected between the high-voltage terminal 3 and the low-voltage terminal 4 or the output terminal 2, by electrically connecting the first source electrode 10 to the output terminal 2 and electrically connecting the first drain electrode 11 to the high-voltage terminal 3. The first gate electrode 12 of each first switching element 5 is electrically connected on a high-voltage side to a first gate terminal 14 (first control terminal).

[0023] The first gate terminal 14 is a terminal by means of which the respective first switching components 5 (each first gate electrodes 12) are driven and controlled. The first source electrodes 10 of each first switching component 5 are electrically connected together to a first source sensing terminal 15, on a high-voltage side in addition to the output-side terminal 2. The first source sensing terminal 15 is a potential sensing terminal for sensing a potential of the first source electrodes 10.

[0024] Every second switching component 6 includes a MISFET formed in a Si substrate, a SiC substrate or a wide bandgap semiconductor substrate, and has a second source electrode 16, a second drain electrode 17 and a second gate electrode 18 in the present preferred embodiment.

[0025] The second source electrode 16 and the second drain electrode 17 form a pair of second main electrodes, and the second gate electrode 18 forms a second control electrode by means of which a current is controlled in every second switching element 6, which flows between the pair of second main electrodes. Every second switching element 6 includes a second diode 19, which is connected with reverse bias between the second drain electrode 17 and the second source electrode 16.

[0026] Every second switching component 6 is connected between the output terminal 2 and the low-voltage terminal 4 by electrically connecting the second drain electrode 17 to the output terminal 2 and electrically connecting the second source electrode 16 to the low-voltage terminal 4.

[0027] The output terminal 2 is a common terminal to which the first source electrodes 10 of the first switching components 5 and the second drain electrodes 17 of the second switching components 6 are jointly connected. The second gate electrode 18 of each second switching component 6 is electrically connected to a second gate terminal 20 (first or second control terminal) on a low-voltage side.

[0028] The second gate terminal 20 is a terminal by means of which the respective second switching components 6 (each second gate electrodes 18) are controlled. The second source electrode 16 of each second switching component 6 is electrically connected to a second source sensing terminal 21 on a low-voltage side, in addition to the low-voltage terminal 4. The second source sensing terminal 21 is a potential sensing terminal for sensing a potential of the second source electrodes 16.

[0029] The semiconductor power module 1 according to the present preferred embodiment is, for example, configured as an inverter module that is arranged or configured to drive or control any phase of a U-phase, a V-phase, and a W-phase in a three-phase motor that has the U-phase, the V-phase, and the W-phase. An inverter component configured to drive a three-phase motor can therefore be provided by incorporating three semiconductor power modules 1 corresponding to the U-phase, the V-phase, and the W-phase.

[0030] In the inverter component, a DC power supply is connected between the high-voltage terminals 3 and the low-voltage terminals 4 of the respective semiconductor power modules 1, and the three-phase motor is connected as a load to the output terminals 2 of the respective semiconductor power modules. A DC voltage of, for example, not less than 500 V and not more than 2000 V is applied between the high-voltage terminals 3 and the low-voltage terminals 4, with the side of the low-voltage terminal 4 serving as a reference potential.

[0031] In the inverter component, the first switching components 5 and the second switching components 6 are driven and controlled by each semiconductor power module 1 using a predetermined switching pattern. This converts the DC voltage into a three-phase AC voltage, which is then supplied to the three-phase motor. This results in the three-phase motor being driven with a sinusoidal waveform.

[0032] The external appearance of the semiconductor power module 1 is now described with reference to the Fig. 2 and Fig. 3 described.

[0033] Fig. Figure 2 is a perspective view of the semiconductor power module 1 of the Fig. 1 from a top view. Fig. Figure 3 is a perspective view of the semiconductor power module 1 of the Fig. 2 from a view from a bottom side.

[0034] The semiconductor power module 1 includes a housing body section 31, which is formed in a rectangular parallelepiped shape. The housing body section 31 has a top surface 32 of a square shape in plan view, a bottom surface 33 of the same shape as the top surface 32, and four side surfaces 34 that connect the top surface 32 and the bottom surface 33.

[0035] The following can be described for the purpose of a simpler description in Fig. 2 and Fig. 3 a +X direction and a -X direction, a +Y direction and a -Y direction, and a +Z direction and a -Z direction are used.

[0036] The +X direction and the -X direction are two directions oriented along one side of the housing body section 31, and these directions are simply referred to collectively as the "X direction". The +Y direction and the -Y direction are two directions oriented along another side of the housing body section 31, orthogonal to the aforementioned one side, and these are simply referred to collectively as the "Y direction". The +Z direction and the -Z direction are two directions oriented along a thickness direction of the housing body section 31, and these are simply referred to collectively as the "Z direction".

[0037] When the housing body section 31 is arranged on a horizontal surface, the X direction and the Y direction become two horizontal directions oriented along two mutually orthogonal horizontal straight lines (an X-axis and a Y-axis), and the Z direction becomes a vertical direction oriented along a vertical straight line (a Z-axis).

[0038] The housing body section 31 is made of a synthetic resin or resin material (a thermosetting resin material), such as an epoxy resin, etc., to give an example, and seals or calibrates the first switching components 5, the second switching components 6, etc.

[0039] The output terminal 2, mentioned above, is exposed opposite the side surface 34 on a +X-direction side along the +X direction, specifically on the side surface 34 in the housing body section 31. In the present preferred embodiment, the output terminal 2 is brought out in a rectangular shape from an inner side to an outer side of the housing body section 31 in a top view.

[0040] The high-voltage terminal 3 and the low-voltage terminal 4 mentioned above are exposed opposite side face 34 on one side along a -X direction, which is a direction opposite to the direction of exposure of the output-side terminal 2. That is, the output-side terminal 2 and the high-voltage terminal 3, plus the low-voltage terminal 4, are arranged in positions opposite each other above the housing body section 31.

[0041] The high-voltage terminal 3 and the low-voltage terminal 4 are each bonded to a section of an insulating substrate 41, which is described below (a first extension or expansion section 74 of the insulating substrate 41). In plan view, the high-voltage terminal 3 and the low-voltage terminal 4 extend in rectangular shapes from the inner side to the outer side of the housing body section 31, together with the section or expansion section of the insulating substrate 41.

[0042] The low-voltage terminal 4 is bonded to a surface on one side of the +Z direction of the insulating substrate 41 (hereinafter simply referred to as the "front surface 42 of the insulating substrate 41"), as shown in Fig. Figure 2 shows that the high-voltage terminal 3 is bonded to a surface on one side of the -Z direction of the insulating substrate 41 (hereinafter simply referred to as the "back surface 43 of the insulating substrate 41"), as shown in Figure 2. Fig. 3 is shown.

[0043] The first gate terminal 14 and the first source sensing terminal 15 mentioned above, as well as the second gate terminal 20 and the second source sensing terminal mentioned above, are exposed opposite the side surface 34 on one side of the +Y direction along the +Y direction, which is a different direction from the direction of exposure of the output-side terminal 2 (the +X direction) and the direction of exposure of the high-voltage-side terminal 3 and the low-voltage-side terminal 4 (the -X direction), in the housing body section 31.

[0044] The first gate terminal 14, the first source acquisition terminal 15, the second gate terminal 20 and the second source acquisition terminal 21 are each bonded to a section of the insulating substrate 41, which is described below (a second extension section 75 of the insulating substrate 41).

[0045] The first gate terminal 14, the first source acquisition terminal 15, the second gate terminal 20 and the second source acquisition terminal 21 are brought out in plan view in a band shape (in square or rectangular shapes in plan view) from the inner side to the outer side of the housing body section 31, together with the section of the insulating substrate 41 (the second extension section 75 of the insulating substrate 41).

[0046] The second gate terminal 20 and the second source acquisition terminal 21 are bonded to the front surface 42 of the insulating substrate 41, as shown in Fig. Figure 2 shows that the first gate terminal 14 and the first source acquisition terminal 15 are bonded to the rear surface 43 of the insulating substrate 41. Fig. 3 is shown.

[0047] As it is in Fig. As shown in Figure 3, a heat dissipation element or heat transfer element 35 is exposed on the lower surface 33 of the housing body section 31. Heat generated by the first switching components 5 and the second switching components 6 is dissipated to the environment via the heat dissipation element 35.

[0048] The internal structure of the semiconductor power module 1 is now specifically described with reference to the Fig. 4 to 8 described.

[0049] Fig. Figure 4 is a perspective exploded view of the internal structure of semiconductor power module 1 of the Fig. 1. Fig. Figure 5 is a top view of the internal structure of semiconductor power module 1 of the Fig. 1. Fig. Figure 6 is a side view of the internal structure of semiconductor power module 1 of the Fig. 1. Fig. 7 is an enlarged view of Region VII of the Fig. 5. Fig. 8 is a sectional view along line VIII-VIII of the Fig. 7.

[0050] With reference to the Fig. Sections 4 to 6 of the semiconductor power module 1 include the insulating substrate 41. The insulating substrate 41 has a front surface 42 and a rear surface 43. The low-voltage terminal 4 is located on the side of the front surface 42 of the insulating substrate 41. The output terminal 2 is located on the side of the rear surface 43 of the insulating substrate 41.

[0051] The high-voltage terminal 3 is located on the side of the rear surface 43 of the insulating substrate 41. The first switching components 5, which are electrically connected to the output-side terminal 2 and to the high-voltage terminal 3, and the second switching components 6, which are electrically connected to the output-side terminal 2 and the low-voltage-side terminal 4, are located on the side of the rear surface 43 of the insulating substrate 41.

[0052] The semiconductor power module 1 has a structure in which the high-voltage terminal 3 and the low-voltage terminal 4 overlap each other via the insulating substrate 41. The high-voltage terminal 3 and the low-voltage terminal 4, and the structure in their vicinity, will now be described.

[0053] With reference to Fig. 4 The semiconductor power module 1 according to the preferred present embodiment comprises a first unit U1, which includes the first switching components 5, the second switching components 6 and the output-side terminal 2, and has a second unit U2, which includes the insulating substrate 41, the high-voltage-side terminal 3 and the low-voltage-side terminal 4, wherein the semiconductor power module 1 has a structure in which the second unit U2 is arranged or stacked on the first unit U1 in a stack-like manner.

[0054] With reference to the Fig. 4 to 6 the first unit U1 includes a carrier substrate 44 which is formed in a square shape in plan view, a first conductor pattern 45 which is formed on the carrier substrate 44, wherein the first switching components 5 are arranged on the first conductor pattern 45, wherein the second switching components 6 are arranged on the first conductor pattern 45, and wherein the output-side terminal 2 is arranged on the first conductor pattern 45.

[0055] The support substrate 44 includes a surface on one side in a +Z direction (hereinafter referred to simply as the "front surface 46 of the support substrate 44") and includes a surface on one side in the -Z direction (hereinafter referred to simply as the "rear surface 47 of the support substrate 44"). The support substrate 44 is positioned at a distance from the insulating substrate 41 with respect to the side of the rear surface 43 of the insulating substrate 41 and carries the first switching components 5 and the second switching components 6 on the side of the front surface 46.

[0056] The support substrate 44 has a thickness of, for example, no more than 5 mm. The support substrate 44 can have a thickness of no less than 0.3 mm and no more than 0.7 mm. The support substrate 44 can be an insulating substrate based on an inorganic material, including a ceramic (for example, AlN, SiN, or SiO2), etc., or it can be an insulating substrate based on an organic material that includes a resin or synthetic resin (for example, epoxy resin), etc.

[0057] The first conductor pattern 45 is a conductor film, made, for example, of Cu (copper), and is bonded directly to the front surface 46 of the support substrate 44. The first conductor pattern 45 includes a first high-voltage-side conductor pattern 48, which electrically connects the high-voltage-side terminal 3 and the first switching components 5, as well as a first output-side conductor pattern 49, which electrically connects the output-side terminal 2 and the second switching components 6.

[0058] The first high-voltage-side conductor pattern 48 is arranged at an end section on the -X-direction side of the support substrate 44 and is formed in a quadrilateral shape extending along the Y-direction in a plan view. Conversely, the first output-side conductor pattern 49 is arranged at an end section on the +X-direction side of the support substrate 44 and is also formed in a quadrilateral shape extending along the Y-direction in a plan view. The X-direction width of the first output-side conductor pattern 49 is set to a value greater than the X-direction width of the first high-voltage-side conductor pattern 48.

[0059] With reference to the Fig. 4 and Fig. The first switching components 5 are bonded to the first high-voltage-side conductor pattern 48. The first switching components 5 are arranged such that they are aligned in a single row or column along the Y-direction.

[0060] With reference to the Fig. 7 and Fig. In 8, each first switching component 5 is a so-called vertical MISFET, which has a first component body section 52 (or 50) having a first front component surface 50 (or 52) on the side of the +Z direction, on which the first source electrode 10 and the first gate electrode 12 are arranged, and a first rear component surface 51 on the side of the -Z direction, on which the first drain electrode 11 is arranged. The first component body section 52 includes a Si substrate, a SiC substrate, or a wide-bandgap semiconductor substrate.

[0061] In the present preferred embodiment, four first source electrodes 10 and one first gate electrode 12 are formed on the first front component surface 50. Each first switching component 5 is bonded to the first high-voltage-side conductor pattern 48 in a state in which the first rear component surface 51 of the first component body section 52 faces the front surface 46 of the support substrate 44.

[0062] Each first switching component 5 is bonded to the first high-voltage-side conductor pattern 48 by bonding the first drain electrode 11 and the first high-voltage-side conductor pattern 48 together via a first conductive bonding material 53. The first conductive bonding material 53 can be a solder or soldering compound.

[0063] With reference to the Fig. 4 and Fig. The second switching components 6 are bonded to the first output-side conductor pattern 49. The second switching components 6 are arranged such that they extend in a single row or column along the Y-direction and are directly opposite the respective first switching components 5 in a one-to-one correspondence in the X-direction.

[0064] With reference to the Fig. 7 and Fig. In 8, every second switching component 6 is a so-called vertical MISFET, which has a second component body section 56 comprising a second front component surface 54 on the +Z direction side, where the second source electrode 16 and the second gate electrode 18 are located, and a second rear component surface 55 on the -Z direction side, where the second drain electrode 17 is located. The second component body section 56 comprises a Si substrate, a SiC substrate, or a wide-bandgap semiconductor substrate.

[0065] In the present preferred embodiment, four second source electrodes 16 and one second gate electrode 18 are formed on the second front component surface 54. Every second switching component 6 is bonded to the first output-side conductor pattern 49 in a state in which the second rear component surface 55 of the second component body section 56 is opposite or points towards the front surface 46 of the support substrate 44.

[0066] Every second switching component 6 is bonded to the first output-side conductor pattern 49 by bonding the second drain electrode 17 and the first output-side conductor pattern 49 together via a second conductive bonding material 57. The second conductive bonding material 57 can be a solder or soldering compound.

[0067] With reference to the Fig. 4 and Fig. 5 the output-side terminal 2 is arranged on one side in the +X direction of an end section of the carrier substrate 44, via distances or intervals from the respective second switching components 6, and is bonded to a central section in a longitudinal direction of the first output-side conductor pattern 49.

[0068] The output terminal 2 has a thickness greater than the thickness of the high-voltage terminal 3 or the thickness of the low-voltage terminal 4. The output terminal 2 is electrically connected to the first switching components 5 and the second switching components 6, as mentioned above.

[0069] The output terminal 2 therefore preferably has a thickness that is at least not less than the combined thickness of the high-voltage terminal 3 and the low-voltage terminal 4, from the point of view of suppressing an increase in a resistance value.

[0070] The output terminal 2 is formed in a plate or block form with a rectangular shape in plan view extending in the X-direction and has, in the present preferred embodiment, a plurality of groove or notch sections 59 at an end section 58 on the side in the X-direction. In the present preferred embodiment, each of the plurality of groove sections 59 is formed in a recess shape extending along the same direction (X-direction).

[0071] The end section 58 of the output terminal 2 is bonded to the first output conductor pattern 49 via a third conductive bonding material 60. The third conductive bonding material 60 can be a solder or soldering compound. In a state where the end section 58 of the output terminal 2 and the first output conductor pattern 49 are bonded together by the third conductive bonding material 60, the third conductive bonding material 60 extends into the interior of the groove sections 59 formed on the end section 58.

[0072] The first unit U1 further includes the heat dissipation element 35, which is arranged on the side of the rear surface 47 of the support substrate 44. The heat dissipation element 35 covers substantially the entire area of ​​the rear surface 47 of the support substrate 44, with the exception of a peripheral section, and is formed by a conductive film of a rectangular shape in plan view, made of copper (Cu), which is bonded directly to the rear surface 47 of the support substrate 44 in the present preferred embodiment.

[0073] The heat generated by the first switching components 5 and by the second switching components 6 is transferred via the first conduction pattern 45 and the support substrate 44 to the heat dissipation element 35 and dissipated to the environment.

[0074] With reference to the Fig. 4 to 6 the second unit U2 includes the insulating substrate 41, a second conduction pattern 71 arranged on the side of the rear surface 43 of the insulating substrate 41, and a third conduction pattern 72 arranged on the side of the front surface 42 of the insulating substrate 41.

[0075] The insulating substrate 41 has a thickness of, for example, no more than 5 mm. The insulating substrate 41 can have a thickness of no less than 0.3 mm and no more than 0.7 mm. The insulating substrate 41 can be an insulating substrate based on an inorganic material, including a ceramic (for example, AlN, SiN, or SiO2), etc., or it can be an insulating substrate based on an organic material, including a synthetic resin (for example, epoxy resin), etc.

[0076] The insulating substrate 41 comprises a body section 73 with a rectangular shape in plan view, which faces the front surface 46 of the support substrate 44 in plan view, comprises a first extension section 74 extending from an end section on the side of the -X direction of the body section 73 along the -X direction to a region outside the support substrate 44, and comprises a second extension section 75 extending from an end section on one side of the +Y direction of the body section 73 along the +Y direction to the region outside the support substrate 44. The insulating substrate 41 is formed in an L-shape in plan view by means of the body section 73, the first extension section 74, and the second extension section 75.

[0077] The body section 73 of the insulating substrate 41 is arranged such that it is opposite the first high-voltage-side conduction pattern 48 and the first output-side conduction pattern 49.

[0078] The body section 73 of the insulating substrate 41 includes a plurality (five in the present preferred embodiment) of first removed regions 76, each exposing in plan view the first front component surfaces 50 of the first switching components 5, a second removed region 77 exposing the second switching components 6, and a plurality (five in the present preferred embodiment) of third removed regions 78 selectively exposing an end section on the -X direction side of the first output-side conductor pattern 49.

[0079] The first recess regions 76, the second recess region 77, and the third recess regions 78 are regions formed by selectively removing sections of the insulating substrate 41, each exposing elements located on a region along the -Z-direction of the insulating substrate 41. The first recess regions 76, the second recess region 77, and the third recess regions 78 each contain openings and / or groove sections or notch sections.

[0080] The respective first recess regions 76 are openings with square shapes in plan view, each exposing one of the first switching components 5 in a one-to-one correspondence, and are formed such that they are aligned at uniform intervals in a single row or column along the Y-direction, in the present preferred embodiment.

[0081] The respective first recess regions 76 can be groove sections with square shapes in plan view, each exposing one of the first switching components 5 in a one-to-one correspondence, instead of openings. Instead of the first recess regions 76, a plurality or a first recess region 76 can be formed, which is an opening and / or a groove section with a square shape in plan view, extending in the Y direction to expose two or more first switching components 5 or all switching components 5 together.

[0082] The second recess region 77 is formed by a circumferential edge or circumferential border on the side of the +X direction of the insulating substrate 41 and exposes an end section on the side of the +X direction of the first output-side conductor pattern 49, in addition to the second switching components 6, in the present preferred embodiment.

[0083] Instead of the second recess region 77 formed by the circumferential edge of the +X direction of the insulating substrate 41, a plurality of second recess regions 77 can be formed, each of which is an opening and / or groove section with square shapes in plan view, each exposing one of the second switching components 6 in a one-to-one correspondence and aligned in a single column along the Y direction.

[0084] Consequently, a plurality or a second recess region 77, which is an opening and / or a groove section having a square shape in plan view and extending in the Y direction, can be formed such that two or more second switching components 6 or all second switching components 6 are exposed.

[0085] The plurality of third recess regions 78 are formed such that they are aligned in a single column along the Y-direction and are opposite the plurality of first recess regions 76 in a one-to-one correspondence in the X-direction. A plurality or a third recess region 78, which is an opening and / or a groove section with a square shape in plan view extending in the Y-direction, can be formed such that it is opposite two or more first switching elements 5 or all of the first switching elements 5 together in the X-direction.

[0086] The first extension section 74 of the insulating substrate 41 is a section which, in the present preferred embodiment, is free from being opposite the support substrate 44 in a top view and is formed in a rectangular shape in a top view. The Y-direction width of the first extension section 74 of the insulating substrate 41 is set to a value smaller than the Y-direction width of the body section 73.

[0087] The second extension section 75 of the insulating substrate 41 is a section that is free, or rather, freed from being opposite the support substrate 44 in plan view, and is formed in a rectangular shape in plan view, in the present preferred embodiment. The X-direction width of the second extension section 75 of the insulating substrate 41 is set to a value smaller than the X-direction width of the body section 73.

[0088] With reference to Fig. 4 is the second conduction pattern 71, which is arranged on the side of the rear surface 43 of the insulating substrate 41, a conduction film or conductor film made of copper (Cu), to give an example, and is bonded directly to the rear surface 43 of the insulating substrate 41.

[0089] The second conductor pattern 71 integrally includes the high-voltage-side terminal 3, which is bonded to the first extension section 74 of the insulating substrate 41, a second high-voltage-side conductor pattern 79, which is bonded to the body section 73 of the insulating substrate 41 and is electrically connected to the high-voltage-side terminal 3 and the first high-voltage-side conductor pattern 48 (first switching components 5), and a second output-side conductor pattern 80, which is electrically connected to the first output-side conductor pattern 49.

[0090] The high-voltage terminal 3 is arranged at a position over an inwardly directed or inner interval or an inner distance from a circumferential edge or circumferential margin of the first extension section 74 on the first extension section 74 of the insulating substrate 41 and is designed in a square shape in top view.

[0091] The circumferential edge of the high-voltage terminal 3 is arranged in a position where it is separated or spaced at least 2 mm from the circumferential edge of the first extension section 74 of the insulating substrate 41, and an insulating region is thereby established between the circumferential edge of the high-voltage terminal 3 and the circumferential edge or periphery of the first extension section 74 of the insulating substrate 41.

[0092] The second high-voltage-side conductor pattern 79 includes a first high-voltage-side section 81, which is bonded to the end section on the -X-direction side of the body section 73 and is connected to the high-voltage-side terminal 3. The first high-voltage-side section 81 is electrically connected to the first high-voltage-side conductor pattern 48 via a fourth conductive bonding material 83.

[0093] The second high-voltage-side conductor pattern 79 includes a second high-voltage-side section 82 of a comb-tooth shape, which extends from the first high-voltage-side section 81 towards the sides of the respective first switching components 5 (first recess regions 76).

[0094] The second output-side conduction pattern 80 is arranged at an end section on the +X-direction side of the insulating substrate 41 and, in plan view, has a rectangular shape extending in the Y-direction. The second output-side conduction pattern 80 is electrically connected to the first output-side conduction pattern 49 via a fifth conductive bonding material 85 in a region between the end section on the -X-direction side of the first output-side conduction pattern 49 and the second switching components 6.

[0095] The second output-side conduction pattern 80 has a plurality (five in the present preferred embodiment) of fourth recess regions 84 which selectively expose the first output-side conduction pattern 49 at positions corresponding to each of the plurality of third recess regions 78 of the insulating substrate 41.

[0096] An end section on the -X-direction side of the second output-side conduit pattern 80 is formed into a comb-like shape by the plurality of fourth recess regions 84. The fourth recess regions 84 can be openings and / or groove sections of quadrilateral shapes in plan view, extending in the Y-direction.

[0097] The end section on the -X direction side of the first output-side conduction pattern 49 is selectively exposed by the third recess regions 78 of the insulating substrate 41 and by the fourth recess region(s) 84 of the second output-side conduction pattern 80.

[0098] The third conduction pattern 72, which is arranged on the side of the front surface 42 of the insulating substrate 41, is a conduction film made, for example, of Cu (copper) and is bonded directly to the front surface 42 of the insulating substrate 41.

[0099] The third conductor pattern 72 integrally includes the low-voltage terminal 4, which is bonded to the second extension section 75 of the insulating substrate 41, and a low-voltage conductor pattern 86, which is bonded to the body section 73 of the insulating substrate 41 and is electrically connected to the low-voltage terminal 4.

[0100] The low-voltage terminal 4 is located at a position on the first extension section 74 of the insulating substrate 41, positioned at an inner or inwardly directed interval or distance from a circumferential edge or border of the first extension section 74, and is rectangular in plan view. The low-voltage terminal 4 is opposite the high-voltage terminal 3 across the first extension section 74 of the insulating substrate 41.

[0101] The low-voltage terminal 4 is formed in plan view in a square shape, which is the same area and shape as the high-voltage terminal 3, and in the present preferred embodiment its entirety is opposite the high-voltage terminal 3 via the first extension section 74 of the insulating substrate 41.

[0102] The circumferential edge of the low-voltage terminal 4 is separated or spaced at a position by at least not less than 2 mm from the circumferential edge of the first extension section 74 of the insulating substrate 41, and an insulating region is thereby established between the circumferential edge of the low-voltage terminal 4 and the circumferential edge of the first extension section 74 of the insulating substrate 41.

[0103] The low-voltage side conductor pattern 86 includes a first low-voltage side section 87, which is bonded to the end section on the -X direction side of the body section 73 and is connected to the low-voltage side terminal 4, a second low-voltage side section 88, which is bonded to the end section on the +X direction side of the body section 73, and a third low-voltage side section 89, which connects the above sections.

[0104] The third low-voltage section 89 connects the first low-voltage section 87 and the second low-voltage section 88, bypassing or avoiding the first exclusion regions 76 and the third exclusion regions 78.

[0105] The low-voltage-side conductor pattern 86 is opposite the second high-voltage-side conductor pattern 79 via the body section 73 of the insulating substrate 41. More precisely, the first low-voltage-side section 87 of the low-voltage-side conductor pattern 86 is opposite the first high-voltage-side section 81 of the second high-voltage-side conductor pattern 79 via the body section 73 of the insulating substrate 41. The third low-voltage-side section 89 of the low-voltage-side conductor pattern 86 is opposite the second high-voltage-side section 82 of the second high-voltage-side conductor pattern 79 via the body section 73 of the insulating substrate 41.

[0106] With reference to the Fig. 4 and Fig. 5 includes the second conduction pattern 71, which is arranged on the side of the rear surface 43 of the insulating substrate 41, as well as the high-voltage-side first gate terminal 14 and the high-voltage-side first source sensing terminal 15, which were mentioned previously.

[0107] The first gate terminal 14 and the first source sensing terminal 15 are arranged adjacent to each other between the second high-voltage-side conductor pattern 79 and the second output-side conductor pattern 80. The first gate terminal 14 is arranged on the -X direction side, and the first source sensing terminal 15 is arranged on the +X direction side, in the present preferred embodiment.

[0108] The first gate terminal 14 and the first source acquisition terminal 15 are each formed in ribbon shapes in top view (in rectangular shapes in top view) which extend along the Y direction and are led out of the body section 73 of the insulating substrate 41 to the second extension section 75.

[0109] Sections of the first gate terminal 14 and the first source acquisition terminal (15), which extend to the second extension section 75 of the insulating substrate 41, are each arranged at positions over an inward interval or an inner distance from the circumferential edge or circumferential margin of the second extension section 75.

[0110] A plurality (five in the present preferred embodiment) of first contact holes 92, which selectively expose the first gate terminal 14, and a plurality (five in the present preferred embodiment) of second contact holes 93, which selectively expose the first source sensing terminal 15, are selectively formed in the body section 73 of the insulating substrate 41.

[0111] Each of the first contact holes 92 is provided in each region between the first cutout region 76 and the third cutout region 78. Each of the second contact holes 93 is provided in each region between the first cutout regions 76 and the third cutout regions 78, such that they are mutually adjacent to the first contact holes 92.

[0112] The third conductor pattern 72, which is arranged on the side of the front surface 42 of the insulating substrate 41, includes a plurality (five in the present preferred embodiment) of gate pads 94 which are connected to the first gate terminal 14 via the respective first contact holes 92, and a plurality (five in the present preferred embodiment) of source sensing pads 95 which are connected to the first source sensing terminal 15 via the respective second contact holes 93.

[0113] The third conductor pattern 72 includes the low-voltage-side second gate terminal 20 and the low-voltage-side second source-sensing terminal 21 mentioned above. The second gate terminal 20 and the second source-sensing terminal 21 are each located at the end section on the +X-direction side of the insulating substrate 41 (in a region between the circumferential edge on the +X-direction side of the insulating substrate 41 and the second low-voltage-side section 88 of the low-voltage-side conductor pattern 86). In the present preferred embodiment, the second gate terminal 20 is located on the -X-direction side, and the second source-sensing terminal 21 is located on the +X-direction side.

[0114] The second gate terminal 20 and the second source detection terminal 21 are each formed in ribbon shapes in top view (in rectangular shapes in top view) extending along the Y direction and leading out of the body section 73 of the insulating substrate 41 towards the second extension section 75.

[0115] Sections of the second gate terminal 20 and the second source socket terminal 21, which extend to the second extension section 75 of the insulating substrate 41, are each arranged at positions over an inwardly directed interval or an inner distance from the circumferential margin or circumferential edge of the second extension section 75.

[0116] The second gate terminal 20 and the second source detection terminal 21 are bonded at positions which, in the present preferred embodiment, are free from overlap with the first gate terminal 14 and the first source detection terminal 15 in top view (see also Fig. 2 and Fig. 3).

[0117] The first conduit pattern 45, which is arranged on the side of the front surface 46 of the support substrate 44, includes a dummy gate terminal 96, which is provided in accordance with the first gate terminal 14, and a dummy source sensing terminal 97, which is provided in accordance with the first source sensing terminal 15.

[0118] The dummy gate terminal 96 and the dummy source detection terminal 97 are arranged between the first high-voltage-side conductor pattern 48 and the first output-side conductor pattern 49, and are positioned as a whole on the front surface 46 of the support substrate 44.

[0119] With reference to the Fig. 5, Fig. 7 and Fig. 8 the first source electrodes 10 of the respective first switching components 5 are electrically connected to the first output-side conduction pattern 49, which is bonded to the front surface 46 of the carrier substrate 44, via first bond wires 101 as connecting elements.

[0120] The first bond wires 101 are arranged on the side of the front surface 42 of the insulating substrate 41 and connect the first source electrodes 10 of the respective first switching components 5 to the first output-side conduction pattern 49, via the first recess regions 76 and the third recess regions 78 (fourth recess regions 84 of the second output-side conduction pattern 80) of the insulating substrate 41.

[0121] The first source electrodes 10 are therefore electrically connected to the output terminal 2 via the first bond wires 101 and the first output conductor pattern 49, at each first switching component 5.

[0122] The first drain electrode 11 is connected to the high-voltage terminal 3 via the first high-voltage line pattern 48 and the second high-voltage line pattern 79 at each first switching component 5. Each first switching component 5 is thus electrically connected between the output terminal 2 and the high-voltage terminal 3.

[0123] The first gate electrode 12 of each first switching component 5 is electrically connected to the gate pad 94 via a second bond wire 102 as a connecting element. The first gate electrode 12 of each first switching component 5 and the first gate terminal 14 are thus electrically connected.

[0124] At least one of the first source electrodes 10 of each first switching component 5 is electrically connected to a source detection pad 95 via a third bond wire 103 as a connecting element. At least one of the first source electrodes 10 of each first switching component 5 and the first source detection terminal 15 are thereby electrically connected.

[0125] On the other hand, the second source electrodes 16 of the respective second switching components 6 are electrically connected to the low-voltage-side conduction pattern 86 (second low-voltage-side section 88 of the low-voltage-side conduction pattern 86), which is bonded to the front surface 42 of the insulating substrate 41, via fourth bond wires 104 as connecting elements.

[0126] The fourth bond wires 104 are arranged on the side of the front surface 42 of the insulating substrate 41 and connect the second source electrodes 16 of the respective second switching components 6 and the low-voltage side conductor pattern 86 via the second recess region 77 of the insulating substrate 41.

[0127] The second source electrodes 16 are therefore electrically connected to the low-voltage terminal 4 via the fourth bond wires 104 and the low-voltage line pattern 86, at every second switching component 6.

[0128] The second drain electrode 17 is electrically connected to the output terminal 2 via the first output conductor pattern 49, specifically at every second switching component 6. Every second switching component 6 is therefore electrically connected between the output terminal 2 and the low-voltage terminal 4.

[0129] The second gate electrode 18 of the respective second switching components 6 is electrically connected to the second gate terminal 20 via a fifth bond wire 105 as a connecting element. The fifth bond wire 105 is arranged on the side of the front surface 42 of the insulating substrate 41 and connects the second gate electrode 18 of the respective second switching components 6 and the second gate terminal 20 via the second recess region 77 of the insulating substrate 41.

[0130] At least one of the second source electrodes 16 of every second switching component 6 is electrically connected to the second source detection terminal 21 via a sixth bond wire 106 as a connecting element.

[0131] The sixth bond wires 106 are arranged on the side of the front surface 42 of the insulating substrate 41 and connect at least one of the second source electrodes 16 of the respective second switching components 6 and the second source sensing terminal 21 via the second recess region 77 of the insulating substrate 41.

[0132] The housing body section 31 seals the insulating substrate 41 and the support substrate 44, respectively, in order to selectively expose a section of the output terminal 2, a section of the high-voltage terminal 3, a section of the low-voltage terminal 4, a section of the first gate terminal 14, a section of the first source sensing terminal 15, a section of the second gate terminal 20, a section of the second source sensing terminal 21 and the heat dissipation element 35.

[0133] The section of the high-voltage terminal 3 and the section of the low-voltage terminal 4, together with the first extension section 74 of the insulating substrate 41, extend outwards to the outer side of the housing body section 31. The section of the first gate terminal 14, the section of the first source sensing terminal 15, the section of the second gate terminal 20, and the section of the second source sensing terminal 21, together with the second extension section 75 of the insulating substrate 41, extend outwards to the outer side of the housing body section 31.

[0134] The housing body section 31 can be formed by a transfer or injection molding process or can be formed by a compression molding process.

[0135] The housing body section 31, which selectively seals the insulating substrate 41, etc., is formed by pouring a synthetic resin into a metallic mold having a cavity of a predetermined shape in which the insulating substrate 41, etc., is received, using a transfer injection molding process. The insulating substrate 41, etc., refers in particular to the internal structure of the semiconductor power module 1, with the exception of the housing body section 31 (the same applies below).

[0136] The housing body section 31, which selectively seals the insulating substrate 41, etc., is formed in the compression molding process by filling a synthetic resin into the interior of a metallic mold which has a cavity of a predetermined shape and thereafter by immersing the insulating substrate 41, etc., into the synthetic resin, or by picking up and arranging the insulating substrate 41, etc., in an interior of a metallic mold which has a cavity of a predetermined shape, and thereafter by the step of filling a resin into the interior of the metallic mold.

[0137] The housing body section 31 can have an arrangement that includes an enclosure made of synthetic resin (a resin case) with an inner space, wherein the insulating substrate 41, etc., is contained within the inner space of the enclosure.

[0138] As described above, according to the semiconductor power module 1, the single half-bridge circuit 7 is formed by the output terminal 2, the high-voltage terminal 3, the low-voltage terminal 4, the first switching components 5 connected to the output terminal 2 and the high-voltage terminal 3, and the second switching components 6 connected to the output terminal 2 and the low-voltage terminal 4.

[0139] In the half-bridge circuit 7, the first switching components 5 form the high-voltage upper arm 8 and the second switching components 6 form the low-voltage lower arm 9.

[0140] According to the semiconductor power module 1, a current path leading from the high-voltage terminal 3 towards the output terminal 2 is formed via the respective first switching components 5 on the side of the rear surface 43 of the insulating substrate 41, and a current path leading from the output terminal 2 towards the low-voltage terminal 4 is formed via the respective second switching components 6 on the side of the front surface 42 of the insulating substrate 41.

[0141] One direction of the current flowing through the high-voltage terminal 3 and one direction of the current flowing through the low-voltage terminal 4 therefore run in opposite directions over or with respect to the insulating substrate 41.

[0142] Furthermore, a distance between the high-voltage terminal 3 and the low-voltage terminal 4 can be set based on the thickness (of no more than 5 mm in the present preferred embodiment) of the insulating substrate 41 on which the high-voltage terminal 3 and the low-voltage terminal 4 are arranged opposite each other, and consequently the high-voltage terminal 3 and the low-voltage terminal 4 can be satisfactorily arranged in close proximity to each other while maintaining an insulating property.

[0143] A magnetic field generated at the high-voltage terminal 3 and a magnetic field generated at the low-voltage terminal 4 can therefore be satisfactorily canceled out, and consequently, a mutual inductance component between the high-voltage terminal 3 and the low-voltage terminal 4 can be satisfactorily reduced. The semiconductor power module 1, in which an inductance component can be satisfactorily reduced, can therefore be provided.

[0144] According to the semiconductor power module 1 of the present preferred embodiment, the insulating substrate 41 selectively includes the first recess regions 76, which expose the first switching components 5 in plan view, and the second recess region 77, which exposes the second switching components 6.

[0145] The heat generated by the first switching components 5 can therefore be dissipated from the side of the rear surface 43 to the side of the front surface 42 of the insulating substrate 41 via the first recess regions 76, and the heat generated by the second switching components 6 can be dissipated from the side of the rear surface 43 to the side of the front surface 42 of the insulating substrate 41 via the second recess region 77.

[0146] Temperature increases of the first switching components 5 and the second switching components 6 can therefore be satisfactorily suppressed. According to an arrangement in which the support substrate 44 is arranged on the side of the -Z direction of the insulating substrate 41, in particular as in the semiconductor power module 1 of the present preferred embodiment, an accumulation or build-up of heat between the insulating substrate 41 and the support substrate 44 can be effectively suppressed by providing the insulating substrate 41 with the first recess regions 76 and the second recess region 77.

[0147] In addition, according to the semiconductor power module 1 of the present preferred embodiment, the heat dissipation element 35 is arranged on the side of the rear surface 47 of the support substrate 44. The heat generated by the first switching components 5 and the heat generated by the second switching components 6 can therefore be satisfactorily dissipated to the outside via the support substrate 44 and the heat dissipation element 35. The semiconductor power module 1, which can effectively suppress the temperature rises of the first switching components 5 and the second switching components 6, can thus be provided.

[0148] Although a preferred embodiment of the present invention has been described above, the present invention can also be implemented in other embodiments.

[0149] For example, in the preferred embodiment described above, an example was described in which the single half-bridge circuit 7 is formed by the first switching components 5 and the second switching components 6. However, the number of first switching components 5 and the number of second switching components 6 is not limited here.

[0150] The single half-bridge circuit 7 can therefore be formed by a first switching element 5 and a second switching element 6. The single half-bridge circuit 7 can be formed by two or more first switching elements 5 and by two or more second switching elements 6.

[0151] Although the preferred embodiment described above includes an example where MISFETs are used as the first switching elements 5 and as the second switching elements 6, the following can be used instead: Fig. 9 or Fig. The arrangements shown in the 10 diagrams can be applied.

[0152] The following describes the arrangement of Fig. 9 described, and according to this the arrangement of the Fig. 10 described. Fig. Figure 9 is an electrical circuit diagram of an electrical structure according to a first modification example of the semiconductor power module 1 of the Fig. 1. In Fig. 9 are arrangements that are in Fig. 1, etc., are shown and described above, are given the same reference numbers and their descriptions are omitted.

[0153] In the execution, which in Fig. As shown in Figure 9, IGBTs (insulated gate bipolar transistors) are used instead of MISFETs as the first switching components 5 and the second switching components 6.

[0154] This means that the half-bridge circuit 7 is formed by IGBTs. Each of the first switching components 5 and the second switching components 6 can have an IGBT formed in a Si substrate, a SiC substrate, or in a wide-bandgap semiconductor substrate.

[0155] In this case, each first switching component 5 includes a first emitter electrode 110 instead of the first source electrode 10, a first collector electrode 111 instead of the first drain electrode 11, and a first gate electrode 112 instead of the first gate electrode 12.

[0156] In each first switching component 5, the first emitter electrode 110 and the first collector electrode 111 form a pair of first main electrodes, and the first gate electrode 112 forms a first control electrode that controls the current flowing between the pair of first main electrodes.

[0157] Every second switching component 6 includes a second emitter electrode 113 instead of the second source electrode 16, a second collector electrode 114 instead of the second drain electrode 17, and a second gate electrode 115 instead of the second gate electrode 18.

[0158] In every second switching component 6, the second emitter electrode 113 and the second collector electrode 114 form a pair of first main electrodes, and the second gate electrode 115 forms a first control electrode that controls a current flowing between the pair of first main electrodes.

[0159] At the in Fig. In the embodiment shown in Figure 9, the first gate electrodes 112 are electrically connected to a first gate terminal 116 instead of the first gate terminal 14, and the first emitter electrodes 110 are electrically connected to a first emitter sensing terminal 117 instead of the first source sensing terminal 15.

[0160] The second gate electrodes 115 are electrically connected to a second gate terminal 118 instead of the second gate terminal 20, and the second emitter electrodes 113 are electrically connected to a second emitter sensing terminal 119 instead of the second source sensing terminal 21. Even with such an arrangement, the same effects can be demonstrated as those described above for the preferred embodiment.

[0161] Fig. Figure 10 is an electrical circuit diagram of an electrical structure according to a second modification example of the semiconductor power module 1 of the Fig. 1. In Fig. 10 will be orders that are in Fig. 1, etc. are shown and described above, provided with the same reference numbers, and a description of these is omitted.

[0162] In the execution, which in Fig. As shown in Figure 10, BJTs (bipolar transistors) are used as the first switching components 5 and the second switching components 6 instead of MISFETs.

[0163] This means that the half-bridge circuit 7 is formed from BJTs. Each of the first switching components 5 and the second switching components 6 can contain a BJT formed in a Si substrate, a SiC substrate, or a wide-bandgap semiconductor substrate.

[0164] In this case, each first switching component 5 includes a first emitter electrode 120 instead of the first source electrode 10, a first collector electrode 121 instead of the first drain electrode 11, and a first base electrode 122 instead of the first gate electrode 12.

[0165] In each first switching component 5, the first emitter electrode 120 and the first collector electrode 121 form a pair of first main electrodes, and the first base electrode 122 forms a first control electrode that controls a current flowing between the pair of first main electrodes.

[0166] Every second switching component 6 includes a second emitter electrode 123 instead of the second source electrode 16, a second collector electrode 124 instead of the second drain electrode 17, and a second base electrode 125 instead of the second gate electrode 18.

[0167] In every second switching component 6, the second emitter electrode 123 and the second collector electrode 124 form a pair of first main electrodes, and the second base electrode 125 forms a first control electrode that controls a current flowing between the pair of first main electrodes.

[0168] At the in Fig.In the embodiment shown in Figure 10, the first base electrodes 122 are electrically connected to a first base terminal 126 instead of the first gate terminal 14, and the first emitter electrodes 120 are electrically connected to a first emitter sensing terminal 127 instead of the first source sensing terminal 15.

[0169] The second base electrodes 125 are electrically connected to a second base terminal 128 instead of the second gate terminal 20, and the second emitter electrodes 123 are electrically connected to a second emitter sensing terminal 129 instead of the second source sensing terminal 21. Even with such an arrangement, the same effects can be demonstrated as those effects or effects described above with regard to the preferred embodiment.

[0170] Of the aforementioned Si substrate, SiC substrate, and wide-bandgap semiconductor substrate, each MISFET, IGBT, and BJT mentioned above is preferably formed in the SiC substrate or the wide-bandgap semiconductor substrate. A further description of the wide-bandgap semiconductor substrate is now presented.

[0171] The term "wide bandgap semiconductor substrate" refers specifically to a substrate formed from a semiconductor material that has a bandgap larger than the bandgap of silicon (approximately 1.0 eV to 1.2 eV).

[0172] Examples of wide-bandgap semiconductor substrates include group III-V semiconductors, including group III and group V elements, nitride semiconductors (e.g., gallium nitride), and diamond, etc. The SiC substrate mentioned above is an example of a wide-bandgap semiconductor substrate.

[0173] Although preferred embodiments of the present invention have been described in detail above, these are merely specific examples used to clarify the technical content of the present invention, and the present invention should not be interpreted as being limited only to these specific examples, the scope of protection of the present invention being limited exclusively by the attached claims. 1 semiconductor power module 2. Outbound terminal 3 High-voltage side terminal 4 Low-voltage side terminal 5 First switching component 6 Second switching component 7 Half-bridge circuit 31 Housing body section 35 Heat dissipation element or cooling element 41 Insulating substrate 42 Front surface of the insulating substrate 43 Rear surface of the insulating substrate 44 Carrier substrate 46 Front surface of the support substrate 47 Rear surface of the support substrate 76 First extraction region of the insulating substrate 77 Second cavity region of the insulating substrate

Claims

[1] Semiconductor power module (1), comprising: an insulating substrate (41) having one surface (43) and another surface (42); a support substrate (44) which is arranged at a distance from one surface (43) of the insulating substrate (41) and which has a front surface (46) which is opposite one surface (43) of the insulating substrate (41); a first power supply terminal (3) which is arranged on the side of one surface (43) of the insulating substrate (41); a second power supply terminal (4) to which a voltage of a magnitude different from a voltage applied to the first power supply terminal (3) is to be applied, wherein the second power supply terminal (4) is arranged on one side of the further surface (42) of the insulating substrate (41) such that it is opposite the first power supply terminal (3) via the insulating substrate (41); a first switching component (5) which is arranged on the side of the front surface (46) of the carrier substrate (44); a second switching component (6) which is arranged on the side of the front surface (46) of the carrier substrate (44) so ​​that it is electrically connected to the first switching component (5); an output terminal (2) located on the side of the front surface (46) of the support substrate (44); and a bond wire (104) which is electrically connected to the second switching component (6) and to the first power supply terminal (3) or the second power supply terminal (4) and which provides the second switching component (6) with at least a part of a terminal voltage between the first and the second power supply terminal (3,4), wherein the insulating substrate (41) has a first and a second recess region (76, 77) through which heat generated by the first switching element (5) and the second switching element (6) is dissipated from the side of one surface (43) to the side of the other surface (42) of the insulating substrate (41), and wherein the first recess region (76) has an opening which has a square shape in plan view and exposes the first switching component (5). [2] Semiconductor power module according to claim 1, wherein a half-bridge circuit is formed by the output terminal (2), the first power supply terminal (3), the second power supply terminal (4), the first switching component (5) and the second switching component (6). [3] Semiconductor power module according to claim 1 or 2, wherein a direction of a current flowing through the first power supply terminal (3) and a direction of a current flowing through the second power supply terminal (4) are selected such that they are opposite or opposite to each other over the insulating substrate (41). [4] Semiconductor power module according to any one of claims 1 to 3, wherein the first power supply terminal (3) is a high-voltage terminal and the second power supply terminal (4) is a low-voltage terminal to which a voltage is to be applied that is lower than the voltage applied to the first power supply terminal (3). [5] Semiconductor power module according to one of claims 1 to 4, wherein the support substrate (44) has a rear surface (47) positioned on a side opposite the front surface (46), and wherein a heat dissipation element (35) is arranged on the rear surface of the support substrate (47). [6] Semiconductor power module according to any one of claims 1 to 5, wherein the insulating substrate (41) has a thickness of not more than 5 mm. [7] Semiconductor power module according to any one of claims 1 to 6, wherein the output terminal (2) has a thickness greater than the thickness of the first power supply terminal (3) or the thickness of the second power supply terminal (4). [8] Semiconductor power module according to any one of claims 1 to 7, wherein the output terminal (2) has a thickness that is not less than the combined thickness of the first power supply terminal (3) and the second power supply terminal (4). [9] Semiconductor power module according to any one of claims 1 to 8, wherein the first switching component (5) or the first switching components (5) is / are arranged on one surface side of the insulating substrate (41) and the second switching component (6) or the second switching components (6) is / are arranged on one surface side of the insulating substrate (41). [10] Semiconductor power module according to any one of claims 1 to 9, further comprising: a synthetic resin that seals the insulating substrate (41) such that the output terminal (2), the first power supply terminal (3) and the second power supply terminal (4) are selectively exposed, and wherein the first power supply terminal (3) and the second power supply terminal (4) together with the insulating substrate (41) are exposed relative to the synthetic resin. [11] Semiconductor power module according to claim 10, wherein the first power supply terminal (3) exposed to the resin is arranged at a position at a distance from a circumferential edge of the insulating substrate (41) in the direction of an inner side exposed to the resin, and wherein the second power supply terminal (4) exposed to the resin is arranged at a position at a distance from a circumferential edge of the insulating substrate (41) in the direction of an inner side exposed to the resin. [12] Semiconductor power module according to claim 11, wherein a distance between a circumferential edge of the first power supply terminal (3) exposed to the resin and the circumferential edge of the insulating substrate (41) exposed to the resin is set to a value of not less than 2 mm, and wherein a distance between a circumferential edge of the second power supply terminal (4) exposed to the resin and the circumferential edge of the insulating substrate (41) exposed to the resin is set to a value of not less than 2 mm. [13] Semiconductor power module according to one of claims 10 to 12, wherein the output terminal (2) is arranged in a position in which, in a top view, it is opposite the first power supply terminal (3) and the second power supply terminal (4) across the resin. [14] Semiconductor power module according to any one of claims 10 to 13, further comprising: a first control terminal (14) that drives and controls the first switching component (5); and a second control terminal (20) that drives and controls the second switching component (6); and wherein the synthetic resin seals the insulating substrate (41) in such a way that the first control terminal (14) and the second control terminal (20) are selectively exposed. [15] Semiconductor power module according to claim 14, wherein the first control terminal (14) and the second control terminal (20) are exposed relative to the resin in a direction that differs from a direction in which the output terminal (2) is exposed relative to the resin and from a direction in which the first power supply terminal (3) and the second power supply terminal (4) are exposed relative to the resin. [16] Semiconductor power module according to claim 14 or 15, wherein the first switching component (5) has a pair of first main electrodes (10, 11) and a first control electrode (12) by which a current flowing between the pair of first main electrodes (10, 11) is controlled, wherein the second switching component (6) has a pair of second main electrodes (16, 17) and a second control electrode (18) by which a current flowing between the pair of second main electrodes (16, 17) is controlled, wherein the first control terminal (14) is electrically connected to the first control electrode (12) of the first switching component (5), and wherein the second control terminal (20) is electrically connected to the second control electrode (18) of the second switching component (6). [17] Semiconductor power module according to any one of claims 1 to 16, wherein the first switching component (5) and the second switching component (6) comprise a MISFET, an IGBT or a BJT, wherein the MISFET, the IGBT or the BJT is preferably formed in a Si substrate, in a SiC substrate or in a substrate of a wide bandgap semiconductor type. [18] Semiconductor power module according to any one of claims 1 to 17, wherein a voltage of not less than 500 V is applied between the first power supply terminal (3) and the second power supply terminal (4). [19] Semiconductor power module according to any one of claims 1 to 18, further comprising: a further bond wire (101) which is electrically connected to the first switching component (5) and to a connection pattern (49).

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