Variable gain signal amplifier, front-end architecture, and wireless device

Abstract

Signal amplifiers (110a; 310a; 310b; 610) with variable gain, comprising: a variable gain stage (120; 220; 320; 612) configured to receive an input signal and produce an amplified output signal; a degeneration switching block (130; 230; 330; 630) coupled to the variable gain stage (120; 220; 320; 612) and configured to provide a variety of gain levels of the variable gain stage (120; 220; 320; 612); and a feedback block (350a; 650) in medium gain mode, coupled to an input of the variable gain stage (120; 220; 320; 612), so that the variable gain stage (120; 220; 320; 612) is provided with feedback for a subset of the multitude of gain levels.

Description

BACKGROUND area

[0001] The present disclosure relates to variable gain signal amplifiers for wireless communication applications, to a front-end architecture with such a signal amplifier, and to a wireless device with such a signal amplifier. Description of related technology

[0002] Wireless communication devices typically include components in a front-end module configured to amplify received radio frequency (RF) signals. The front-end module can incorporate a variety of amplification modes to provide different levels of gain.

[0003] German patent application DE 11 2017 004 355 T5 discloses variable-gain amplifiers and multiplexers that incorporate programmable attenuators in switchable paths, allowing signals in a high-gain mode to bypass the attenuation. German patent application US 2014 / 0 240 048 A1 discloses wireless devices and integrated circuits with a gain transistor and a configurable degradation inductor for the amplifier. German patent application US 2015 / 0 137 884 A1 discloses amplifiers for high-frequency applications with multiple transistors and a bypass switch.

[0004] It is an object of the present invention to find a signal amplifier with which impedances for input signals can be selectively provided depending on different amplification modes. SUMMARY

[0005] According to a number of implementations, the present disclosure relates to a variable-gain signal amplifier comprising: a variable-gain stage configured to receive an input signal and produce an amplified output signal; a degeneration circuit block coupled to the variable-gain stage and configured to provide a plurality of gain levels of the variable-gain stage; and a mid-gain-mode feedback block coupled to an input of the variable-gain stage such that feedback is provided to the variable-gain stage for a subset of the plurality of gain levels.

[0006] In some embodiments, the variable gain stage is designed to process high-frequency signals as input signals. In some embodiments, the amplifier is configured to selectively provide a bypass path (also called a loop-through path) that bypasses the variable gain stage and a gain path that passes through the variable gain stage.

[0007] In some embodiments, the degeneration circuit block includes a variable impedance stage designed to provide different inductances to the variable-gain stage. In other embodiments, the variable impedance stage is configured to provide improved linearity of the amplified output signal by means of selectable impedances.

[0008] In further embodiments, the variable impedance stage of the degeneration switching block is configured to select a first impedance for a first gain level of the plurality of gain levels and a second impedance for a second gain level of the plurality of gain levels. In still further embodiments, the first matched impedance is greater than the second matched impedance, and the first gain level is less than the second gain level.

[0009] In some embodiments, the amplifier also includes a control circuit configured to generate a gain control signal for controlling the variable gain stage and the degeneration circuit.

[0010] In further embodiments, the control circuit is configured to provide a variety of gain control signals corresponding to the variety of gain levels.

[0011] In some embodiments, the amplifier further includes a bypass block coupled to an input of the variable gain stage and configured to be activated at a low gain level of the multitude of gain levels to provide a bypass path that does not include the variable gain stage.

[0012] In other embodiments, the bypass path does not include the degeneration switching block.

[0013] In some embodiments, the amplifier also includes a cascode buffer coupled to an output of the variable gain stage.

[0014] In some embodiments, the variable impedance stage is designed to provide different impedance values ​​associated with the different gain levels, and the degeneration switching block further includes a switch functionally associated with the variable impedance stage and configured to selectively isolate the variable impedance stage from a reference potential node.

[0015] According to a number of implementations, the present disclosure relates to a front-end architecture comprising a variable-gain signal amplifier according to the invention, which has a plurality of input nodes coupled to the variable-gain stage.

[0016] The front-end architecture also includes a filter array coupled to the variable-gain signal amplifier to direct frequency bands to select input nodes of the variable-gain signal amplifier. The front-end architecture also includes a controller configured to operate the variable-gain signal amplifier to provide a variety of gain modes, allowing the variable-gain signal amplifier to route signals in a low-gain mode along a path that bypasses the variable-gain stage.

[0017] According to a number of implementations, the present disclosure relates to a wireless device comprising a diversity antenna and a filter arrangement coupled to the diversity antenna for receiving signals and directing frequency bands along selected paths.

[0018] The wireless device also includes a variable-gain signal amplifier according to the invention. The wireless device also includes a controller configured to control the variable-gain signal amplifier in order to provide a variety of gain modes, such that in a low-gain mode the variable-gain signal amplifier routes signals along a path that bypasses the variable-gain stage.

[0019] For the purposes of summarizing the disclosure, certain aspects, advantages, and innovations are described here. It should be noted that not all of these advantages can necessarily be achieved in accordance with a particular embodiment. Thus, the disclosed embodiments may be implemented in a manner that achieves or optimizes one advantage or group of advantages as taught herein, without necessarily achieving other advantages as may be taught or suggested herein. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates a wireless device with a primary antenna and a secondary antenna. Fig. Figure 2 illustrates a diversity receiver (DRx) configuration with a DRx front-end module (FEM). Fig. Figure 3A illustrates an exemplary variable amplifier configuration that includes a multi-input gain stage configured to receive multiple inputs and selectively amplify the received signals with the gain stage or provide a bypass path through a bypass block. Fig. Figure 3B illustrates another example of a variable gain amplifier, which uses the same components as the variable gain amplifier from Fig. 3A includes the addition of certain elements. Fig. 3C illustrates another example of a variable gain amplifier, similar to the variable gain amplifier of Fig. 3A is the case, with the bypass switch removed. Fig. 3D illustrates another example of a variable gain amplifier that uses the same components as the variable gain amplifier from Fig. 3C contains certain elements. Fig. Figure 4 illustrates a variable gain signal amplifier that includes a variable gain stage configured to receive an input signal and produce an amplified output signal. Fig. Figure 5 illustrates a degeneration circuit that includes a variable impedance stage coupled to a signal amplifier with different gain levels. Fig. Figure 6 illustrates an exemplary variable-gain amplifier configuration, similar to the variable-gain amplifier of Fig. 3B is configured. Fig. 7A, Fig. 7B and Fig. 7C illustrates examples of operating modes of the variable gain amplifier configuration of Fig. 6. Fig. Figure 8 illustrates a variable gain signal amplifier, which corresponds to the configuration of the variable gain signal amplifier of Fig. 6 is similar, but without a bypass switch. Fig. Figure 9 illustrates a variable gain signal amplifier, which is similar to the variable gain signal amplifier configuration of Fig. 6, however, with a shutdown switch block instead of the feedback module with a medium gain mode. Fig. Figure 10 illustrates a variable gain signal amplifier, similar to the variable gain signal amplifier configuration of Fig. 9 is, however with the bypass switch removed. Fig. Figure 11 shows that in some embodiments some or all diversity receiver configurations can be implemented wholly or partially in one module. Fig. Figure 12 shows that in some embodiments, some or all of the diversity receiver configurations can be implemented wholly or partially in one architecture. Fig. Figure 13 illustrates an example of a wireless device with one or more advantageous features, which are described here. DETAILED DESCRIPTION OF SOME EXECUTION FORMS

[0020] The headings included here, if any, are for convenience only and do not necessarily affect the scope or significance of the claimed invention. Overview

[0021] Fig. Figure 1 illustrates a wireless device 100 with a primary antenna 160 and a diversity antenna 170. The wireless device 100 includes a radio frequency module (RF module) 106 and a transceiver 104, which can be controlled by a controller 102. The transceiver 104 is configured to convert between analog signals (e.g., radio frequency (RF) signals) and digital data signals. For this purpose, the transceiver 104 may include a digital-to-analog converter, an analog-to-digital converter, a local oscillator for modulating or demodulating a baseband analog signal onto or from a carrier frequency, a baseband processor that converts between digital samples and data bits (e.g., speech or other types of data), or other components.

[0022] The RF module 106 is coupled between the primary antenna 160 and the transmitter-receiver 104. Since the RF module 106 can be physically located close to the primary antenna 160 to reduce attenuation due to cable losses, it can be referred to as a front-end module (FEM). The RF module 106 can process an analog signal received by the primary antenna 160 for the transmitter-receiver 104, or received by the transmitter-receiver 104 and transmitted via the primary antenna 160. For this purpose, the RF module 106 can include filters, power amplifiers, low-noise amplifiers, band selectors, attenuators, matching circuits, and other components.

[0023] When a signal is transmitted to the wireless device 100, the signal can be received at both the primary antenna 160 and the diversity antenna 170. The primary antenna 160 and the diversity antenna 170 can be physically separated such that the signal is received at the primary antenna 160 and the diversity antenna 170 with different characteristics. For example, in one embodiment, the primary antenna 160 and the diversity antenna 170 can receive the signal with different attenuation, noise, frequency response, and / or phase shift. The transmitter-receiver 104 can use both of the signals with their different characteristics to determine data bits that correspond to the signal. In some implementations, the transmitter-receiver 104 selects between the primary antenna 160 and the diversity antenna 170 based on characteristics such as selecting the antenna with the highest signal-to-noise ratio.In some implementations, the transmitter-receiver 104 combines the signals from the primary antenna 160 and the diversity antenna 170 to increase the signal-to-noise ratio of the combined signal. In some implementations, the transmitter-receiver 104 processes the signals to perform MIMO (Multiple Input / Multiple Output) communication.

[0024] In some embodiments, the diversity antenna 170 is configured to receive signals within multiple cellular frequency bands and / or frequency bands of a wireless local area network (WLAN). In such embodiments, the wireless device 100 may include a multiplexer, a switching network, and / or a filter arrangement coupled to the diversity antenna 170, which is configured to separate the diversity signal into different frequency ranges. For example, the multiplexer may be configured to include a low-pass filter that passes through a frequency range containing cellular low-pass frequencies, a band-pass filter that passes through a frequency range containing low-band WLAN signals and mid- and high-band signals, and a high-pass filter that passes through a frequency range containing high-band WLAN signals. This example is for illustrative purposes only.As another example, the multiplexer can have a variety of different configurations, such as a diplexer / two-way crossover that offers the functionality of a high-pass filter and a low-pass filter.

[0025] Since the diversity antenna 170 is physically separated from the primary antenna 160, it can be coupled to the transmitter-receiver 104 via a transmission line, such as a cable or a printed circuit board (PCB) trace. In some implementations, the transmission line is lossy and attenuates the signal received at the diversity antenna 170 before it reaches the transmitter-receiver 104. Therefore, in some implementations, amplification is applied to the signal received at the diversity antenna 170. This amplification (and other analog processing, such as filtering) can be applied by the diversity receiver module 108. Because such a diversity receiver module 108 can be physically located near the diversity antenna 170, it can be referred to as a diversity receiver front-end module, examples of which are described in more detail below.

[0026] The RF module 106 and the diversity receiver module 108 include variable-gain amplifiers 110a and 110b, configured to provide a variety of gain modes for amplifying signals from the primary antenna 160 and the diversity antenna 170, respectively. Each variable-gain amplifier 110a or 110b may include a gain stage 120 and a degeneration circuit block 130, which changes the inductance, at least partially, based on a gain mode of the variable-gain amplifier 110a or 110b. Signals received at the variable-gain amplifiers 110a and 110b may be amplified by the gain stage 120, or the signals may bypass the gain stage 120, as described in more detail below. The selected inductance of the degeneration switching block 130, the bypass path and / or the amplification mode of the variable gain amplifier 110a, 110b can be controlled by the control unit 102.The degeneration block 130 can be configured to change the inductance, thereby increasing the performance of the variable-gain amplifier 110a, 110b relative to an amplifier with a fixed inductance. Performance can be increased by improving linearity and / or reducing noise, such as that generated during amplification. The variable-gain amplifier 110a, 110b can receive multiple input signals and output a single signal or a variety of output signals. In certain implementations, individual inputs may have corresponding individual degeneration blocks to improve input isolation between the input ports.

[0027] Advantageously, the architecture of the 110a, 110b variable gain amplifier allows for multi-input processing without the use of a switch. The 110a, 110b variable gain amplifier can achieve targeted or improved linearity by employing a switchable degeneration block with matched inductors. The 110a, 110b variable gain amplifier can provide targeted or improved isolation between input and output by using a shunt switch in the bypass path. The 110a, 110b variable gain amplifier can provide a low-loss direct bypass mode in certain gain modes, such as a low-gain mode.

[0028] The controller 102 can be configured to generate control signals and / or send them to other components of the wireless device 100. In some embodiments, the controller 102 provides signals that are based, at least in part, on specifications of the Mobile Industry Processor Interface Alliance (MIPL®). The controller 102 can be configured to receive signals from other components of the wireless device 100 and process them to determine control signals to be received by other components. In some embodiments, the controller 102 can be configured to analyze signals or data to determine control signals to be sent to other components of the wireless device 100. The controller 102 can be configured to generate control signals based on gain modes provided by the wireless device 100.For example, the controller 102 can send control signals to the variable gain amplifiers 110a and 110b to control the gain mode. Likewise, the controller 102 can be configured to generate control signals for selecting the inductors of the degeneration switching block 130. The controller can also be configured to generate control signals to control the variable gain amplifiers 110a and 110b to provide a bypass path.

[0029] In some implementations, the controller 102 generates an amplifier control signal (or signals) based on a quality of service (QoS) metric of an input signal received at the input. In other implementations, the controller 102 generates the amplifier control signals based on a signal received from a communication controller, which in turn may be based on a quality of service (QoS) metric of the received signal. The QoS metric of the received signal may be based, at least in part, on the diversity signal received by the diversity antenna 170 (e.g., an input signal received at the input). The QoS metric of the received signal may also be based on a signal received by a primary antenna 160. In some implementations, the controller 102 generates the amplifier control signals based on a QoS metric of the diversity signal without receiving a signal from the communication controller.In some implementations, the QoS metric includes signal strength. As another example, the QoS metric may include a bit error rate, data throughput, transmission delay, or another QoS metric. In some implementations, the controller 102 controls the gain (and / or current) of the amplifiers in the variable gain amplifiers 110a, 110b. In some implementations, the controller 102 controls the gain of other components of the wireless device based on an amplifier control signal.

[0030] In some implementations, the variable-gain amplifiers 110a, 110b may include a step-variable-gain amplifier configured to amplify received signals with a gain of one of a variety of configured amounts, indicated by an amplifier control signal. In some implementations, the variable-gain amplifiers 110a, 110b may include a continuously variable-gain amplifier configured to amplify received signals with a gain proportional to, or specified by, the amplifier control signal. In some implementations, the variable-gain amplifiers 110a, 110b may include a step-variable-current amplifier configured to amplify received signals by drawing a current from one of a variety of configured amounts, indicated by the amplifier control signal.In some implementations, the variable gain amplifiers 110a, 110b may include a continuously variable current amplifier configured to amplify received signals by drawing a current proportional to the amplifier control signal.

[0031] Fig. Figure 2 illustrates a diversity receiver (DRx) configuration 200 with a DRx front-end module (FEM) 208. The DRx configuration 200 includes a diversity antenna 170 configured to receive a diversity signal and deliver the diversity signal to the DRx FEM 208 via a filter arrangement 272. The filter arrangement 272 may, for example, include a multiplexer configured to selectively route signals within specific frequency ranges along the respective paths to a multi-input amplifier 220 coupled to a degeneration switching block 230. The signals can be radio frequency (RF) signals, which include, for example, and without limitation, cellular signals (e.g., low, medium, high and / or ultra-high band mobile frequencies), WLAN signals, BLUETOOTH® signals, GPS signals and the like.

[0032] The DRx FEM 208 is configured to process the diversity signals received by the filter array 272. For example, the DRx FEM 208 can be configured to filter the diversity signals to one or more active frequency bands, which may include cellular and / or WLAN frequency bands. The controller 102 can be configured to control the DRx FEM 208 to selectively route signals to specific filters to perform the filtering. As another example, the DRx FEM 208 can be configured to amplify one or more of the filtered signals using the amplifier 220. For this purpose, the DRx FEM 208 may include filters, low-noise amplifiers, band selector switches, matching circuits, and other components.The controller 102 can be configured to interact with components in the DRx FEM 208 and intelligently select paths for the diversity signals via the DRx FEM 208.

[0033] The DRx FEM 208 transmits at least a portion of the processed diversity signals to the transceiver 104. The transceiver 104 can be controlled by the controller 102. In some implementations, the controller 102 can be implemented within the transceiver (transceiver) 104.

[0034] The DRx FEM 208 can be configured to provide a variety of amplification modes. Different inductances can be provided for these amplification modes via a variable impedance stage 232 of the degeneration switching circuit 230. In one or more amplification modes, a switch 234 of the variable impedance stage 232 can be configured to select an impedance (e.g., an inductance) that is coupled to the amplifier 220. This can be done, for example, to improve the linearity of the amplification process. These selectable impedances can be integrated into a multi-input amplifier architecture.

[0035] In some embodiments, the use of selectable impedances coupled to a gain stage, e.g., an LNA, can provide improved linearity and / or IIP3. The variable impedance stage 232 with the switch 234 can advantageously allow the amplifier 220 to be coupled to a desired or target impedance for specific gain modes and / or signal amplitudes. In some embodiments, the DRx configuration 200 is configured to bypass the gain when operating in a low-gain mode and to amplify signals with the amplifier 220 when operating in other gain modes. This can advantageously allow the DRx configuration 200 to improve linearity in certain gain modes.

[0036] In some embodiments, the amplifier 220 is configured to receive a variety of input signals and provide a single output signal. In certain embodiments, the amplifier 220 can be configured to receive a variety of input signals and provide a corresponding variety of output signals. The filter arrangement 272 can be configured to route signals corresponding to specific frequency bands to the amplifier 220 via specific paths. In certain implementations, the amplifier 220 can provide different gain modes for the received signals. The variable impedance stage 232 can select different impedances for coupling with the amplifier 220 via the switch 234, the selected impedances being based at least partially on the gain mode of the amplifier 220.In certain implementations, the amplifier 220 can be operated in a bypass configuration, so that the signal passes through a bypass path, and in a gain configuration, so that the signal passes through a gain path with a selected impedance provided by the variable impedance stage 232. This can advantageously allow the DRx FEM 208 to provide variable gain and / or a variety of gain modes while reducing the negative effects on linearity (e.g., IIP3) and / or noise (LF) compared to configurations that do not provide selective bypass paths and / or variable impedances. The amplifier 220 can incorporate any suitable amplifier circuit configured to provide a desired or targeted gain.In some embodiments, the amplifier 220 includes a low-noise amplifier (LNA) circuit configured to amplify signals from a variety of frequency bands (e.g., cellular bands and / or WLAN frequency bands) received at a variety of inputs, or a multi-input LNA. It should be noted, however, that the embodiments described here are not limited to implementations using low-noise amplifiers, but also include implementations using a variety of amplifiers.

[0037] The amplifier 220 can be configured to amplify signals based, at least in part, on a variety of amplification modes. For example, the amplifier 220 can be configured to provide a first amplification or amplification for a first amplification mode, a second amplification or amplification for a second amplification mode, and so on. The amplifier 220 can be controlled by the controller 102 to control the amplification provided by the amplifier 220. For example, the controller 102 can provide the amplifier 220 with a signal indicating a desired or targeted amplification, and the amplifier 220 can provide the desired amplification. The controller 102 can, for example, receive an indication of the desired amplification from another component in a wireless device and control the amplifier 220, at least in part, based on this indication.Likewise, the degeneration switching block 230 can be controlled at least partially based on an amplification mode and / or a targeted amplification of the amplifier 220.

[0038] The controller 102 can be configured to control the DRx FEM 208 and selectively provide tailored or adapted impedances. For example, the controller 102 and the DRx FEM 208 can control the variable impedance stage 232 to configure the switch 234 to provide a targeted impedance based, at least in part, on a gain mode. As another example, the controller 102 and the DRx FEM 208 can control the amplifier to provide a bypass path based, at least in part, on a gain mode. As yet another example, the controller 102 and the DRx FEM 208 can use the amplifier 220 to provide a variety of gain modes. Example architectures of amplifiers with variable gain

[0039] Front-end modules typically include amplifiers, such as low-noise amplifiers (LNAs), to amplify received signals. In wireless devices offering a variety of gain modes, it can be advantageous to selectively provide a variable, customized, or specially tailored impedance in a gain stage to improve performance. Similarly, for at least one gain mode, it can be beneficial to bypass a gain stage to improve performance (e.g., to improve linearity).

[0040] Accordingly, variable-gain amplifiers are provided here, which selectively supply variable or matched impedances at a degeneration block and / or feedback block, depending at least partially on a gain mode of the variable amplifier. This advantageously reduces or eliminates power losses in one or more gain modes. Furthermore, the variable impedances can be configured to improve the linearity of the amplification process in specific gain modes. Likewise, the variable-gain amplifier can be configured to provide a low-loss bypass mode in a low-gain mode to improve signal quality.

[0041] Fig. Figure 3A illustrates an exemplary variable-gain amplifier configuration 310a, which includes a multi-input amplification stage 312 configured to receive multiple inputs and selectively amplify the received signals with the amplification stage 320 or provide a bypass path through a bypass block 340. The amplification stage 320 is coupled to a degeneration block 330 configured to selectively provide tailored impedances based at least partially on an amplification mode of the variable-gain amplifier configuration 310a. In certain implementations, the multi-input amplification stage 312 is configured to receive multiple signals at different input ports, with each individual input port configured to receive signals in one or more specific cellular frequency bands.For example, a signal in a first band can be received at a first input port, a signal in a second band at a second input port, and a signal in a third band at a third input port.

[0042] The variable-gain amplifier 310a can be configured to enable multi-input processing without the use of a switching network. The variable-gain amplifier 310a can be configured to achieve relatively high linearity through the use of the degeneration switching block 330. In certain implementations, the bypass block 340 includes a shunt switch, which can provide high input-to-output isolation compared to configurations with such a switch. The variable-gain amplifier 310a can be configured to provide a low-loss direct bypass mode by routing signals from the input through the bypass block 340 instead of the gain stage 320. The low-loss direct bypass mode can be implemented, for example, in a low-gain mode.

[0043] The variable-gain amplifier 310a includes the multi-input gain stage 312, which provides a voltage-to-current gain stage 320. The multi-input gain stage 312 can be configured to provide isolation between the inputs. In some embodiments, the variable-gain amplifier 310a may include a degeneration block 330 for each input to further isolate the inputs.

[0044] The degeneration block 330 is configured to provide an impedance for the input of the gain stage 320. This can improve performance by enabling power and / or noise matching with previous stages in the processing chain. The degeneration block 330 can be configured to improve the linearity of the gain stage 320 through a feedback mechanism. In some embodiments, the degeneration block 330 is configured to provide a first impedance for a first gain mode and a second impedance for a second gain mode. The selected impedances provided by the degeneration block 330 can also be configured to improve the linearity of the gain stage 320. The variable gain amplifier 310a can be configured to bypass the degeneration block 330.This can improve the linearity behavior by reducing or minimizing the leakage current flowing through the gain stage 320.

[0045] The bypass block 340 is configured to receive signals from the multiple inputs and provide a path to the output that bypasses the gain stage 320 or the degeneration circuit block 330. The bypass block 340 may include components that serve to isolate the input and output in one or more of the gain modes provided by the variable-gain amplifier 310a.

[0046] The feedback block 350a in medium-gain mode is configured to be activated for a subset of the gain modes provided by the variable-gain amplifier 310a. The feedback block 350a in medium-gain mode is configured to provide targeted impedances for the input signals. This can help improve the linearity of the amplification process. The feedback block 350a in medium-gain mode can also be configured to control the feedback within the variable-gain amplifier 310a. The feedback block 350a in medium-gain mode can be configured to provide functionality similar to including a second degeneration block in the circuit.

[0047] The bypass switch 360 is configured to selectively provide a path from the inputs through the bypass block 340 to the output, or a path from the inputs through the gain stage 320 to the output. The bypass switch 360 may include one or more switching elements for isolating and / or selecting the desired path, which are based at least partially on a gain mode of the amplifier 310a.

[0048] In certain embodiments, the variable-gain amplifier 310a can be configured to provide a variety of gain modes, e.g., gain modes G0, G1, ..., GN with G0 as the highest gain and GN as the bypass mode. When the variable-gain amplifier 310a is operated in gain mode GN, it can be configured to route signals from the inputs to the bypass block 340. When operating in gain modes G0 to GN-1, the variable-gain amplifier 310a can be configured to route signals through the gain stage 320 and activate the degeneration block 330. The degeneration block 330 can be configured to provide different impedance levels for individual gain modes or for groups of gain modes.Even in these gain modes, the bypass block 340 can be at least partially activated by activating a shunt switch within the bypass block 340 to ensure isolation between the inputs and the output. The variable gain amplifier 310a can be configured to activate the feedback block 350a for one or more of the gain modes G0 to GN-1.

[0049] The 310a variable-gain signal amplifier can be configured to achieve relatively low noise and high linearity (e.g., higher IIP3) compared to amplifiers without the disclosed feedback block 350a, bypass block 340, and degeneration switching block 330. The 310a variable-gain signal amplifier can be configured to amplify radio frequency (RF) signals such as cellular, Wi-Fi, Bluetooth®, GPS, and similar signals. The 310a variable-gain signal amplifier can be configured to provide broadband capabilities by receiving and processing signals across a variety of frequency bands at its multiple inputs. The 310a variable-gain signal amplifier can be configured to process signals at each input independently.The variable-gain signal amplifier 310a can be configured to be controlled by a control circuit arrangement, such as a controller (e.g., the controller 102 described here with reference to FIGS. 1 and 2). The control circuit arrangement can intelligently and selectively switch paths between an amplification path and a bypass path and selectively provide impedances with the degeneration switching block 330.

[0050] It should be noted that, although three inputs are shown, the 310a variable gain amplifier can include any number of inputs. For example, the 310a variable gain amplifier can, without restriction, include at least 2 inputs, at least 4 inputs, at least 8 inputs, at least 16 inputs, at least 32 inputs, at least 64 inputs, or any number of inputs within the ranges described. As another example, and without restriction, the 310a variable gain amplifier can include less than or equal to 64 inputs, less than or equal to 32 inputs, less than or equal to 16 inputs, less than or equal to 8 inputs, less than or equal to 4 inputs, or less than or equal to any number of inputs within the ranges described.

[0051] Fig. Figure 3B illustrates another example of a variable gain amplifier 310b, which uses the same components as the variable gain amplifier 310a. Fig. 3A contains, with the addition of certain elements. For example, the variable-gain amplifier 310b includes matching networks 313, 318, and 345. The input matching network 313 is configured to provide impedance matching for the signals received at the inputs. The output matching network 318 is similarly configured to provide impedance matching for an output load 316 and the amplifier comprising the gain stage 320 and a cascode buffer 314. The bypass matching network 345 similarly provides impedance matching for the bypass block 340. For matching networks 313, 318, and 345, any suitable combination of inductors and capacitors can be used to provide the desired impedances.

[0052] The variable-gain amplifier 310b also includes the output load 316 and the cascode buffer 314 as part of the amplification chain. The cascode buffer 314 can be configured to act as a current buffer. The cascode buffer 314 is configured to provide isolation between the amplification stage 320 and the output. The cascode buffer 314 can also be configured to improve the gain of the variable-gain amplifier 310b. The output load 316 is configured to provide a load to the current to generate an output voltage swing. The output load 316 can be configured to be tuned or tunable for each band received at the inputs. The output load 316 can be configured to improve the return loss and / or increase the bandwidth by adjusting the resistance of the output load 316.The voltage VDD can be configured to set the gain mode of amplifier 310b. For example, the voltage VDD can be configured so that a lower current flowing through the output load 316 corresponds to a lower gain of amplifier 310b.

[0053] Fig. 3C illustrates another example of a variable gain amplifier 310c, which is similar to the variable gain amplifier 310a from Fig. 3A is similar, except that the bypass switch 360 is removed. Without the bypass switch 360, the output of the bypass block 340 is coupled to the output of the gain stage 320. Furthermore, in medium gain mode, the feedback block is replaced by a cutoff switch block 350c, which is not coupled to the output, as in the variable gain amplifier 310a. Fig. 3A. Instead, the shutdown switch block 350c is configured to selectively isolate input nodes to reduce leakage in the amplifier 310c. In some examples, this can be achieved by activating a switch between an input node and a reference potential node when the input is not in use. In other examples, the switch can couple the input node to a reference potential node via a capacitive element.

[0054] Fig. 3D illustrates another example of a variable gain amplifier 310d, which uses the same components as the variable gain amplifier 310c. Fig. 3C contains certain elements added. For example, the variable-gain amplifier 310d includes matching networks 313, 318, and 345. The input matching network 313 is configured to provide impedance matching for the signals received at the inputs. The output matching network 318 is also configured to provide impedance matching for an output load 316 and the amplifier comprising the gain stage 320 and a cascode buffer 314. The bypass matching network 345 similarly provides impedance matching for the bypass block 340. Any suitable combination of inductors and capacitors can be used for the matching networks 313, 318, and 345 to provide the desired impedances.

[0055] The variable-gain amplifier 310d also includes the output load 316 and the cascode buffer 314 as part of the amplification chain. The cascode buffer 314 can be configured to act as a current buffer. The cascode buffer 314 is configured to provide isolation between the amplification stage 320 and the output. The cascode buffer 314 can also be configured to improve the gain of the variable-gain amplifier 310d. The output load 316 is configured to provide a current load to generate an output voltage swing. The output load 316 can be configured to be tuned or tunable for each band received at the inputs. The output load 316 can be configured to improve return loss and / or increase bandwidth by adjusting its resistance.The voltage VDD can be configured to set the gain mode of the amplifier 310d. For example, the voltage VDD can be configured so that a lower current flowing through the output load 316 corresponds to a lower gain of the amplifier 310d.

[0056] Fig. Figure 4 illustrates a variable-gain signal amplifier 410, which includes a variable-gain stage 420 configured to receive an input signal and generate an amplified output signal. The variable-gain signal amplifier 410 also includes a degeneration circuit 430 coupled to the variable-gain stage 420. The degeneration circuit 430 can be configured to provide a variety of different gain levels (gains) of the variable-gain stage 420.

[0057] Fig. Figure 5 illustrates a degeneration circuit 530, which includes a variable impedance stage 532 coupled to a signal amplifier 520, with different gain levels (amplifications). The variable impedance stage 532 can be configured to provide different impedance values ​​corresponding to the different gain levels. The degeneration circuit 530 includes a switch 534, which is functionally associated with the variable impedance stage 532 and is implemented to selectively isolate the variable impedance stage 532 from a reference potential node.

[0058] Fig. Figure 6 illustrates an example of the configuration of the variable gain amplifier 610, which is similar to the variable gain amplifier 310b described here with reference to Fig. 3B is configured. The variable gain amplifier 610 includes exemplary electrical components to demonstrate an exemplary implementation of the amplifier. However, it should be noted that this is only an exemplary implementation and the scope of the disclosure extends to additional implementations that incorporate similar architectures.

[0059] The variable-gain amplifier configuration 610 includes a multi-input amplification stage 612, configured to receive inputs A, B, and C and selectively amplify the received signals using the corresponding transistors Q3, Q4, and Q5 in conjunction with the cascode buffer 614 containing transistor Q10. The multi-input amplification stage 612 is also configured to provide a bypass path through a bypass block 340, which includes the switching transistors Q6, Q7, and Q8 for the respective inputs A, B, and C.

[0060] The multi-input gain stage 612 is coupled to a degeneration block 630, which is configured to selectively provide tailored or adapted impedances based at least partially on a variable-gain gain mode of the amplifier configuration 610. In certain implementations, the multi-input gain stage 612 is configured to receive multiple signals at different input ports, with each input port configured to receive signals in one or more specific cellular frequency bands. For example, input A receives a signal in a first band, input B receives a signal in a second band, and input C receives a signal in a third band. In some embodiments, each of the transistors Q3, Q4, and Q5 can be coupled to a dedicated degeneration block 630 to increase isolation between the input ports.The inputs are each coupled to the inductors L4, L5 and L6 to match the input impedance.

[0061] The 610 variable-gain amplifier configuration can be configured to enable multi-input processing without the use of a switching network. The 610 variable-gain amplifier configuration can be configured to achieve relatively high linearity through the use of the 630 degeneration switch block. In certain implementations, the 640 bypass block includes a shunt switch Q9, which can provide high input-to-output isolation compared to configurations with such a switch. The 610 variable-gain amplifier configuration can be configured to provide a low-loss direct-bypass mode by routing signals from the inputs through the 640 bypass block. The low-loss direct-bypass mode can be implemented, for example, in a low-gain mode.

[0062] The 610 variable-gain amplifier configuration includes the 312 multi-input gain stage, which provides a voltage-to-current gain stage with transistors Q3-Q5. The 312 multi-input gain stage is configured to provide voltage-to-current gain. Furthermore, the 312 multi-input gain stage is configured to amplify appropriate input signals in conjunction with the 614 cascode buffer, which includes transistor Q10. The 614 cascode buffer is configured to act as a current buffer, reducing the input impedance and increasing the output impedance.

[0063] The degeneration block 630 is configured to provide an impedance for the gain stage of the multi-input amplifier stage 612. This can improve performance by enabling power and / or noise matching with preceding stages in the processing chain. The degeneration block 630 can be configured to improve the linearity of the gain stage (e.g., transistors Q3-Q5) through a feedback mechanism. The degeneration block 630 can be configured to provide a first impedance L1 for a first gain mode and a second impedance L1 and L2 for a second gain mode by activating transistors Q2 and Q1, respectively. The selected impedances provided by the degeneration block 630 can also be configured to improve the linearity of the gain stage.The variable-gain amplifier configuration 610 can be configured to bypass the degeneration block 630. This can improve linearity performance by reducing or minimizing the leakage current flowing through the gain stage. In certain implementations, the degeneration block 630 can be configured to provide lower inductance for higher gain modes. The amount of inductance provided by the degeneration block 630 may change with changes in the gain mode of the variable-gain amplifier configuration 610.

[0064] Bypass block 640 is configured to receive signals from the multiple inputs and provide a path to the output that bypasses the gain stage (e.g., transistors Q3-Q5) or the degeneration block 630. Bypass block 640 is configured to provide a single path to the output through transistor Q11 and capacitor C1. Capacitor C1 can be configured to block direct current (DC) voltages from an output supply. Bypass block 640 also includes a shunt switch through transistor Q9, which selectively couples bypass block 640 to a reference potential node to isolate the inputs from the output. A bypass matching network 645 can provide additional flexibility in impedance matching.

[0065] The feedback block 650 in medium-gain mode is configured to be activated for a subset of the gain modes provided by the variable-gain amplifier configuration 610. The feedback block 650 in medium-gain mode is configured to provide targeted impedances for the input signals. This can help improve the linearity of the amplification process. An RC matching network 651 can be used to control the amount of feedback in the system. Furthermore, the RC matching network 651 can be configured as a block of DC voltages. The RC matching network 651 can be configured to control the feedback behavior in amplitude and phase.The RC matching network 651 can include a capacitor, a resistor, a capacitor and a resistor in series, or any suitable combination of capacitors, resistors, and other components. The feedback block 650 in medium gain mode can also be configured to control the feedback within the variable gain amplifier 610. The feedback block 650 in medium gain mode can be configured to provide functionality similar to including a second degeneration block in the circuit.

[0066] When activated, signals from the respective inputs A, B, and C enter the medium-gain feedback block 650 at points A, B, and C, and exit the block at point D. This point D is coupled to the circuit preceding an output matching network 618 and a bypass switch 660. In other words, the medium-gain feedback block 650 couples the respective inputs A, B, and C to the output via transistors Q14-Q16 and Q18. The additional transistor Q17 can be configured to provide a shunt switch for a reference potential node, similar to the bypass block 640. Point D can be positioned before, within, or after the output matching network 618.Since the feedback block 650 can be configured in medium gain mode to create resolution between input and output, point D can be positioned within the variable gain amplifier configuration 610 to improve performance.

[0067] The bypass switch 660 is configured to selectively provide a path from inputs A, B, and C through the bypass block 640 to the output, or a path from inputs A, B, and C through the gain and amplifier elements (e.g., the cascode buffer 614 and the output matching network 618) to the output. The bypass switch 660 includes a transistor Q12, which controls the connection of a gain path to the output, and a transistor Q13, which controls the connection of a bypass path to the output. The bypass switch 660 can be controlled, at least partially, based on a gain mode of the amplifier 610.

[0068] The matching networks 618 and 645 can include any suitable combination of inductors and capacitors to provide the desired impedances. The output matching network 618 is configured to provide impedance matching for an output load 616 and the amplifier comprising the gain stage (e.g., transistors Q3-Q5) and the cascode buffer 614. The bypass matching network 645 also provides impedance matching for the bypass block 640.

[0069] The variable-gain amplifier 610 includes the output load 616 and the cascode buffer 614 as part of the amplification path. The cascode buffer 614 includes transistor Q10, which is configured as a current buffer. The cascode buffer 614 is configured to provide isolation between the amplification stage and the output. The cascode buffer 614 can also be configured to improve the gain of the variable-gain amplifier 610. The output load 616 is configured to provide a load to the current in order to generate an output voltage swing. The output load 616 can be configured to be tuned or tunable for each band received at the inputs. For example, the output load includes a variable capacitor C2, which can be tuned for specific mobile phone frequency bands.The output load 616 can also be configured to improve return loss and / or increase bandwidth by adjusting the resistance R1 of the output load 616.

[0070] The voltage VDD can be configured to set the gain mode of amplifier 310b. For example, the voltage VDD can be configured so that a lower current flowing through the output load 316 corresponds to a lower gain of amplifier 310b.

[0071] The Fig. 7A-7C illustrate examples of operating modes of the 610 variable gain signal amplifier configuration from Fig. 6. Fig. Figure 7A illustrates operation in one or more high-gain modes. In these high-gain modes, bypass block 640 is deactivated, except for shunt switch Q9. Signals received at inputs A, B, and C are passed through the amplification stage with transistors Q3-Q5 and through cascode buffer 614 to the output via output matching network 618 and bypass switch 660. The bypass switch activates Q12 and deactivates Q13 in these high-gain modes. Furthermore, transistor Q2 is on and transistor Q1 is off in these high-gain modes, so the inductance supplied to the amplification stage via degeneration block 630 is L1. The feedback block 650, normally used in medium-gain mode, is also deactivated in these high-gain modes.

[0072] Fig. Figure 7B illustrates operation in one or more medium-gain modes. These modes can also be referred to as low-gain and high-linearity modes. In these medium-gain modes, operation is similar to operation in one or more high-gain modes, with significant differences. First, in the degeneration block 630, transistor Q2 is off and transistor Q1 is on, so that the inductance supplied to the gain stage by the degeneration block 630 is provided by both L1 and L2. Thus, an increased impedance is provided for lower-gain modes, or a lower impedance for higher-gain modes. Second, the feedback block 650 is activated in medium-gain mode. This provides additional feedback to the circuit, similar to adding a second degeneration block.

[0073] Fig. Figure 7C illustrates operation in one or more low-gain modes. In these low-gain modes, bypass block 640 is activated and the gain stage transistors Q3-Q5 are deactivated. The signals received at inputs A, B, and C are routed to the output via bypass block 640, through bypass matching network 645, and bypass switch 660. The bypass switch activates Q13 and deactivates Q12 in these low-gain modes. Furthermore, transistors Q1 and Q2 are switched off to deactivate the degeneration circuit block 630, thus improving linearity by reducing or minimizing leakage current through the gain stage transistors Q3-Q5. The feedback block 650, which operates in medium-gain mode, is also deactivated in these low-gain modes.

[0074] Fig. Figure 8 illustrates a variable gain signal amplifier 810, which corresponds to the variable gain signal amplifier configuration 610 of Fig. 6 is similar, but without the bypass switch 660. Removing the bypass switch couples the output of the bypass matching network 645 to an input node of the output matching network 618 instead. In this configuration, there is no bypass switch to control the selection of a gain or bypass path. Rather, the selected transistors of the gain stage (e.g., transistors Q3-Q5) and the bypass block (e.g., transistors Q6-Q8) are selectively enabled and disabled to provide the bypass or gain path.

[0075] Fig. Figure 9 illustrates a variable gain signal amplifier 910, which corresponds to the variable gain signal amplifier configuration 610 of Fig. 6 is similar, but with a cutoff switch block 950 instead of a medium-gain feedback module. In this configuration, point D is omitted because the cutoff switch block 950 does not couple to the gain path at an output node of the output matching network 618. Instead, the cutoff switch block 950 includes transistors Q14-Q16 and capacitors C3-C5, configured to selectively disconnect input nodes A, B, and C. In some examples, the cutoff switch block 950 does not include capacitors C3-C5. The cutoff switch block 950 can be configured to turn on a switch (e.g., to activate a transistor) when a corresponding input is not in use. This can be done to disconnect that input to ground to reduce or eliminate leakage in the amplifier configuration.

[0076] Fig. Figure 10 illustrates a variable gain signal amplifier 1010, which corresponds to the variable gain signal amplifier configuration 910 of Fig. 9 is similar, but without the bypass switch 660. As with the variable gain signal amplifier 810 from Fig. 8. Removing the bypass switch results in the output of the bypass matching network 645 being coupled to an input node of the output matching network 618. In this configuration, there is no bypass switch to control the selection of a gain or bypass path. Instead, the selected transistors of the gain stage (e.g., transistors Q3-Q5) and the bypass block (e.g., transistors Q6-Q8) are selectively enabled and disabled to provide the bypass or gain path. Examples of products and architectures

[0077] Fig. Figure 11 shows that in some embodiments, some or all diversity receiver configurations, including some or all diversity receiver configurations with combinations of features (e.g., Figures 1-10), can be implemented wholly or partially in a single module. Such a module can be, for example, a front-end module (FEM). Such a module can be, for example, a diversity receiver (DRx) FEM. Such a module can be, for example, a MiMo (multi-input, multi-output) module.

[0078] In the example of Fig. A module 1108 can contain a packing substrate 1101, and a number of components can be mounted on such a packing substrate 1101. For example, a controller 1102 (which may include an integrated front-end power management circuit [FE-PIMC]), a combination assembly 1106, a variable-gain amplifier assembly 1110, which includes a gain stage 1120 and a degeneration block 1130 with one or more of the features described herein, and a filter bank 1109 (which may include one or more bandpass filters) can be mounted and / or implemented within the packing substrate 1101. Other components, such as a number of SMT devices 1105, can also be mounted on the packing substrate 1101.Although all the different components are shown on the packaging substrate 1101, it is understood that some components can be implemented via other components.

[0079] Fig. Figure 12 shows that in some embodiments some or all diversity receiver configurations, including some or all diversity receiver configurations with combinations of features (e.g. Fig. 1-10), can be implemented wholly or partially in an architecture. Such an architecture can include one or more modules and can be configured to provide frontend functionality such as diversity receiver (DRx) frontend functionality.

[0080] In the example of Fig. An architecture 1208 can include a controller 1202 (which may include an integrated front-end power management circuit [FE-PIMC]), a combination assembly 1206, a variable-gain amplifier assembly 1210, which includes a gain stage 1220 and a degeneration block 1230 with one or more of the features described herein, and a filter bank 1209 (which may include one or more bandpass filters) mounted and / or implemented on and / or within the packing substrate 1201. Other components, such as a number of SMT devices 1205, can also be implemented in the architecture 1208.

[0081] In some implementations, a device and / or circuit with one or more of the features described herein can be integrated into an electronic RF device, such as a wireless device. Such a device and / or circuit can be implemented directly in the wireless device, in a modular form as described herein, or in a combination of both. In some embodiments, such a wireless device may, for example, include a mobile phone, a smartphone, a portable wireless device with or without telephone functionality, a wireless tablet, etc.

[0082] Fig. Figure 13 represents an exemplary wireless device 1300 with one or more advantageous features described herein. Within the framework of one or more modules with one or more features as described herein, such modules can generally be represented by a dashed box 1306 (which can be implemented, for example, as a front-end module) and a diversity receiver (DRx) module 1308 (which can be implemented, for example, as a front-end module).

[0083] With reference to Fig. 13 Power amplifiers (PAs) 1382 can receive their respective RF signals from a transmitter-receiver 1304, which can be configured and operated to generate RF signals to be amplified and transmitted, and to process received signals. It is shown that the transmitter-receiver 1304 interacts with a baseband subsystem 1305, which is configured to provide conversion between user-friendly data and / or voice signals and RF signals suitable for the transmitter-receiver 1304. The transmitter-receiver 1304 can also be connected to a power management component 1307, which is configured to manage the power for the operation of the wireless device 1300. Such power management can also control the operation of the baseband subsystem 1305 and the modules 1306 and 1308.

[0084] It is shown that the baseband subsystem 1305 is connected to a user interface 1301 to enable various inputs and outputs of voice and / or data, which are made available to and received by the user. The baseband subsystem 1305 can also be connected to a memory 1303, which is configured to store data and / or instructions to facilitate the operation of the wireless device and / or to allow the user to store information.

[0085] In the example of the wireless device 1300, the outputs of the PAs 1382 are shown as matched (via corresponding matching circuits 1384) and routed to their respective duplexers 1386. Such amplified and filtered signals can be routed for transmission via a coupling network 1309 to a primary antenna 1360. In some embodiments, the duplexers 1386 can enable simultaneous transmitting and receiving operations using a common antenna (e.g., primary antenna 1360). Fig. Figure 13 shows that received signals are routed to a variable-gain amplifier arrangement 1310a, which provides the features and advantages of the variable-gain amplifiers described here. The DRx module 1308 also includes a similar variable-gain amplifier arrangement 1310b.

[0086] In the example of the wireless device 1300, signals received at the primary antenna 1360 can be sent to a variable-gain amplifier 1310a in the front-end module 1306. The variable-gain amplifier 1310a can include a gain stage 1320 and a degeneration circuit 1330. The variable-gain amplifier 1310a is configured to receive a variety of signals at its inputs 1311 and to output a variety of processed signals at its outputs 1319. The variable-gain amplifier 1310a is configured to amplify signals that are at least partially based on a gain mode and to provide targeted impedances with the degeneration circuit 1330, which is also at least partially based on the gain mode.This can be done to improve the linearity of signals with respect to variable-gain amplifiers that contain none or several of the described features. In at least one low-gain mode, the gain stage 1320 and the degeneration circuit block 1330 can be bypassed. In at least one non-low-gain mode, additional feedback can be provided in the variable-gain amplifier 1310a to improve the linearity of the amplification process, for example, by means of a feedback module in medium-gain mode, as described here.

[0087] The wireless device also includes a diversity antenna 1370 and a diversity receiver module 1308, which receives signals from the diversity antenna 1370. The diversity receiver module 1308 includes a variable gain amplifier 1310b, similar to the variable gain amplifier 1310a in the front-end module 1306. The diversity receiver module 1308 and the variable gain amplifier 1310b process the received signals and transmit the processed signals to the transmitter-receiver 1304. In some embodiments, as described herein, a diplexer / two-way crossover, triplexer / three-way crossover, or other multiplexer or filter arrangement may be installed between the diversity antenna 1370 and the diversity receiver module 1308.

[0088] One or more features of the present disclosure can be implemented using various cellular frequency bands, as described herein. Examples of such bands are listed in Table 1. It should be noted that at least some of the bands can be subdivided into subbands. It should also be noted that one or more features of the present disclosure can be implemented using frequency ranges that do not have designations such as the examples in Table 1. It should be noted that the terms high-frequency (RF) and radio frequency signals refer to signals that include at least the frequencies listed in Table 1. Table 1 Band Modus Tx Frequenzbereich (MHz) Rx Frequenzbereich (MHz) B1 FDD 1.920 - 1.980 2.110 - 2.170 B2 FDD 1.850 - 1.910 1.930 - 1.990 B3 FDD 1.710 - 1.785 1.805 - 1.880 B4 FDD 1.710 - 1.755 2.110 - 2.155 B5 FDD 824 - 849 869 - 894 B6 FDD 830 - 840 875 - 885 B7 FDD 2.500 - 2.570 2.620 - 2.690 B8 FDD 880 - 915 925 - 960 B9 FDD 1.749,9 - 1.784,9 1.844,9 - 1.879,9 B10 FDD 1.710 - 1.770 2.110 - 2.170 B11 FDD 1.427,9 - 1.447,9 1.475,9 - 1.495,9 B12 FDD 699 - 716 729 - 746 B13 FDD 777 - 787 746 - 756 B14 FDD 788 - 798 758 - 768 B15 FDD 1.900 - 1.920 2.600 - 2.620 B16 FDD 2.010 - 2.025 2.585 - 2.600 B17 FDD 704 - 716 734 - 746 B18 FDD 815 - 830 860 - 875 B19 FDD 830 - 845 875 - 890 B20 FDD 832 - 862 791 - 821 B21 FDD 1.447,9 - 1.462,9 1.495,9 - 1.510,9 B22 FDD 3.410 - 3.490 3.510 - 3.590 B23 FDD 2.000 - 2.020 2.180 - 2.200 B24 FDD 1.626,5 - 1.660,5 1.525 - 1.559 B25 FDD 1.850 - 1.915 1.930 - 1.995 B26 FDD 814 - 849 859 - 894 B27 FDD 807 - 824 852 - 869 B28 FDD 703 - 748 758 - 803 B29 FDD N / A 716 - 728 B30 FDD 2.305 - 2.315 2.350 - 2.360 B31 FDD 452,5 - 457,5 462,5 - 467,5 B32 FDD N / A 1.452 - 1.496 B33 TDD 1.900 - 1.920 1.900 - 1.920 B34 TDD 2.010 - 2.025 2.010 - 2.025 B35 TDD 1.850 - 1.910 1.850 - 1.910 B36 TDD 1.930 - 1.990 1.930 - 1.990 B37 TDD 1.910 - 1.930 1.910 - 1.930 B38 TDD 2.570 - 2.620 2.570 - 2.620 B39 TDD 1.880 - 1.920 1.880 - 1.920 B40 TDD 2.300 - 2.400 2.300 - 2.400 B41 TDD 2.496 - 2.690 2.496 - 2.690 B42 TDD 3.400 - 3.600 3.400 - 3.600 B43 TDD 3.600 - 3.800 3.600 - 3.800 B44 TDD 703 - 803 703 - 803 B45 TDD 1.447 - 1.467 1.447 - 1.467 B46 TDD 5.150 - 5.925 5.150 - 5.925 B65 FDD 1.920 - 2.010 2.110 - 2.200 B66 FDD 1.710 - 1.780 2.110 - 2.200 B67 FDD N / A 738 - 758 B68 FDD 698 - 728 753 - 783

[0089] Unless the context clearly requires otherwise, the terms “comprise,” “comprehensive,” and the like are to be interpreted in an inclusive sense, as opposed to an exclusive or exhaustive one; that is, in the sense of “including but not limited to.” The word “coupled,” as used generally here, refers to two or more elements, which may be either directly connected or linked by one or more intermediate elements. Furthermore, the words “here,” “above,” “below,” and words of similar meaning, when used in this application, refer to this application as a whole and not to a particular part thereof. Where the context permits, words in the above description that use singular or plural number may also include singular or plural number.The word "or" in relation to a list of two or more elements covers all of the following interpretations of the word: any of the elements in the list, all the elements in the list, and any combination of the elements in the list.

[0090] The foregoing detailed description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the form disclosed above. While specific embodiments and examples of the invention have been described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as recognized by those skilled in the art. For example, while processes or blocks are presented in a particular sequence, alternative embodiments may execute routines with steps or use systems with blocks in a different sequence, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these processes or blocks may be implemented in different ways.Although processes or blocks are sometimes depicted as being executed sequentially, these processes or blocks may instead be executed in parallel or at different times.

[0091] The teachings of the invention contained herein can be applied to other systems, not necessarily to the system described above. The elements and actions of the various embodiments described above can be combined to form further embodiments.

[0092] Although some embodiments of the inventions have been described, these embodiments are presented only as examples and are not intended to limit the scope of the disclosure. In fact, the new processes / methods and systems described herein can be embodied in a multitude of other embodiments; furthermore, various omissions, substitutions, and modifications to the form of the methods and systems described herein can be made without departing from the fundamental idea of ​​the disclosure.

Claims

[1] Variable gain signal amplifier (110a; 310a; 310b; 610), comprising: a variable gain stage (120; 220; 320; 612) configured to receive an input signal and produce an amplified output signal; a degeneration switching block (130; 230; 330; 630) coupled to the variable gain stage (120; 220; 320; 612) and configured to provide a variety of gain levels of the variable gain stage (120; 220; 320; 612); and a feedback block (350a; 650) in medium gain mode, coupled to an input of the variable gain stage (120; 220; 320; 612), so that the variable gain stage (120; 220; 320; 612) is provided with feedback for a subset of the multitude of gain levels. [2] Amplifier (110a; 310a; 310b; 610) according to claim 1, wherein the variable gain stage (120; 220; 320; 612) is designed to process high-frequency signals as input signals. [3] Amplifier (110a; 310a; 310b; 610) according to claim 1, wherein the amplifier (110a; 310a; 310b; 610) is configured to selectively provide a bypass path that bypasses the variable gain stage (120; 220; 320; 612) and a gain path that passes through the variable gain stage (120; 220; 320; 612). [4] Amplifier (110a; 310a; 310b; 610) according to claim 1, wherein the degeneration switching block (130; 230; 330; 630) has a variable impedance stage (232) designed to provide different inductances to the variable gain stage (120; 220; 320; 612). [5] Amplifier (110a; 310a; 310b; 610) according to claim 4, wherein the variable impedance stage (232) is configured to provide improved linearity of the amplified output signal by means of selectable impedances. [6] Amplifier (110a; 310a; 310b; 610) according to claim 4, wherein the variable impedance stage (232) of the degeneration switching block (130; 230; 330; 630) is configured to select a first impedance for a first gain level of the plurality of gain levels and a second impedance for a second gain level of the plurality of gain levels. [7] Amplifier (110a; 310a; 310b; 610) according to claim 6, wherein the first selectable impedance is greater than the second selectable impedance and the first gain is less than the second gain. [8] Amplifier (110a; 310a; 310b; 610) according to claim 1, further comprising a control circuit (102) configured to generate a gain control signal for controlling the variable gain stage (120; 220; 320; 612) and the degeneration switching block (130; 230; 330; 630). [9] Amplifier (110a; 310a; 310b; 610) according to claim 8, wherein the control circuit (102) is configured to provide a plurality of gain control signals corresponding to the plurality of gain levels. [10] Amplifier (110a; 310a; 310b; 610) according to claim 1, further comprising a bypass block (340; 640) coupled to an input of the variable gain stage (120; 220; 320; 612) and configured to be activated at a low gain level of the plurality of gain levels to provide a bypass path that does not include the variable gain stage (120; 220; 320; 612). [11] Amplifier (110a; 310a; 310b; 610) according to claim 10, wherein the bypass path does not include the degeneration switching block (130; 230; 330; 630). [12] Amplifier (310b; 610) according to claim 1 further comprising a cascode buffer (314; 614) coupled to an output of the variable gain stage. [13] Amplifier (110a; 310a; 310b; 610) according to claim 1, further comprising a plurality of input nodes (A, B, C) coupled to the variable gain stage (120; 220; 320; 612). [14] Amplifier (110a; 310a; 310b; 610) according to claim 4, wherein the variable impedance stage (232; Q2; L1; L2) is configured to provide different impedance values ​​associated with the different gain levels, and the degeneration switching block (130; 230; 330; 630) further comprises a switch (Q1) functionally associated with the variable impedance stage (232; Q2; L1; L2) and configured to selectively isolate the variable impedance stage (232; Q2; L1; L2) from a reference potential node. [15] Frontend architecture (1208), comprising: a signal amplifier (110a; 310a; 310b; 610; 1210) with variable gain according to claim 13; a filter arrangement (1209) coupled to the variable-gain signal amplifier (110a; 310a; 310b; 610; 1210) to direct frequency bands to select input nodes of the variable-gain signal amplifier (110a; 310a; 310b; 610; 1210); and a controller (1202) configured to control the variable gain signal amplifier (110a; 310a; 310b; 610; 1210) to provide a variety of gain modes, such that the variable gain signal amplifier (110a; 310a; 310b; 610; 1210) in a low gain mode directs signals along a path bypassing the variable gain stage. [16] Wireless device (100; 1300), comprising: a diversity antenna (160; 1360); a filter arrangement (1386) coupled to the diversity antenna (160; 1360) for receiving signals and directing frequency bands along selected paths; a signal amplifier (110a; 310a; 310b; 610; 1310a) with variable gain according to any one of claims 1 to 14; and a controller (1307) configured to control the variable-gain signal amplifier (110a; 310a; 310b; 610; 1310a) to provide a variety of gain modes, such that the variable-gain signal amplifier (110a; 310a; 310b; 610; 1310a) in a low-gain mode directs signals along a path bypassing the variable-gain stage.

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