Variable gain signal amplifier with programmable embedded attenuators, front-end architecture, and wireless device comprising such a signal amplifier

Abstract

A signal amplifier (310a; 310b; 410; 510; 910a; 910b) with variable gain, comprising: a first attenuation stage (320; 420; 620) having a plurality of branches, each of which includes a switch arrangement (324a-c; S1-S3; Q1-Q6) and a variable attenuation element (326a-c; R1), and having a common output (328; 628) and an input (322a-c; 622) for each branch, wherein the switch arrangement (324a-c; S1-S3; Q1-Q6) is designed to provide a bypass path bypassing the respective variable attenuation element (326a-c; R1) in a first switching state, to provide a path through the respective variable attenuation element (326a-c; R1) in a second switching state, and to prevent any signal path through the respective branch in a third switching state; an amplification stage (330; 930a; 930b) coupled to the common output (328; 628) of the first attenuation stage (320; 420; 620) to provide a multiplexed output; and a second attenuation stage (340; 540; 740) configured to receive the multiplexed output of the gain stage (330; 930a; 930b) to provide an amplified output signal to maintain various desired characteristics over a range of gain levels.

Description

BACKGROUND area

[0001] The present disclosure generally relates to amplifiers for wireless communication devices. More particularly, the invention relates to a variable gain signal amplifier, a front-end architecture, and a wireless device including such a signal amplifier. Description of related technology

[0002] In electronic applications, such as radio frequency (RF) applications, it is sometimes desirable to amplify or attenuate a signal. For example, a transmitted signal may be amplified by a power amplifier, and a received signal may be amplified by a low-noise amplifier. In another example, one or more attenuators may be implemented along one or both of the aforementioned transmit and receive paths, as needed or desired, to attenuate the respective signals.

[0003] US 2016 / 0 077 158 A1 discloses a transmit front-end module with variable attenuators and corresponding switches. US 2012 / 0 206 205 A1 discloses a variable-gain amplifier comprising a plurality of sequentially arranged attenuators and amplifier stages. SUMMARY

[0004] According to a number of implementations, the present disclosure relates to a variable gain signal amplifier including a first attenuation stage having a plurality of branches, each branch including a switch and a variable attenuation element, the first attenuation stage having a common output and an input for each branch. The amplifier also includes a gain stage coupled to the common output of the first attenuation stage to provide a multiplexed output. The amplifier also includes a second attenuation stage configured to receive the multiplexed output of the gain stage to provide an amplified output signal to maintain various desired characteristics over a range of gain levels.

[0005] In some embodiments, the signal includes a radio frequency signal. In some embodiments, the first attenuation stage is configured to provide a bypass path such that a signal received at an input is directed to the common output without being attenuated by the variable attenuation element. In further embodiments, the first attenuation stage is configured to provide the bypass path in a high-gain mode. In still further embodiments, in the high-gain mode, a noise figure of a signal is not increased because the variable attenuation element is at least partially bypassed. In further embodiments, in other gain modes, IIP3 of the signal is at least partially increased by adjusted attenuation by the variable attenuation element.

[0006] In some embodiments, the amplifier is configured to receive signals at respective inputs covering a plurality of cellular frequency bands. In some embodiments, the amplifier is configured to attenuate or amplify a signal received at a particular input independently of the attenuation or amplification of other signals received at other inputs.

[0007] In some embodiments, the amplifier further includes a control circuit configured to send control signals to the first attenuation stage, the gain stage, or the second attenuation stage. In further embodiments, the control circuit includes a controller configured to provide a gain control signal in a high-gain mode that causes the first attenuation stage to provide a path that bypasses the variable attenuation element.

[0008] According to a number of implementations, the present disclosure relates to a variable gain amplifier including a switching stage having a plurality of branches, each branch including a switch and an embedded programmable attenuator, the first switching stage having a common output and an input for each branch. The amplifier also includes a gain stage coupled to the common output of the switching stage to provide a multiplexed output.The amplifier also includes a post-amplification attenuation stage configured to receive the multiplexed output of the gain stage, wherein the post-amplification attenuation stage is configured to provide an attenuation path through an embedded programmable attenuator and a bypass path, the paths configured to maintain various desired characteristics over a range of gain levels. The amplifier also includes a splitter configured to receive a single input and provide a plurality of outputs.

[0009] In some embodiments, the first switching stage is configured to selectively route targeted signals to the gain stage. In some embodiments, the switching stage is configured, for individual branches of the plurality of branches, to provide an attenuation path that passes through the embedded programmable attenuation element and a bypass path that does not pass through the embedded programmable attenuation element. In further embodiments, the switching stage is configured in a high-gain mode to route signals along the bypass path. In still further embodiments, in high-gain mode, the signals directed along the bypass path before and after the switching stage maintain substantially the same value of a noise figure.In further embodiments, in other amplification modes, signals passed along attenuation paths improve linearity, at least in part through adjusted attenuations provided by the embedded programmable attenuation elements.

[0010] In some embodiments, the amplifier further includes a control circuit configured to send control signals to the switching stage, the gain stage, the post-amplification attenuation stage, or the distributor. In further embodiments, the control circuit includes a controller configured to provide a gain control signal in a high-gain mode that causes the switching stage to provide a path that bypasses the variable attenuation element.

[0011] According to a number of implementations, the present disclosure relates to a front-end architecture including a variable gain signal amplifier including a first attenuation stage having a plurality of branches, each branch including a switch and a variable attenuation element, the first attenuation stage having a common output and an input for each branch; an amplification stage coupled to the common output of the first attenuation stage to provide a multiplexed output; and a second attenuation stage configured to receive the multiplexed output of the amplification stage to provide an amplified output signal to maintain various desired characteristics over a range of gain levels.The front-end architecture also includes a filter arrangement coupled to the variable-gain signal amplifier to control frequency bands and select inputs of the variable-gain signal amplifier. The front-end architecture also includes a controller implemented to control the variable-gain signal amplifier to provide a variety of gain modes, such that, in a high-gain mode, the variable-gain signal amplifier routes signals along a path that bypasses the variable-attenuation element in a particular branch.

[0012] In some embodiments, in high-gain mode, a noise figure of a signal is not increased because the variable attenuation element is at least partially bypassed. In further embodiments, in other gain modes, the IIP3 of the signal is at least partially increased by adjusted attenuation by the variable attenuation element.

[0013] According to a number of implementations, the present disclosure relates to a wireless device including a diversity antenna and a filter arrangement coupled to the diversity antenna to receive signals and route frequency bands along selected paths.The wireless device also includes a variable gain signal amplifier coupled to the filter assembly to receive signals from selected paths, the variable gain signal amplifier including a first attenuator stage having a plurality of branches, each branch including a switch and a variable attenuation element, the first attenuator stage having a common output and an input for each branch; a gain stage coupled to the common output of the first attenuator stage to provide a multiplexed output; and a second attenuator stage configured to receive the multiplexed output of the gain stage to provide an amplified output signal to maintain various desired characteristics over a range of gain levels.The wireless device also includes a controller implemented to control the variable gain signal to provide a plurality of gain modes such that, in a high gain mode, the variable gain signal amplifier directs signals along a path that bypasses the variable attenuation element in a particular branch.

[0014] In some embodiments, in high-gain mode, a noise figure of a signal is not increased because the variable attenuation element is at least partially bypassed. In further embodiments, in other gain modes, the IIP3 of the signal is at least partially increased by adjusted attenuation by the variable attenuation element.

[0015] To summarize the disclosure, certain aspects, advantages, and novel features are described herein. It should be understood that not all of these advantages may necessarily be achieved in accordance with a particular embodiment. Thus, the disclosed embodiments may be practiced in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates a wireless device with a primary antenna and a diversity antenna. Fig. Figure 2 illustrates a diversity receiver (DRx) configuration with a DRx front-end module (FEM). Fig. Figure 3A illustrates an example of a variable gain amplifier that can be implemented in a front-end module, such as a diversity receive module. Fig. Figure 3B illustrates an example of a variable gain amplifier similar to the variable gain amplifier of Fig. 3A is configured. Fig. Figure 4 illustrates an example of a variable gain amplifier with a first attenuator stage having a plurality of inputs and a common output. Fig. Figure 5 illustrates an example of a variable gain amplifier with one gain stage and a second attenuation stage. Fig. Figure 6 illustrates an exemplary multiplexer having an input port, a band select switch, an attenuation select branch, and an output port. Fig. Figure 7 illustrates an exemplary post-amplification attenuation stage configured to provide an attenuation path and a bypass / bypass path. Fig. 8A and Fig. 8B illustrate examples of an attenuation stage operating in a bypass mode and an attenuation mode, respectively. Fig. 9A and Fig. 9B illustrate exemplary variable gain amplifiers including a pre-amplification attenuation stage, corresponding gain stages, an output matching network, and a post-amplification attenuation stage. Fig. 10A and Fig. 10B illustrate performance diagrams of the variable gain amplifiers of the Fig. 9A and Fig. 9B. Fig. Figure 11 shows that in some embodiments, some or all diversity receiver configurations may be implemented in whole or in part in a module. Fig. 12 shows that in some embodiments, some or all diversity receiver configurations may be implemented in whole or in part in one architecture. Fig. 13 illustrates an example of a wireless device having one or more of the advantageous features described herein. DETAILED DESCRIPTION OF SOME EMBODIMENTS

[0016] The headings contained herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the claimed invention. Overview

[0017] Fig. 1 illustrates a wireless device 100 having a primary antenna 160 and a diversity antenna 170. The wireless device 100 includes an RF module 106 and a transceiver 104 that can be controlled by a controller 102. The transceiver 104 is configured to convert between analog signals (e.g., radio frequency (RF) signals) and digital data signals. To this end, the transceiver 104 may include a digital-to-analog converter, an analog-to-digital converter, a local oscillator for modulating or demodulating a baseband analog signal to or from a carrier frequency, a baseband processor that converts between digital samples and data bits (e.g., voice or other types of data), or other components.

[0018] The RF module 106 is coupled between the primary antenna 160 and the transceiver 104. Because the RF module 106 may be physically located near the primary antenna 160 to reduce attenuation due to cable loss, the RF module 106 may be referred to as a front-end module (FEM). The RF module 106 may perform processing of an analog signal received by the primary antenna 160 for the transceiver 104 or received by the transceiver 104 and transmitted via the primary antenna 160. For this purpose, the RF module 106 may include filters, power amplifiers, low-noise amplifiers, band select switches, attenuators, matching circuits, and other components.

[0019] When a signal is transmitted to wireless device 100, the signal may be received at both primary antenna 160 and diversity antenna 170. Primary antenna 160 and diversity antenna 170 may be physically spaced such that the signal is received at primary antenna 160 and diversity antenna 170 with different characteristics. For example, in one embodiment, primary antenna 160 and diversity antenna 170 may receive the signal with different attenuation, noise, frequency response, and / or phase shift. Transceiver 104 may use both signals with different characteristics to determine data bits corresponding to the signal. In some implementations, transceiver 104 selects between primary antenna 160 and diversity antenna 170 based on the characteristics, such as selecting the antenna with the highest signal-to-noise ratio.In some implementations, transceiver 104 combines the signals from primary antenna 160 and diversity antenna 170 to increase the signal-to-noise ratio of the combined signal. In some implementations, transceiver 104 processes the signals to perform multiple-input / multiple-output (MIMO) communication.

[0020] In some embodiments, the diversity antenna 170 is configured to receive signals within cellular bands and wireless local area network (WLAN) frequency bands. In such embodiments, the wireless device 100 may include a multiplexer, a switching network (also referred to as a switching fabric), and / or a filter arrangement coupled to the diversity antenna 170 configured to separate the diversity signal into different frequency ranges. For example, the multiplexer may be configured to include a low-pass filter that sweeps a frequency range including low-band frequencies, a band-pass filter that sweeps a frequency range including low-band WLAN signals and mid- and high-band cellular signals, and a high-pass filter that sweeps a frequency range including high-band WLAN signals. This example is for illustrative purposes only.As another example, the multiplexer may have a variety of different configurations, such as a diplexer / two-way crossover that provides the functionality of a high-pass filter and a low-pass filter.

[0021] Because the diversity antenna 170 is physically spaced from the primary antenna 160, the diversity antenna 170 may be coupled to the transceiver 104 via a transmission line, such as a cable or a printed circuit board trace. In some implementations, the transmission line is lossy and attenuates the signal received at the diversity antenna 170 before it reaches the transceiver 104. Thus, in some implementations, gain is applied to the signal received at the diversity antenna 170. The gain (and other analog processing, such as filtering) may be applied by the diversity receiver module 108. Because such a diversity receiver module 108 may be physically located near the diversity antenna 170, it may be referred to as a diversity receiver front-end module, examples of which are described in more detail herein.

[0022] The RF module 106 and the diversity receiver module 108 include variable gain amplifiers 110a, 110b configured to selectively attenuate and amplify signals from the primary antenna 160 and the diversity antenna 170, respectively. Each variable gain amplifier 110a, 110b may include a programmable attenuation stage before and after a gain stage. Signals received at the variable gain amplifiers 110a, 110b may be attenuated by the pre-amplification attenuation stage, or the signals may bypass the attenuation, as further described herein. The selected attenuation or designated bypass path (also referred to as a bypass or bypass path) may be controlled by the controller 102. The variable, programmable attenuation may be embedded in the variable gain amplifier 110a, 110b.The variable gain amplifier 110a, 110b can receive multiple input signals and output a single signal or a plurality of output signals. Advantageously, the architecture of the variable gain amplifier 110a, 110b can enable a single amplifier, such as a low-noise amplifier (LNA), to process signals covering multiple cellular bands.

[0023] The controller 102 may be configured to generate and / or send control signals to other components of the wireless device 100. In some embodiments, the controller 102 provides signals based at least in part on specifications from the Mobile Industry Processor Interface Alliance (MIPI® Alliance). The controller 102 may be configured to receive signals from other components of the wireless device 100 to perform processing to determine control signals to be received by other components. In some embodiments, the controller 102 may be configured to analyze signals or data to determine control signals to be sent to other components of the wireless device 100. The controller 102 may be configured to generate control signals based on gain modes provided by the wireless device 100.For example, controller 102 may send control signals to variable-gain amplifiers 110a, 110b to control the attenuation and gain provided by the amplifiers. Similarly, controller 102 may be configured to generate control signals based on programmed attenuations. For example, controller 102 may send control signals to the pre- and post-amplification stages to control the amount of attenuation provided at those stages.

[0024] In some implementations, the controller 102 generates amplifier control signals based on a quality of service metric of an input signal received at the input. In some implementations, the controller 102 generates the amplifier control signals based on a signal received from a communication controller, which in turn may be based on a quality of service (QoS) metric of the received signal. The QoS metric of the received signal may be based at least in part on the diversity signal received from the diversity antenna 170 (e.g., an input signal received at the input). The QoS metric of the received signal may further be based on a signal received at a primary antenna 160. In some implementations, the controller 102 generates the amplifier control signals based on a QoS metric of the diversity signal without receiving a signal from the communication controller.In some implementations, the QoS metric includes signal strength. As another example, the QoS metric may include bit error rate, data throughput, transmission delay, or another QoS metric. In some implementations, the controller 102 controls the gain (and / or current) of the amplifiers in the variable gain amplifiers 110a, 110b. In some implementations, the controller 102 controls the gain of other components of the wireless device based on an amplifier control signal.

[0025] In some implementations, the variable gain amplifiers 110a, 110b may include a step-variable gain amplifier configured to amplify received signals with a gain of one of a plurality of configured amounts / degrees indicated by an amplifier control signal. In some implementations, the variable gain amplifiers 110a, 110b may include a continuously variable gain amplifier configured to amplify received signals with a gain proportional to or dictated by the amplifier control signal.In some implementations, the variable-gain amplifiers 110a, 110b may include a step-variable current amplifier configured to amplify received signals by drawing a current from one of the plurality of configured amounts indicated by the amplifier control signal. In some implementations, the variable-gain amplifiers 110a, 110b may include a continuously variable current amplifier configured to amplify received signals by drawing a current proportional to the amplifier control signal.

[0026] Fig. 2 shows a diversity receiver (DRx) configuration 200 with a DRx front-end module (FEM) 208. The DRx configuration 200 includes a diversity antenna 170 configured to receive a diversity signal and route the diversity signal to the DRx FEM 208 via a filter arrangement 272. The filter arrangement 272 may, for example, include a multiplexer configured to selectively route signals within targeted frequency ranges along the respective paths to a programmable attenuation multiplexer 210. The signals may include cellular signals (e.g., cellular frequencies in a low, mid, high, and / or ultra-high band) mixed with WLAN signals. In some embodiments, signals directed on a first path include cellular signals (e.g., mid and / or high band frequencies) with WLAN signals, and signals directed on a second path include cellular signals (e.g.,Low-band frequencies) without Wi-Fi signals.

[0027] The DRx FEM 208 is configured to perform processing of the diversity signals received from the filter assembly 272. For example, the DRx FEM 208 may be configured to filter the diversity signals to one or more active frequency bands, which may include cellular and / or WLAN frequency bands. The controller 102 may be configured to control the DRx FEM 208 to selectively route signals to targeted filters to perform the filtering. As another example, the DRx FEM 208 may be configured to amplify one or more of the filtered signals using the programmable attenuation multiplexer 210. For this purpose, the DRx FEM 208 may include filters, low-noise amplifiers, band select switches, matching circuits, and other components.The controller 102 may be configured to interact with components in the DRx FEM 208 to intelligently select paths for the diversity signals across the DRx FEM 208. In certain implementations, the filter assembly 272 is located on a separate chip from the DRx FEM 208.

[0028] The DRx FEM 208 transmits at least a portion of the processed diversity signals to the transceiver 104. The transceiver 104 may be controlled by the controller 102. In some implementations, the controller 102 may be implemented within the transceiver 104.

[0029] The DRx FEM 208 can be configured to provide a plurality of gain modes. Different attenuations can be applied in the multiplexer 210 for the plurality of gain modes. In one or more gain modes, the multiplexer 210 can be configured to route signals through an attenuation path that selectively attenuates the signal, such as with a variable and / or programmable attenuator. These programmable attenuators can be embedded in a multi-input amplifier architecture. In a high-gain mode, the multiplexer 210 can be configured to provide a bypass path so that the signal does not pass through the attenuation path. The programmable attenuators can be used before and / or after a gain stage.

[0030] In some embodiments, the use of programmable attenuation in a multiplexer before a gain stage, e.g., an LNA, may provide improved linearity and / or IIP3. The programmable attenuation may advantageously allow the signal to be tailored to a desired or targeted range of the amplifier. In certain implementations, attenuating a signal before the gain stage may increase noise in the signal. However, the DRx configuration 200 may be configured to attenuate signals with a relatively high signal-to-noise ratio and bypass attenuation for signals with a relatively low signal-to-noise ratio. In some embodiments, the DRx configuration 200 is configured to bypass attenuation when operating in a high-gain mode and attenuate signals when operating in other gain modes.This can advantageously allow the DRx configuration 200 to attenuate certain signals to improve linearity, while allowing other signals to bypass the attenuation so as not to increase noise in the signal. Another advantage of this configuration is that large signals entering the DRx FEM 208 can be selectively attenuated, preventing the amplifier from being damaged by signals larger than the amplifier is designed to handle. The embedded attenuators can allow the DRx FEM 208 to adjust the attenuation based on signals, gain mode, and amplifier operating characteristics to maintain and / or improve signal quality (e.g., by increasing or maintaining linearity through the amplification process).

[0031] In some embodiments, the programmable attenuation multiplexer 210 is configured to receive a plurality of input signals and provide a single output signal. In certain embodiments, the multiplexer 210 may be configured to receive a plurality of input signals and provide a corresponding plurality of output signals. The multiplexer 210 may be configured to provide a single output signal that is transmitted to a single amplifier, allowing the DRx FEM 208 to use one amplifier or amplifier stage for a plurality of frequency bands. This may advantageously reduce the number of components used in the DRx FEM 208 and thus reduce the cost of manufacturing the DRx FEM 208.

[0032] The multiplexer 210 may include switches that provide a plurality of switchable paths through the multiplexer 210. The plurality of switchable paths may correspond to a plurality of frequency bands, with each switchable path corresponding to a particular frequency band or bands (e.g., overlapping frequency bands). The filter arrangement 272 may be configured to route signals corresponding to particular frequency bands to the multiplexer 210 via particular paths. In certain implementations, the switchable paths through the multiplexer 210 may also be configured to selectively route signals to a particular path along an attenuation path or to bypass the attenuation path. For example, one or more switches may be operated in parallel with a variable attenuator such that, in a bypass configuration, the signal passes through the switch rather than the variable attenuator (e.g.,the switch is closed) and in an attenuation configuration, the signal passes through the variable attenuator (e.g., the switch is open). In the bypass configuration, the signal does not suffer any noise impact associated with the attenuation configuration. This can advantageously allow the DRx FEM 208 to provide variable gain and / or a variety of gain modes while reducing the impact on noise figure (NF) relative to configurations that do not selectively attenuate signals or configurations that do not adjust the attenuation of signals.

[0033] The switches of multiplexer 210 may be embedded on the same die as multiplexer 210. These embedded switches may be configured to selectively provide paths through multiplexer 210 and may be configured to selectively route signals along attenuation paths or bypass paths. The attenuation paths may be configured to attenuate signals, with the attenuation tailored to the gain stage following the switchable paths in multiplexer 210. The DRx FEM 208 with multiplexer 210 may be an architecture that provides a plurality of switchable paths with programmable attenuation, where each switchable path may be amplified with a variable-gain amplifier.

[0034] The controller 102 may be configured to control the DRx FEM 208 to selectively route signals to appropriate signal paths. For example, the controller 102 and the DRx FEM 208 may control the multiplexer 210 to route signals along an attenuation path or a bypass path. As another example, the controller 102 and the DRx FEM 208 may control the multiplexer 210 to provide switchable paths through the multiplexer 210 based on desired or targeted cellular or Wi-Fi signals. As another example, the controller 102 and the DRx FEM 208 may control the multiplexer 210 to adjust the attenuation for signals directed along the attenuation path. As another example, the controller 102 and the DRx FEM 208 may provide a variety of gain modes. Example architectures of variable gain amplifiers

[0035] Front-end modules typically include amplifiers such as low-noise amplifiers (LNAs) to amplify the received signals. In wireless devices that offer a variety of amplification modes, it can be advantageous to attenuate signals before amplification. However, this can negatively impact small signals, increase noise, and degrade the signal-to-noise ratio.

[0036] Accordingly, variable-gain amplifiers and multiplexers are provided herein that embed programmable attenuators in switchable paths that allow signals in a high-gain mode to bypass the attenuation. This advantageously reduces or eliminates performance degradation in the high-gain mode. Furthermore, the programmable attenuators can be configured to improve the linearity of the amplification process through pre-LNA attenuation in targeted gain modes. Although noise may increase in these gain modes that are attenuated before amplification, this increase in noise may be negligible or sufficiently small that the benefits of improved linearity make the trade-off desirable or advantageous.

[0037] Programmable attenuators can be embedded in switches located before and after an amplification stage. These programmable input and output attenuations can be adjusted to achieve targeted gain, noise figure (NF), and linearity (IIP3). Furthermore, these attenuations can be configured to make the amplifier less susceptible to noise when receiving large signals, as the attenuators can reduce the amplitude of these signals so that they fall within a targeted or suitable range for the amplifier.

[0038] Accordingly, the variable-gain amplifiers described here include integrated attenuators in a switching network. The attenuators can be embedded in switches and can be configured to have little or no impact on a noise figure in a high-gain mode, as the switching network can provide attenuation bypass in a high-gain mode and attenuation in other gain modes. The programmable attenuators can be embedded in a multi-input LNA architecture. For example, an attenuator block can be embedded in a multi-input switch, and an attenuator block can be embedded in an output switch.

[0039] Fig. 3A illustrates an example of a variable gain amplifier 310a that may be implemented in a front-end module 308a, such as a diversity receive module. The variable gain amplifier 310a includes a first attenuation stage 320, a gain stage 330, and a second attenuation stage 340. The first attenuation stage 320 provides pre-amplification attenuation, and the second attenuation stage 340 provides post-amplification attenuation. A controller 102 may be configured to control the operation of the first attenuation stage 320, the gain stage 330, and the second attenuation stage 340. The controller 102 is similar to the one described herein with reference to Fig. 1 and Fig. 2 described controller 102 is configured.

[0040] The variable gain amplifier 310a includes a plurality of input ports 312a-312c configured to receive input signals (e.g., RF signals) and an output port 318 configured to provide a processed (e.g., amplified and / or attenuated) signal. The first attenuation stage 320 includes a plurality of inputs 322a-322c corresponding to the input ports 312a-312c and a common output 328. The first attenuation stage 320 provides a plurality of branches with individual branches having a switch (e.g., switch 324a, 324b, or 324c) and a variable attenuation element (e.g., attenuator 326a, 326b, or 326c) configured to selectively provide a path through the first attenuation stage 320.Switches 324a-324c are configured to provide a path through first attenuation stage 320 and selectively pass signals through a corresponding attenuator 326a-326c or bypass attenuator 326a-326c. A signal passed along a single path through first attenuator 320 can be selectively attenuated with a customized attenuation at a corresponding attenuator 326a-326c or bypass attenuation. Switches 324a-324c can also be configured to selectively provide a path through first attenuator 320 to gain stage 330 for targeted or selected signals. For example, switches 324a-324c may be configured to pass signals arriving at certain input ports through first attenuator 320 while blocking signals from other input ports from arriving at output port 328.

[0041] The gain stage 330 is configured to amplify signals received from the first attenuator stage 320 and to provide the amplified signals to the second attenuator stage 340. In this way, the variable gain amplifier 310a can be configured to provide a multiplexed output, as the first attenuator stage 320 receives signals at a plurality of input ports 322a-322c and the gain stage 330 receives an input signal at a single input port and provides a processed signal at a single output port. The gain stage 330 can include any suitable amplifier circuit configured to provide a desired or targeted gain. In some embodiments, the gain stage 330 includes a single low-noise amplifier (LNA) circuit configured to receive signals from a plurality of frequency bands (e.g.,cellular bands and / or WLAN frequency bands). Thus, as used herein, the first attenuation stage 320 may be referred to as pre-LNA attenuation and the second attenuation stage 340 may be referred to as post-LNA attenuation. However, it should be noted that the embodiments described herein are not limited to implementations using low-noise amplifiers, but include implementations using a plurality of amplifiers in the variable-gain amplifier 310a.

[0042] The amplification stage 330 may be configured to amplify signals based at least in part on a plurality of amplification modes. For example, the amplification stage 330 may be configured to provide a first amplification or gain for a first amplification mode, a second amplification or gain for a second amplification mode, and so on. The amplification stage 330 may be controlled by the controller 102 to control the gain provided in the amplification stage. For example, the controller 102 may provide a signal to the amplification stage 330 indicative of a desired or targeted amplification, and the amplification stage 330 may provide the targeted amplification.For example, controller 102 may receive an indication of the desired gain from another component in a wireless device and control gain stage 330 based at least in part on that indication. Similarly, first and second attenuation stages 320, 340 may be controlled based at least in part on a gain mode and / or a targeted gain of amplifier 310a.

[0043] The second attenuation stage 340 may be configured similarly to the first attenuation stage 320. In particular, the second attenuation stage 340 may be similar to the first attenuation stage 320, configured to receive a signal at a single input and provide a signal at a single output. The second attenuation stage 340 is configured to receive a multiplexed output from the gain stage 330 and route the signal through switchable paths to selectively attenuate the signal with programmable attenuation or to bypass the attenuation. In certain embodiments, the second attenuation stage 340 provides at least two switchable paths through the stage, with a first path passing through an attenuator and a second path bypassing the attenuator.In various embodiments, the second attenuation stage 340 represents a single path through the stage, attenuating the signal with a fixed or programmable attenuation. The signal output from the second attenuation stage 340 is routed to the output port 318 of the amplifier 310a.

[0044] Accordingly, Fig. 3A illustrates a variable gain signal amplifier 310a including a first attenuation stage 320 having a plurality of branches, each branch including a switch 324a-324c and a variable attenuation element 326a-326c. The first attenuation stage 320 includes an input 322a-322c for each branch and a common output 328. The variable gain amplifier 310a includes a gain stage 330 coupled to the common output 328 of the first attenuation stage 320 to provide a multiplexed output. The variable gain amplifier 310a includes a second attenuation stage 340 configured to receive the multiplexed output of the gain stage 330 to provide an amplified output signal to maintain various desired characteristics over a range of gain levels.Each branch through the first attenuation stage 320 may include a bypass path and a switch-controlled attenuation path. The attenuation path includes variable or fixed attenuation for each branch.

[0045] The variable gain signal amplifier 310a may be configured to achieve relatively low noise and high linearity (e.g., higher IIP3) compared to amplifiers without an integrated switching network with programmable attenuators. The variable gain signal amplifier 310a may be configured to amplify radio frequency (RF) signals such as cellular signals, Wi-Fi signals, Bluetooth signals, GPS signals, and the like. The variable gain signal amplifier 310a may be configured to provide broadband capabilities by receiving signals across a plurality of frequency bands at the multiple inputs 312a-312c and processing those signals. The variable gain signal amplifier 310a may be configured to process signals at the respective inputs 312a-312c independently of one another.The variable gain signal amplifier 310a may be configured to be controlled by control circuitry, such as the controller 102. The control circuitry may intelligently and selectively switch paths in the first attenuation stage 320 and selectively program attenuations of the attenuators 326a-326c.

[0046] As described herein, the variable gain signal amplifier 310a provides a high-gain mode that does not suffer from the performance degradation experienced by other gain modes when passed through an attenuator prior to amplification. By embedding attenuators into existing switching architectures, high-gain or other gain modes can be configured to bypass attenuation, thus eliminating a noise source in the processing chain. In some implementations, the variable gain signal amplifier 310a is a multi-input LNA with tunable pre- and / or post-LNA attenuations. Pre-LNA attenuation can be used to achieve targeted linearity, e.g., for large signals. In certain implementations, a single amplifier or LNA can be used for multiple cellular bands.

[0047] Fig. 3B illustrates an example of a variable gain amplifier 310b that is similar to the variable gain amplifier 310a described herein with reference to Fig. 3A. The variable gain amplifier 310b includes a splitter 350 configured to receive a signal at a single input port and provide signals at a plurality of output ports. The splitter 350 is controlled by the controller 102 to direct input signals to a particular output. Accordingly, the variable gain amplifier 310b may be configured to receive signals at a plurality of inputs 312a-312c and provide processed signals at a corresponding plurality of outputs 318a-318c. These signals may be selectively attenuated and amplified, as described herein with reference to Fig. 3A.

[0048] Fig. 3B thus illustrates a variable gain amplifier 310b including a first attenuation stage 320 having a plurality of branches, each branch including a switch 324a-324c and an attenuation element 326a-326c. The first attenuation stage 320 includes a common output 328 and an input 322a-322c for each branch. The variable gain amplifier 310b includes a gain stage 330 coupled to the common output 328 of the first attenuation stage 320 to provide a multiplexed output. The variable gain amplifier 310b includes a second attenuation stage 340 configured to receive the multiplexed output of the gain stage 330 to provide an amplified output signal to maintain various desired characteristics over a range of gain levels. The variable gain amplifier 310b includes a distributor or splitter 350.Each branch through the first attenuation stage 320 may include a bypass path and an attenuation path controlled by a switch. The attenuation path includes variable or fixed attenuation for each branch.

[0049] Fig. Figure 4 illustrates an example of a variable gain amplifier 410 having a first attenuator stage 420 with a plurality of inputs 322a-322c and a common output 328. The signals output at the common output 328 are passed to a gain stage 330, as described herein with reference to Figure 4. Fig. 3A and Fig. 3B. The variable gain amplifier 410 includes a controller 102 configured to provide control signals to the first attenuation stage 420 and the gain stage 330. These control signals may be configured to control the attenuation and / or gain of the variable gain amplifier 410.

[0050] Between the plurality of inputs 322a-322c and the common output 328 of the first attenuation stage 420, a plurality of branches 425a-425c are provided to provide switchable paths through the stage. Signals received at individual inputs 322a-322c are routed to a corresponding branch 425a-425c, with the corresponding branch 425a-425c configured to selectively provide a path through branch 425a-425c to the common output 328. If a path through branch 425a-425c is provided, the first attenuation stage 420 may be further configured to selectively route the signal path through a variable attenuator R1 or to bypass the attenuator R1. It should be noted that although three inputs 322a-322c and branches 425a-425c are shown, the variable gain amplifier 410 may include any number of inputs and corresponding branches.For example, and without limitation, the variable gain amplifier 410 may include at least 2 inputs and corresponding branches, at least 4 inputs and corresponding branches, at least 8 inputs and corresponding branches, at least 16 inputs and corresponding branches, at least 32 inputs and corresponding branches, at least 64 inputs and corresponding branches, or at least any number of inputs and corresponding branches in the described ranges.As another example, and without limitation, the variable gain amplifier 410 may include less than or equal to 64 inputs and corresponding branches, less than or equal to 32 inputs and corresponding branches, less than or equal to 16 inputs and corresponding branches, less than or equal to 8 inputs and corresponding branches, less than or equal to 4 inputs and corresponding branches, or less than or equal to any number of inputs and corresponding branches in the described ranges.

[0051] As an example, a single branch 425a-425c may be configured to open appropriate switches so that there is no signal path through the branch. The first attenuation stage 420 may thus be configured to select signals or frequency bands for processing by selectively providing paths from the inputs 322a-322c to the output 328.

[0052] For example, if the first attenuation stage 420 provides a path from an input 322a-322c through a corresponding branch 425a-425c to the output 328, individual branches 425a-425c can be further configured to selectively provide paths that attenuate signals or bypass attenuation. To bypass attenuation, e.g., in a high-gain mode, a branch 425a-425c closes switch S1 and opens switches S2 and S3. To attenuate the signal, such as in other gain modes, a branch 425a-425c opens switch S1 and closes switches S2 and S3, allowing the signal to pass through the variable attenuator R1. The switches S1-S3 can be any suitable component or combination of components that provide switching capabilities. The variable attenuator R1 can be any suitable component or combination of components that allows for programmable attenuation.The variable attenuator R1 may be configured to provide different levels of attenuation based at least in part on signals received from the controller 102, the gain mode provided by the variable gain amplifier 410, or a combination of both. The variable attenuators R1 may be programmable attenuators embedded in input switches. This may reduce or eliminate negative effects on the noise figure (NF) in certain gain modes that bypass the attenuators, such as high-gain modes.

[0053] Fig. Figure 5 illustrates an example of a variable gain amplifier 510 having a gain stage 330, as described herein with respect to the Fig. 3A and Fig. 3B, and a second attenuation stage 540. The variable gain amplifier 510 includes a controller 102 configured to provide control signals to the gain stage 330 and the second attenuation stage 540. These control signals can be configured to control the attenuation and / or gain provided by the variable gain amplifier 510.

[0054] The second attenuation stage 540 may be configured to selectively pass signals received from the gain stage 330 through a variable attenuator R1 or to bypass the attenuator R1. To bypass the attenuation, such as in a high-gain mode, the second attenuator stage 540 closes switch S1 and opens switches S2 and S3. To attenuate the signal, such as in other gain modes, the second attenuator stage 540 opens switch S1 and closes switches S2 and S3 so that the signal passes through the variable attenuator R1. The variable attenuator R1 may be integrated into the output switch. The variable attenuator R1 may be bypassed in certain gain modes, thereby reducing or eliminating the negative effects of attenuating signals for those gain modes, such as a high-gain mode.

[0055] Fig. 6 illustrates an exemplary multiplexer 620 having an input port 622, a band selection switch 623, an attenuation selection branch 625, and an output port 628. For clarity, a single branch is represented by the multiplexer 620, but it should be understood that multiple switches and branches may be provided by the multiplexer, as described herein with reference to Fig. 4, and these signals can be output at the common output port 628. Signals passed from the input port 622 to the output port 628 are transmitted to an amplification stage 330, which is described here with respect to the Fig. 3A and Fig. 3B. It is also to be understood that the multiplexer 620 and the gain stage 330 may be controlled by a controller (not shown), as described herein with respect to the Fig. 3A-5. Because the multiplexer 620 includes an attenuation selection branch 625, the multiplexer 620 may also be referred to as an attenuation stage, such as the one described here with respect to the Fig. 3A, Fig. 3B and Fig. 4 damping levels 320, 420 described in more detail.

[0056] With reference to Fig. 6, the band selection switch 623 allows the multiplexer 620 to select which signals are passed to the gain stage 330. This can be used to select signals from targeted, selected, or desired frequency bands. With multiple branches in the multiplexer 620, corresponding band selection switches 623 can be used to select targeted frequency bands for processing. These band selection switches 623 can be opened and closed in any suitable pattern (e.g., time-dependent) or based on signals from a controller. In this way, the multiplexer 620 and the gain stage 330 are configured to provide a multiplexed output. The band selection switch 623 includes transistors Q1, Q2, which are configured to selectively route signals to a ground potential or other reference voltage.The band select switch 623 may include other components to provide appropriate bias voltages for operating the transistors Q1, Q2 and / or for impedance matching or other signal conditioning elements.

[0057] The attenuation selection branch 625 is configured to selectively provide an attenuation path through the variable attenuator R1 and a bypass path through transistors Q3 and Q4. The attenuation path is controlled by transistors Q5 and Q6 and includes the variable attenuator R1 and resistors R2-R4. Resistors R2-R4 may have fixed resistance values and may be selected to provide desired signal characteristics over a range of gain modes, signal amplitudes, and / or programmed attenuations. The variable attenuator R1 may be configured to have a plurality of values that depend at least in part on an operating gain mode, frequency band, signal amplitude, or the like.The bypass path is controlled by transistors Q3 and Q4 and may include additional electrical components (not shown) to provide desired signal characteristics across a range of gain modes, signal amplitudes, and / or programmed attenuation. In some embodiments, the bypass path is selected during operation in a high-gain mode, and the attenuation path is selected during operation in other gain modes.

[0058] The multiplexer 620 may be configured as a multiplexer with variable gain in each branch. The programmable attenuation may be provided in a switching stage or switching network (also referred to as a switching network) prior to the gain stage 330. This switching stage may include a plurality of attenuation selection branches 625.

[0059] Fig. Figure 7 illustrates an example of a post-amplification attenuation stage 740 configured to provide an attenuation path and a bypass path. Signals received by an amplification stage 330, described here with respect to the Fig. 3A and Fig. 3B, can be selectively attenuated with a programmable attenuator R1. It should be noted that the post-amplification attenuator stage 740 and the gain stage 330 can be controlled by a controller (not shown), as described herein with reference to Fig. 3A-5. The post-amplification attenuation stage 740 can be implemented as a second attenuation stage 340, 540, which is described here with respect to the Fig. 3A, Fig. 3B and Fig. 5 is described in more detail.

[0060] Similar to the one with reference to Fig. 6, the post-amplification attenuation stage 740 is configured to selectively provide an attenuation path through the variable attenuator R1 and a bypass path through transistors Q3 and Q4. The attenuation path is controlled by transistors Q5 and Q6 and includes the variable attenuator R1 and resistors R2-R4. The resistors R2-R4 may have fixed resistance values and may be selected to provide desired signal characteristics across a range of gain modes, signal amplitudes, and / or programmed attenuations. The variable attenuator R1 may be configured to have a plurality of values that depend at least in part on an operating gain mode, frequency band, signal amplitude, or the like.The bypass path is controlled by transistors Q3 and Q4 and may include additional electrical components (not shown) to provide desired signal characteristics across a range of gain modes, signal amplitudes, and / or programmed attenuation. In some embodiments, the bypass path is selected during operation in a high-gain mode and the attenuation path is selected during operation in other gain modes.

[0061] The Fig. 8A and Fig. 8B illustrate examples of an attenuation stage 740 operating in a bypass mode ( Fig. 8A) and in a damping mode ( Fig. 8B). The attenuation stage 740 may be a post-amplification stage, as described herein with reference to Fig. 7, or a branch in a pre-amplification stage or a multiplexer, as described herein with reference to Fig. 6. In Fig. In the bypass mode shown in Figure 8A, transistors Q3 and Q4 are activated, while transistors Q5 and Q6 are deactivated. In this configuration, the signals pass through the electrical components provided between transistors Q3 and Q4, if any, before leaving the attenuator stage 740. In the bypass mode shown in Fig. In the attenuation mode illustrated in Figure 8B, transistors Q3, Q4 are deactivated while transistors Q5, Q6 are activated. In this configuration, the signals pass through resistors R2-R4 and variable attenuator R1 before exiting attenuation stage 740. The activation and deactivation of the transistors may be controlled by a controller (not shown). The value of variable attenuator R1 may be controlled by a controller (not shown). Although not shown for clarity, attenuation stage 740 may include other electrical components configured to provide appropriate control signals and bias voltages to transistors Q3-Q6 and variable attenuator R1.

[0062] The Fig. 9A and Fig. 9B illustrate, by way of example, variable gain amplifiers 910a, 910b, which include a pre-amplification attenuation stage 620, respective gain stages 930a, 930b, an input matching network 913, an output matching network 914, and a post-amplification attenuation stage 740. Variable gain amplifiers 910a, 910b include a plurality of input ports 912 and a common output port 918. Pre-amplification attenuation stage 620 may be similar to the attenuation stage or multiplexer 620 described in more detail herein with reference to Fig. 6. The post-amplification attenuation stage 740 may be configured similarly to the attenuation stage 740 described in more detail here with reference to Fig. 7 must be configured.

[0063] With reference to Fig. 9A, the gain stage 930a may include a cascode amplifier including transistors Q1, Q2, a voltage source VDD, a load ZL, and the inductance element ZS, which together amplify the signals received via the input matching network 913. The output matching network 914 includes components configured to adjust the impedances of the gain stage 930a to maintain desired signal characteristics. For example, the output matching network 914 may include one or more capacitors, one or more resistors, a combination of capacitors or resistors in series or parallel, or the like. The input matching network 913 includes components configured to adjust the impedances of the first attenuation stage 920 to maintain desired signal characteristics.For example, input matching network 914 may include one or more capacitors, one or more resistors, a combination of capacitors or resistors in series or parallel, or the like. In some embodiments, input matching network 913 may be included in gain stage 930a.

[0064] With reference to Fig. 9B, the gain stage 930b is similar to the gain stage 930a and additionally includes a degeneration circuit block 932. The degeneration circuit block 932 includes a second inductor ZS1 and the transistor Q3. The degeneration circuit block 932 is configured to add an additional inductance element ZS1 in one or more gain modes. For example, in a selected gain mode, the degeneration circuit block 932 may deactivate the transistor Q3 so that the path to ground or another reference voltage passes through both the inductance element ZS and the inductance element ZS1. In other gain modes, the degeneration circuit block 932 may activate the transistor so that the path to ground or another reference voltage passes through the inductance element ZS and not through the inductance element ZS1.This may affect the noise figure (NF) and / or the linearity (IIP3) of the gain stage 930b, as described herein with reference to . Fig. 10B is described in more detail.

[0065] The Fig. 10A and Fig. 10B show performance curves ie the operating behavior of amplifiers with variable gain 910a, 910b, each with respect to the Fig. 9A and Fig. 9B. Fig. Figure 10A illustrates noise figure (NF) and linearity (IIP3) curves of amplifier 910a (described with reference to Fig. 9A) and the effects of including the described pre-amplification attenuation stage 620. Also illustrated Fig. 10B Noise figure (NF) and linearity (IIP3) curves of the amplifier 910b (described with reference to Fig. 9B) and the effects of including the described pre-amplification attenuation stage 620.

[0066] In relation to Fig. 10A, the upper plots show the noise figure (NF) as a function of gain mode, where G4 is a low gain mode and the gain increases to G0, a high gain mode. On the upper left plot 1000a, the NF from the gain stage 930a (or LNA) is shown as a solid line 1002a, which is the NF without a pre-LNA attenuation stage 620. The target NF is shown as a dash-dotted line 1004a. The difference between the target NF 1004a and the NF from the LNA 1002a is the allowable pre-LNA attenuation, shown as a dashed line 1006a (e.g., the NF margin). By programming the variable attenuation of the pre-LNA attenuation stage, the target NF can be achieved, as shown in the upper right plot 1010a. The NF from the LNA with pre-LNA attenuation is shown as the solid line 1012a, which is substantially aligned with the target LNA, again as the dash-dotted line 1004a.

[0067] With further reference to Fig. 10A, the lower plots show linearity (IIP3) as a function of gain mode, where G4 is a low-gain mode and the gain increases to G0, a high-gain mode. On the lower left plot 1020a, the IIP3 from gain stage 930a (or LNA) is shown as solid line 1022a, which is the IIP3 without a pre-LNA attenuation stage 620. The target IIP3 is shown as dashed-dotted line 1024a. The allowable pre-LNA attenuation is again shown as dashed line 1006a. By programming the variable attenuation of the pre-LNA attenuation stage, linearity can be achieved that exceeds the target IIP3, as shown in plot 1030a. The IIP3 from the LNA with pre-LNA attenuation is shown as the solid line 1032a, which exceeds the target IIP3, again as the dashed line 1024a.

[0068] The diagrams in Fig. 10A illustrate that the disclosed variable-gain amplifiers can be configured to achieve a targeted or higher IIP3 in non-high-gain modes. Furthermore, the pre-LNA attenuation can be adjusted with the allowable LF margin to achieve a targeted front-end loss to increase the linearity (IIP3) performance in low-gain modes.

[0069] Continue in Fig. 10B, diagrams 1000, 1010b, 1020b, 1030b, 1030b illustrate the same parameters as in Fig. 10A, wherein the gain stage 930a is replaced by the gain stage 930b, which includes a degeneration circuit block 932. In other words, a difference between the variable gain amplifiers 910a, 910b includes the presence of the degeneration circuit block 932 in the variable gain amplifier 910b. In the plots / diagrams of Fig. Figure 10B shows the effect of turning on the degeneration block for gain mode G3 in the NF and IIP3 plots.

[0070] The upper graphs show the noise figure (NF) as a function of gain mode, where G4 is a low-gain mode and the gain increases to G0, a high-gain mode. On the upper left graph 1000b, the NF from the gain stage 930b (or LNA) is shown as a solid line 1002b, which is the NF without a pre-LNA attenuation stage 620. The target NF is shown as a dash-dotted line 1004b. The difference between the target NF 1004b and the NF from the LNA 1002b is the allowable pre-LNA attenuation, shown as a dashed line 1006b (e.g., the NF margin). By programming the variable attenuation of the pre-LNA attenuation stage, the target NF can be achieved, as shown in the upper right graph 1010b. The NF from the LNA with pre-LNA attenuation is shown as the solid line 1012b, which is substantially aligned with the target LNA, which in turn is shown as the dash-dotted line 1004b.

[0071] With continued reference to Fig. 10B, the lower plots show linearity (IIP3) as a function of gain mode, where G4 is a low-gain mode and the gain increases to G0, a high-gain mode. On the lower left plot 1020b, the IIP3 from gain stage 930b (or LNA) is shown as solid line 1022b, which is IIP3 without a pre-LNA attenuation stage 620. The target IIP3 is shown as dash-dotted line 1024b. The allowable pre-LNA attenuation is again shown as dashed line 1006b. By programming the variable attenuation of the pre-LNA attenuation stage, linearity can be achieved that exceeds the target IIP3, as shown in plot 1030b. The IIP3 from the LNA with pre-LNA attenuation is shown as the solid line 1032b, which exceeds the target IIP3, which in turn is shown as the dash-dotted line 1024b.

[0072] The diagrams in Fig. 10B illustrate that the disclosed variable-gain amplifiers can be configured to achieve a targeted or higher IIP3 in non-high-gain modes. Furthermore, the pre-LNA attenuation can be adjusted with the allowable NF margin to achieve a targeted front-end loss to increase linearity (IIP3) in low-gain modes. Examples of products and architectures

[0073] Fig. Figure 11 shows that in some embodiments, some or all diversity receiver configurations, including some or all diversity receiver configurations with combination of features (e.g., Fig. 1-9B), can be implemented entirely or partially in a module. Such a module can be, for example, a front-end module (FEM). Such a module can be, for example, a diversity receiver (DRx) FEM. Such a module can be, for example, a MIMO (multiple-input / multiple-output) module.

[0074] In the example of Fig. 11, a module 1108 may include a packaging substrate 1101, and a number of components may be mounted on such packaging substrate 1101. For example, a controller 1102 (which may include a front-end power management integrated circuit [FE-PIMC]), a combiner assembly 1106, a variable gain amplifier assembly 1110 including embedded programmable attenuators 1116 having one or more of the features described herein, and a filter bank 1109 (which may include one or more bandpass filters) may be mounted and / or implemented on and / or within the packaging substrate 1101. Other components, such as a number of SMT devices 1105, may also be mounted on the packaging substrate 1101. Although all of the various components are illustrated on the packaging substrate 1101, it should be understood that some components may be implemented over other components.

[0075] In some embodiments, the diversity receive module 1108 includes two or more variable gain amplifier assemblies 1110. In various implementations, the two or more variable gain amplifier units 1110 may be implemented on a single chip. Each assembly 1110 may include a first attenuation stage, a gain stage, and a second attenuation stage. The outputs of each assembly 1110 may be connected together. This may be advantageous to enable performance tuning over a wider frequency range. For example, a first assembly (assembly) may be tuned for a first frequency range and a second assembly (assembly) for a second frequency range. Signals may be directed to the corresponding assemblies 1110 and connected at a common output.Thus, the diversity receive module 1108 may be configured to cover a wider frequency range with improved performance compared to a configuration including a single amplifier arrangement.

[0076] Fig. Figure 12 shows that in some embodiments, some or all diversity receiver configurations, including some or all diversity receiver configurations with combinations of features (e.g., Fig. 1-9b), may be implemented in whole or in part in an architecture. Such an architecture may include one or more modules and may be configured to provide front-end functionality such as diversity receiver (DRx) front-end functionality.

[0077] In the example of Fig. 12, an architecture 1208 may include a controller 1202 (which may include a front-end power management integrated circuit [FE-PIMC]), a combination assembly 1206, a variable gain amplifier assembly 1210 including embedded programmable attenuators 1216 having one or more of the features described herein, and a filter bank 1209 (which may include one or more bandpass filters) may be mounted and / or implemented on and / or within the packaging substrate 1201. Other components, such as a number of SMT devices 1205, may also be implemented in the architecture 1208.

[0078] In some implementations, a device and / or circuit having one or more of the features described herein may be integrated into an RF electronic device, such as a wireless device. Such a device and / or circuit may be implemented directly in the wireless device, in modular form as described herein, or in a combination thereof. In some embodiments, such a wireless device may include, for example, a mobile phone, a smartphone, a portable wireless device with or without phone functionality, a wireless tablet, etc.

[0079] Fig. 13 illustrates an exemplary wireless device 1300 having one or more advantageous features described herein. Within the context of one or more modules having one or more features as described herein, such modules may generally be represented by a dashed box 1306 (which may be implemented, for example, as a front-end module) and a diversity receiver (DRx) module 1308 (which may be implemented, for example, as a front-end module).

[0080] With reference to Fig. 13, power amplifiers (PAs) 1382 may receive their respective RF signals from a transceiver 1304, which may be configured and operated to generate RF signals to be amplified and transmitted, and to process received signals. The transceiver 1304 is shown interacting with a baseband subsystem 1305 configured to provide conversion between data and / or voice signals suitable for a user and RF signals suitable for the transceiver 1304. The transceiver 1304 may also be in communication with a power management component 1307 configured to manage power for operation of the wireless device 1300. Such power management may also control the operation of the baseband subsystem 1305 and modules 1306 and 1308.

[0081] Baseband subsystem 1305 is shown connected to a user interface 1301 to facilitate various inputs and outputs of voice and / or data provided to and received from the user. Baseband subsystem 1305 may also be connected to a memory 1303 configured to store data and / or instructions to facilitate operation of the wireless device and / or to allow the user to store information.

[0082] In the example of wireless device 1300, it is shown that the outputs of PAs 1382 are matched (via corresponding matching circuits 1384) and routed to their respective duplexers 1386. Such amplified and filtered signals may be routed to a primary antenna 1360 for transmission via a coupling network 1309. In some embodiments, duplexers 1386 may enable transmit and receive operations to be performed simultaneously with a common antenna (e.g., primary antenna 1360). Fig. Figure 13 illustrates that received signals are routed to a variable gain amplifier assembly 1310a, which provides the features and advantages of the variable gain amplifiers described herein. The DRx module 1308 also includes a similar variable gain amplifier assembly 1310b.

[0083] In the example of wireless device 1300, the signals received at primary antenna 1330 may be adjusted (via appropriate adjustment circuits 1385) and sent to a variable gain amplifier 1310a in front-end module 1306. Variable gain amplifier 1310a may include a programmable pre-amplification attenuation arrangement 1320, an amplifier 1330, a programmable post-amplification attenuation arrangement 1340, and a splitter 1350. Variable gain amplifier 1310a is configured to receive a plurality of signals at inputs 1312 and output a plurality of processed signals at outputs 1318.The variable gain amplifier 1310a is configured to provide a plurality of switchable paths for the amplifier 1310a, the plurality of switchable paths including embedded programmable attenuators that provide targeted gain across a plurality of gain modes and improve linearity for signals relative to variable gain amplifiers that do not include embedded programmable attenuators. In at least one high-gain mode, programmable attenuators may be bypassed to reduce or eliminate the impact on noise figure. In at least one non-high-gain mode, programmable attenuators may be adjusted to improve linearity for signals amplified in the at least one non-high-gain mode.

[0084] The wireless device also includes a diversity antenna 1370 and a diversity receiver module 1308 that receives signals from the diversity antenna 1370. The diversity receiver module 1308 includes a variable gain amplifier 1310b, similar to the variable gain amplifier 1310a in the front-end module 1306. The diversity receiver module 1308 and the variable gain amplifier 1310b process the received signals and transmit the processed signals to the transceiver 1304. In some embodiments, as described herein, a diplexer / two-way crossover, triplexer / three-way crossover, or other multiplexing or filtering arrangement may be incorporated between the diversity antenna 1370 and the diversity receiver module 1308.

[0085] One or more features of the present disclosure may be implemented using various cellular frequency bands, as described herein. Examples of such bands are listed in Table 1. It should be noted that at least some of the bands may be divided into subbands. It should also be noted that one or more features of the present disclosure may be implemented using frequency ranges that do not include designations like the examples in Table 1. It should also be noted that the term radio frequency (RF) and radio frequency signals refers to signals that include at least the frequencies listed in Table 1. Table 1 Band Modus Tx Frequenzbereich (MHz) Rx Frequenzbereich (MHz) B1 FDD 1.920 - 1.980 2.110 - 2.170 B2 FDD 1.850 - 1.910 1.930 - 1.990 B3 FDD 1.710 - 1.785 1.805 - 1.880 B4 FDD 1.710 - 1.755 2.110 - 2.155 B5 FDD 824 - 849 869 - 894 B6 FDD 830 - 840 875 - 885 B7 FDD 2.500 - 2.570 2.620 - 2.690 B8 FDD 880 - 915 925 - 960 B9 FDD 1.749,9 - 1.784,9 1.844,9 - 1.879,9 B10 FDD 1.710 - 1.770 2.110 - 2.170 B11 FDD 1.427,9 - 1.447,9 1.475,9 - 1.495,9 B12 FDD 699 - 716 729 - 746 B13 FDD 777 - 787 746 - 756 B14 FDD 788 - 798 758 - 768 B15 FDD 1.900 - 1.920 2.600 - 2.620 B16 FDD 2.010 - 2.025 2.585 - 2.600 B17 FDD 704 - 716 734 - 746 B18 FDD 815 - 830 860 - 875 B19 FDD 830 - 845 875 - 890 B20 FDD 832 - 862 791 - 821 B21 FDD 1.447,9 - 1.462,9 1.495,9 - 1.510,9 B22 FDD 3.410 - 3.490 3.510 - 3.590 B23 FDD 2.000 - 2.020 2.180 - 2.200 B24 FDD 1.626,5 - 1.660,5 1.525 - 1.559 B25 FDD 1.850 - 1.915 1.930 - 1.995 B26 FDD 814 - 849 859 - 894 B27 FDD 807 - 824 852 - 869 B28 FDD 703 - 748 758 - 803 B29 FDD N / A 716 - 728 B30 FDD 2.305 - 2.315 2.350 - 2.360 B31 FDD 452,5 - 457,5 462,5 - 467,5 B32 FDD N / A 1.452 - 1.496 B33 TDD 1.900 - 1.920 1.900 - 1.920 B34 TDD 2.010 - 2.025 2.010 - 2.025 B35 TDD 1.850 - 1.910 1.850 - 1.910 B36 TDD 1.930 - 1.990 1.930 - 1.990 B37 TDD 1.910 - 1.930 1.910 - 1.930 B38 TDD 2.570 - 2.620 2.570 - 2.620 B39 TDD 1.880 - 1.920 1.880 - 1.920 B40 TDD 2.300 - 2.400 2.300 - 2.400 B41 TDD 2.496 - 2.690 2.496 - 2.690 B42 TDD 3.400 - 3.600 3.400 - 3.600 B43 TDD 3.600 - 3.800 3.600 - 3.800 B44 TDD 703 - 803 703 - 803 B45 TDD 1.447 - 1.467 1.447 - 1.467 B46 TDD 5.150 - 5.925 5.150 - 5.925 B65 FDD 1.920 - 2.010 2.110 - 2.200 B66 FDD 1.710 - 1.780 2.110 - 2.200 B67 FDD N / A 738 - 758 B68 FDD 698 - 728 753 - 783

[0086] The present disclosure describes various features, none of which is solely responsible for the advantages described herein. It should be understood that various features described herein may be combined, modified, or omitted as would be apparent to one of ordinary skill in the art. Combinations and sub-combinations other than those specifically described herein will be apparent to one of ordinary skill in the art and are intended to form a part of this disclosure. Various methods are described herein in connection with various flowchart steps and / or phases. It should be understood that in many cases, certain steps and / or phases may be combined with one another so that multiple steps and / or phases depicted in the flowcharts may be performed as a single step and / or phase.Furthermore, certain steps and / or phases may be divided into further subcomponents that are to be performed separately. In some cases, the order of the steps and / or phases may be rearranged, and certain steps and / or phases may be omitted entirely. Furthermore, the methods described here are intended to be open-ended, so that additional steps and / or phases may be performed in addition to those presented and described here.

[0087] Some aspects of the systems and methods described herein may advantageously be implemented, for example, by computer software, hardware, firmware, or any combination of computer software, hardware, and firmware. Computer software may include computer-executable code stored on a computer-readable medium (e.g., a non-transitory computer-readable medium) that, when executed, performs the functions described herein. In some embodiments, computer-executable code is executed by one or more general-purpose computer processors. One of ordinary skill in the art will appreciate, in light of this disclosure, that any feature and function that can be implemented with software executing on a general-purpose computer may also be implemented with a different combination of hardware, software, or firmware.For example, such a module may be implemented entirely in hardware through a combination of integrated circuits. Alternatively or additionally, such a feature or function may be implemented, in whole or in part, using special-purpose computers designed to perform the functions described herein, rather than general-purpose computers.

[0088] Multiple distributed computing devices may be replaced by one of the computing devices described herein. In such distributed embodiments, the functions of the one computing device are distributed (e.g., across a network) such that some functions are performed on each of the distributed computing devices.

[0089] Some embodiments may be described with reference to equations, algorithms, and / or flowchart representations. These methods may be implemented using computer program instructions executable on one or more computers. These methods may also be implemented as computer program products, either separately or as part of an apparatus or system. In this regard, each equation, algorithm, block, or step of a flowchart, and any combination thereof, may be implemented by hardware, firmware, and / or software, including one or more computer program instructions embodied in computer-readable program code logic.As will be appreciated, such computer program instructions may be loaded onto one or more computers, including, but not limited to, a general-purpose computer or a special-purpose computer or other programmable processing device for fabricating a machine, such that the computer program instructions executing on the computer or other programmable processing device implement the functions specified in the equations, algorithms, and / or flowcharts. It should also be understood that each equation, algorithm, and / or block in flowchart representations, and combinations thereof, may be implemented by special-purpose hardware-based computer systems that perform the specified functions or steps, or combinations of special-purpose hardware and computer-readable program code logic means.

[0090] In addition, computer program instructions, as embodied in computer-readable program code logic, may also be stored in computer-readable memory (e.g., a non-transitory, computer-readable medium) that can direct one or more computers or other programmable processing devices to operate in a particular manner such that the instructions stored in the computer-readable memory implement the function(s) specified in the block(s) of the flowchart(s).The computer program instructions may also be loaded onto one or more computers or other programmable computing devices to cause a series of operational steps to be performed on one or more computers or other programmable computing devices to produce a computer-implemented process, such that the instructions executing on the computer or other programmable processing device provide steps for performing the functions specified in the equation(s), algorithm(s), and / or block(s) of the flowchart(s).

[0091] Some or all of the methods and tasks described herein may be performed and fully automated by a computer system. The computer system may, in some cases, include several different computers or computing devices (e.g., physical servers, workstations, storage arrays, etc.) that communicate and interact over a network to perform the described functions. Each of these computing devices typically includes a processor (or multiple processors) that executes program instructions or modules stored in a memory or other non-transitory, computer-readable storage medium or device. The various functions disclosed herein may be embodied in such program instructions, although some or all of the disclosed functions may alternatively be implemented in application-specific circuits (e.g., ASICs or FPGAs) of the computer system.If the computer system includes multiple computing devices, these devices may, but need not, be co-located. The results of the disclosed methods and tasks may be permanently stored by changing physical storage devices, such as semiconductor memory chips and / or magnetic disks, to a different state.

[0092] Unless the context clearly dictates otherwise, the terms "comprise," "comprising," and the like are intended to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is, in the sense of "including, but not limited to." The term "coupled," as used generally herein, refers to two or more elements that are either directly connected to one another or may be connected through one or more intermediate elements. Furthermore, the terms "here," "above," "below," and words of similar import, when used in this application, refer to this application as a whole and not to any particular part of this application. Where the context permits, words in the above detailed description containing the singular or plural may also include the plural or singular.The word "or" with reference to a list of two or more items covers all of the following interpretations of the word covers: any of the items in the list, all of the items in the list, and any combination of the items in the list. The word "exemplary" is used herein solely to mean "serving as an example, instance, or illustration." An implementation described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other implementations.

[0093] The disclosure is not intended to be limited to the implementations presented herein. Various changes to the implementations described in this disclosure may be readily apparent to those of ordinary skill in the art, and the general principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. The teachings of the invention contained herein may be applied to other methods and systems and are not limited to the methods and systems described above, and elements and acts of the various embodiments described above may be combined to form further embodiments.Accordingly, the novel methods and systems described herein may be embodied in a variety of other embodiments; further, various omissions, substitutions, and changes may be made to the embodiment of the methods and systems described herein without departing from the spirit of the disclosure.

Claims

[1] A signal amplifier (310a; 310b; 410; 510; 910a; 910b) with variable gain, comprising: a first attenuation stage (320; 420; 620) having a plurality of branches, each of which includes a switch arrangement (324a-c; S1-S3; Q1-Q6) and a variable attenuation element (326a-c; R1), and having a common output (328; 628) and an input (322a-c; 622) for each branch, wherein the switch arrangement (324a-c; S1-S3; Q1-Q6) is designed to provide a bypass path bypassing the respective variable attenuation element (326a-c; R1) in a first switching state, to provide a path through the respective variable attenuation element (326a-c; R1) in a second switching state, and to prevent any signal path through the respective branch in a third switching state; an amplification stage (330; 930a; 930b) coupled to the common output (328; 628) of the first attenuation stage (320; 420; 620) to provide a multiplexed output; and a second attenuation stage (340; 540; 740) configured to receive the multiplexed output of the gain stage (330; 930a; 930b) to provide an amplified output signal to maintain various desired characteristics over a range of gain levels. [2] Amplifier (310a; 310b; 410; 510; 910a; 910b) according to claim 1, which is designed to provide amplified output signals in the high frequency range. [3] The amplifier (310a; 310b; 410; 510; 910a; 910b) of claim 1 or 2, wherein the first attenuation stage (320; 420; 620) is configured to provide the bypass path in a high gain mode by setting the switch arrangement (324a-c; S1-S3; Q1-Q6) to the first switching state. [4] The amplifier (310a; 310b; 410; 510; 910a; 910b) according to claim 3, wherein in the high gain mode, a noise factor (NF) of the amplified output signal is not increased. [5] The amplifier (310a; 310b; 410; 510; 910a; 910b) of any one of claims 1 to 4, wherein the first attenuation stage (320; 420; 620) is configured to provide the path through the respective variable attenuation element (326a-c; R1) in a low gain mode by setting the switch arrangement (324a-c; S1-S3; Q1-Q6) to the second switching state. [6] Amplifier (310a; 310b; 410; 510; 910a; 910b) according to claim 5, wherein in the low gain mode the variable attenuation of the attenuation element (326a-c; R1) increases a linearity (IIP3) of the gain stage (330; 930a; 930b). [7] The amplifier (310a; 310b; 410; 510; 910a; 910b) of any one of claims 1 to 6, wherein the amplifier is configured to attenuate or amplify a signal received at a particular input (322a-c; 622) independently of the attenuation or amplification of other signals received at other inputs. [8] The amplifier (310a; 310b; 410; 510; 910a; 910b) according to any one of claims 1 to 7, further comprising a control circuit (102) configured to send control signals to the first attenuation stage (320; 420; 620), the amplification stage (330; 930a; 930b) or the second attenuation stage (340; 540; 740). [9] The amplifier (310a; 310b; 410; 510; 910a; 910b) of claim 8, wherein the control circuit (102) includes a controller configured to provide a gain control signal in a high gain mode to the bypass path by setting the switch arrangement (324a-c; S1-S3; Q1-Q6) to the first switching state. [10] The variable gain amplifier (310a; 310b; 410; 510; 910a; 910b) of any one of claims 1 to 9, wherein the second attenuation stage (340; 540; 740) is further configured to provide an attenuation path through an embedded programmable attenuator and a bypass path. [11] A variable gain amplifier (310a; 310b; 410; 510; 910a; 910b) according to any one of claims 1 to 10, further comprising: a distributor (350) configured to receive the amplified output signal at a single input and to provide a plurality of outputs (318a-c). [12] Frontend architecture (1208), comprising: a variable gain signal amplifier (310a; 310b; 410; 510; 910a; 910b) according to one of claims 1 to 11; a filter arrangement coupled to the variable gain signal amplifier (310a; 310b; 410; 510; 910a; 910b) for directing frequency bands to select inputs of the variable gain signal amplifier (310a; 310b; 410; 510; 910a; 910b); and a controller (102) configured to control the variable gain signal amplifier (310a; 310b; 410; 510; 910a; 910b) to provide a plurality of gain modes. [13] A wireless device (1300) comprising: a diversity antenna (1370); a filter arrangement (1308) coupled to the diversity antenna (1370) for receiving signals and directing frequency bands along selected paths; a variable gain signal amplifier (1310b) according to any one of claims 1 to 11 coupled to the filter arrangement (1308); and a controller (1307) configured to control the variable gain signal amplifier (1310b) to provide a plurality of gain modes.

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