Semiconductor device and power conversion device

Abstract

Semiconductor device, exhibiting: - an insulating substrate (2); - a semiconductor chip (6) arranged on the insulating substrate (2); - a conductor frame (8) bonded to an upper surface of the semiconductor chip (6); - a sealing resin (12) that covers the semiconductor chip (6), the insulating substrate (2) and the conductor frame (8); and - a resin (13) for stress reduction, which is partially applied to one end of the conductor frame (8) and has a lower modulus of elasticity than that of the sealing resin (12), wherein the resin (13) is applied in a plurality of lines parallel to each other on the upper surface of the conductor frame (8) to reduce stress.

Description

Area

[0001] The present invention relates to a semiconductor device and a power conversion device, wherein a semiconductor chip is sealed by means of a sealing resin. background

[0002] With the development of industrial equipment, electric railways, and automobiles, the operating temperature of semiconductor chips for use in these applications has also improved. In recent years, vigorous development has focused on semiconductor chips capable of operating at high temperatures, resulting in advances in miniaturization, increased breakdown voltage, and higher current density. In particular, the use of a wide-bandgap semiconductor such as SiC or GaN, with a larger bandgap than that of Si, has promised higher breakdown voltage, smaller size, higher current density, and operation at higher temperatures. To integrate a semiconductor chip with such characteristics into a device, especially when the chip operates at temperatures up to 150°C or higher, it is necessary to prevent delamination or other damage.To suppress detachment of a sealing resin, damage to wires and cracking of a connecting material in order to ensure stable operation of the semiconductor device.

[0003] In contrast, to prevent the reduction in moisture resistance caused by delamination at the interface between an epoxy sealant and a conductor frame, a semiconductor device has been proposed in which a low-hardness resin layer, such as a silicone resin, is applied to the top surface of the conductor frame to improve adhesion (e.g., see PTL 1). Meanwhile, a semiconductor device has been proposed that is pre-coated with a polyimide resin exhibiting excellent heat and moisture resistance before being sealed with an epoxy resin, thereby simultaneously improving the thermal fatigue life and moisture resistance of the solder joint component (e.g., see PTL 2). List of citations from patent literature [PTL 1] Japanese Patent JP 2 972 679 B2 [PTL 2] Japanese Patent JP 4 492 448 B2

[0004] German patent application DE 10 2015 215 786 A1 discloses a semiconductor device comprising a semiconductor element with a lower surface connected to an insulating side of a substrate, and a plate-shaped conductor connection connected to an upper surface of the semiconductor element, which has a horizontally extending region. The horizontally extending region of the conductor connection is connected to the semiconductor element and includes a linearly extending region in a top view. The semiconductor device further comprises a sealing resin that seals the semiconductor element together with the linearly extending region in the conductor connection.A linear expansion coefficient of the sealing resin represents a value between a linear expansion coefficient of the conductor terminal and a linear expansion coefficient of the semiconductor element, and the conductor terminal includes a recess or projection to horizontally and partially divide the linearly extending area into parts. Summary Technical Problem

[0005] A semiconductor device contains a component or element with a low coefficient of linear expansion, such as a semiconductor chip or an insulating substrate. Therefore, delamination between an element with a low coefficient of linear expansion and an epoxy resin becomes a problem due to thermal cycling, affecting the reliability of the insulation in an epoxy-sealed semiconductor device, although delamination was not a problem for a prior art silicone gel-sealed semiconductor device. For this reason, in recent years, a sealing resin with a low coefficient of linear expansion has been used, obtained by adding a large amount of ceramic filler to an epoxy resin.

[0006] A sealing resin with a high filler content exhibits an increased modulus of elasticity and reduced strength and robustness. Furthermore, the conductor frame contains a metal element and has a higher coefficient of linear expansion than a semiconductor chip or insulating substrate. Consequently, delamination occurs at the interface between the sealing resin, which has a low coefficient of linear expansion, and the conductor frame. This undesirably leads to cracking within the resin. Additionally, the viscosity of the resin tends to increase with a higher filler content, and this also undesirably causes the mixing and introduction of voids within the sealing resin.

[0007] The methods disclosed in PTL 1 and 2 have an effect on improving the adhesion between an epoxy resin and other elements and improving moisture resistance. However, in PTL 1, the end of the conductor frame, where internal stress tends to be generated, thus causing resin cracking, is not coated with a stress-relieving resin; this raises concerns regarding the reduction of the insulating properties associated with resin cracking in a semiconductor device. In contrast, in PTL 2, the entire area of ​​a semiconductor device is coated with a stress-relieving resin; accordingly, a narrow gap region, such as the underside of the conductor frame, is also coated with the stress-relieving resin, resulting in an even narrower gap region.Therefore, the sealing resin does not flow in the narrow gap area, leaving voids. This significantly and adversely affects the reliability of the semiconductor device's insulation.

[0008] The present invention was developed to solve the aforementioned problem. Its objective is to provide a semiconductor device and a power conversion device with highly reliable insulation, achieved by suppressing delamination and cracking of the sealing resin and reducing voids remaining in the sealing resin. Solution to the problem

[0009] The problem underlying the invention is solved according to the invention in a semiconductor device by the features of claim 1 and in an electrical power conversion device by the features of claim 11. Advantageous embodiments are the subject of the respective dependent claims.

[0010] A semiconductor device according to the present invention comprises: an insulating substrate; a semiconductor chip arranged on the insulating substrate; a conductor frame bonded to an upper surface of the semiconductor chip; a sealing resin covering the semiconductor chip, the insulating substrate, and the conductor frame; and a stress-reducing resin partially applied to one end of the conductor frame, having a lower modulus of elasticity than that of the sealing resin. According to the invention, the stress-reducing resin is applied to the upper surface of the conductor frame in a plurality of lines parallel to one another. Advantageous effects of the invention

[0011] In the present invention, the end of the conductor frame is coated with a stress-reducing resin having a lower modulus of elasticity than that of the sealing resin. Therefore, a semiconductor device and a power conversion device with high insulation reliability can be obtained by suppressing delamination and cracking of the sealing resin and reducing voids remaining in the sealing resin. Brief description of the drawings Fig. Figure 1 is a top view showing a semiconductor device according to embodiment 1 to explain the further technical background of the present invention. Fig. 2 is a cross-sectional view along I-II of Fig. 1. Fig.Figure 3 is a perspective view showing a ladder frame according to embodiment 1 to illustrate the further technical background of the present invention. Fig. Figure 4 is a perspective view to illustrate the dam structure according to embodiment 1 for the purpose of explaining the further technical background of the present invention. Fig. Figure 5 is a cross-sectional view to illustrate the inflow path of a sealing resin in a semiconductor device according to a comparative example. Fig. Figure 6 is a cross-sectional view showing the inflow path of the sealing resin in the semiconductor device according to embodiment 1 to explain the further technical background of the present invention. Fig.Figure 7 is a cross-sectional view illustrating the end of a ladder frame according to embodiment 2 for the purpose of explaining the further technical background of the present invention. Fig. Figure 8 is a cross-sectional view illustrating the end of the ladder frame according to a comparative example. Fig. Figure 9 is a cross-sectional view illustrating a modified example 1 of the end of the ladder frame according to embodiment 2 for the purpose of explaining the further technical background of the present invention. Fig. Figure 10 is a perspective view illustrating a modified inventive example 2 of the end of the ladder frame based on embodiment 2. Fig. Figure 11 is a cross-sectional view showing a semiconductor device according to embodiment 3 for the purpose of explaining the further technical background of the present invention. Fig. Figure 12 is a top view showing the semiconductor device according to embodiment 3 for the purpose of explaining the further technical background of the present invention. Fig. Figure 13 is a block diagram illustrating a configuration of an electrical power conversion system for which the electrical power conversion device according to the fourth embodiment is used to explain the further technical background of the present invention. Description of embodiments

[0012] With reference to the drawings, a semiconductor device and a power conversion device according to embodiments are described to explain the further technical background of the present invention and the invention itself. The same components are designated by the same symbols, and their repeated description can be omitted. Design 1 (for further technical background)

[0013] Fig. Figure 1 is a top view showing a semiconductor device according to embodiment 1 for the purpose of explaining the further technical background of the present invention. Fig. 2 is a cross-sectional view along I-II of Fig. 1. The semiconductor device of the present embodiment, for further technical background, is a semiconductor power module which is intended to be widely used for, for example, electrical household appliances, for industry, for automobiles, for trains and the like.

[0014] An insulating substrate 2 is provided on a base plate 1. An electrode pattern 3 is provided on the lower surface of the insulating substrate 2, and an electrode pattern 4 is provided on its upper surface. The electrode pattern 3 of the insulating substrate 2 is connected to the base plate 1 by a bonding material 5, such as solder.

[0015] The insulating substrate 2 is a ceramic plate made of Al₂O₃, SiO₂, Al₂O₃, BN, Si₃N₄, or the like. The insulating substrate 2 must have heat-dissipating and insulating properties and may, but is not limited to the above description, be a product of cured resin containing a ceramic powder dispersed therein, or a product of cured resin containing a ceramic plate embedded therein. A structure in which the insulating substrate 2 and the base plate 1 are integral or one-piece is also permissible. The ceramic powders to be used for the insulating substrate 2 are those of Al₂O₃, SiO₂, Al₂O₃, BN, Si₃N₄, and the like. However, diamond, SiC, B₂O₃, and the like are also permissible, but are not limited to these. The resins for use in the insulating substrate 2 are usually epoxy resins, but are not limited to these.A polyimide resin, a silicone resin, an acrylic resin and the like are also permissible, and any materials are permissible as long as they are materials with both the insulating property and the adhesive property.

[0016] A semiconductor chip 6 is arranged on the insulating substrate 2. The semiconductor chip 6 is an IGBT, a MOSFET, a diode, or the like. The main electrode on the lower surface of the semiconductor chip 6 is connected to the electrode pattern 4 of the insulating substrate 2 by a bonding material 7. Furthermore, only two semiconductor chips 6 are mounted on one electrode pattern 4 in the drawing. However, the semiconductor chips 6 can be mounted in any number required for their application, but this is not limited to the above.

[0017] A conductor frame 8 is bonded to the main electrode on the upper surface of the semiconductor chip 6 by means of a bonding material 9. A wire 10 is connected to a control electrode on the upper surface of the semiconductor chip 6. The semiconductor chip 6 is electrically connected to the external environment via the conductor frame 8 and the wire 10.

[0018] Copper is typically used for the base plate 1, the electrode arrays 3 and 4, and the conductor frame 8. However, any material can be used, provided it has heat-dissipating properties. For example, aluminum or iron, or a composite material thereof, can be used. Alternatively, a composite material such as copper / Invar / copper, or an alloy such as SiCal or CuMo, can be used. Furthermore, their surface is usually nickel-plated. However, gold or tin plating is also possible, but this is not limited to other options. Any structure is permissible as long as it is capable of supplying the necessary current and voltage to the semiconductor chip 6.

[0019] The wire 10 is a linear body with a circular cross-section, made of aluminum or gold, but could, for example, be a ribbon-like copper plate with a rectangular cross-section. Furthermore, four wires 10 are connected to the semiconductor chip 6 in the drawing; however, the number of wires 10 required according to the current density of the semiconductor chip 6 or the like may be provided, but this is not limited to the wire 10. Molten metal such as copper, tin, or the like, ultrasonic bonding, and the like can be used to bond the wire 10. The method / structure has no particular limitations, however, as long as it is a method / structure capable of supplying the necessary current and voltage to the semiconductor chip 6.

[0020] A housing 11 is arranged on the outer circumference of the base plate 1 and surrounds the semiconductor chip 6, the insulating substrate 2, and the conductor frame 8. The housing 11 is preferably a resin material with a high thermal softening temperature and is, for example, a PPS (polyphenylene sulfide) resin. However, the material is not subject to any particular restrictions as long as it is a material that does not thermally deform within the operating temperature range of the semiconductor device and has insulating properties. Any structure is permissible as long as it is a structure obtained by combining the conductor frame 8 by insert forming or outsert forming.

[0021] The housing 11 is filled with a sealing resin 12 and covers the semiconductor chip 6, the insulating substrate 2, and the conductor frame 8. The sealing resin 12 is, for example, an epoxy resin, but can, but is not limited to, be a resin with a favorable modulus of elasticity and heat resistance. Furthermore, to improve adhesion with the sealing resin 12, at least part of the surfaces of the electrode patterns 3 and 4 and the conductor frame 8 can be provided with microscopic irregularities or can be coated with an adhesion promoter such as a primer. Alternatively, a semiconductor device with a mold-type structure without the housing 11 formed therein is also permissible.

[0022] Fig.Figure 3 is a perspective view showing a conductor frame according to embodiment 1 to illustrate the further technical background of the present invention. The stress caused by the difference in the linear coefficient of thermal expansion between the sealing resin 12 and the conductor frame 8 is concentrated at the end of the conductor frame 8. Consequently, in the present embodiment, for further technical background, the end of the conductor frame 8, which is the region with concentrated stress, is coated with a resin 13 to reduce stress, having a lower modulus of elasticity than that of the sealing resin 12. This can reduce the stress applied to the sealing resin 12. For this reason, it is possible to suppress delamination and cracking of the sealing resin 12 at the interface between the conductor frame 8 and the sealing resin 12 in connection with the thermal cycle.The end of the ladder frame 8 is defined here as the outer circumferential part of the ladder frame 8, the corner part of the bent part of the ladder frame 8, and the perimeter of an opening or slot formed in the ladder frame 8. Furthermore, to reduce stress, the resin 13 covers not only the upper surface but also the lateral surface of the end of the ladder frame 8. As a result, the effect of suppressing crack formation in the resin is further improved.

[0023] The materials for resin 13 for stress reduction are silicone resins, urethane resins, polyimide resins, polyamide resins, polyamide-imide resins, acrylic resins, and the like. However, any materials are permissible, not limited to those listed here, as long as they possess both insulating and adhesive properties.

[0024] The coating process for the stress-reducing resin 13 generally involves application using a dispenser. Various elements, such as the semiconductor chip 6 or the insulating substrate 2, are bonded to the base plate 1. After the base plate 1 and the housing 11 have been bonded together and before being filled with the sealing resin 12, the stress-reducing resin 13 is applied. Alternatively, the stress-reducing resin 13 can be applied before the base plate 1, the housing 11, and the conductor frame 8 are bonded together. If the curing conditions for the stress-reducing resin 13 and the curing conditions for the adhesive used for bonding between the housing 11 and the base plate 1 can be used in combination, the stress-reducing resin 13 can also be cured simultaneously with the bonding process.Alternatively, if necessary, the resin 13 for stress reduction can be applied to a specific location on the conductor frame 8 using a mask. If a mask is used, application via a dispenser, spray coating using a spraying process, or direct immersion in the resin 13 solution for stress reduction are all permissible.

[0025] The stress-reducing resin 13 is partially applied to the end of the conductor frame 8, leaving an exposed portion on the upper surface of the conductor frame 8. This exposed portion is surrounded by the stress-reducing resin 13, forming a dam structure. Specifically, within this dam structure, the exposed portion of the upper surface of the conductor frame 8 is surrounded either by the stress-reducing resin 13 applied along all four sides, by the stress-reducing resin 13 applied along three sides and the bent portion of the conductor frame 8 applied along one side, or by the stress-reducing resin 13 applied along three sides and the inner wall of the housing 11 applied along one side.

[0026] Fig.Figure 4 is a perspective view to illustrate the dam structure according to embodiment 1 for the purpose of explaining the further technical background of the present invention. The dam structure formed from the resin 13 for stress reduction impounds the sealing resin 12 flowing over the upper surface of the conductor frame 8. Incidentally, if the entire surface of the conductor frame 8 is covered with the resin 13 for stress reduction, such a dam structure is not formed. Consequently, the sealing resin 12 flowing on the upper surface of the conductor frame 8 cannot be impounded.

[0027] Subsequently, by means of a comparison with a comparative example, the manner of injecting the sealing resin into the semiconductor device according to the present embodiment is described for further technical background. Fig.Figure 5 is a cross-sectional view to illustrate the inflow path of a sealing resin in a semiconductor device according to a comparative example. Fig. Figure 6 is a cross-sectional view showing the inflow path of the sealing resin in the semiconductor device according to embodiment 1, to illustrate the further technical background of the present invention. In the comparative example, the resin 13 for stress reduction is not provided.

[0028] Examples of methods for filling with the sealing resin 12 include a method in which the sealing resin 12 is injected from a prescribed point to fill the interior of the housing 11 with the sealing resin 12. In the vicinity of the semiconductor chip 6, from the inlet R1 on the lower side of the conductor frame 8, there is a narrow gap area with a height of approximately 1 to 3 mm. The insulating substrate 2 is generally a ceramic with a low coefficient of linear expansion. In the case of a highly elastic type of sealing resin 12, a typical example of which is an epoxy resin, a filler is added in large quantities to achieve a low coefficient of linear expansion and to suppress detachment of the insulating substrate 2 from the sealing resin 12 in connection with a thermal cycle.Accordingly, the elastic modulus and viscosity of the sealing resin 12 are increased, and therefore the sealing resin 12 has low flowability, and it may be difficult to fill the sealing resin 12 into the narrow gap area.

[0029] If the viscosity of the sealing resin 12 is low, the filled resin flows into the narrow gap and successively seals the upper surface of the insulating substrate 2, the semiconductor chip 6, and the connecting material 9. For this reason, even in the comparative example, a very reliable seal is achieved that leaves no voids in the sealing resin 12. On the other hand, if the viscosity of the sealing resin 12 is high, it takes time to pass through the inlet R1 of the narrow gap, causing the resin to accumulate at the inlet R1. The accumulated resin then begins to spread from the inlet path R2 onto the upper surface of the conductor frame 8.For this reason, in the comparative example, before the sealing resin 12 passes through the narrow gap region, the sealing resin 12 flowing onto the upper surface of the conductor frame 8 flows around it to flow into the narrow gap region from the inlet R3 opposite the inlet R1. The sealing resin 12 flowing from the opposite sides prevents air from escaping on the lower side of the conductor frame 8, thus trapping voids in the sealing resin 12. Void inclusions at the time of resin injection tend to occur particularly in the narrow gap region between the semiconductor chips 6 or between the interconnect materials on the upper part of the semiconductor chips 6, and tend to occur particularly in the structure where the conductor frame 8 covers 50% or more of the surface of the upper surface of the semiconductor chip 6.

[0030] In the present embodiment, as in the comparative example, the sealing resin 12 extends from the inlet path R2 onto the upper surface of the conductor frame 8. However, the sealing resin 12 is held back by the dam structure of the resin 13 for stress reduction and remains on the upper surface of the conductor frame 8 until its height reaches the height of the resin 13 for stress reduction. For this reason, the flow of the sealing resin 12 from inlet R3 to the lower upper surface of the conductor frame 8 can be prevented, allowing the sealing resin 12 to flow into the narrow gap on the lower surface of the conductor frame 8 from a single direction. This can suppress the formation of void inclusions in the sealing resin 12.For this reason, it is possible to obtain a semiconductor device with high reliability in terms of its electrical insulation properties.

[0031] A semiconductor device was then fabricated for evaluation testing, and a thermal cycle test was performed. The results of this test are described. The conductor frame 8 was formed from a copper plate bonded to the semiconductor chip 6 via a solder jointing material, and the housing 11 was attached to it using an adhesive. Resins 13 with prescribed moduli of elasticity were then applied for stress reduction. A seal was then applied using the liquid sealing resin 12, which contained an epoxy resin in which the modulus of elasticity was adjusted by increasing or decreasing the filler content. The sealed product was then heated to 160°C for two hours. Semiconductor devices for evaluation were then fabricated. The entire semiconductor device was placed in a thermostat suitable for temperature control.The thermostat temperature was repeatedly changed between -40°C and 160°C to perform a thermal cycling test. In this test, the evaluation sample was held at -40°C for 30 minutes, followed by 30 minutes at 160°C. This procedure, considered one cycle, was repeated 1000 times. Following the thermal cycling test, the defects were assessed through non-destructive observation of delamination using an ultrasonic reflectoscope and observation of resin cracking via cross-sectional analysis.

[0032] A large number of evaluation samples corresponding to embodiment 1 (further technical background) and a reference sample with a conductor frame 8 not coated with the resin 13 for stress reduction were prepared. Table 1 shows the results of the thermal cycling test of the samples according to embodiment 1 (further technical background) and the reference sample. Polyimide resins with four types of elastic moduli were applied as the stress-reducing resins 13 using a dispenser to achieve a film thickness of 20 µm or more. Three types of epoxy resins with elastic moduli of 10 GPa, 12 GPa, and 15 GPa were used as the sealing resins 12. Each evaluation was performed for two semiconductor devices.After 1000 cycles of the thermal cycle test, the entry indicating that both devices passed is represented as "o"; the entry indicating that one device passed is represented as "Δ"; and the entry indicating that neither device passed is represented as "x". [Table 1] No 2 GPa 5 GPa 8 GPa 10 GPa 10 GPa Replacement ◯ ◯ ◯ ◯ ◯ Cracking ◯ ◯ ◯ ◯ ◯ 12 GPa Replacement × ◯ ◯ ◯ Δ Cracking Δ ◯ ◯ ◯ ◯ 15 GPa Replacement × ◯ ◯ ◯ × Cracking × ◯ ◯ ◯ Δ

[0033] For the reference sample, in which the conductor frame 8 was not coated with the resin 13 for stress reduction, neither delamination nor cracking was observed when the elastic modulus of the sealing resin was 12 10 GPa. However, when the elastic modulus of the sealing resin was 12 12 GPa or higher, delamination and cracking occurred.

[0034] For the semiconductor device coated with resin 13 for stress reduction with a modulus of elasticity of 2 GPa to 8 GPa, it was found that no delamination or cracking occurred even after 1000 cycles of the thermal cycle test. However, for the semiconductor device coated with resin 13 for stress reduction with 10 GPa, the following was observed: when the modulus of elasticity of the sealing resin 12 was 10 GPa, no delamination or cracking was observed after the thermal cycle test; however, when the modulus of elasticity of the sealing resin 12 was 12 GPa, delamination occurred; and when the modulus of elasticity of the sealing resin was 15 GPa, delamination and cracking occurred.

[0035] The experiment demonstrated that coating the conductor frame 8 with the stress-reducing resin 13 suppresses delamination and cracking of the sealing resin 12 due to thermal cycling in a high-temperature environment. Furthermore, it was proven that if the elastic modulus of the stress-reducing resin 13 is 8 GPa or less, a semiconductor device with higher reliability can be produced.

[0036] Furthermore, the upper surface of the stress-reducing resin 13 is 5 µm to 5 mm higher than the upper surface of the conductor frame 8. The stress-reducing resin 13 is 5 µm or more thick. This can suppress the formation of void inclusions in the sealing resin 12. Moreover, the stress-reducing resin 13 preferably has a thickness of 5 µm or more to ensure that the uncoated portion of the end of the conductor frame 8 is not exposed to the stress-reducing resin 13. However, the stress-reducing resin 13 is preferably thinner than the height of the sealing resin 12 on the conductor frame 8. If the stress-reducing resin 13 is thicker than 5 mm, wet spreading often occurs on the conductor frame 8, causing the stress-reducing resin 13 itself to crack due to thermal cycling. For this reason, 5 mm or less is preferable.

[0037] In the present embodiment, for further technical background, increases in current density and wire separation associated with the thermal cycling environment were suppressed, thereby improving the reliability of the semiconductor device. For this purpose, the conductor frame 8 is used. However, a wire 10 can be partially used in such a region to avoid impairing the reliability characteristics of the semiconductor device. If the flowability of the sealing resin 12 is low, there is concern that voids may be mixed into or introduced into the lower part of the conductor frame 8. By partially using the wire 10, however, the remaining voids are more likely to escape. Design 2 (for further technical background)

[0038] Fig.Figure 7 is a cross-sectional view illustrating the end of a ladder frame according to embodiment 2 for the purpose of explaining the further technical background of the present invention. The present embodiment for the purpose of explaining the further technical background differs from embodiment 1 for the purpose of explaining the further technical background in the structure of the end of the ladder frame 8, but is otherwise identical to embodiment 1 for the purpose of explaining the further technical background. A thin structure is formed on the upper surface, in which a step 14, resulting in a reduced thickness of the ladder frame 8, is provided on the upper surface of the end of the ladder frame 8. The stress-reducing resin 13 is applied to the upper part of the step 14.

[0039] The effects of the present embodiment are described below with further technical background by means of a comparison with a comparative example. Fig.Figure 8 is a cross-sectional view illustrating the end of the conductor frame according to the comparative example. In the comparative example, step 14 is not present. Stress resulting from a thermal cycle is induced, in particular, at the corner sections C1 and C2 of the end of the conductor frame 8. Therefore, to reduce the stress at the end of the conductor frame 8, the corner sections C1 and C2 are preferably coated with the stress-reducing resin 13.

[0040] In the present embodiment, the stress generated at corner section C2 of the comparative example is distributed to corner sections C3 and C4 for further technical background. Therefore, the present embodiment produces a greater stress reduction effect than that of the comparative example. Furthermore, the resin 13 is applied to stage 14 for stress reduction when it is applied to the end of the conductor frame 8. This can suppress wet spreading.

[0041] If, after bonding the housing 11 and the base plate 1, the resin 13 is applied from the upper surface of the device for stress reduction, covering corner section C1 is easy in the comparative example, but covering corner section C2 is difficult. In contrast, in the present embodiment, for further technical background, the distance between corner section C3 and corner section C4 is short. For this reason, both applications can be carried out simultaneously when the application is performed on the step 14. Moreover, the thickness and length of the step 14, namely the distance between C3 and C4 and the distance between C3 and C5, are not limited and can be adjusted to the distance suitable for stress reduction depending on the viscosity of the resin 13.

[0042] Fig.Figure 9 is a cross-sectional view illustrating a modified example 1 of the end of the conductor frame according to embodiment 2, to explain the further technical background of the present invention. A thin structure with upper / lower surfaces is formed, in which steps 14 and 15, which result in a reduced thickness of the conductor frame 8, are arranged on the upper and lower surfaces, respectively, of the end of the conductor frame 8. The stress-reducing resin 13 is applied to the upper part of step 14 and the lower part of step 15. As a result, steps 14 and 15 of the end of the conductor frame 8 can be covered with the stress-reducing resin 13.

[0043] However, it is difficult to apply the stress-reducing resin 13 to the corner piece C2 after the housing 11 and the base plate 1 have been bonded together. If the stress-reducing resin 13 is applied before the housing 11 is bonded, the distances between C1 and C2 and C3 and C4 can be adjusted according to the viscosity of the stress-reducing resin 13, thus ensuring that the resin is applied to the corner pieces. For this reason, it is possible to obtain a semiconductor device with high reliability. Furthermore, it is understood that the effects are not affected even if the stress-reducing resin 13 is applied not only to stages 14 and 15, but also to other areas. Inventive embodiment

[0044] Fig.Figure 10 is a perspective view illustrating a modified and inventive example 2 of the end of the conductor frame based on embodiment 2. Depending on the type of stress-reducing resin 13, it is difficult to ensure the film thickness of the stress-reducing resin 13 to be applied to the upper part of the step 14. Consequently, the stress-reducing resin 13 is applied to the upper surface of the conductor frame 8 in a plurality of lines parallel to one another. This results in a longer path for the sealing resin 12, which flows to the upper surface of the conductor frame 8 from a direction at right angles to it. For this reason, circulation of the sealing resin 12 can be suppressed, thus preventing the formation of air inclusions in the sealing resin 12.

[0045] In the drawing, the number of linear resins 13 for stress reduction is 4. However, it is understood that this number can be increased or decreased depending on the viscosity of the sealing resin 12 and the thickness of the resin 13 for stress reduction. The shape of the resin 13 for stress reduction is not limited to a linear shape and can be curved. Furthermore, the configuration in which the resin 13 for stress reduction is applied in a plurality of lines is not limited to embodiment 2 and is also applicable to other embodiments. Design 3 (for further technical background)

[0046] Fig.Figure 11 is a cross-sectional view illustrating a semiconductor device according to embodiment 3 for further technical background of the present invention. A temperature sensor or a wire, such as a gate, is arranged on the upper surface of the semiconductor chip 6. For this purpose, an emitter electrode is divided into spaced-apart upper electrodes 16 and 17. Using bonding materials 9, such as solder, the conductor frame 8 is bonded to the upper electrodes 16 and 17. A tunnel R4, not connected to the conductor frame 8, is located between the bonding materials 9 of the upper electrodes 16 and 17.

[0047] Fig.Figure 12 is a top view illustrating the semiconductor device according to embodiment 3 to explain the further technical background of the present invention. The sealing resin 12 is less likely to flow into the tunnel R4. For this reason, voids tend to accumulate in the sealing resin 12. Therefore, in a top view perpendicular to the upper surface of the semiconductor chip 6, the conductor frame 8 has a recess 18 between the upper electrode 16 and the upper electrode 17. The voltage-reducing resin 13 is also arranged around the recess 18.

[0048] The recess 18 eliminates a portion of the conductor frame 8 that serves as a cover on the tunnel R4. As a result, the sealing resin 12 is more likely to flow into the tunnel R4, thus suppressing voids. Consequently, by combining the control of the flowability of the sealing resin 12 by each resin 13 for stress reduction in embodiments 1 and 2, it is possible to further suppress the voids.

[0049] Furthermore, the semiconductor chip 6 is not limited to those made of silicon and can be one made of a wide-bandgap semiconductor with a bandgap larger than that of silicon. Examples of wide-bandgap semiconductors include silicon carbide, gallium nitride materials, and diamond. The present embodiment, for further technical background, suppresses resin cracking caused by differences in the coefficients of linear expansion between elements when the semiconductor device is used in a temperature range of up to 150°C or higher, and is therefore particularly effective when the wide-bandgap semiconductor chip 6 is used.

[0050] A semiconductor chip 6 formed from such a wide-bandgap semiconductor exhibits high voltage withstand capability and a high permissible current density, and can therefore be miniaturized. The use of such a miniaturized semiconductor chip 6 enables the miniaturization and high integration of the semiconductor device in which the semiconductor chip 6 is incorporated. Since the semiconductor chip 6 exhibits high thermal resistance, a heat sink's heat sink fin can also be miniaturized, and a water-cooled component can be air-cooled, leading to further miniaturization of the semiconductor device. Moreover, since the semiconductor chip 6 exhibits low power loss and high efficiency, a highly efficient semiconductor device can be achieved. Fourth embodiment

[0051] In this embodiment, the semiconductor devices according to the first to third embodiments described above are used for an electrical power conversion device. For example, the electrical power conversion device is an inverter device, a converter device, a servo amplifier, or a power supply unit. Although the present invention is not limited to a specific power conversion device, a case is described below in which the present invention is used for a three-phase inverter.

[0052] Fig.Figure 13 is a block diagram illustrating a configuration of an electrical power conversion system for which the electrical power conversion device of the fourth embodiment is used. This electrical power conversion system comprises a power supply 100, an electrical power conversion device 200, and a load 300. The power supply 100 is a DC power supply and provides DC power to the electrical power conversion device 200. The power supply 100 can consist of various components. For example, the power supply 100 can consist of a DC system, a solar cell, or a storage battery, or it can consist of a rectifier or an AC / DC converter connected to an AC system. Alternatively, the power supply 100 can consist of a DC / DC converter that converts DC power supplied by a DC system into a predetermined power output.

[0053] The electrical power conversion device 200 is a three-phase inverter connected at a node between the power supply 100 and the load 300. It converts DC power supplied by the power supply 100 into AC power and supplies the AC power to the load 300. The electrical power conversion device 200 includes a main conversion circuit 201, which converts DC power into AC power and supplies the AC power, and a control circuit 203, which outputs a control signal to the main conversion circuit 201 to control it.

[0054] The Last 300 is a three-phase electric motor driven by AC power supplied by the electrical power conversion device 200. The Last 300 is not limited to a specific application. It can be used as an electric motor mounted on various electrical devices, such as a hybrid vehicle, an electric vehicle, a rail vehicle, a lift, or an air conditioning system.

[0055] The electrical power conversion device 200 is described in detail below. The main conversion circuit 201 includes a switching device and a reflux diode (not illustrated). When the switching device is switched, the main conversion circuit 201 converts DC power supplied by the power supply 100 into AC power and supplies the AC power to the load 300. The main conversion circuit 201 can have various types of specific circuit configurations. The main conversion circuit 201 according to this embodiment is a three-phase, two-level full-bridge circuit, which can consist of six switching devices and six reflux diodes connected antiparallel to the respective switching devices.Each switching device and each reflux diode of the main conversion circuit 201 consists of a semiconductor device 202 according to any one of the first to third embodiments described above. Two switching devices of the six switching devices are connected in series to form a vertical arm. Each vertical arm forms one phase (U-phase, V-phase, W-phase) of the full bridge circuit. The output terminals of each vertical arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0056] Furthermore, the main conversion circuit 201 includes a (not illustrated) control circuit that controls each switching device. The control circuit may be integrated into the semiconductor device 202. Alternatively, a different control circuit, distinct from the semiconductor device 202, may be provided. The control circuit generates a control signal to actuate each switching device of the main conversion circuit 201 and provides the generated control signal to a control electrode of each switching device of the main conversion circuit 201. Specifically, the control circuit outputs a control signal to the control electrode of each switching device to turn each switching device on and a control signal to turn each switching device off, according to the control signal output by the control circuit 203, which is described later.When the ON state of each switching device is maintained, the control signal is a voltage signal (ON signal) with a voltage equal to or higher than the threshold voltage of the switching device. When the OFF state of each switching device is maintained, the control signal is a voltage signal (OFF signal) with a voltage equal to or lower than the threshold voltage of the switching device.

[0057] The control circuit 203 controls each switching device of the main conversion circuit 201 to supply the desired power to the load 300. Specifically, the control circuit 203 calculates a period (ON period) during which each switching device of the main conversion circuit 201 is in the ON state, based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by means of a PWM controller to modulate the ON period of each switching device depending on the voltage to be supplied. Furthermore, the control circuit 203 sends a control command (control signal) to the drive circuit contained in the main conversion circuit 201, so that at any given time the ON signal is sent to each switching device to be switched on and an OFF signal is sent to each switching device to be switched off.The control circuit outputs the ON signal or OFF signal as the control signal to the control electrode of each switching device, according to the control signal.

[0058] In this embodiment, the semiconductor devices according to the first to third embodiments are used as the semiconductor device 202. Accordingly, a semiconductor device and a power conversion device with high insulation reliability can be obtained by suppressing delamination and cracking of the sealing resin and reducing voids remaining in the sealing resin.

[0059] While this embodiment illustrates an example in which the present invention is used for a two-level three-phase inverter, the present invention is not limited to this and can be used for various power conversion devices. While this embodiment illustrates a two-level electrical power conversion device, the present invention can also be used for an electrical power conversion device with three or more levels. When power is supplied to a single-phase load, the present invention can be used for a single-phase inverter. The present invention can also be used for a DC / DC converter or an AC / DC converter when power is supplied to a DC load or the like.

[0060] Furthermore, in the electrical power conversion device for which the present invention is used, the load mentioned above is not limited to an electric motor. For example, the load can also be used as a power supply device for an electrical discharge machine, a laser beam machine, a cooking appliance with induction heating, or a system for the contactless supply of device power. Alternatively, the electrical power conversion device can also be used as a power conditioner for a photovoltaic energy generation system, an electricity storage system, or the like. Reference symbol list

[0061] 2 Insulation substrate; 6 Semiconductor chip; 8 Conductor frame; 11 Housing; 12 Sealing resin; 13 Voltage reduction resin; 14, 15 Stage; 16, 17 Top electrode; 18 Recess; 200 Electrical power conversion device; 201 Main conversion circuit; 202 Semiconductor device; 203 Control circuit

Claims

[1] Semiconductor device, exhibiting: - an insulating substrate (2); - a semiconductor chip (6) arranged on the insulating substrate (2); - a conductor frame (8) bonded to an upper surface of the semiconductor chip (6); - a sealing resin (12) that covers the semiconductor chip (6), the insulating substrate (2) and the conductor frame (8); and - a resin (13) for stress reduction, which is partially applied to one end of the conductor frame (8) and has a lower modulus of elasticity than that of the sealing resin (12), wherein the resin (13) is applied in a plurality of lines parallel to each other on the upper surface of the conductor frame (8) to reduce stress. [2] Semiconductor device according to claim 1, wherein: - an upper surface of the conductor frame (8) has an exposed part which is not covered with the resin (13) for stress reduction and - the exposed part is surrounded by the resin (13) to reduce stress and form a dam structure. [3] Semiconductor device according to claim 2, - further comprising a housing (11) that surrounds the semiconductor chip (6), the insulating substrate (2) and the conductor frame (8); - wherein in the dam structure the exposed part is surrounded only by the resin (13) for stress reduction, by the resin (13) for stress reduction and a bending part of the conductor frame (8), or by the resin (13) for stress reduction and an inner wall of the housing (11). [4] Semiconductor device according to any one of claims 1 to 3, wherein: - a step (14) which results in a reduced thickness of the ladder frame (8) is formed on an upper surface of the end of the ladder frame (8) and - the resin (13) is applied to an upper part of the step (14) to reduce stress. [5] Semiconductor device according to any one of claims 1 to 3, wherein: - Steps (14, 15) which result in a smaller thickness of the ladder frame (8) are arranged on an upper surface and a lower surface of the end of the ladder frame (8) and - the resin (13) is applied to an upper part and a lower part of the steps (14, 15) to reduce stress. [6] Semiconductor device according to any one of the preceding claims, wherein: - the semiconductor chip (6) has first and second upper electrodes (16, 17) formed on the upper surface of the semiconductor chip (6), spaced apart from each other and bonded to the conductor frame (8), and - the conductor frame (8) has a recess (18) between the first upper electrode (16) and the second upper electrode (17) in a top view perpendicular to the upper surface of the semiconductor chip (6). [7] Semiconductor device according to one of the preceding claims, wherein the resin (13) covers not only a top surface but also a side surface of the end of the conductor frame (8) for the purpose of reducing voltage. [8] Semiconductor device according to one of the preceding claims, wherein an upper surface of the resin (13) is 5 µm to 5 mm higher than an upper surface of the conductor frame (8) for the purpose of reducing voltage. [9] Semiconductor device according to one of the preceding claims, wherein the elastic modulus of the resin (13) for stress reduction is 2 GPa to 8 GPa. [10] Semiconductor device according to one of the preceding claims, wherein the semiconductor chip (6) consists of a wide bandgap semiconductor. [11] Electrical power conversion device (200), comprising: - a main conversion circuit (201) comprising the semiconductor device (202) according to any of the preceding claims and configured to convert input power and output converted power; and - a control circuit (203) which is configured to send a control signal to the main conversion circuit (201) for controlling the main conversion circuit (201).

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