CONTROL CIRCUIT, SEMICONDUCTOR STORAGE DEVICE, INFORMATION PROCESSING DEVICE AND CONTROL METHOD

Abstract

Control circuit (100) which outputs a first signal to discharge charges accumulated in a source line (SL) and a bit line (BL) according to the activation of a word line (WL) and outputs a second signal to put the source line and the bit line into a potential-free state until the start of writing or reading, with respect to a memory cell which has the source line (SL), the bit line (BL), a transistor (Tr5) which is provided between the source line (SL) and the bit line (BL) and is switched on and off by a potential of the word line (WL), and a storage element (R1) connected in series with the transistor (TR5), wherein the control circuit (100) has a first transistor (Tr3) connected to the source line (SL) and a second transistor (Tr4) connected to the bit line (BL), and the first transistor (Tr3) includes a first gate terminal and the second transistor (Tr4) includes a second gate terminal, wherein the first gate terminal is connected to a first NAND gate (69) and the second gate terminal is connected to a second NAND gate (70), and wherein both the source line (SL) and the bit line (BL) are short-circuited to a ground potential at a first time point in response to the first signal and transition from their respective first potential-free states to their respective non-potential-free states, and transition at a second time point in response to the second signal to their respective second potential-free states.

Description

TECHNICAL AREA

[0001] The present disclosure relates to a control circuit, a semiconductor storage device, an information processing device and a control method. BACKGROUND

[0002] As a measure for reducing power consumption in a spin-torque transfer magnetoresistive random access memory (STT-MRAM), a method is disclosed for keeping a source line and a bit line in a potential-free or floated state at the time of standby. Furthermore, a method is disclosed for preventing the destruction of a magnetic tunnel junction (MTJ) element by inserting a transistor between a source line and a bit line to short-circuit the source line and the bit line (see, for example, patent document 1). CITATION LIST PATENT STATEMENT

[0003] Patent Document 1: Japanese Patent Application Publication No. JP 2014 - 191 835 A

[0004] Document US 2016 / 0 064 059 A1 relates to a semiconductor storage device comprising a write line driver, a read amplifier, a reference circuit, an analog voltage generator, a write terminal voltage generator, a write driver and a controller.

[0005] Document US 2017 / 0 263 297 A1 relates to a semiconductor memory device comprising a first bit line, a first source line, a first word line, a first control line, a first memory cell with a first variable resistor, and a first transistor. The first transistor has a gate coupled to the first word line, and the first memory cell has one end coupled to the first bit line and another end coupled to the first source line. The semiconductor memory device comprises a second transistor with one end coupled to the first bit line, and a third transistor with a gate coupled to the first control line, one end coupled to the first bit line, and another end coupled to the first source line. SUMMARY OF THE INVENTION PROBLEMS THAT ARE TO BE SOLVED BY THE INVENTION

[0006] The method disclosed in patent document 1 requires the insertion of transistors between all the source lines and the bit lines, thus complicating the control and increasing the wiring resources.

[0007] Therefore, the present disclosure proposes a novel and improved control circuit, a semiconductor storage device, an information processing device and a control method that can not only suppress an increase in power consumption with a simple configuration, but also prevent incorrect writing and destruction of a storage element. PROBLEM SOLVING

[0008] The invention is defined by the attached claims.

[0009] According to the present disclosure, a control circuit is provided which outputs a first signal to discharge charges accumulated in a source line and a bit line upon activation of a word line, and outputs a second signal to bring the source line and the bit line into a potential-free state before the start of the write or read operation. This circuit comprises a memory cell that includes the source line, the bit line, a transistor located between the source line and the bit line and switched on and off by a potential of the word line, and a storage element connected in series with the transistor. The control circuit includes a first transistor connected to the source line and a second transistor connected to the bit line. The first transistor includes a first gate terminal, and the second transistor includes a second gate terminal.The first gate terminal is connected to a first NAND gate, and the second gate terminal is connected to a second NAND gate. Both the source line and the bit line are short-circuited to ground potential in response to the first signal at a first time point, transitioning from their respective first potential-free states to their respective non-potential-free states, and then transitioning to their respective second potential-free states in response to the second signal at a second time point.

[0010] Furthermore, according to the present disclosure, a semiconductor storage device is provided, comprising: a memory cell with a storage element provided or arranged between a source line and a bit line, and a transistor provided in series with the storage element and switched on and off by a potential of a word line; and a control circuit that outputs a first signal to discharge charges accumulated in the source line and the bit line according to the activation of the word line, and outputs a second signal to bring the source line and the bit line into a potential-free state before writing or reading begins. The control circuit has a first transistor connected to the source line and a second transistor connected to the bit line.The first transistor has a first gate terminal, and the second transistor has a second gate terminal. The first gate terminal is connected to a first NAND gate, and the second gate terminal is connected to a second NAND gate. Both the source line and the bit line are short-circuited to ground potential at a first time point in response to the first signal, transitioning from their respective first potential-free states to their respective potential-independent states. At a second time point, they transition to their respective second potential-free states in response to the second signal.

[0011] Furthermore, according to the present disclosure, an information processing device is provided which includes at least one semiconductor storage device.

[0012] Furthermore, according to the present disclosure, a control procedure by a processor is provided which includes: outputting a first signal to discharge charges accumulated in a source line and a bit line, according to the activation of a word line;and outputting a second signal to place the source line and the bit line into a potential-free state before the start of writing or reading, with respect to a memory cell comprising the source line, the bit line, a transistor provided between the source line and the bit line and switched on and off by a potential of the word line, and a memory element connected in series with the transistor, wherein both the source line and the bit line are short-circuited to a ground potential at a first time point in response to the first signal and transition from respective first potential-free states to respective non-potential-free states, and transition at a second time point in response to the second signal to respective second potential-free states. EFFECTS OF THE INVENTION

[0013] As described above, according to the present disclosure, a novel and improved control circuit, a semiconductor storage device, an information processing device and a control method can be provided which, with a simple configuration, can not only suppress an increase in power consumption but also prevent faulty writing and destruction of a storage element.

[0014] It should be noted that the effect described above is not necessarily limiting, and any of the effects shown in this specification, or other effects that can be understood from this specification, may occur together with or instead of the effect described above. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is an explanatory diagram showing an example of a functional configuration of a semiconductor storage device according to an embodiment of the present disclosure. Fig. Figure 2 is an explanatory diagram showing an example of a circuit configuration of the memory cell arrangement 10 and a peripheral of the memory cell arrangement 10. Fig. Figure 3 is an explanatory diagram showing a circuit that serves as a comparative example of the one in Fig. The circuit shown is shown in section 2. Fig. Figure 4 is an explanatory diagram showing a circuit that serves as a comparative example of the one in Fig. The circuit shown is shown in section 2. Fig. 5 is an explanatory diagram showing how the [function] works. Fig. The circuit shown in section 3 is represented by a timing diagram. Fig. 6 is an explanatory diagram showing how the function of the Fig. The circuit shown in section 4 is represented by a timing diagram. Fig. 7 is an explanatory diagram showing how the function of the Fig. The circuit shown in section 2 is represented by a timing diagram. Fig. 8 is an explanatory table that shows the state transition of each line and a transistor in the circuit of the in Fig. 3 is the comparative example shown. Fig. Figure 9 is an explanatory table that shows the transition of the state of lines and a transistor of the circuit in the Fig. The comparison example shown in section 4 illustrates this. Fig. Table 10 is an explanatory table that illustrates the state transition of lines and a transistor in Fig. The circuit shown in section 2 is represented. Fig. Figure 11 is a flowchart that illustrates a functional example of the semiconductor storage device 1 according to the same embodiment. Fig. Figure 12 is an explanatory diagram showing an example of a configuration of the semiconductor storage device 1 according to the same embodiment. Fig. Figure 13 is an explanatory diagram showing an example of a functional configuration of an electronic device 1000 on which the semiconductor storage device 1 can be mounted according to the same embodiment. MODE FOR IMPLEMENTING THE INVENTION

[0015] Preferred embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. It should be noted that in this specification and the drawings, components having essentially the same functional configuration are given the same reference designations, and redundant explanations are omitted.

[0016] Please note that the description follows this order. 1. Implementation of the present disclosure 1.1. Overview 1.2. Configuration example 2. Application example 3. Conclusion <1. Implementation of the present disclosure>[1.1. Overview]

[0017] Before the embodiments of the present disclosure are described in detail, an overview of the embodiments of the present disclosure is given.

[0018] As described above, a measure to reduce power consumption in a spin-torque transfer magnetoresistive random-access memory (STT-MRAM) involves keeping a source line and a bit line in a potential-free state during standby operation. Keeping the source and bit lines in a potential-free state reduces current consumption due to transistor leakage currents flowing from VDD to VSS through these lines. Short-circuiting the source and bit lines to VSS during standby operation results in a noticeable through-current, especially at high temperatures, which can increase to the same extent as the write pulse, even though it is a standby current.To most easily reduce leakage current, one can initially increase the resistance of a leakage path by switching off a column switch on the VSS side. However, if a transition to the active state occurs in this state, a large potential difference is created across the magnetic tunnel junction (MTJ), depending on the timing of the charge accumulation in the source and bit lines by the leakage current. This can lead to phenomena such as data loss recorded in the MTJ and MTJ destruction. These phenomena can occur because the charges accumulated in the source and bit lines are not necessarily equal, resulting in a potential difference between them.

[0019] Therefore, a method for preventing the destruction of a magnetic tunnel junction (MTJ) element by inserting a transistor between a source line and a bit line is disclosed to short-circuit the source line and the bit line. Short-circuiting the source line and the bit line eliminates the potential difference between the source line and the bit line described above. By eliminating this potential difference, phenomena such as data loss in the MTJ element and destruction of the MTJ element do not occur.

[0020] However, if transistors are inserted into all pairs of source and bit lines, not only the transistors themselves but also lines for controlling them are required. Since the wiring is crowded around the cell array, it is undesirable to create more wiring than necessary.

[0021] Therefore, the person making this disclosure carefully investigated a technology capable of not only suppressing an increase in the power consumption of a simple-configuration semiconductor memory device, but also preventing erroneous writes and the destruction of a memory element. As a result, the person making this disclosure designed, as described below, a technology capable of not only suppressing the increase in the power consumption of a simple-configuration semiconductor memory device, but also preventing erroneous writes and the destruction of a memory element. [1.2. Configuration example]

[0022] One embodiment of the present disclosure is described in detail below. Fig. Figure 1 is an explanatory diagram showing an example of a functional configuration of a semiconductor storage device according to an embodiment of the present disclosure. An example of a functional configuration of the semiconductor storage device according to the embodiment of the present disclosure is described below with reference to Fig. 1 described.

[0023] As in Fig. Figure 1 shows a semiconductor storage device 1 according to the embodiment of the present disclosure comprising a memory cell arrangement 10, a reference cell arrangement 20, column control switches 31 and 32 on a VDD side, column control switches 33 and 34 on a VSS side, a column decoder, COL dec 41, a word line decoder, WL dec 42, a word line driver, WL driver 43, a read amplifier, SA 50, a control circuit 100, a program counter 110, a temperature sensor 120, a timer 130 and a clock counter 140.

[0024] The memory cell arrangement 10 comprises memory cells with memory elements arranged in a matrix. In the present embodiment, the memory element used is one that utilizes the fact that its resistance state changes reversibly according to the polarity of the potential difference applied across both ends to store information. An MTJ element as described above can be used as such an element. The memory element has two distinguishable resistance states (a low-resistance state and a high-resistance state). Furthermore, the memory cell arrangement 10 also includes a plurality of word lines extending in a row direction (horizontal direction), and a plurality of bit lines and a plurality of source lines extending in a column direction (vertical direction).One end of each word line is connected to the word line driver 43, and each bit line is connected to the column control switch 31 on the VDD side and the column control switch 33 on the VSS side.

[0025] The reference cell arrangement 20 has a plurality of reference cells arranged in a matrix. Furthermore, the reference cell arrangement 20, similar to the memory cell arrangement 10, has a plurality of word lines extending in a row direction (horizontal direction), and a plurality of bit lines and a plurality of source lines extending in a column direction (vertical direction). One end of each word line is connected to the word line driver 43, and each bit line is connected to the column control switch 32 on the VDD side and the column control switch 34 on the VSS side.

[0026] In the present embodiment, the reference cells provided in the reference cell arrangement 20 comprise a high-resistance reference cell and a low-resistance reference cell. The combined resistance value of the reference cells is achieved by combining the high-resistance and low-resistance reference cells to form a target value between high and low resistance.

[0027] Column control switches 31 to 34 connect a bit line and a source line, corresponding to a memory cell to be addressed among the multitude of bit lines and source lines of the memory cell arrangement 10, to a bit line driver unit and a source line driver unit (not shown) based on control signals. The control signals supplied to column control switches 31 to 34 include a read enable signal RDen and a write enable signal WRen. Furthermore, a data signal and a signal from the column decoder 41 (a decoded column address signal) are sent to column control switches 31 to 34.

[0028] The column decoder 41 decodes the address signal and sends the decoded signal to the column control switches 31 to 34. The word line decoder 42 decodes the address signal and sends the decoded signal to the word line driver 43. The word line driver 43 selects a memory cell to be addressed in the memory cell array 10 based on a control signal. Specifically, the word line driver 43 applies a signal to the word line of the memory cell array 10 to select the row to which the memory cell belongs that is to be subjected to the data write or read operation. In addition to the signal from the word line decoder 42, an ACTen signal is sent to the word line driver 43 to activate the word line.

[0029] When reading data from the memory cell of the memory cell arrangement 10, the read amplifier 50 compares the potential output via the bit line with the reference potential generated by the reference cell of the reference cell arrangement 20 and outputs data indicating whether the potential is higher (H) or lower (L) than the reference potential.

[0030] As described later, the control circuit 100 is a circuit that outputs a signal to release charges that have accumulated in the source line and the bit line before a high-level potential is applied to a word line WL (before activation of the word line).

[0031] Fig. Figure 2 is an explanatory diagram showing an example of a circuit configuration for the memory cell arrangement 10 and a peripheral of the memory cell arrangement 10. The in Fig. The peripheral circuits of the memory cell arrangement 10 shown in Figure 2 are circuits for performing write operations on a memory cell. Fig. Figure 2 shows registers 61 and 63, NOT gates 62 and 64, NAND gates 65 to 70, and transistors Tr1 to Tr5. In the memory cell arrangement 10, when one of transistors Tr1 and Tr2 is switched on, and when one of transistors Tr3 and Tr4 is switched on, data can be written to the memory element R1 via NOT gates 62 and 64; that is, the resistance state of the memory element R1 can be changed.

[0032] Here, the output of NAND gate 67 and a signal DSCHGenb are fed into NAND gate 69. Similarly, the output of NAND gate 68 and the signal DSCHGenb are fed into NAND gate 70. The signal DSCHGenb is output by control circuit 100. By setting the signal DSCHGenb to a low level before a high-level potential is applied to (before activation of) the word line WL, transistors Tr3 and Tr4 are switched on, and the source line SL and the bit line BL are short-circuited to VSS. When the source line SL and the bit line BL are short-circuited to VSS, the charges accumulated in the source line SL and the bit line BL are discharged.

[0033] Here are two circuits from the comparison example shown to illustrate the functionality of the circuit in Fig. to explain the circuit shown in section 2. Fig. 3 and Fig. 4 are explanatory diagrams showing the circuit that serves as the comparison example for the one in Fig. The circuit shown is shown in section 2. Fig. Figure 3 shows a circuit example in which the potentials of the source line and the bit line are fixed to VSS in standby mode, and OR gates 79 and 80, into which ACTf is inverted and fed, are provided instead of the NAND gates 67 to 70. Fig. Figure 4 shows a circuit example for the case where the source line and the bit line are in a potential-free state in standby mode, and AND gates 89 and 90 are provided instead of NAND gates 67 to 70.

[0034] First, consider the [details omitted]. Fig. 3. Circuit shown. This circuit is designed to maintain the potential across both ends of the memory element, i.e., the potentials of the source line and the bit line at VSS during standby without access to the memory, thereby preventing an excessive potential difference across both ends of the memory element and reliably maintaining a value for the memory element.

[0035] Fig. 5 is an explanatory diagram showing how the [function] works. Fig. The circuit shown in section 3 is represented by a timing diagram. As in Fig. 5 shown, holds the in Fig. 3. The circuit shown has different potentials for the source line and the bit line during VSS standby mode compared to the read and write operations.

[0036] However, if the potentials of the source line and the bit line are set to VSS in standby mode, a leakage current (through current) can occur from VDD to VSS. As described above, if the source line and the bit line are short-circuited to VSS in standby mode, this through current becomes particularly noticeable at high temperatures and can increase to the same extent as the pulse during writing, even though it is a standby current. One reason for this is that, in order to increase the headroom at the time of reading, the resistance of the column control switch transistor is reduced by increasing the size of the column control switch. In other words, the relatively low resistance also contributes to the power increase in standby mode, even when the column switch transistor is off.

[0037] The in Fig. The circuit shown in Figure 4 is therefore intended to suppress the short-circuit current by also switching off the transistor on the VSS side and putting it into a potential-free state in standby mode. Fig. 6 is an explanatory diagram showing how the function of the Fig. The circuit shown in section 4 is represented by a timing diagram. As in Fig. 5 shown, are located in the Fig. In the circuit shown in section 4, the source line and the bit line are in a potential-free state in standby mode, unlike during the read and write operations.

[0038] The short-circuit current can be suppressed by switching off the transistor on the VSS side even in standby mode, but on the other hand, charges accumulate in the source line and in the bit line in standby mode, which can destroy data accumulated in the memory element (in other words: erroneously written data) during a process of transitioning to the active state or destroy the memory element itself.

[0039] Also in the steady state, a difference in the resistance division value exists between VDD and VSS at the node to which the memory element is connected, and a potential difference can occur between the source line and the bit line. If the word line is activated in this state, the potential difference between the source line and the bit line can lead to electrostatic destruction of the memory element. Therefore, the generation of the potential difference across both ends of the memory element cannot be suppressed simply by switching off the transistor on the VSS side.

[0040] As described above, the potential difference between the source line and the bit line can be eliminated by inserting a transistor between them to short-circuit them. However, if transistors are inserted into all source-bit line pairs, not only the transistors themselves but also wires for controlling them are required. Since the wiring is crowded around the cell array, it is undesirable to create more wiring than necessary.

[0041] Therefore, the control circuit 100 in the present embodiment, as in Fig. Figure 2 shows the signal DSCHGenb being set to a low level before the high-level potential is applied to the word line WL. The semiconductor storage device 1 according to the embodiment of the present disclosure has a configuration in which, by setting the signal DSCHGenb to a low level before the high-level potential is applied to the word line WL, the source line and the bit line are short-circuited with VSS and the charges accumulated in the source line and the bit line are discharged.

[0042] Fig. 7 is an explanatory diagram showing how the function of the Fig. The circuit shown in 2 is represented by a timing diagram. In the circuit shown in Fig. In the circuit shown in section 2, the source line SL and the bit line BL are in a potential-free state until the DSCHGenb signal becomes low. This potential-free state of the source line SL and the bit line BL reduces leakage current. Furthermore, because the source line SL and the bit line BL are in a potential-free state, no erroneous writes to the data stored in the memory element occur. Then, when the activation of the word line WL is instructed, control circuit 100 changes the DSCHGenb signal to a low level before the potential of the word line WL becomes high. When the DSCHGenb signal becomes low, transistors Tr3 and Tr4 are switched on, and the source line SL and the bit line BL are short-circuited to VSS.When the source line SL and the bit line BL are short-circuited with VSS, the charges accumulated in the source line SL and the bit line BL are dissipated. This discharge of charges equalizes the potential of the source line SL and the potential of the bit line BL, preventing a large potential difference between them.

[0043] After the DSCHGenb signal goes low, the potential of the word line WL goes high, and after the potential of the word line WL goes high, the control circuit 100 changes the DSCHGenb signal to a high level. When the DSCHGenb signal goes high, the source line SL and the bit line BL are in a floating state until the ACTf signal goes high. This also makes it possible to suppress the short-circuit current in the active standby state, in which the write or read pulse does not occur, when the source line SL and the bit line BL are floating. Especially in a memory where input and output are performed via burst transmission, suppressing the leakage current in the active standby state is also very important and effective from the perspective of suppressing memory current consumption, since the duration of the active standby state is also long.

[0044] In the case of a write operation to the memory element, the write command is first received, and the data is then received and stored once in a register. The stored data controls the column control switch transistor in the desired direction by setting the ACTf signal to a high level before the write pulse occurs. After the write pulse breaks (the PLSen signal goes low), the ACTf signal also goes low, and the source line SL and the bit line BL are in a floating state.

[0045] In a case where data is read from the storage element, data (the high-level data in the example of Fig. 7), which generate a potential that is in one of the source lines SL and bit line BL connected to the reading amplifier 50 (the source line SL in the circuit of Fig. 2) is to be generated and transferred to the register. After the read pulse breaks (the PLSen signal becomes low), the ACTf signal becomes low, and the source line SL and the bit line BL are in a potential-free state.

[0046] Steering committee 100 informs the in Fig. The circuit shown in Figure 2 outputs a signal to discharge the charges accumulated in the source line SL and the bit line BL before the potential of the word line WL reaches a high level. Through this process, the control circuit 100 can not only suppress an increase in the power consumption of the semiconductor memory device 1 with a simple configuration, but also prevent faulty writing and destruction of a memory element.

[0047] Fig. 8 is an explanatory table that shows the state transition of each line and a transistor in the circuit of the in Fig. 3 is the comparative example shown. Fig. Figure 9 is an explanatory table that shows the transition of the state of lines and a transistor of the circuit in the Fig. 4. Then it is Fig. 10. An explanatory table showing the transition of the state of the lines and a transistor in Fig. The circuit shown in section 2 represents the circuit. Fig. 8, Fig. 9 to Fig. 10 means H high level and L low level.

[0048] As in Fig. As shown in Figure 8, in a case where the potentials of the source line and the bit line are fixed at VSS in standby mode, SLN and BLN are both high (H) in the idle state, during activation, and in the active state. Furthermore, as shown in Figure 8, SLN and BLN are... Fig. Figure 9 shows a case in which the potentials of the source line and the bit line are in a potential-free state in standby mode, both low (L) in the idle state, during activation and in the active state.

[0049] On the other hand, SLN and BLN are in the Fig. In the circuit shown in Figure 10, both SLN and BLN are low in the idle state. Then, during activation, both SLN and BLN become high, and in this state, the charges accumulated in the source line SL and the bit line BL are discharged. In the active state, SLN and BLN are again low. This transition allows the semiconductor memory device 1, according to the present embodiment, not only to suppress an increase in power consumption but also to prevent faulty writing and the destruction of a memory element.

[0050] Fig. Figure 11 is a flowchart illustrating a functional example of the semiconductor storage device 1 according to the embodiment of the present disclosure. The following is an example of the operation of the semiconductor storage device 1 according to the embodiment of the present disclosure with reference to Fig. 11 described.

[0051] During standby, the semiconductor storage device 1 maintains the source line SL and the bit line BL in a potential-free state by means of the signal from the control circuit 100 (step S101). If the control circuit 100 detects an activation command during standby mode (step S102), it outputs a signal to short-circuit the source line SL and the bit line BL to VSS (step S103). Short-circuiting the source line SL and the bit line BL to VSS dissipates the charges accumulated in the source line SL and the bit line BL as described above and eliminates the potential difference between the source line SL and the bit line BL.

[0052] When the source line SL and the bit line BL are short-circuited with VSS, the semiconductor memory device 1 then supplies the bit line BL with a predetermined potential (e.g., a high-level potential) and switches on the transistor connected in series with the memory element to connect the source line SL and the bit line BL via the memory element (step S104).

[0053] When the source line SL and the bit line BL are connected via the memory element and the active standby state is established, the semiconductor memory device 1 subsequently keeps the source line SL and the bit line BL in a potential-free state by means of a signal from the control circuit 100 (step S105).

[0054] Then, when a write or read command is generated (step S106), the semiconductor storage device 1 switches the source line SL and the bit line BL to a desired data state and performs a write or read operation (step S107). Afterward, when a preload (PRE) command is generated (step S108), the semiconductor storage device 1 returns to standby mode and keeps the source line SL and the bit line BL in a potential-free state via the signal from control circuit 100.

[0055] Through this process, the semiconductor storage device 1 according to the present embodiment can not only suppress an increase in power consumption, but also prevent faulty writing and destruction of a storage element. <2. Application Example>

[0056] In the semiconductor storage device 1 according to the embodiment of the present disclosure, all configurations can be formed on one chip and some configurations on another chip. Fig. Figure 12 is an explanatory diagram showing a configuration example of the semiconductor storage device 1 according to the embodiment of the present disclosure. For example, the semiconductor storage device 1 can include a memory chip 2 and a processing chip 3. As shown in Fig. As shown in Figure 12, the instruction counter 110, the temperature sensor 120, the timer 130, and the clock counter 140 can be implemented in the processing chip 3, and other configurations in the memory chip 2. The memory chip 2 and the processing chip 3 can then be mounted on a system-in-package or a system-on-a-chip. It should be noted that in Fig. 12. Reference cells in the reference cell arrangement 20 are provided as a high-impedance reference cell 20a and a low-impedance reference cell 20b. Furthermore, it shows Fig. 12 the column control switches 32a and 34a for the high-impedance reference cell 20a and the column control switches 32b and 34b for the low-impedance reference cell 20b.

[0057] Subsequently, the semiconductor storage device 1 according to the embodiment of the present disclosure can be mounted on various electronic devices. Examples of electronic devices onto which the semiconductor storage device 1 according to the embodiment of the present disclosure can be mounted are a smartphone, a tablet terminal, a digital camera, a digital video camera, a music player, a set-top box, a computer, a television, a clock, an active loudspeaker, headsets, a game console, a radio, a measuring instrument, an electronic label, and a beacon.

[0058] Fig. Figure 13 is an explanatory diagram showing an example of a functional configuration of an electronic device 1000 on which the semiconductor storage device 1 can be mounted according to the embodiment of the present disclosure. The diagram in Fig.Figure 13 shows an electronic device 1000 comprising a system-in-package 1100, an antenna 1110, a loudspeaker 1120, a microphone 1130, a display device 1140, an input device 1150, a sensor 1160, and a power supply 1170. Furthermore, the system-in-package 1100 includes a processor 1200, a wireless communication interface 1210, and an audio circuit 1220.

[0059] The antenna 1110 is used for mobile communication, wireless LAN, or near-field communication and is connected to the wireless communication interface 1210. The loudspeaker 1120 outputs sound and is connected to the audio circuit 1220. The microphone 1130 is used to collect sound around the electronic device 1000 and is also connected to the audio circuit 1220.

[0060] The display device 1140 includes, for example, a liquid crystal display, an organic EL display, a light-emitting diode (LED) display, and the like, and is connected to the processor 1200. The input device 1150 includes, for example, a keyboard, a button or key, a touch panel, and the like, and is connected to the processor 1200.

[0061] The sensor 1160 has functions such as an optical sensor, a position sensor, an accelerometer, a live-body sensor, a magnetic sensor, a mechanical quantity sensor, a thermal sensor, an electrical sensor, or a chemical sensor. The variable-resistance semiconductor memory device 1 according to the embodiment of the present disclosure can be connected to the sensor 1160. The power supply 1170 provides power to the electronic device 1000 and is a power supply that is powered, for example, by a battery or an AC adapter.

[0062] The processor 1200 is an electronic circuit for controlling the operation of the electronic device 1000, and the variable resistance semiconductor storage device 1 according to the embodiment of the present disclosure can be connected inside or outside the system in the housing 1100.

[0063] The wireless communication interface 1210 has a function for mobile communication, wireless LAN, or near-field communication. The semiconductor variable-resistance storage device 1 according to the embodiment of the present disclosure can be connected to the wireless communication interface 1210. The audio circuit 1220 has a function for controlling the loudspeaker 1120 and the microphone 1130, and the semiconductor variable-resistance storage device 1 according to the embodiment of the present disclosure can be connected to the audio circuit 1220.

[0064] By assembling the semiconductor storage device with variable resistance 1 according to the embodiment of the present disclosure, such an electronic device 1000 can improve write reliability when writing data while keeping power consumption low. <3. Conclusion>

[0065] As described above, according to the embodiment of the present disclosure, the semiconductor memory device 1 is capable of reducing the standby current without adding the transistor and wiring to the memory cell assembly, and of preventing erroneous writes to the memory element and destruction of the memory element due to charges accumulated in the source line and the bit line. The semiconductor memory device 1 according to the embodiment of the present disclosure can suppress standby leakage currents not only in standby mode but also in active standby mode.

[0066] Furthermore, according to the embodiment of the present disclosure, the semiconductor storage device 1 can suppress power consumption, which leads to an improvement in the product value of the end product or chip on which the semiconductor storage device 1 is mounted and contributes to cost reduction. In addition, the end product on which the semiconductor storage device 1 is mounted according to the embodiment of the present disclosure can improve its service life and suppress heat generation during operation, thereby reducing costs by decreasing the number of elements required to prevent heat generation and extending the product's lifespan.

[0067] While the preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to such examples. It is obvious that various variations and modifications within the scope of the technical idea described in the claims can be conceived by a person with ordinary knowledge in the field of technology to which the present disclosure belongs, and it is naturally understood that these variations and modifications fall within the technical scope of the present disclosure.

[0068] Furthermore, the effects described in this specification are merely illustrative or exemplary and not limiting. That is to say, the technology according to this disclosure may exhibit other effects, obvious to a person skilled in the art, either in addition to or instead of the effects described above, as described in this specification.

[0069] It should be noted that the following configuration is also within the technical scope of the present disclosure. (1) Control circuit which outputs a signal to discharge charges accumulated in a source line and a bit line according to the activation of a word line and outputs a signal to bring the source line and the bit line into a potential-free state before writing or reading begins, in relation to a storage element comprising the source line, the bit line, a transistor provided between the source line and the bit line and switched on and off by a potential of the word line, and a storage element connected in series with the transistor. (2) Control circuit according to (1) in which both the source line and the bit line are short-circuited to a ground potential in response to the activation of the word line. (3) The control circuit described above according to (2), in which the transistor is switched on after both the source line and the bit line are short-circuited to ground potential. (4) The control circuit described above according to (3), in which, after switching on the transistor, a signal is output to put the source line and the bit line into a potential-free state. (5) Semiconductor storage device comprising: a memory cell comprising a memory element positioned between a source line and a bit line, and a transistor arranged in series with the memory element, which is switched on and off by a potential of a word line; and a control circuit that outputs a signal to discharge charges accumulated in the source line and the bit line according to the activation of the word line, and outputs a signal to bring the source line and the bit line into a potential-free state by starting a write or read operation. (6) The semiconductor storage device described above according to (5) in which both the source line and the bit line are short-circuited to a ground potential in response to the activation of the word line. (7) The semiconductor storage device described above according to (6) wherein the transistor is switched on after both the source line and the bit line are short-circuited to ground potential. (8) The semiconductor storage device described above according to (7) wherein, after switching on the transistor, a signal is output to bring the source line and the bit line into a potential-free state. (9) Semiconductor storage device according to any of (5) to (8) described above, wherein the storage element is a variable resistance storage element. (10) The semiconductor storage device described above according to (9), wherein the storage element is a variable magnetoresistive storage element. (11) Information processing device comprising at least one semiconductor storage device as described in any of (5) to (10) above. (12) Control procedure by a processor, comprising: Outputting a signal to discharge charges accumulated in a source line and a bit line, according to the activation of a word line; and Output of a signal to bring the source line and the bit line into a potential-free state by initiating a write or read operation, with respect to a memory element comprising the source line, the bit line, a transistor provided between the source line and the bit line and switched on and off by a potential of the word line, and a memory element connected in series with the transistor. REFERENCE MARK LIST 1 Semiconductor storage device 100 control circuit

Claims

[1] Control circuit (100) which outputs a first signal to discharge charges accumulated in a source line (SL) and a bit line (BL) according to the activation of a word line (WL) and outputs a second signal to put the source line and the bit line into a potential-free state until the start of writing or reading, with respect to a memory cell which has the source line (SL), the bit line (BL), a transistor (Tr5) which is provided between the source line (SL) and the bit line (BL) and is switched on and off by a potential of the word line (WL), and a storage element (R1) connected in series with the transistor (TR5), wherein the control circuit (100) has a first transistor (Tr3) connected to the source line (SL) and a second transistor (Tr4) connected to the bit line (BL), and the first transistor (Tr3) includes a first gate terminal and the second transistor (Tr4) includes a second gate terminal, wherein the first gate terminal is connected to a first NAND gate (69) and the second gate terminal is connected to a second NAND gate (70), and wherein both the source line (SL) and the bit line (BL) are short-circuited to a ground potential at a first time in response to the first signal and transition from their respective first potential-free states to their respective non-potential-free states, and transition at a second time in response to the second signal to their respective second potential-free states. [2] Control circuit (100) according to claim 1, wherein the transistor (Tr5) is switched on after both the source line (SL) and the bit line (BL) are short-circuited to ground potential. [3] Control circuit (100) according to claim 2, wherein after switching on the transistor (Tr5) the second signal is output to put the source line (SL) and the bit line (BL) into a potential-free state. [4] Semiconductor storage device (1) comprising: a memory cell comprising a memory element (R1) provided between a source line (SL) and a bit line (BL) and a transistor (Tr5) arranged in series with the memory element (R1) and switched on and off by a potential of a word line (WL); and a control circuit (100) which outputs a first signal to discharge charges accumulated in the source line (SL) and the bit line (BL) according to the activation of the word line (WL) and outputs a second signal to put the source line (SL) and the bit line (BL) into a potential-free state until a writing or reading operation begins, wherein the control circuit (100) has a first transistor (Tr3) connected to the source line (SL) and a second transistor (Tr4) connected to the bit line (BL), and the first transistor (Tr3) includes a first gate terminal and the second transistor (Tr4) includes a second gate terminal, wherein the first gate terminal is connected to a first NAND gate (69) and the second gate terminal is connected to a second NAND gate (70), and wherein both the source line (SL) and the bit line (BL) are short-circuited to a ground potential at a first time in response to the first signal and transition from their respective first potential-free states to their respective non-potential-free states, and transition to their respective second potential-free states at a second time in response to the second signal. [5] Semiconductor storage device (1) according to claim 4, wherein the control circuit (100) switches on the transistor (Tr5) after both the source line (SL) and the bit line (BL) are short-circuited to ground potential. [6] Semiconductor storage device (1) according to claim 5, wherein the control circuit (100) outputs the second signal to shift the source line (SL) and the bit line (BL) into a potential-free state after the transistor (Tr5) is switched on. [7] Semiconductor storage device (1) according to claim 4, wherein the storage element (R1) is a storage element with variable resistance. [8] Semiconductor storage device (1) according to claim 4, wherein the storage element (R1) is a variable magnetoresistive storage element. [9] Information processing device comprising at least the semiconductor storage device (1) according to claim 4. [10] Control procedure by a processor (1200), comprising: Output (S103) of a first signal to discharge charges accumulated in a source line (SL) and a bit line (BL), according to the activation of a word line (WL); and Output (S105) of a second signal to put the source line (SL) and the bit line (BL) into a potential-free state until the start of writing or reading, with respect to a memory cell comprising the source line (SL), the bit line (BL), a transistor (Tr5) provided between the source line (SL) and the bit line (BL) and switched on and off by a potential of the word line (WL), and a memory element (R1) connected in series with the transistor (Tr5), wherein both the source line (SL) and the bit line (BL) are short-circuited to a ground potential at a first time in response to the first signal and transition from their respective first potential-free states to their respective non-potential-free states, and transition at a second time in response to the second signal to their respective second potential-free states.

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