Semiconductor unit and power converter

Abstract

Semiconductor unit comprising: - a first semiconductor layer (3) with a first conductivity type; - a first semiconductor region (5) with the first conductivity type, selectively arranged in an upper layer of the first semiconductor layer (3); - a second semiconductor region (15) with a second conductivity type, arranged in the upper layer of the first semiconductor layer (3) such that it is in contact with the first semiconductor region (5); - a third semiconductor region (4) with the second conductivity type, arranged on lower surfaces of the first and second semiconductor regions (5, 15); - a plurality of gate trenches (6) arranged to penetrate the first and third semiconductor regions (5, 4) in the thickness direction of the first and third semiconductor regions (5, 4), the plurality of gate trenches (6) each having a bottom surface.extending into the interior of the first semiconductor layer (3), wherein the plurality of gate trenches (6) have a strip-like form and extend in one direction in a top view; - a field-reducing region (13) of the second conductivity type, arranged at the bottom surface of each of the plurality of gate trenches (6); - an intermediate insulating layer (9) having contact openings (16) over the first and second semiconductor regions (5, 15); - a plurality of interconnection layers (12, 12c, 12d) arranged in the first semiconductor layer (3) at intervals such that each is in contact with at least one of the side walls of a corresponding plurality of gate trenches (6) in a second direction perpendicular to a first direction parallel to a direction in which the plurality of gate trenches (6) extend,wherein the distances between the plurality of spaced interconnect layers (12, 12c, 12d) in the first direction are such that they are as large as or larger than a distance at which the plurality of gate trenches (6) are arranged, wherein the plurality of interconnect layers (12, 12c, 12d) each electrically connect the field-reducing region (13) to the third semiconductor region (4); a first main electrode (10) arranged above the intermediate insulating layer (9) and inserted into the contact openings; and a second main electrode (11) arranged on a main surface of the first semiconductor layer (3), the main surface being opposite that on which the first main electrode (10) is arranged, wherein the first direction is parallel to an offset direction, wherein the plurality of interconnect layers (12, 12c,12d) is spaced apart from each other in the first direction and each of the plurality of interconnect layers (12, 12c, 12d) is connected to the first semiconductor region (5),- wherein the first semiconductor layer (3) has a silicon carbide layer,- wherein the first semiconductor layer (3) has an offset angle of more than 0 degrees in a <11-20> direction, and- wherein the plurality of gate trenches (6) each have a sidewall surface having a (1-100) plane or a (-1100) plane,- wherein the plurality of interconnect layers (12, 12c, 12d) each have:- a first interconnect layer (12c) arranged to be in contact with the corresponding of the plurality of gate trenches (6), and- a second interconnect layer (12d) located further away from the corresponding of the plurality of gate trenches (6) than the first interconnect layer (12c),- wherein the first compound layer (12c) consists of the first conductivity type and- wherein the second compound layer (12d) consists of the second conductivity type.

Description

TECHNICAL AREA The present invention relates to semiconductor units and in particular to a semiconductor unit with trench gates. STATE OF THE ART An electronic power device incorporates switching units, such as insulated-gate silicon bipolar transistors (IGBTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs), as devices for switching between conducting and stopping a current supply to drive a load (e.g., an electric motor). Vertical MOSFETs and vertical IGBTs are frequently used as switching devices in power semiconductor applications. These vertical MOSFETs are classified into different types according to their gate structures: planar-type vertical MOSFETs, trench-type vertical MOSFETs (trench-gate types), and other types. A trench-gate MOSFET, which has gate trenches (i.e., grooves) formed in an active region of a drift layer with the first conductivity type (the n-type), receives a high electric field due to structural causes when the MOSFET is off. This field is applied to a gate insulating layer at the bottom surfaces of the gate trenches. Such an applied field can cause breakdown of the gate insulating layer at the bottom surfaces of the gate trenches. To address this problem, patent document 1 specifies a technique in which a field-reducing region (i.e., a protective diffusion layer) with the second conductivity type (the p-type) is formed over the bottom surfaces of the gate trenches, thus reducing the electric field applied to a gate insulating layer at the bottom surfaces of the gate trenches. Patent document 1 further describes a technique in which a second base area is formed on the surface of a trench side wall with a large offset angle, and the protective diffusion layer is connected to a ground potential. Such a structure enables a depletion layer, extending from the protective diffusion layer to the drift layer during switching operations, to react effectively, thereby reducing switching losses. Patent document 2 discloses a technique in which a field concentration of trench soils is reduced by forming a deep p-type layer extending in a direction perpendicular to a direction in which a plurality of gate trenches extend and which is in contact with the side faces and bottom faces of the gate trenches. Patent document 3 discloses a semiconductor device comprising the following: strip-shaped trenchgate structures extending along a first horizontal direction in a semiconductor body based on a semiconductor material with a hexagonal crystal lattice, wherein side walls of the trenchgate structures are (-1100) and (1-100) crystal planes; transistor mesas between adjacent trenchgate structures, wherein the transistor mesas have body regions forming first pn junctions with a drift structure and second pn junctions with source zones. State-of-the-art documentation Patent documents Patent document 1: International publication WO 2014 / 122 919 A1 or family member DE 11 2014 000 679 B4; Patent document 2: Japanese patent application publication JP 2009 - 302 436 A; Patent document 3: DE 10 2014 119 465 B3 SHORT DESCRIPTION Problems to be solved with the invention The configuration disclosed in patent document 1 presents some problems. These problems arise because the second base region is formed in a crystal surface with an offset angle that exhibits the lowest channel mobility. The first problem is that if the second base area is formed over the entire surface of a trench sidewall with low channel mobility, the channel density is greatly reduced, potentially increasing the EIN resistance. The second problem is that if the second base area is formed only over a portion of a trench sidewall surface with low channel mobility, the channel mobility of other trench sidewall surfaces where channels are formed is not necessarily uniform. This is because in the other trench sidewall surfaces on which the channels are formed, there are partially active areas in the trench sidewall surfaces that exhibit low channel mobility and in the trench sidewall surfaces that do not exhibit low channel mobility; consequently, the channel mobility is not uniform. As a result, the reliability of a switching unit can deteriorate due to a current concentration on a specific channel surface. Furthermore, operating characteristics can become unstable due to fluctuations in the threshold voltage. In order to maintain a breakdown voltage when the MOSFET is switched off, the configuration disclosed in patent document 2 has no other option than to form deep p-type layers with small spacings, thus increasing the ON resistance of the switching unit because the channel density is greatly reduced. To solve these problems, the object of the present invention is to provide a semiconductor unit in which the reliability and operating characteristics are improved by reducing electric fields at the bottom surfaces of the trench gates, and in which the ON resistance is kept low and no current concentration is caused in a particular channel surface and no fluctuations in the threshold voltage are caused. Means of solving the problems The problem is solved by a semiconductor unit and a power converter with the features of the independent claims. Advantageous further developments result from the dependent claims. Effects of the invention In the semiconductor device according to the present invention, which has the field-reducing region at the bottom surface of the gate trench, electric fields present at the bottom surfaces of the gate trenches are reduced when the semiconductor device is in the OFF state. In the semiconductor device, which has the interconnect layer connecting the field-reducing region to the third semiconductor region, a current path for charging and discharging at a pn junction is also provided, formed by the field-reducing region and the first semiconductor layer, thus reducing switching losses. BRIEF DESCRIPTION OF THE DRAWINGS The figures show: Fig. 1 a top view schematically illustrating the configuration of the upper surface of an entire semiconductor unit according to an illustrative example; Fig. 2 a top view illustrating the configuration of a semiconductor unit according to a first illustrative example; Fig. 3 a cross-sectional view illustrating the configuration of the semiconductor unit according to the first illustrative example; Fig. 4 a cross-sectional view illustrating the configuration of the semiconductor unit according to the first illustrative example of the present invention; Fig. 5 a cross-sectional view illustrating a process step for manufacturing the semiconductor unit according to the first illustrative example; Fig. 6 a cross-sectional view illustrating a process step for manufacturing the semiconductor unit according to the first illustrative example; Fig.Fig. 7 shows a cross-sectional view showing a process step for manufacturing the semiconductor unit according to the first explanatory example; Fig. 8 shows a cross-sectional view showing a process step for manufacturing the semiconductor unit according to the first explanatory example; Fig. 9 shows a cross-sectional view showing a process step for manufacturing the semiconductor unit according to the first explanatory example; Fig. 10 shows a cross-sectional view showing a process step for manufacturing the semiconductor unit according to the first explanatory example; Fig. 11 shows a cross-sectional view showing a process step for manufacturing the semiconductor unit according to the first explanatory example; Fig. 12 shows a cross-sectional view showing a process step for manufacturing the semiconductor unit according to the first explanatory example; Fig. 13 shows a cross-sectional view showing a process step for manufacturing the semiconductor unit according to the first explanatory example; Fig.Fig. 14 is a cross-sectional view showing a process step for manufacturing the semiconductor unit according to the first explanatory example; Fig. 15 is a cross-sectional view showing a process step for manufacturing the semiconductor unit according to the first explanatory example; Fig. 16 is a top view showing the configuration of a semiconductor unit according to a modification of the first explanatory example; Fig. 17 is a cross-sectional view showing the configuration of the semiconductor unit according to the modification of the first explanatory example; Fig. 18 is a cross-sectional view showing the configuration of the semiconductor unit according to the modification of the first explanatory example; Fig. 19 is a cross-sectional view showing a process step for manufacturing the semiconductor unit according to the modification of the first explanatory example; Fig.Fig. 20 a top view showing the configuration of a semiconductor unit according to a modification of the first explanatory example; Fig. 21 a top view showing the configuration of a semiconductor unit according to a modification of the first explanatory example; Fig. 22 a top view showing the configuration of the semiconductor unit according to the modification of the first explanatory example; Fig. 23 a top view showing the configuration of a semiconductor unit according to a second explanatory example; Fig. 24 a cross-sectional view showing the configuration of the semiconductor unit according to the second explanatory example; Fig. 25 a cross-sectional view showing the configuration of the semiconductor unit according to the second explanatory example; Fig. 26 a top view showing the configuration of a semiconductor unit according to a modification of the second explanatory example; Fig.27 a cross-sectional view showing the configuration of a semiconductor unit according to a modification of the second explanatory example; Fig. 28 a cross-sectional view showing the configuration of a semiconductor unit according to an embodiment of the present invention; Fig. 29 a top view showing the configuration of a semiconductor unit according to a third explanatory example; Fig. 30 a cross-sectional view showing the configuration of the semiconductor unit according to the third explanatory example; Fig. 31 a top view showing the configuration of a semiconductor unit according to a fourth explanatory example; Fig. 32 a cross-sectional view showing the configuration of the semiconductor unit according to the fourth explanatory example; Fig. 33 a cross-sectional view showing the configuration of the semiconductor unit according to the fourth explanatory example; Fig.34 a cross-sectional view showing the configuration of a semiconductor unit according to an illustrative example; Fig. 35 a block diagram showing the configuration of a power conversion system according to a sixth illustrative example. The following describes embodiments with reference to the accompanying drawings. The drawings are schematic. The interrelationship between the dimensions and positions of representations shown in different drawings is not necessarily exact and is subject to change where necessary. In the following description, similar components are shown with the same reference numerals and have similar designations and functions. In some cases, their description is not elaborated upon or repeated. In some cases, the following description uses terms that refer to specific positions and directions (e.g., "above," "downward," "sideways," "below," "front," and "back"). These terms are used solely for the purpose of facilitating understanding of what is disclosed in the respective embodiment and therefore have nothing to do with actual directions. The term "MOS" has long been used to describe a structure in which a metal, an oxide, and a semiconductor are combined, and it is an abbreviation for "metal-oxide-semiconductor." With regard to integration, improvements in manufacturing processes, and the like in recent years, a field-effect transistor with a MOS structure (referred to hereafter simply as a "MOS transistor") features, in particular, a gate insulating layer and a gate electrode made of an improved material. For example, a MOS transistor has a gate electrode made of polycrystalline silicon instead of metal, in order to form its source and drain in a self-aligning manner. Furthermore, to improve electrical properties, the gate insulating layer consists of a material with a high dielectric constant, which is not necessarily limited to an oxide. The term "MOS" is not necessarily used only for a stacked structure consisting of a metal, an oxide, and a semiconductor. Therefore, this term is not used in the description based on such a restriction. That is to say, in a common technical sense, the term "MOS" here is not merely an abbreviation for its etymology, but also frequently refers to a stacked structure consisting of an electrical conductor, an insulator, and a semiconductor. This text refers to conductivity types of faults. In the following description, an n-type is generally defined as a "first conductivity type" and a p-type as a "second conductivity type". These definitions are also reversible. First illustrative example Unit configuration Fig. 1 is a top view schematically illustrating the configuration of the upper surface of an entire semiconductor unit. As shown in Fig. 1, the semiconductor unit has a rectangular appearance. An active region 30 is located in the center of the semiconductor unit, containing a plurality of minimal unit structures (MOSFET cells) of a MOSFET, referred to as "unit cells". The active region 30 is surrounded by a termination region 32. The active area 30 has a plurality of gate trenches 6 arranged parallel to each other at intervals. The gate trenches 6 are connected by gate wires located within the active area 30. The gate wires are connected to a gate terminal. The gate wires and the gate terminal are not described in detail. Fig. 2 is an enlarged top view of an area “X” shown in Fig. 1. Characteristic configurations of area “X” and their modifications are described below as illustrative examples. Fig. 1 is also commonly used to describe the illustrative examples and their modifications. Fig. 2 is a top view showing the configuration of a semiconductor unit according to a first illustrative example. In particular, Fig. 2 is a top view showing a characteristic region of a trench-gate MOSFET 100 mounted on a silicon carbide semiconductor substrate (i.e., a SiC substrate). As shown in Fig. 2, the trench-gate MOSFET 100 in the first illustrative example has a unit cell 31 consisting of two adjacent gate trenches 6 and defect regions located between the two gate trenches 6. The gate grooves 6 are arranged in the form of strips such that they extend in a direction parallel to an offset direction of the silicon carbide semiconductor substrate. The gate grooves 6 subdivide the active region 30 into MOSFET cell units. The inner walls of the gate grooves 6 are covered with gate insulating layers 7. Gate electrodes 8 are inserted into the regions surrounded by the gate insulating layers 7. The active region 30 between the gate grooves 6 is provided with source contacts 16 that penetrate an intermediate insulating layer (not shown). The lower surfaces of the source contacts 16 are provided with a plurality of recessed contacts 15. The opening widths of the source contacts 16 are uniform within the active area 30. In other words, these opening widths are desirablely uniform in one direction (i.e., the second direction, which is the lateral direction of Fig. 3) perpendicular to a direction (i.e., the first direction, which is the lateral direction of Fig. 2) in which the gate grooves 6 extend, and in particular, the opening widths are desirablely within a range of ±25%. If the opening widths of the source contacts 16 in the active area are not uniform, the source electrode 10 may not be inserted uniformly into the interior of the source contacts 16. If this is the case, the semiconductor unit will no longer have a flat surface, potentially impairing reliability during assembly and packaging. Ensuring that the opening widths of the source contacts 16 in the active area 30 are uniform prevents this problem. Fig. 3 is a cross-sectional view along a line AA, which is indicated by arrows in Fig. 2. Fig. 4 is a cross-sectional view along a line BB, which is indicated by arrows in Fig. 2, and shows the periodic configuration of the unit cell 31 in its cross-section in the active area 30 at a location that has the gate trenches 6. For simplicity, a configuration above a line WW in Fig. 3 has been omitted in Fig. 2 to aid understanding of how sidewall trough connection layers 12 are arranged in a drift layer 3. As shown in Fig. 3, the trench-gate MOSFET 100 according to the first illustrative example comprises: the n-type drift layer 3 (i.e., the first semiconductor layer) arranged on one of the main surfaces (i.e., the first main surface) of a silicon carbide semiconductor substrate 1; a heavily doped n-type layer 14 (i.e., a second semiconductor layer) arranged on the drift layer 3; a p-type trough region 4 (i.e., a third semiconductor region) arranged on the heavily doped layer 14; an n-type source region 5 (i.e., a first semiconductor region) arranged on the trough region 4; and the p-type trough contact region 15 (i.e., a second semiconductor region) arranged on the trough region 4.The gate trenches 6, which penetrate the source area 5, the trough area 4, and the highly doped layer 14 in their thickness direction from the upper surface of the source area 5 and extend into the interior of the drift layer 3, have bottom surfaces beneath which field-reducing areas 13 of p-type are arranged on the trench bottom surfaces (i.e., field-reducing areas). Each sidewall trough connection layer 12 of p-type (i.e., each connection layer) is arranged such that it is in contact with one of the lateral surfaces of the corresponding field-reducing area 13 on the trench bottom surface and one of the sidewalls of the corresponding gate trench 6. The trench-gate MOSFET 100 also has an intermediate insulating layer 9 arranged over each gate trench 6 and its surrounding area. The space between the gate trenches 6 that is not covered by the intermediate insulating layer 9 is the source contact 16 (i.e., a contact opening), the lower surface of which is covered with a silicide layer 17. The silicide layer 17 is connected via the source contact 16 to the source electrode 10 (i.e., the first main electrode). The trench-gate MOSFET 100 also has a drain electrode 11 (i.e., a second main electrode) arranged on the other main surface (i.e., a second main surface) of the silicon carbide semiconductor substrate 1, opposite the surface on which the source electrode 10 is located. Here, the silicon carbide semiconductor substrate 1 has a polytype 4H. Furthermore, the main surfaces of the silicon carbide semiconductor substrate 1 and a main surface of the drift layer 3 are (0001) planes, each exhibiting an offset angle θ inclined in the direction of a [11-20] axis. The offset angle θ must, for example, be equal to a value of 10° or less. The recessed area 4 in the upper layer of the drift layer 3 is located in the active area 30, where the MOSFET cells are arranged. The source area 5 and the recessed contact area 15 are selectively (partially) located in the recessed area 4. The recessed contact area 15 is surrounded by the source area 5 in a top view, as shown in Fig. 2. Each gate groove 6 contains a gate electrode 8, with the gate insulating layer 7 inserted between the gate groove 6 and the gate electrode 8. Each gate electrode 8 has a top surface that is recessed below the top surface of the source region 5. In other words, the gate electrode 8 has a top surface that is set back from the opening end of the gate groove 6. This is true for the cross-section shown in Fig. 4 along line BB. The field-reducing areas 13 on the trench bottom surfaces beneath the respective bottom surfaces of the gate trenches 6 are arranged to reduce the electric fields present on the bottom and side surfaces of the gate trenches 6 when the MOSFET is switched off. The field-reducing areas 13 on the trench bottom surfaces are preferably in contact with the respective gate trenches 6. Each sidewall trough connection layer 12, which is arranged to be in contact with an area of ​​the lateral surface of the corresponding field-reducing area 13 on the trench bottom surface and an area of ​​the sidewall of the corresponding gate trench 6, is also in contact with the trough area 4 and electrically connects the field-reducing area 13 on the trench bottom surface to the trough area 4. The sidewall trough connection layer 12 is only in contact with a portion of the sidewall of the gate trench 6, as shown in Figs. 2 and 4. In Fig. 2, the sidewall trough connection layer 12 is not continuous and is only arranged on one of the sidewalls of the gate trench 6. When a gate bias is applied, the sidewall of each gate trench 6 has an inverting channel formed in a region without the sidewall trough connection layer 12. This inverting channel serves as a channel region of the MOSFET. The channel properties of each sidewall of the gate trench 6 are configured to be approximately identical and are configured to be non-dissimilar. In other words, if the direction in which the gate trenches 6 extend (i.e., the first direction) is specified to be parallel to a <11-20> direction, which is an offset direction, this causes the trench sidewall to be nearly a (1-100) plane and a (-1100) plane perpendicular to a (0001) plane. Even though the drift layer 3 has an offset angle in the <11-20> direction, the drift layer 3 is consequently not affected by the anisotropy of electrical properties resulting from differences between crystal surfaces in each trench sidewall, thus achieving identical and uniform channel properties. This eliminates the need to form the sidewall trough connection layer 12 on the entire specified trench sidewall, thus preventing a reduction in channel density and an increase in the MOSFET's ON resistance. No trench gates with differing channel characteristics are included, so no current concentration is caused in a specific channel surface and no instability occurs at a threshold voltage. Since the gate trench 6 penetrates the source region 5, the n-type source region 5 is located in a region corresponding to the edge of the gate trench 6's opening end. However, the edge of the gate trench 6's opening end, designated by region "Y", is covered by the gate insulating layer 7 and the intermediate insulating layer 9. Therefore, the upper surface of the gate electrode 8 does not extend to the edge of the opening end. This means that the source region 5 and the gate electrode 8 do not face each other across the gate insulating layer 7 at the edge of the gate trench 6's opening end in the active region 30. It should be noted that not the entire active area 30 needs to adopt the top-view configuration and the cross-sectional configurations shown in Figures 2, 3 to 4. A portion of the active area 30 may adopt these configurations. It should also be noted that the ratio between the cross-sectional configuration according to Figure 3 and the cross-sectional configuration according to Figure 4 is not limiting. The ratio can be freely chosen; in one example, the ratio of one of these cross-sectional configurations is higher than the other, and one of them is lower than the other. Methods for manufacturing If the defect concentration of each defect layer and defect area exhibits a concentration profile as described below, the defect concentration (cm-3) indicates the peak value of the defect concentration of each defect layer and defect area. Examples of n-type impurities include nitrogen (N) or phosphorus (P). Examples of p-type impurities include aluminum (Al) or boron (B). The following describes a method for manufacturing the MOSFET 100 with trench gate according to the first illustrative example with reference to Figs. 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 to 15, which are cross-sectional views showing successive process steps. In the first step (see Fig. 5), the silicon carbide drift layer 3, which contains a relatively low concentration of n-type (n-) defects and has a relatively high resistivity, is epitaxially grown onto one of the main surfaces of the silicon carbide semiconductor substrate 1 in the form of a wafer with a polytype 4H. The drift layer 3 is formed such that it has a defect concentration of 1 x 10¹⁴ cm⁻³ or a higher defect concentration, and a lower defect concentration of 1 x 10¹⁷ cm⁻³ or a lower defect concentration. The drift layer 3 is then subjected to reactive ion etching (RIE) photolithography with reference to an alignment marker located on a chip singulation line. In the next step (see Fig. 6), an ion implantation mask (not shown) is formed on the drift layer 3, and defect ions are introduced or injected through the ion implantation mask to form the heavily doped layer 14 in the upper layer of the drift layer 3. This layer contains a relatively high concentration of n-type (n+) defects and exhibits relatively low resistivity. This is followed by the formation of the p-type trough region 4 in the upper surface of the heavily doped layer 14, and finally, the formation of the source region 5, which also contains a relatively high concentration of n-type (n+) defects and exhibits relatively low resistivity, in the upper layer of the p-type trough region 4.One example of an ion implantation mask that can be used here is a resist mask. Source region 5 is formed such that it has a defect concentration of 5 x 10¹⁸ cm⁻³ or higher, and a defect concentration of 5 x 10²⁸ cm⁻³ or lower. Furthermore, trough region 4 is formed such that it has a defect concentration of 1 x 10¹⁶ cm⁻³ or higher, and a defect concentration of 3 x 10¹⁹ cm⁻³ or lower. Additionally, the concentration of n-type defects in source region 5 is specified to be higher than the concentration of p-type defects in trough region 4, in order to form the n-type source region 5 within the upper layer of the p-type trough region 4. The heavily doped layer 14 is formed such that it has a defect concentration of 5 x 10¹⁶ cm⁻³ or higher, and a defect concentration of 1 x 10¹⁸ cm⁻³ or lower. The heavily doped layer 14 acts as a current distribution layer when the MOSFET is switched on and is able to reduce the ON-resistance. The concentration in depression area 4 can be uniform in its depth direction or not. For example, the concentration can assume a distribution such that the surface concentration of depression area 4 is reduced, or it can assume a distribution such that the surface concentration exhibits a peak in the depth direction of depression area 4. In the next step (see Fig. 7), the p-type trough contact regions 15 are formed by ion implantation in the source region 5. The trough contact regions 15 are formed such that they have a p-type defect concentration of 1 x 10¹⁹ cm⁻³ or higher, and a defect concentration of 1 x 10²² cm⁻³ or lower. The trough contact regions 15 are also formed to be as thick as or thicker than the source region 5, ensuring that the trough contact regions 15 come into contact with the trough region 4. It should be noted that this defect layer and defect region can be formed in any order within the drift layer 3. In the next step (see Fig. 8), an etch mask RM1, which has openings OP1 at locations corresponding to the areas for forming the gate grooves 6, is structured on the drift layer 3 using a resist material. This layer now includes the source area 5 and the trough contact area 15. The etch mask RM1 must be formed with reference to the alignment mark mentioned above. After structuring, the gate grooves 6 are formed by RIE over the etch mask RM1 such that they penetrate the source area 5 and the trough area 4 in their thickness direction and extend into the interior of the drift layer 3. In the next step (see Fig. 9), the field-reducing areas 13 of p-type are formed on the trench bottom surfaces beneath the bottom surfaces of the respective gate trenches 6 by introducing or injecting p-type defect ions using the etching mask RM1 as an ion implantation mask. The field-reducing areas 13 on the trench bottom surfaces exhibit a defect concentration of 1 x 10¹⁷ cm⁻³ or a higher defect concentration, and a defect concentration of 1 x 10²⁷ cm⁻³ or a lower defect concentration. After removing the etching mask RM1, an ion implantation mask RM11 is structured in the next step (see Fig. 10) using a resist material. The ion implantation mask RM11 has a structure in which openings OP11 are arranged only in a region that forms the side wall of the corresponding gate groove 6, specifically where the side wall trough connection layer 12 is to be placed. Furthermore, the ion implantation mask RM11 has no opening in a region that forms the side wall of the corresponding gate groove 6 where the side wall trough connection layer 12 is not to be placed. By introducing or injecting the p-type disturbance ions from an oblique direction via the ion implantation mask RM11 (such introduction or injection is referred to as oblique ion implantation), the sidewall trough connection layers 12 are formed, each of which is in contact with one of the sidewalls of the corresponding gate trench 6 and one of the lateral surfaces of the corresponding field-reducing area 13 on the trench bottom surface. During the introduction or injection of ions to form the sidewall trough connection layers 12, the silicon carbide semiconductor substrate 1 is tilted in the form of a wafer. This ion implantation is performed under the following conditions: an angle of incidence in the range of 20° to 60° with respect to implantation at 0°, which is an implantation procedure in which defects are introduced or injected in a direction perpendicular to a wafer; a defect concentration of 5 x 10¹⁶ cm⁻³ or higher and 1 x 10²⁻³ or lower; and a depth (a length in the thickness direction of the drift layer 3) of 0.3 µm or more from a surface of the trough region 4.Accordingly, the side wall of the gate trench 6 and the lateral surface of the field-reducing area 13 on the trench floor surface are successfully covered with the side wall trough connecting layer 12. It should be noted that, although the above shows by way of example the formation of the field-reducing areas 13 on the ditch bottom surfaces followed by the formation of the side wall trough connection layers 12, the side wall trough connection layers 12 followed by the field-reducing areas 13 can be formed on the ditch bottom surfaces. It should also be noted that, although the above shows by way of example the formation of the gate ditches 6 followed by the formation of the field-reducing areas 13 on the ditch bottom surfaces and the side wall trough connection layers 12, the field-reducing areas 13 on the ditch bottom surfaces and the side wall trough connection layers 12 can be formed individually and the gate ditches 6 can then be formed at places where the respective field-reducing areas 13 on the ditch bottom surfaces and the side wall trough connection layers 12 are arranged. In this case, the formation of the field-reducing areas 13 on the trench bottom surfaces at a later stage allows the ion implantation mask, which is used for introducing or injecting ions into the field-reducing areas 13 on the trench bottom surfaces, to be used to form the gate trenches 6. The ion implantation can be carried out in a direction perpendicular to the wafer. The next step involves annealing for 0.5 minutes or longer and for 60 minutes or less at a temperature of 1500 °C or higher and 2200 °C or lower to activate the introduced or injected ions. Furthermore, the silicon carbide semiconductor substrate 1 is subjected to thermal oxidation, chemical vapor deposition (CVD), or other processes to form an insulating layer on it, followed by a wet or dry etching process to form a field insulating layer (not shown) to protect the termination area 32 (see Fig. 1). Subsequently, the gate insulating layer 7 is formed by thermal oxidation, CVD, or other processes to cover the inner wall surfaces and the area surrounding the gate grooves 6. In the next step (see Fig. 11), a conductive PS layer (e.g., a polysilicon layer) containing a relatively high concentration of defects is formed on the drift layer 3, which is now covered with the gate insulating layer 7, by CVD or other methods. When a polysilicon layer is formed by CVD, the polysilicon grows not only vertically from the bottom surface of each gate trench 6, but also horizontally from the lateral surfaces of each gate trench 6. Thus, the polysilicon is introduced relatively easily into the interior of the gate trench 6. The polysilicon layer on drift layer 3 is then removed by an etching process. While the polysilicon layer on the surface of drift layer 3 is removed by the etching process, the polysilicon layer remains inside each gate trench 6 due to its thickness, thus forming the gate electrodes 8. Slight over-etching is not required to completely remove the polysilicon layer on the surface of drift layer 3 within the wafer surface. Once the polysilicon layer on the surface of drift layer 3 is completely etched, the upper surface of the gate electrode 8 within the gate trench 6 is consequently formed at a location that is recessed relative to the opening end of the gate trench 6. In the next step (see Fig. 12), the intermediate insulating layer 9 is formed such that it covers the termination area 32 (see Fig. 1) and the active area 30, followed by the structuring of an etch mask RM2 with openings OP2 at locations corresponding to the areas for forming the source contacts 16 on the intermediate insulating layer 9 using a resist material. The etch mask RM2 must be formed with reference to the alignment mark mentioned above. The intermediate insulating layer 9 is then subjected to a dry etching process or other method via the etching mask RM2 to form the source contacts 16, which penetrate the intermediate insulating layer 9 and extend to a point above the drift layer 3, as shown in Fig. 13. The gate insulating layer 7, which is no longer needed, is removed along with the intermediate insulating layer 9. It should be noted that the etching mask RM2 may have an opening for forming a gate contact (not shown), which is formed in the termination area 32 (see Fig. 1), and that a dry etching process or other methods can be carried out through this opening to remove the intermediate insulating layer 9 and simultaneously form the gate contact. Of course, the source contacts 16 and the gate contact can be formed in separate process steps. In the next step (see Fig. 14), a metal layer ML (e.g., a nickel layer) is formed over the source contacts 16 and the intermediate insulating layer 9 by sputtering or other methods. In the subsequent step, annealing takes place at a temperature in the range of 300 °C to 1200 °C to form a metal silicide layer (i.e., here a NiSi2 layer) in the upper regions of the source areas 5 and the recessed contact areas 15, which are exposed towards the lower surfaces of the source contacts 16, as shown in Fig. 15. This metal silicide layer is the silicide layer 17. In the next step, the source electrode 10 is formed by sputtering or other methods so that it is inserted into the source contacts 16, and the source electrode 10 is electrically connected to the recessed contact areas 15 and the source area 5. This results in the cross-sectional configurations shown in Figures 3 and 4. The gate terminal or the wires for a connection to the gate terminal are formed from the interior to an upper region of a gate contact (not shown). In the final step, the drain electrode 11 is formed on the other main surface of the silicon carbide semiconductor substrate 1 by sputtering or other methods. These process steps produce the trench-gate MOSFET 100 shown in Figures 2 and 3. Features The following describes features of the trench-gate MOSFET 100. As shown in Figures 3 and 4, the field-reducing regions 13 are located on the trench bottom surfaces beneath the respective gate trenches 6. Consequently, depletion layers extending from the field-reducing regions 13 on the trench bottom surfaces enable a significant reduction of the electric field present at the gate insulating layer 7 when the MOSFET is in the OFF state. As shown in Fig. 3, the sidewall trough connection layers 12 are each in contact with one of the lateral surfaces of the corresponding field-reducing region 13 on the trench bottom surface, as well as with the trough region 4. The field-reducing region 13 on the trench bottom surface is thus electrically connected to the trough region 4. This electrical connection provides a current path for charging and discharging at a pn junction formed by the field-reducing region 13 on the trench bottom surface and the drift layer 3 during the switching operations of the MOSFET. As a result, switching losses are reduced. In other words, the sidewall trough connection layers 12 each provide a current path for a displacement current that flows in conjunction with the expansion and contraction of the depletion layer formed at the pn junction. The field-reducing regions 13 at the trench bottom surfaces each establish a floating potential when the sidewall trough connection layer 12 is not present. This reduces the potential lag in the field-reducing region 13 at the trench bottom surface with respect to the ON and OFF operations of the MOSFET. The reaction rate of the depletion layer formed at the pn junction slows down as a result, creating a structure in which the MOSFET is less likely to switch on and off. Consequently, switching losses increase. An arrangement of the sidewall trough interconnection layers 12 improves the reaction rate of the depletion layers formed at the pn junctions, thereby reducing switching losses. The sidewall trough connection layer 12, which is only arranged in one area of ​​the trench sidewall, does not cause a significant reduction in channel density. This prevents an increase in the inward flow resistance resulting from the arrangement of the sidewall trough connection layer 12. Furthermore, the trench sidewall where the sidewall trough connection layer 12 is not arranged extends in a direction parallel to an offset direction. This results in uniform channel characteristics, preventing current concentration in a specific channel surface and avoiding instability in a threshold voltage, thus achieving a MOSFET that operates in a highly stable manner. The sidewall trough connection layer 12, which is arranged only on one of the sidewalls of each gate trench 6, significantly prevents an increase in the EIN resistance resulting from the arrangement of the sidewall trough connection layer 12. The sidewall trough connecting layers 12, which are adjacent to each other in a plan view in the direction in which the gate trenches 6 extend, are desirablely arranged at intervals equal to or greater than the spacing of the gate trenches 6. Arranging the sidewall trough connecting layers 12 at such intervals further prevents a reduction in channel density and largely prevents an increase in the EIN resistance resulting from the arrangement of the sidewall trough connecting layers 12. The sidewall trough connecting layers 12 are each arranged such that they extend from the sidewall of the corresponding gate trough 6 in one direction (i.e., a second direction, which is the lateral direction in Fig. 3) perpendicular to a direction (i.e., a first direction, which is the lateral direction in Fig. 2) in which the gate troughs 6 extend. The sidewall trough connecting layer 12 is shorter in the second direction than the length between the gate troughs that are adjacent to each other. Furthermore, the sidewall trough connection layer 12 does not block the space between adjacent gate trenches. Consequently, a current flows through the drift layer 3 between the sidewall trough connection layers 12 that are adjacent to each other in the direction in which the gate trenches 6 extend, and thus spreads within the drift layer 3. This current flow and propagation prevent an increase in the ON resistance resulting from the arrangement of the sidewall trough connection layers 12. Each sidewall trough connection layer 12 is configured such that its depth (i.e., the length in the thickness direction of the drift layer) decreases with the distance in the second direction from the sidewall of the gate trench 6. Such a configuration facilitates current propagation, thus further preventing an increase in the ON resistance. First modification The following describes the configuration of a trench-gate MOSFET 100A according to a modification of the first illustrative example, with reference to Figures 16, 17 to 18. Figures 16, 17 to 18 correspond to Figures 2, 3 to 4. Components identical to those shown in Figures 2, 3 to 4 are designated with the same reference numerals and are not described in detail. Figure 17 is a cross-sectional view along a line CC, which is indicated by arrows in Figure 16. Figure 18 is a cross-sectional view along a line DD, which is indicated by arrows in Figure 16. As shown in Figs. 16, 17 to 18, the MOSFET 100A with trench gate has n-type current distribution areas 19, each adjacent to the corresponding side wall trough connection layer 12 and the corresponding field-reducing area 13 on the trench bottom surface, and arranged to surround the corresponding side wall trough connection layer 12 and the corresponding field-reducing area 13 on the trench bottom surface. As shown in Fig. 18, the current distribution area 19 is arranged at a location without the sidewall trough connection layer 12 in the drift layer 3 such that the circumferential line of the current distribution area 19 extends beyond both lateral surfaces and the lower surface of the field-reducing area 13 at the trench bottom surface. As shown in Fig. 17, the current distribution area 19 is arranged at a location provided with the sidewall trough connection layer 12 in the drift layer 3 such that the circumferential line of the current distribution area 19 extends beyond one of the lateral surfaces and the lower surface of the field-reducing area 13 at the trench bottom surface, and beyond one lateral surface of the sidewall trough connection layer 12 and the lower surface of the sidewall trough connection layer 12. As shown in Fig. 16, the current distribution areas 19 are each arranged along the entire length of the corresponding gate trench 6. The current distribution areas 19 can be formed using the etching mask RM1 with openings OP1 at locations corresponding to the areas for forming the gate trenches 6. In other words, the current distribution area 19 is formed in the drift layer 3 by the following process steps such that it has a perimeter line extending beyond both lateral surfaces and the lower surface of the field-reducing area 13 on the trench bottom surface: Forming the p-type field-reducing area 13 on the trench bottom surface below the lower surface of the gate trench 6 in the process step shown in Fig. 9, followed by introducing or injecting n-type defect ions from oblique directions (such introduction or injection being referred to as oblique ion implantation) by using the etching mask RM1 as an ion implantation mask, as shown in Fig. 19. When introducing or injecting ions to form the current distribution area 19, the silicon carbide semiconductor substrate 1 is tilted in the form of a wafer. This ion implantation is performed on both side walls of the gate trench 6 under the following condition: an angle of incidence in a range of 20° to 60° relative to an implantation at 0°, which is an implantation procedure in which defects are introduced or injected in a direction perpendicular to the wafer. This ion implantation is also performed under the following conditions: an impurity concentration of 5 x 10¹⁵ cm⁻³ or higher, and an impurity concentration of 1 x 10¹⁸ cm⁻³ or lower. Although the etching mask RM1 is used here as an example, the entire wafer surface can be subjected to ion implantation after the etching mask RM1 has been removed. As described above, the impurity concentration of drift layer 3 is equal to 1 x 10¹⁴ cm⁻³ or higher and equal to 1 x 10¹⁷ cm⁻³ or lower. The current distribution areas 19 are formed such that they have a higher impurity concentration than drift layer 3 within the aforementioned impurity concentration range. After the formation of the current distribution areas 19, the side wall trough connection layers 12 are formed, each of which is in contact with one of the side walls of the corresponding gate trench 6 and one of the lateral surfaces of the corresponding field-reducing area 13 on the trench floor surface. As described above with reference to Fig. 10, the sidewall trough connection layers 12 are formed using an ion implantation mask having a structure that is provided with the openings OP11 only in areas which have the sidewalls of the gate trenches 6 in which the sidewall trough connection layers 12 are to be formed, and which does not have openings in areas which have the sidewalls of the gate trenches 6 in which the sidewall trough connection layers 12 are not to be formed. Arranging the current distribution regions 19 with a higher impurity concentration than that of the drift layer 3 creates a higher resistance in a region of the drift layer 3 not covered with the current distribution regions 19 than that of the current distribution regions 19. This allows current to flow through the current distribution regions 19 with lower resistance on a priority basis, thereby reducing the ON resistance of the MOSFET. The arrangement of the current distribution regions 19 determines whether or not the heavily doped layer 14 is formed. It should be noted that, although Figs. 16, 17 to 18 illustrate by way of example that the circumferential line of the current distribution area 19 is arranged so that it extends beyond both lateral surfaces of the field-reducing area 13 on the trench bottom surface, the circumferential line of the current distribution area 19 can also be arranged so that it extends beyond only one of the lateral surfaces of the field-reducing area 13 on the trench bottom surface. Second modification Referring to Fig. 2, which shows a top view of the configuration of the MOSFET 100 with a trench gate according to the first explanatory example, it is shown above that the sidewall trough connection layers 12 are arranged only on one of the sidewalls of the gate trench 6. In one example, the sidewall trough connection layers 12 can alternatively be arranged on both sidewalls of the gate trench, as can be seen in a MOSFET 100B with a trench gate shown in Fig. 20. In such a configuration, the channel surfaces on both side walls of the gate trench 6 are equal in area. Furthermore, the balance of flows passing through the channels is improved compared to a configuration where the side wall trough connection layers 12 are located only on one of the side walls of the gate trench 6. In another example, the sidewall trough connection layers 12 can be arranged on both sidewalls of the gate trench 6, as can be seen in a trench-gate MOSFET 100C shown in Fig. 21. Fig. 22 is a cross-sectional view along a line EE, which is indicated by arrows in Fig. 21. Forming the sidewall trough connection layers 12 on both sidewalls of the gate trench 6 in this way doubles the number of sidewall trough connection layers 12. Such a configuration provides a wider current path for charging and discharging at a pn junction formed by the field-reducing region 13 at the trench bottom surface and the drift layer 3 when the MOSFET switches. As a result, switching losses are reduced with greater safety. The channel surfaces on both sidewalls of the gate trench 6 are equal in area. Furthermore, the balance of the flows passing through the channels is improved compared to a configuration where the sidewall trough connection layers 12 are located only on one of the sidewalls of the gate trench 6. It is possible for the sidewall trough connection layers 12 to have the same or different concentrations on both sidewalls of the gate trench 6. It should be noted that the arrangement of the sidewall trough connection layers 12 can assume any structure, unless it impairs the operation of the MOSFET. Third modification Referring to Fig. 2, which shows the configuration of the MOSFET 100 with a trench gate according to the first explanatory example in a top view, the foregoing merely illustrates by way of example that each unit cell 31 in the active region 30 is arranged in the form of a continuous strip in a top view. In one example, the gate trenches 6 can be arranged in the form of a grid, a ladder, or a T in a top view, with the adjacent gate trenches 6 being partially coupled. Furthermore, each gate trench 6 can be partially polygonal or wavy. Fourth modification The first illustrative example describes that the drift layer 3 has a main surface, which is a (0001) plane with an offset angle θ, at which the (0001) plane is inclined in the direction of an [11-20] axis. The main surface of the drift layer 3 can also be a (000-1) plane with an offset angle θ, at which the (000-1) plane is inclined in the direction of the [11-20] axis. With such a configuration, a trench-gate MOSFET is also obtained, achieving a similar effect. It is understood that the surface of the drift layer 3 can also be a (1-100) or (03-38) plane. Fifth modification The first illustrative example describes a configuration in which the sidewall trough connection layer 12 is arranged on the sidewall of each gate trench 6 in a strip shape extending in a direction parallel to an offset direction. The sidewall trough connection layer 12 can also be arranged on the sidewall of each gate trench 6 in a strip shape extending in a direction perpendicular to the offset direction. In such a configuration, the EIN resistance is also reduced without significantly decreasing the channel density. Sixth modification The first illustrative example describes the formation of the sidewall trough connection layers 12 by oblique ion implantation. The field-reducing regions 13 on the trench bottom surfaces can each exhibit a concentration distribution including reflected ions, which are added when the trench sidewall undergoes oblique ion implantation. In other words, the trench sidewall is subjected to oblique ion implantation, so that ions reflected from the trench sidewall are also introduced or injected into the trench bottom surface; consequently, p-type defects are added to the field-reducing region 13 on the trench bottom surface. The amount of ions reflected from the trench sidewall ranges from several percent to 10 percent of the amount of ions introduced or injected into the trench sidewall by oblique ion implantation. Furthermore, the field-reducing zone 13 at the trench bottom surface exhibits a concentration of defects that increases with approach to the sidewall trough connection layer 12. This is because the amount of ions reflected from the trench wall increases with approach to the trench wall. A portion of the defect concentration in the field-reducing region 13 at the trench bottom surface is high, thus providing a sufficient current path for charging and discharging at a pn junction with lower resistance. Consequently, switching losses are reduced. Second illustrative example A trench-gate MOSFET 200 is described below according to a second illustrative example with reference to Figures 23, 24 to 25. Figures 23, 24 to 25 correspond to Figures 2, 3 to 4. Components identical to those shown in Figures 2, 3 to 4 are designated with the same reference numerals and are not described in detail. Figure 24 is a cross-sectional view along a line FF, which is indicated by arrows in Figure 23. Figure 25 is a cross-sectional view along a line GG, which is indicated by arrows in Figure 23. As shown in Fig. 23, the MOSFET 200 with trench gate according to the second explanatory example is configured such that each side wall trough connection layer 12 is arranged to be connected to its adjacent trough contact area 15. In other words, the sidewall trough connection layer 12, which is arranged in contact with a lateral surface of the field-reducing area 13 on the trench bottom surface and an area of ​​a sidewall of the gate trench 6, is also arranged in contact with the trough area 4 and the trough contact area 15, as shown in Fig. 24. The sidewall trough connection layer 12, which is in low-resistance contact with the trough contact area 15, reduces the resistance of a current path through which a displacement current flows from a pn junction formed by the field-reducing area 13 on the trench bottom surface and the drift layer 3 when the MOSFET switches, compared to the sidewall trough connection layer 12 that is only in contact with the trough area 4. This allows the MOSFET to switch faster and achieve lower switching losses. The first illustrative example describes that the trough area 4 is formed such that it has a defect concentration of 1 x 1016cm-3 or a higher defect concentration and of 3 x 1019cm-3 or a lower defect concentration, and that the side wall trough connecting layer 12 is formed such that it has a defect concentration of 5 x 1016cm-3 or a higher defect concentration and of 1 x 1020cm-3 or a lower defect concentration. The sidewall trough connection layer 12 is formed such that it has a defect concentration that, within the aforementioned range of defect concentration (e.g., a range of 1 x 10¹⁷ cm⁻³ or higher and 5 x 10¹⁹ cm⁻³ or lower), is higher than that of the trough area 4. Accordingly, the sidewall trough connection layer 12 can be considered to be in contact with the trough contact area 15. First modification The side wall recess connection layers 12 do not necessarily have to be connected to a single recess contact area 15. The side wall recess connection layers 12 can each be connected to a plurality of recess contact areas 15. In other words, each sidewall trough connection layer 12 can be arranged to extend from one of two trough contact areas 15, which are adjacent to each other in a direction in which the gate trench 6 extends, to the other, and can be connected to these two trough contact areas 15, as can be seen in a trench-gate MOSFET 200A shown in Fig. 26. An increase in the number of trough contact areas 15 to be connected is equivalent to an increase in the current path for a displacement current flowing from a pn junction formed by the field-reducing area 13 at the trench bottom surface and the drift layer 3. As a result, the resistance of the path is reduced, thus further reducing switching losses. Second modification The sidewall trough connection layers 12 can each have a bilayer structure. In other words, each sidewall trough connection layer 12 has a bilayer structure consisting of a first p-type sidewall trough layer 12a (i.e., a first connection layer) and a second p-type sidewall trough layer 12b (i.e., a second connection layer), as can be seen in a trench-gate MOSFET 200B shown in Fig. 27. The first sidewall trough layer 12a is in contact with the gate trench 6 and has a high impurity concentration. The second sidewall recess layer 12b is located outside the first sidewall recess layer 12a and has a lower concentration of defects than the first sidewall recess layer 12a. A region of the first sidewall recess layer 12a is in contact with the source region 5. Furthermore, a region of the second sidewall recess layer 12b is in contact with the recess contact region 15. As described above, the first sidewall well layer 12a of the sidewall well interconnect layer 12 exhibits a high impurity concentration. This provides a current path for charging and discharging at a pn junction with lower resistance, thereby reducing switching losses. Furthermore, the second sidewall well layer 12b exhibits a lower impurity concentration. This reduces the electric field present at a pn junction between the sidewall well interconnect layer 12 and the drift layer 3 when the MOSFET is off. Consequently, the avalanche breakdown voltage is improved. The defect concentrations of the first sidewall trough layer 12a and the second sidewall trough layer 12b are specified individually to satisfy the aforementioned relationship regarding the defect concentration between these layers within a range of 5 x 1016cm-3 or higher and 1 x 1020cm-3 or lower, or more desirablely within a range of 1 x 1017cm-3 or higher and 5 x 1019cm-3 or lower. The first lateral wall well layer 12a and the second lateral wall well layer 12b can be formed by oblique ion implantation by varying the dose and injection energy of the p-type defects. In other words, introducing or injecting the p-type defects by oblique ion implantation with a high injection energy and a low dose can form the second lateral wall well layer 12b; furthermore, introducing or injecting the p-type defects by oblique ion implantation with a low injection energy and a high dose can form the first lateral wall well layer 12a. Third modification The sidewall recess connection layer 12 with a double-layer structure is not limited to a structure consisting of two layers with the same conductivity type, as shown in Fig. 27. The sidewall recess connection layer 12 can have a structure consisting of two layers with different conductivity types. In other words, the sidewall recess connection layer 12 has a double-layer structure consisting of a first sidewall recess layer 12c of the n type (i.e., a first connection layer) and a second sidewall recess layer 12d of the p type (i.e., a second connection layer), as shown in Fig. 28. The first sidewall trough layer 12c is in contact with the gate trench 6 and exhibits a high concentration of defects. The second sidewall trough layer 12d is located outside the first sidewall trough layer 12c and exhibits a lower concentration of defects than the first sidewall trough layer 12c. A region of the first sidewall trough layer 12c is in contact with the source region 5. Furthermore, a region of the second sidewall trough layer 12d is in contact with the source region 5 and the trough contact region 15. As described above, the first sidewall trough layer 12c of the sidewall trough connection layer 12 exhibits a high concentration of defects. This provides a current path for charging and discharging at a pn junction with lower resistance. The defect concentration of the first sidewall trough layer 12c and the second sidewall trough layer 12d are specified individually to satisfy the aforementioned relationship regarding the defect concentration between these layers within a range of 5 x 1016cm-3 or higher and 1 x 1020cm-3 or lower, or more desirablely within a range of 1 x 1017cm-3 or higher and 5 x 1019cm-3 or lower. The first sidewall trough layer 12c and the second sidewall trough layer 12d are formed in the following manner: introduction or injection of p-type impurity ions by oblique ion implantation to form the second sidewall trough layer 12d in the entire sidewall trough connection layer 12, followed by introduction or injection of n-type impurity ions by oblique ion implantation at a higher dose than that of the p-type impurity ions to form the first sidewall trough layer 12c. The first lateral wall trough layer 12c is formed by oblique ion implantation with an oblique injection angle that is smaller than that used for the formation of the second lateral wall trough layer 12d, so that it is formed from a trench side wall at a very shallow depth. Accordingly, the inclined first lateral wall trough layer 12c is also formed in the upper layer of the field-reducing area 13 at the trench bottom surface. Third illustrative example A trench-gate MOSFET 300 is described below according to a third illustrative example with reference to Figures 29 and 30. Figures 29 and 30 correspond to Figures 23 and 25. Components identical to those shown in Figures 23 and 25 are designated by the same reference numerals and are not described in detail. Figure 30 is a cross-sectional view along a line HH, which is indicated by arrows in Figure 29. As shown in Fig. 29, the MOSFET 300 with trench gate according to the third explanatory example is configured such that the opening of each source contact 16 has a stem shape (i.e. a rectangular shape) in a plan view, arranged to have two trough contact areas 15 in a plan view, adjacent to each other in a direction in which the gate trenches 6 extend. As shown in Fig. 30, the trench-gate MOSFET 300 has a region without the source contact 16. The area ratio of this region within the active region 30 must be specified such that the region does not impair the operation of the MOSFET. The openings of the source contacts 16 can have any shape in a top view, as long as this condition is met. The openings can be circles with a uniform diameter, rectangles with a uniform width, or other shapes. Fourth illustrative example A trench-gate MOSFET 400 is described below according to a fourth illustrative example with reference to Figures 31, 32 to 33. Figures 31, 32 to 33 correspond to Figures 23, 24 to 25. Components identical to those shown in Figures 23, 24 to 25 are designated with the same reference numerals and are not described in detail. Figure 32 is a cross-sectional view along line II, which is indicated by arrows in Figure 31. Figure 33 is a cross-sectional view along line JJ, which is indicated by arrows in Figure 31. As shown in Fig. 32, the trench-gate MOSFET 400, according to the fourth explanatory example, is configured such that some of the gate trenches 6 lack the gate insulating layer 7 and the gate electrode 8, and their inner wall surfaces are covered with Schottky electrodes 18. Such a gate trench 6, lacking the gate insulating layer 7 and the gate electrode 8 and having an inner wall surface covered with a Schottky electrode 18, is referred to as a second gate trench. Furthermore, the gate trench 6, which includes the gate insulating layer 7 and the gate electrode 8, is referred to as a first gate trench. As shown in Fig. 32, the Schottky electrode 18 is in contact with the field-reducing area 13 on the trench bottom surface at the bottom of the gate trench 6. The field-reducing area 13 on the trench bottom surface is connected to the source contact 16 via the side wall trough connection layer 12. The gate trench 6 (i.e., the second gate trench), whose inner wall surface is covered with the Schottky electrode 18, is located at the bottom of the source contact 16 and has the source electrode 10 embedded in a region surrounded by the Schottky electrode 18. The Schottky electrode 18 can be deposited by sputtering a material such as Ti, Mo, or Ni. When a high current (e.g., a recovery current flowing during a recovery process) flows through a pn diode formed by the trough region 4 and the field-reducing region 13 on the trench bottom surface and through the drift layer 3, causing a silicon carbide MOSFET to operate as a bipolar transistor, crystal defects in the drift layer 3 expand and may degrade the operating characteristics of the silicon carbide MOSFET. The MOSFET 400 with trench gate allows a recovery current to flow as a unipolar current through the Schottky electrode 18 without switching on a pn diode. This recovery current is formed by the trough region 4 and the field-reducing region 13 at the trench bottom surface and by the drift layer 3. In other words, a reverse current flows from the source electrode 10 towards the drain electrode 11 when a low voltage is applied to the drain electrode 11 with respect to the source electrode 10, that is, when an electromotive reverse voltage is applied to the MOSFET. In this state, a forward-biased electric field (i.e., a forward voltage) is applied to a Schottky junction formed at the contact between the field-reducing region 13 on the trench bottom surface and the Schottky electrode 18. This allows a unipolar current, which is an electric current, to flow as a recovery current from the Schottky electrode 18 towards the field-reducing region 13 on the trench bottom surface. This prevents the propagation of crystal defects and the deterioration of the operating characteristics. When a high voltage is applied to the drain electrode 11 with respect to the source electrode 10, and when a positive voltage not less than a threshold value is applied to the gate electrode 8, the MOSFET is in the ON state. In the ON state, an inverting channel is formed in a channel region, and a path for electrons or charge carriers that are to flow is also formed in the channel region. In contrast, no current flows through the Schottky junction at the contact between the Schottky electrode 18 and the field-reducing region 13 on the trench bottom surface, because an electric field in a direction in which current is less likely to flow, i.e., a reverse-biased electric field (i.e., a reverse voltage), is present at the Schottky junction. Such a Schottky barrier diode, formed by the Schottky electrode 18 and the field-reducing region 13 on the trench bottom surface, functions as a recovery diode (i.e., as a freewheeling diode). The field-reducing area 13 on the trench bottom surface beneath the bottom surface of the gate trench 6, which is equipped with the Schottky electrode 18, reduces the electric field present at the Schottky electrode 18 when the MOSFET is off. Furthermore, the field-reducing area 13 on the trench bottom surface, which is electrically connected to the trench area 4 via the sidewall trough connection layer 12, provides a current path for charging and discharging at a pn junction formed by the field-reducing area 13 on the trench bottom surface and the drift layer 3 during switching operations. This enables a rapid response of a depletion layer formed at the pn junction during switching operations, thereby reducing switching losses. The sidewall trough connection layer 12, which is only located on a portion of the trench sidewall, allows the Schottky electrode, acting as a Schottky barrier diode, to maintain sufficient density while preserving the density of a channel acting as a MOSFET. This reduces the recovery current that would otherwise flow through a single Schottky electrode 18 during a recovery operation, such as switching a high current. Consequently, degradation of the MOSFET is prevented. modification In this illustrative example, the current distribution areas 19 can be of the n type, each adjacent to the side wall trough connection layer 12 and the field-reducing area 13 on the trench bottom surface, and arranged such that they at least cover the field-reducing area 13 on the trench bottom surface, as described above with reference to Fig. 16, Fig. 17 to Fig. 18. Arranging the current distribution areas 19 further reduces the ON resistance and also reduces losses caused by recovery currents flowing through the Schottky electrodes 18. Fifth illustrative example A trench-gate MOSFET 500 is described below according to a fifth illustrative example with reference to Fig. 34. Fig. 34 corresponds to Fig. 24. Components identical to those shown in Fig. 24 are designated with the same reference numerals and are not described further. Fig. 34 is a cross-sectional view along line FF, which is indicated by arrows in Fig. 23. As shown in Fig. 34, the trench-gate MOSFET 500 according to the fifth explanatory example has the sidewall trough connection layers 12 and the field-reducing areas 13 on the trench bottom surfaces, each of which is located deep in the drift layer 3 and extends to the vicinity of one of the main surfaces of the silicon carbide semiconductor substrate 1. Each sidewall trough junction layer 12 and each field-reducing area 13 on the trench floor surface forms a p-type support (i.e., a support with the second conductivity type), and the drift layer 3 between the adjacent p-type supports forms an n-type support (i.e., a support with the first conductivity type), so that a super-junction structure is formed. The arrangement of such a p-type support extending deep into the drift layer 3 and formed by the sidewall trough junction layer 12 and the field-reducing area 13 at the trench bottom surface to form a super-junction structure allows the drift layer 3 to have a high fault concentration and reduces the EIN resistance. In other words, the n-type drift layer 3 provides a depletion layer extending from the surface of a pn junction between the p-type support layer and the n-type support layer, in addition to a depletion layer extending from the surface of a pn junction or the surface of a metal junction located on the surface of the trench-gate MOSFET 500. In short, drift layer 3 exhibits a depletion layer that is as deep as the support layers. Even if the defect concentration of the n-type support layer, i.e., the defect concentration of drift layer 3, is set high, it is consequently brought into equilibrium with the defect concentration of the p-type support layer, so that the n-type support layer is completely depleted in order to maintain the breakdown voltage. As a result, the compromise relationship between the breakdown voltage and the ON resistance of the trench-gate MOSFET 500 is significantly improved, and the drift resistance is reduced. This, in turn, reduces the ON resistance. Other applicable examples The first to fifth illustrative examples describe by way of example how the present invention is applied to a MOSFET. The present invention can also be applied to any other device. For example, the present invention can be applied to an IGBT obtained by removing the silicon carbide semiconductor substrate 1 and instead introducing or injecting p-type impurities into the back surface of the drift layer 3 to form a p-type impurity layer (i.e., a third semiconductor layer). Alternatively, the present invention can be applied to an IGBT obtained by using a p-type substrate as the silicon carbide semiconductor substrate 1. Such IGBTs achieve effects similar to those achieved by a MOSFET. In this case, the source region 5 corresponds to an emitter region of the IGBT, and the drain electrode 11 corresponds to a collector electrode of the IGBT. Although the first five illustrative examples describe a semiconductor unit made of silicon carbide, other semiconductor materials besides silicon carbide can also be used. Examples of such semiconductor materials include silicon (Si) and other materials with a larger band gap than silicon carbide. Examples of materials with a large band gap other than silicon carbide are Ga2O3, gallium nitride (GaN) and diamond. A semiconductor device made of a material with a large bandgap, such as silicon carbide, is a promising semiconductor device for high temperatures and high voltages. Since the reliability of an insulating layer deteriorates at high temperatures, the implementation of the aforementioned measures has a significant impact. Furthermore, since improving the breakdown voltage increases the voltage across the insulating layer, the implementation of these measures is even more effective. It is known that a silicon carbide semiconductor unit exhibits more electron traps generated at a MOS junction between the gate insulating layer 7 and the drift layer 3 (i.e., the silicon carbide layer) than a silicon semiconductor unit. In such a silicon carbide semiconductor unit, the reliability of the MOS junction and the gate insulating layer 7 is lower than in a silicon semiconductor unit. Therefore, a significant effect is achieved by implementing the preceding examples, where an electric field applied to the gate insulating layer 7 is successfully reduced. Sixth illustrative example In the sixth illustrative example, a power converter is described that incorporates the semiconductor unit according to one of the first five illustrative examples. The semiconductor unit according to one of the first five illustrative examples is not only contained in a specific power converter, but also in any power converter. The sixth illustrative example describes an example in which the semiconductor unit is contained in a three-phase inverter. Fig. 35 is a block diagram showing the configuration of a power conversion system that includes the power converter according to the sixth explanatory example. The power conversion system in Fig. 35 comprises a power supply 800, a power converter 600, and a load 700. The power supply 800 is a DC power supply and provides a DC current to the power converter 600. The power supply 800 can be composed of various components (e.g., a DC system, a photovoltaic cell, or a storage battery) and can consist of a rectifier circuit or an AC / DC converter connected to an AC system. Alternatively, the power supply 800 can consist of a DC / DC converter that converts a DC current supplied by a DC system into a predetermined current level. The power converter 600 is a three-phase inverter connected between the power supply 800 and the load 700. It converts direct current supplied by the power supply 800 into alternating current and supplies the alternating current to the load 700. The power converter 600 comprises the following circuits: a main converter circuit 601, which converts direct current into alternating current and supplies the alternating current; a driver circuit 602, which outputs a driver signal to drive each switching element of the main converter circuit 601; and a control circuit 603, which outputs a control signal to the driver circuit 602 to control the driver circuit 602. The Last 700 is a three-phase motor driven by alternating current supplied by the power converter 600. It should be noted that the Last 700 is not limited to a specific application; it is a motor that can be mounted on various electrical devices and is used, for example, in hybrid vehicles, electric vehicles, rail vehicles, elevators, or air conditioning systems. The power converter 600 is described in detail below. The main converter circuit 601 has switching elements and freewheeling diodes (not shown). The switching elements are switched to convert the direct current supplied by the power supply 800 into alternating current and to deliver the alternating current to the load 700. Although the specific configuration of the main converter circuit 601 can take various forms, according to the sixth illustrative example, the main converter circuit 601 is a two-stage, three-phase full-bridge circuit, which can be formed from six switching elements and six freewheeling diodes connected antiparallel to the respective switching elements. The semiconductor unit according to any one of the first to fifth examples is used for each switching element of the main converter circuit 601. The six switching elements are configured such that each pair of two switching elements connected in series forms a set of an upper and a lower branch, and that the sets of upper and lower branches form the respective phases (i.e., U, V, and W phases) of the full bridge circuit. Furthermore, the output terminals of each set of upper and lower branches, that is, three output terminals of the main converter circuit 601, are connected to the load 700. The driver circuit 602 generates a driver signal to drive the switching elements of the main converter circuit 601 and supplies the driver signal to the control electrodes of the switching elements of the main converter circuit 601. Specifically, in response to a control signal from the control circuit 603, which will be described later, the driver circuit 602 outputs a driver signal to switch the switching elements on and a driver signal to switch the switching elements off to the control electrodes of the individual switching elements. To keep the switching elements in the ON state, the driver signal is a voltage signal that is higher than or equal to a threshold voltage (this driver signal is referred to as an ON signal). To keep the switching elements in the OFF state, the driver signal is a voltage signal that is lower than a threshold voltage (this driver signal is referred to as an OFF signal). The control circuit 603 controls the switching elements of the main converter circuit 601 so that a desired current level is supplied to the load 700. Specifically, based on a current level to be supplied to the load 700, the control circuit 603 calculates a time during which each switching element of the main converter circuit 601 should be in the ON state. The control circuit 603 can control the main converter circuit 601, for example, by means of PWM control, which is a method in which the ON time of the switching elements is modulated according to a voltage to be output. The control circuit 603 then outputs a control instruction (i.e., a control signal) to the driver circuit 602 such that an ON signal is output to the switching elements to be switched on each time, and an OFF signal is output to the switching elements to be switched off each time. In response to the control signal, the driver circuit 602 outputs the ON signal or the OFF signal as a driver signal to the control electrode of each switching element. The power converter according to the sixth explanatory example incorporates the semiconductor unit according to any one of the first through fifth explanatory examples as switching elements of the main converter circuit 601. The power converter thus successfully reduces electric fields present at the bottom surfaces of the gate trenches when the switching elements are in the OFF state. Furthermore, the field-reducing region 13 at the trench bottom surface and the trough region 4 are electrically connected by the sidewall trough connection layer 12. This provides a current path for charging and discharging at a pn junction formed by the field-reducing region 13 at the trench bottom surface and the drift layer 3. Consequently, switching losses are reduced. Although the sixth explanatory example describes a two-stage three-phase inverter, it can be applied to various power converters. Similarly, it can be used for three-stage or multi-stage power converters. To supply current to a single-phase load, the sixth illustrative example can alternatively be used with a single-phase inverter. To supply current to a DC load or similar, the sixth illustrative example can also be used with a DC / DC converter or an AC / DC converter. The aforementioned load is not limited to a motor and can be used as a power supply unit for a discharge device, a laser device, an induction cooktop device, or a contactless power supply system. The aforementioned load can also be used as an energy processor for a solar power system, a battery storage system, or other systems.

Claims

Semiconductor unit comprising: - a first semiconductor layer (3) with a first conductivity type; - a first semiconductor region (5) with the first conductivity type, selectively arranged in an upper layer of the first semiconductor layer (3); - a second semiconductor region (15) with a second conductivity type, arranged in the upper layer of the first semiconductor layer (3) such that it is in contact with the first semiconductor region (5); - a third semiconductor region (4) with the second conductivity type, arranged on lower surfaces of the first and second semiconductor regions (5, 15); - a plurality of gate trenches (6) arranged to penetrate the first and third semiconductor regions (5, 4) in the thickness direction of the first and third semiconductor regions (5, 4), the plurality of gate trenches (6) each having a bottom surface.extending into the interior of the first semiconductor layer (3), wherein the plurality of gate trenches (6) have a strip-like form and extend in one direction in a top view; - a field-reducing region (13) of the second conductivity type, arranged at the bottom surface of each of the plurality of gate trenches (6); - an intermediate insulating layer (9) having contact openings (16) over the first and second semiconductor regions (5, 15); - a plurality of interconnection layers (12, 12c, 12d) arranged in the first semiconductor layer (3) at intervals such that each is in contact with at least one of the side walls of a corresponding plurality of gate trenches (6) in a second direction perpendicular to a first direction parallel to a direction in which the plurality of gate trenches (6) extend,wherein the distances between the plurality of spaced interconnect layers (12, 12c, 12d) in the first direction are such that they are as large as or larger than a distance at which the plurality of gate trenches (6) are arranged, wherein the plurality of interconnect layers (12, 12c, 12d) each electrically connect the field-reducing region (13) to the third semiconductor region (4); a first main electrode (10) arranged above the intermediate insulating layer (9) and inserted into the contact openings; and a second main electrode (11) arranged on a main surface of the first semiconductor layer (3), the main surface being opposite that on which the first main electrode (10) is arranged, wherein the first direction is parallel to an offset direction, wherein the plurality of interconnect layers (12, 12c,12d) is spaced apart from each other in the first direction and each of the plurality of interconnect layers (12, 12c, 12d) is connected to the first semiconductor region (5),- wherein the first semiconductor layer (3) has a silicon carbide layer,- wherein the first semiconductor layer (3) has an offset angle of more than 0 degrees in a <11-20> direction, and- wherein the plurality of gate trenches (6) each have a sidewall surface having a (1-100) plane or a (-1100) plane,- wherein the plurality of interconnect layers (12, 12c, 12d) each have:- a first interconnect layer (12c) arranged to be in contact with the corresponding of the plurality of gate trenches (6), and- a second interconnect layer (12d) located further away from the corresponding of the plurality of gate trenches (6) than the first interconnect layer (12c),- wherein the first compound layer (12c) consists of the first conductivity type and- wherein the second compound layer (12d) consists of the second conductivity type. Semiconductor unit according to claim 1, wherein each of the plurality of interconnect layers (12, 12c, 12d) is arranged such that it extends in the second direction from the side wall of the corresponding plurality of gate grooves (6), and wherein the plurality of interconnect layers (12, 12c, 12d) is shorter in the second direction than the length between the plurality of adjacent gate grooves (6). Semiconductor unit according to one of claims 1 to 2, wherein the first interconnect layer (12c) has an impurity concentration that is higher than the impurity concentration of the second interconnect layer (12d). Semiconductor unit according to one of claims 1 to 3, wherein the plurality of interconnect layers (12, 12c, 12d) each have an impurity concentration of 1 x 1017cm-3 or a higher impurity concentration and of 5 x 1019cm-3 or a lower impurity concentration. Semiconductor unit according to one of claims 1 to 4, wherein the plurality of interconnect layers (12, 12c, 12d) in the thickness direction of the first semiconductor layer (3) each have a length of 0.3 µm or more. Semiconductor unit according to one of claims 1 to 5, wherein each of the plurality of interconnect layers (12, 12c, 12d) is arranged such that it has a length in the thickness direction of the first semiconductor layer (3) such that this length decreases with the distance in the second direction from the side wall of the corresponding plurality of gate grooves (6). Semiconductor unit according to one of claims 1 to 6, wherein the plurality of interconnect layers (12, 12c, 12d) is arranged only on one of the side walls of the corresponding plurality of gate grooves (6) in the second direction. Semiconductor unit according to one of claims 1 to 6, wherein the plurality of interconnect layers (12, 12c, 12d) are arranged alternately on one of the side walls and the other side wall of the corresponding plurality of gate grooves (6) in the second direction. Semiconductor unit according to one of claims 1 to 8, wherein the plurality of interconnect layers (12, 12c, 12d) are arranged such that they are in contact with the third semiconductor area (4) and the second semiconductor area (15). Semiconductor unit according to one of claims 1 to 9, further comprising: - a current distribution area (19) with the first conductivity type, which is arranged in the first semiconductor layer (3), wherein the current distribution area (19) is in contact with each of the plurality of interconnect layers (12, 12c, 12d) and the field-reducing area (13), - wherein the current distribution area (19) is arranged such that it has an impurity concentration which is higher than that of the first semiconductor layer (3). Semiconductor unit according to one of claims 1 to 10, which further comprises a second semiconductor layer (14) of the first conductivity type, which is arranged on a lower surface of the third semiconductor region (4). Semiconductor unit according to one of claims 1 to 11,- wherein the plurality of gate grooves (6) comprises:- a first gate groove having an inner wall surface covered with a gate insulating layer (7), wherein a gate electrode (8) is inserted into the first gate groove, and- a second gate groove having an inner wall surface covered with a Schottky electrode (18), wherein the first main electrode (10) is inserted into the second gate groove, and- wherein the first gate groove has an upper region covered with the intermediate insulating layer (9). Semiconductor unit according to one of claims 1 to 12, which further comprises a third semiconductor layer with the second conductivity type, arranged between the second main electrode (11) and the first semiconductor layer (3). Semiconductor unit according to one of claims 1 to 13, wherein the contact openings have a uniform length in at least the second direction in an active area (30) in which the plurality of gate grooves (6) are arranged. Power converter comprising: - a main converter circuit (601) comprising a semiconductor unit according to any one of claims 1 to 14, wherein the main converter circuit (601) is configured to convert received power and then output it; - a driver circuit (602) configured to output a driver signal to the semiconductor unit for driving the semiconductor unit; and - a control circuit (603) configured to output a control signal to the driver circuit (602) for controlling the driver circuit (602).

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