AUTONOMOUS PROCESSING UNIT OF A MICROCONTROLLER AND RELATED SYSTEMS, METHOD AND DEVICES

Abstract

Microcontroller system, including: a central processing unit of a microcontroller configured to execute a first control loop at the central processing unit while a second control loop is executed, wherein the second control loop can be executed at least partially without interrupting the first control loop; one or more input / output (I / O) ports configured to receive an input signal; an autonomously adjustable analog-to-digital converter (ADC) configured to: to amplify the input signal in response to a desired number of resolution bits; to observe a signal level of the amplified input signal; to adjust a gain parameter in response to the observed signal level in order to keep the amplified signal within a predefined dynamic range of the autonomously adjustable ADC; to sample the amplified input signal with the desired number of resolution bits; to provide a digital output signal in response to the amplified signal, and a computing unit configured to provide one or more computational results in response to the digital output signal.

Description

PRIORITY CLAIM

[0001] This application claims priority over U.S. patent application number 16 / 144,700, filed on September 27, 2018, pending, which is a partial continuation under 35 USC § 120 of U.S. patent application number 15 / 901,420, filed on February 21, 2018, pending, which claims the benefit under 35 USC § 119(e) of the preliminary U.S. patent application number 62 / 599,460, filed on December 15, 2017. TECHNICAL AREA

[0002] The embodiments of the present disclosure relate generally to signal processing and more specifically to analog-to-digital converters (ADCs), including ADCs used in applications requiring a large dynamic signal range. STATE OF THE ART

[0003] Many embedded digital applications read analog inputs and therefore need to convert these inputs into digital results. An analog-to-digital converter (ADC) accepts an analog input signal (usually a voltage or current), samples it, and converts each sample into a digital value that can be read by, for example, a microcontroller, microprocessor, digital circuit, etc. Generally, the measurable output of an ADC is its (Vin / Vref)x resolution. Resolution is a characteristic of an ADC and can be expressed as the quantum of analog input voltage change required to increase the digital output of an ADC from one value to the next higher code value. For example, the resolution of an 8-bit ADC can be expressed as a fraction of 255, or as 0.4% of the full-scale value, or simply as 8-bit resolution.If such an ADC has a full analog input signal range of 10 V, it can resolve a change in the input signal of 40 mV. The step size is the voltage difference between one digital stage (i.e., 0001) and the next (i.e., 0010 or 0000). For example, if an ADC has a step size of 40 mV, an input of 40 mV in an 8-bit converter will produce an output of 0000 0001.

[0004] Thus, to accurately measure and convert small signal changes, conventional ADCs use a higher resolution (i.e., the ability to resolve a small mV change in the input), while still being able to accurately measure and convert large signal changes (i.e., the ability to resolve a larger mV change in the input). For a conventional ADC expected to measure a large dynamic range, measurements are relatively coarse when measuring small analog signals (i.e., the relative step size between each digital code is large), while measurements are relatively fine when measuring large analog signals (i.e., the relative step size between each digital code is relatively small).

[0005] Many embedded applications for reading an analog input signal require a large dynamic range and accurate measurements, meaning the ability to measure from a low voltage (e.g., ground voltage) to a high voltage (e.g., up to the system supply voltage) while maintaining accuracy. For this reason, many applications require increasing ADC resolution. Traditional embedded applications therefore typically use a high-resolution ADC, e.g., 12-bit, 14-bit, or higher, or an internal programmable gain stage for the ADC so that small signals can be amplified, as in Fig. 1 shown.

[0006] US 9 473 161 B1 discloses a combination of a precise analog-to-digital converter (ADC), an analog amplifier with selectable gain factors, and an intelligent controller that work together to coordinate the selection of gain and the placement of the digital conversion results in at least one register.

[0007] EP 1 305 882 B1 discloses an amplifier with programmable gain for use in a data network. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The purpose and advantages of the embodiments of the disclosure will be apparent to those skilled in the art from the summary in conjunction with the detailed description and the accompanying drawings: Fig. Figure 1 shows a state-of-the-art ADC with an internal gain stage. Fig. Figure 2 shows functional blocks of an ADC with autonomous gain stage and gain setting, as well as automatic scaling, according to an embodiment of the disclosure. Fig. 3A shows an autonomous gain adjustment method according to an embodiment of the disclosure. Fig. Figure 3B shows a method for determining gain settings according to one or more embodiments of the disclosure. Fig. Figure 4 shows an implementation of an ADC circuit with autonomous analog gain stage and automatic digital result scaling according to an embodiment of the disclosure. Fig. Figure 5 shows an exemplary method for monitoring a battery, which includes an ADC circuit with autonomous analog gain stage and automatic digital result scaling according to an embodiment of the disclosure. Fig. Figure 6 shows an analog signal of the system from Fig. 5. Fig. 7A and Fig. Figure 7B shows examples of a gain adjustment procedure according to one embodiment of the disclosure. Fig. Figure 8 shows a functional block diagram of an autonomous processing unit according to one or more embodiments of the disclosure. Fig. Figure 9 shows a functional block diagram of an autonomous battery monitoring and control system according to one or more embodiments of the disclosure. Fig. Figure 10 shows a flowchart of a control procedure according to one or more embodiments of the disclosure. Fig. Figure 11 shows a functional block diagram of a microcontroller according to one or more embodiments of the disclosure. TYPE(S) OF IMPLEMENTATION OF THE INVENTION

[0009] The following detailed description refers to the accompanying drawings, which form part thereof and show, for illustrative purposes, specific examples of embodiments in which the present disclosure can be carried out. These embodiments are described in sufficient detail to enable a person skilled in the art to carry out the present disclosure. However, other embodiments may also be used, and changes to the structure, material, and process may be made without departing from the scope of the disclosure. The illustrations shown herein are not intended to be actual views of any particular method or system, or of any particular device or structure, but are merely idealized representations used to describe the embodiments of the present disclosure.The drawings shown herein are not necessarily to scale. Similar structures or components in the various drawings may retain the same or similar numbering for the convenience of the reader; however, the similarity in numbering does not imply that the structures or components are necessarily identical in size, composition, configuration, or any other property.

[0010] The following description may include examples to enable a person skilled in the art to carry out the disclosed embodiments. The use of the terms "by way of example", "as an example", or "for instance" means that the accompanying description is explanatory, and while the scope of protection of the disclosure is intended to include the examples and their legal equivalents, the use of such terms is not intended to limit the scope of protection of any embodiment or of this disclosure to the specified components, steps, features, functions, or the like.

[0011] It is self-evident that the components of the embodiments, as generally described herein and illustrated in the drawing, can be arranged and designed in a multitude of different configurations. Therefore, the following description of various embodiments is not intended to limit the scope of this disclosure, but merely to be representative of different embodiments. While the various aspects of the embodiments may be illustrated in drawings, the drawings are not necessarily drawn to scale unless expressly stated otherwise.

[0012] Furthermore, the specific implementations shown and described are only examples and should not be interpreted as the only way to implement the present disclosure unless otherwise stated herein. Elements, circuits, and functions may be shown in block diagram form to avoid obscuring the present disclosure with unnecessary details. Conversely, the specific implementations shown and described are only examples and should not be interpreted as the only way to implement the present disclosure unless otherwise stated herein. Additionally, block definitions and the partitioning of logic between different blocks are examples of a specific implementation. It is readily apparent to those skilled in the art that the present disclosure can be implemented by numerous other partitioning solutions.Details regarding timing considerations and the like have been largely omitted where such details are not necessary to obtain a complete understanding of the present disclosure and are within the capabilities of average professionals in the relevant field.

[0013] Average persons will understand that information and signals can be represented using a wide variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced in this description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may illustrate signals as a single signal for the clarity of representation and description. It is apparent to an average person that the signal can represent a bus of signals, the bus being of a variety of bit widths, and the present disclosure can be implemented using any number of data signals, including a single data signal.

[0014] The various illustrative logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or carried out using a general-purpose processor, a specialized processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a free form factor gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. A general-purpose processor (which may also be referred to herein as the host processor or simply the host) may be a microprocessor; alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine.A processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a specialized computer, while the general-purpose computer is configured to execute computing instructions (e.g., software code) relating to embodiments of the present disclosure.

[0015] The embodiments can be described in terms of a process represented as a flowchart, flow diagram, structure diagram, or block diagram. Although a flowchart can describe operational processes as a sequential process, many of these processes can be performed in a different order, in parallel, or substantially simultaneously. Furthermore, the sequence of operations can be rearranged. A process can correspond to a method, thread, function, procedure, subroutine, subprogram, etc. Furthermore, the methods disclosed herein can be implemented in hardware, software, or both. When implemented in software, the functions can be stored or transmitted as one or more instructions or code on computer-readable media.Computer-readable media include both computer storage media and communication media, including all media that facilitate the transfer of a computer program from one place to another.

[0016] Any reference to an element herein using a label such as "first," "second," etc., does not restrict the set or order of those elements unless such restriction is expressly stated. Rather, these labels herein may be used as a convenient method for distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements may be placed there, or that the first element must in any way precede the second element. Furthermore, unless otherwise stated, a set of elements may comprise one or more elements.

[0017] As used herein, the term "essentially" means, with respect to a given parameter, property, or condition, and includes, to an extent understandable to those skilled in the art, that the given parameter, property, or condition is satisfied within a small degree of variance, such as within acceptable manufacturing tolerances. For example, depending on the specific parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be satisfied to at least 90%, at least 95%, or even at least 99%.

[0018] As used herein, the terms “automated,” “autonomous,” or “automatic,” when used to describe a gain stage or scaling (e.g., “autonomous gain stage” or “automatic scaling”), mean that the adjustment of the gain stage or scaling occurs without the monitoring of a host processor. Accordingly, an ADC that incorporates an “autonomous gain stage” or “automatic scaling” can, for example, be a core-independent peripheral device.

[0019] As used herein, the term "gain" is generally used to refer to the amplification or reduction of an input signal in order to produce a larger or smaller output signal, respectively, that is proportional to the input signal. Thus, in the case of reduction, the gain can be considered "fractional gain," where the output signal may be smaller than the input signal. Furthermore, in cases where the gain is one, the output signal may be identical to the input signal.

[0020] High-resolution ADCs are expensive, so it's desirable to use gain adjustment on an input signal to allow a lower-resolution ADC to be used for conversion. One way to implement gain adjustment is via software control (e.g., using a microcontroller module). However, the originators of this approach now know that software-controlled gain adjustment can introduce delays and interfere with sampling at a normal, desired frequency. Thus, implementing gain adjustment in software may not be practical for applications requiring a high sampling rate. Addressing these drawbacks increases complexity and leads to further trade-offs in terms of delay and processing power. For example, tracking the gain for each sample in software so it can be reduced later significantly increases memory requirements.

[0021] Furthermore, automated features that allow independent task execution without monitoring by a CPU or other host are limited by the software. Any application that integrates an ADC with a software-controlled gain stage cannot be operated as a core-independent peripheral.

[0022] Various embodiments of the disclosure generally relate to a system that includes an ADC, autonomous gain adjustment of the analog input signal for the ADC, and automatic scaling of the ADC output. In one embodiment, a control circuit monitors the ADC and configures the gain setting of the analog input signal and the automatic scaling of the ADC output. Such a system does not suffer from the same delay and overhead disadvantages of conventional ADCs with an internal gain stage or techniques that control the gain and scaling in software.

[0023] An ADC and a circuit for autonomously adjusting the gain of the input signal to the ADC and for automatically scaling the ADC result can also be characterized in this disclosure as an “autonomously adjustable ADC” or “autonomously adjustable ADC circuit”.

[0024] Fig. Figure 2 shows a functional block diagram of a system including an ADC 202 with an autonomous analog gain stage (AAGS) 200 and an automatic digital result scaling (ADRS) 204 according to an embodiment of the disclosure.

[0025] The AAGS 200 can be configured to amplify (or reduce) an analog input signal 210 according to a gain setting, and the amplified analog signal can be provided to the ADC 202. The gain of the AAGS 200 can be configurable. In one embodiment, a gain can be selected from a number of gain options, e.g., selecting N, where 2 N = 2 -2 , 2 -1 , 2 0 , 2 1 , 2 2 , 2 3 , 2 4 , 2 5 or 2 6(N is limited only by the maximum available gain). In some embodiments, the gain options can be fractional to produce signal reduction rather than signal amplification.

[0026] The ADRS 204 can be configured to downscale (or upscale) a digital result, including a digital result received from the ADC 202. The ADRS 204 can scale the digital result based on a scaling component, for example, a scaling component associated with a gain applied to the analog signal in an AAGS 200. In one embodiment, the ADRS 204 can scale a digital result proportionally to the gain applied to the analog input signal. If no gain is applied, then the result is naturally not downscaled in response to any gain. In one embodiment (and most applications), the digital result is scaled to the assumed function of the ADC 202 (e.g., as provided in the ADC specification), although a different scaling factor may be used in some applications.In one embodiment, the scaling component can be selected from a number of scaling options, e.g., selection of -N, where, 2. -N = 2 2 , 2 1 , 2 0 , 2 -1 , 2 -2 , 2 -3 , 2 -4 , 2 -5 or 2 -6 (N is limited only by the maximum available scaling). In one embodiment, the scaling component or an indicator displaying the scaling components is provided to the ADRS 204.

[0027] The gain setting logic 206 can be configured to monitor a signal level at the input of the ADC 202, to configure the gain of the analog input signal 210, and to configure the scaling of the digital result output by the ADC 202. In various embodiments, the gain setting logic 206 can be configured to monitor the signal level of the analog signal 210 by monitoring the input of the AAGS 200 and / or the output of the signal processing unit 202.

[0028] In various embodiments, the gain setting logic 206 can be an analog or digital circuit. In analog embodiments, the gain setting logic 206 can be, as a non-limiting example, a threshold detection circuit. In digital embodiments, the gain setting logic 206 can be, as a non-limiting example, a configurable state machine coupled to a memory (e.g., flip-flop, register, etc.), an FPGA, or another type of digital circuit. The gain setting logic 206 can be configured to compare the signal levels at the input of the ADC 202 with a gain setting threshold. A gain setting threshold can be based on the dynamic range of an ADC or a subrange within the dynamic range of the ADC.For example, the gain setting threshold can be defined as a sub-range within the dynamic range of an ADC, selected to keep the analog input within the dynamic range of the ADC.

[0029] As a non-restrictive example, assume that the amplitude of the analog signal at the input of ADC 202 increases by 5% of the ADC reference per sample, starting from 50% of the ADC reference (i.e., at the midpoint of ADC 202's dynamic range). At the 10th sample, the increase is 50%, which is added to the starting point, which was 50% of ADC 202's dynamic range. Therefore, at an 11th sample (without intervention), ADC 202 would be saturated, as the input is 5% above the maximum limit that ADC 202 can measure (i.e., outside of ADC 202's dynamic range). Since the gain setting logic 206 reduces the gain when ADC 202's input reaches / exceeds a gain setting threshold, saturation can be avoided.

[0030] Continuing the non-restrictive example, it is assumed that a gain setting threshold is set to 95% of the ADC reference, and that the gain setting threshold is a threshold for an increasing analog signal 210. At a 9th sample, the ADC 202 exceeds the threshold (i.e., samples an input signal at 95% of its reference), and the gain setting logic 206 reduces the gain, thus reducing the analog signal by 50%, or (50% + 45%) / 2. After the signal has been reduced, it lies within the range defined by the gain setting threshold, which is 47.5% of the dynamic range. At 47.5% of the dynamic range, the ADC 202 will not saturate if the input increases by 5%.

[0031] As another example, if the input of ADC 202 increases in steps of 20% of the ADC reference per sample, then the ADC input reaches 90% after two samples and is saturated at the third sample (110%). In one embodiment, the input rate of change can be used to set a gain setting threshold. For example, if the input changes at a rate of up to 20% of the dynamic range per sample, then the gain setting threshold can be set to 75% or lower (75% + 20 = 95%, or just below the saturation limit).

[0032] In embodiments where the gain setting logic 206 is a digital circuit, for example, a configurable state machine with memory, the gain setting logic 206 can configure the gain at least partially based on a digital result or parts of a digital result. In particular, the gain setting logic 206 can be configured to digitally compare an input signal level with the gain setting threshold based on the digital result from the ADC 202. In another embodiment, the gain setting logic 206 can be an analog circuit configured to compare the signal level of the analog signal 210 with the gain setting threshold.Thus, depending on the implementation, the signal used by the gain setting logic 206 to determine the signal level at the input of AAGS 200 can be digital or analog, and the gain setting logic 206 can be either analog, digital, or a mixture of analog and digital.

[0033] In one embodiment, the gain setting logic 206 can be configured to determine a gain by resolving for the gain that would cause the monitored analog signal level to be close to the reference level of the ADC 202, and to configure the AAGS 200 to use that specific gain. The gain setting logic 206 can be configured to provide the ADRS 204 with a scaling component based on a gain. In one embodiment, the scaling component can be based on a specific gain. In one embodiment, the gain setting logic 206 can be configured to resolve for N in Equation 1: (Analog signal level × ADC reference gain × digital ADC resolution) × result scaling = digital result

[0034] Fig. Figure 3A shows an autonomous gain adjustment method 100 according to an embodiment of the disclosure. The autonomous gain adjustment method 100 can be used in conjunction with a system 2 ( Fig. 2) according to one embodiment of the disclosure. An input signal is observed in Operation 101. If the input signal level is at or below a lower gain setting threshold, then the gain on the input signal is increased in Operation 102a. If the input signal level is at or above an upper gain setting threshold, the gain of the input signal is decreased in Operation 102b. In various embodiments, a gain can be selected from the available / optional gains, the selected gain providing a matched input signal level that is within the dynamic range of an ADC. The set input signal is converted into a digital result in Operation 103. The digital result is reduced based on the gain applied to the analog signal in Operation 104.

[0035] In particular, in autonomous gain setting method 100, the set analog signal can have the same level as the input signal if the gain is 1x. If the gain applied to the set input signal is 1x, the digital result is not reduced.

[0036] Fig. Figure 3B discloses a method 110 for determining gain settings according to one or more embodiments of the disclosure. In operation 111, the signal level of an amplified input signal is observed. In operation 112, it is determined whether the signal level of the amplified signal is increasing or decreasing. In one embodiment, the current signal level observation can be compared with the immediately preceding signal level observation to determine whether the signal level is increasing or decreasing. If the signal level is increasing in operation 112, it is determined whether the signal level has exceeded the upper gain setting threshold since the last observation. In one embodiment, an exceedance can be determined if the immediately preceding signal level observation is less than or equal to the gain setting threshold and the current signal level observation is at or above the gain setting threshold.If no exceedance is detected, the gain is not adjusted. If an exceedance is detected, the gain applied to the input signal is reduced in operation 114.

[0037] If it is determined that the signal level is decreasing, Operation 115 determines whether the signal level has exceeded the gain setting threshold since the last observation. In one embodiment, an exceedance can be determined if the immediately preceding single level observation is equal to or greater than the gain setting threshold and the current signal level observation is equal to or less than the gain setting threshold. If no exceedance is detected, the gain is not adjusted. If an exceedance is detected, then the gain applied to the input signal is increased in Operation 116.

[0038] In one or more embodiments, the upper gain setting threshold and the lower gain setting threshold can be the same or different. In some embodiments, particular consideration is given to using a single gain setting threshold to determine whether the gain should be increased or decreased.

[0039] In particular, the signal levels of an input signal and an amplified signal can be equal if the gain is 1 or unity. In one or more embodiments, the input signal and the amplified signal will initially have the same amplitude. In other embodiments, a signal level of the input signal can initially be expected, and gain can be applied to the originally received input signal.

[0040] Fig. Figure 4 shows an implementation of an analog-to-digital converter with an autonomous gain stage and gain adjustment according to embodiments of the disclosure. The differential ADC 406 is a 10-bit ADC coupled to an adjustable gain stage 404; however, those skilled in the art will recognize that ADCs of any resolution can be used. In another embodiment, the differential ADC 406 can be a multi-stage pipeline ADC. The ADC 406 is a differential ADC that includes a differential input 408 (e.g., negative and positive), and for asymmetric measurements, a negative input of the differential input 408 of the ADC can be coupled to a fixed internal value. In another embodiment, a single-ended ADC can be used.The differential ADC 406 can support other functions, including functions that do not use gain, and thus gain activation can be included (not shown). The differential ADC 406 can include a number of internal inputs 410, including a voltage reference (Vref), and can include additional internal inputs, such as a temperature sensor.

[0041] In one embodiment, a gain setting logic 414 can be coupled to the differential ADC 406, the gain stage 404, and the result scaler 412. The gain setting logic 414 can be configured to digitally monitor the result output by the differential ADC 406 and to configure a gain selection 418 of the gain stage 404 and a scaling selection 418 of the result scaler 412. The gain setting logic 414 can include one or more control inputs 416 to configure the operation of the gain setting logic 414. In one embodiment, the gain setting logic 414 is a configurable state machine with memory.

[0042] In one embodiment, the amplification stage 404 can be configured to directly amplify an analog input signal and can, for example, be or include one or more operational amplifiers. The amplification stage 404 can include differential inputs 402a and 402b, receiving, for example, positive and negative inputs.

[0043] The result register 422 can be a 16-bit register coupled to the result scaler 412. If the 10-bit differential ADC 406 has a unity gain (x1), its maximum value will use all bits in the result register 422, which in this example is 16 bits. The lower 4 bits are not used for the unity gain. However, if the analog signal level is at or below a lower gain setting threshold, then the gain can be autonomously increased (e.g., doubled) and the digital result scaled down accordingly to compensate for the analog gain. Furthermore, if the analog signal level is at or above an upper gain setting threshold, then the gain can be autonomously decreased (e.g.,halved) and the digital result is scaled down accordingly to compensate for any analog gain (unless gain=1x, in which case the digital result is not scaled down).

[0044] The result register 422 can be coupled to, accessible to, or form part of a microcontroller 424 with integrated non-volatile memory. Several inputs of the microcontroller 424 can include an analog-to-digital converter with an autonomous gain stage and gain adjustment. In one embodiment, the microcontroller 424, according to embodiments of the disclosure, includes one or more peripheral devices that include an analog-to-digital converter with an autonomous gain stage and gain adjustment.

[0045] Fig. Figure 5 shows a battery monitoring system 500 with an embedded microcontroller 502 that executes a battery monitoring application, wherein the embedded microcontroller 502 includes one or more ADCs 504 with autonomous gain stage and gain setting according to embodiments of the disclosure. The embedded microcontroller 502 is configured to measure the current flowing into and out of the battery and estimate the remaining battery life or provide the measurements to a software application that estimates the remaining battery life. The embedded microcontroller 502 can be configured to measure current into and out of a motor 506, a GSM (Global Mobile Communication System) connected actuator 508, and a WiFi antenna 510 in a drone.Experts will recognize that the embedded microcontroller 502, which incorporates the ADC 504 with autonomous gain adjustment, can be incorporated into any device that has power-consuming components sensitive to battery life, such as a mobile phone (e.g., antenna, display), a drone (e.g., motor, GSM-connected actuator), a pacemaker, or any other medical device (e.g., an electrical pulse generator), etc.

[0046] Fig. Figure 6 shows the dynamic range within which the embedded microcontroller 502 and the associated ADC 504 operate in the battery monitoring system of Fig. 5. A typical standby current for a 506 motor can be 30 mA, and the maximum current during high power consumption by a 506 motor can be 30 A. For a 508 actuator connected to a GSM, the current when the GSM is active can be approximately 2 A. For the 510 WiFi antenna, the current when the antenna is active is approximately 30 mA. Therefore, the dynamic range within which the 502 embedded microcontroller operates can be approximately 30 mA to 30 A.

[0047] Fig. 7A and Fig. Figure 7B shows examples of a gain adjustment method according to an embodiment of the disclosure. To measure and monitor the battery, a desired resolution might be, for example, about 1 mA or better, so that there would be 30,000 steps in the range from 30 mA to 30 A. However, the ADC 504 is a 12-bit ADC and has 4,096 steps, so the resolution at unity gain is coarse compared to the analog signal.

[0048] As in Fig. As shown in Figure 7B, when the gain setting starts at approximately timeslot 43, a 4x gain is applied, allowing the ADC 504 to measure the signal resolution down to about 1.25 mA while still being able to measure up to 30 A. A 64x gain would allow the ADC 504 to measure the signal resolution down to about 100 µA while still being able to measure up to 30 A.

[0049] Experts will recognize many advantages and benefits of the embodiments described herein, including those compared to conventional ADCs with internal programmable gain stages.

[0050] One advantage of an ADC with AAGS and ADRS is that ADCs are typically calibrated and optimized for an input signal level at or near a reference signal level. Therefore, an ADC with AAGS and ADRS operates under ideal conditions for signal measurement at any given time, providing high resolution and dynamic range.

[0051] One advantage of an ADC with AAGS and ADRS is the ability to adjust the AAGS gain cycle by cycle without CPU intervention at any signal level. When an input signal level is high (i.e., at the upper end of the ADC's dynamic range), the ADC with AAGS automatically reduces the gain, and when the signal level is low (i.e., at the lower end of the ADC's dynamic range), it automatically increases the gain without CPU intervention.

[0052] Experts will understand that the principles described herein are applicable to and can be implemented in both digital-to-analog converters and analog-to-digital converters.

[0053] In one embodiment, the ADC is integrated with AAGS and ADRS as a core-independent peripheral of a microcontroller. In another embodiment, the ADC with AAGS and ADRS can be coupled to an event system bus. Additional details regarding a type of event system and event bus, as well as overall configurations of microcontroller systems, can be found in U.S. Patent No. 9,256,399 entitled "BREAKING PROGRAM EXECUTION ON EVENTS," filed on June 27, 2013, the disclosure of which is incorporated herein in its entirety by this reference.

[0054] In applications requiring a high sampling rate, it is impractical to adjust the gain of a peripheral device on a microcontroller's CPU. Furthermore, in data acquisition applications that require post-processing and regular data output or interrupts (e.g., from another peripheral device), using CPU time would delay other processes managed by the microcontroller, introduce latency due to CPU involvement, and generally reduce the system's computational efficiency considerably. Therefore, one or more embodiments generally refer to an autonomous processing unit of a microcontroller. In one or more embodiments, the autonomous processing unit can be a peripheral device of the microcontroller.A peripheral device that includes an autonomous processing unit can also be characterized as a "core-independent peripheral" configured to perform at least some (or all) functions without requiring time from the microcontroller's processing core(s). This allows the microcontroller to execute fewer control loops (compared to an MCU that includes a CPU-dependent processing unit), thus reducing the likelihood of missing interrupts from competing input signals.

[0055] Fig. Figure 8 shows a functional block diagram of an autonomous processing unit 800 according to one or more embodiments of the disclosure. In one or more embodiments, the autonomous processing system 800 can include an autonomously adjustable ADC 802, a result register 816, and an arithmetic unit 818.

[0056] The result register 816 can be operationally coupled to the autonomously adjustable ADC 802 and configured to receive a digital signal. The arithmetic unit 818 can be operationally coupled to the result register 816 and configured to receive one or more data bits stored in the result register 816.

[0057] The autonomously adjustable ADC 802 can be configured according to one or more of the embodiments of analog-to-digital converters with adjustable gain stages, result scalers, and gain logic of this disclosure, and can generally include the gain stage 804, ADC 808, gain setting logic 814, and result scaler 812. The gain setting logic 814 can be configured to receive ADC input 806 and / or ADC output 810 and to provide a gain selection and a scaling selection for the gain stage 804 and the result scaler 812.

[0058] The arithmetic logic 818 can be configured to output one or more computational results (e.g., data signals) that respond to the processing logic. In one or more embodiments, the arithmetic logic 818 can, as a non-limiting example, include registers and / or digital logic circuits configured to produce computational results that respond to one or more bits stored in registers (e.g., a register of the arithmetic logic unit 818, result register 816, and / or combinations thereof). In one or more embodiments, the arithmetic logic 818 can be a configurable state machine configured to produce results that respond to one or more detectable conditions, such as data bits in result register 816. As a non-limiting example, the arithmetic logic 818 can include a comparator, a timer / counter, if-then-else logic, arithmetic (e.g., addition, averaging, etc.).) and implement combinations thereof.

[0059] In one or more embodiments, the computation logic 818 can be configured to generate computation results 820 and 822 that respond to one or more operations. Some or all operations can be performed entirely on the computation logic 818 without input from a CPU (e.g., a microcontroller). Furthermore, the computation logic 818 does not require any capability (e.g., logic, circuitry, etc.) that allows an ADC to be at least partially "sensed" at its input, since the autonomously adjustable ADC 802 handles input signals independently.

[0060] In one or more embodiments, the autonomous processing system 800 can provide the results 820 and / or 822 to the peripheral bus 824 and the event system 826. In this way, the autonomous processing system 800 can be configured to communicate with one or more peripheral devices 828 and the microcontroller CPU, as well as to execute one or more control loops with other peripheral devices 828 without interrupting the microcontroller CPU.

[0061] The peripheral devices 828 can be configured, as a non-limiting example, for pulse width modulation, frame generation, interrupts (e.g., periodic, event-driven), input acquisition, time and frequency measurement of analog and digital signals, noise reduction, and combinations thereof. In one or more embodiments, one or more of the aforementioned peripheral device functions can be triggered by the event system 826, which responds to results 822, and / or can be triggered directly by results 820 enclosed in messages provided by the autonomous processing system 800 to the peripheral bus 824.

[0062] One aspect of the System 800 is that the autonomously adjustable ADC 802 can be optimized for an optimal number of bits by the gain-setting logic 814 and the gain stage 804. The optimal number of bits may depend on the amplitude of an input signal and / or the dynamic range of the processing unit 818. For example, if the processing unit 818 requires 16-bit resolution for a low-amplitude signal (e.g., 10 V) and the ADC 802 is configured for 8-bit resolution, the gain-setting logic 814 and the gain stage 804 can optimize the autonomously adjustable ADC 802 for 16-bit resolution by amplifying the input signal and monitoring and adjusting the amplified signal to prevent the ADC 802 from becoming saturated.Furthermore, the autonomously adjustable ADC 802 can be optimized without interrupting the processing cores of an embedded system, nor does the 818 compute unit need to perform any input signal optimization. The 818 compute unit can operate independently of the ADC's limitations, whereas conventional compute units must monitor and configure the ADC.

[0063] Various autonomous control loops can be enabled by autonomous processing units of the disclosure. One or more monitored operations can be modified in response to the control loops, e.g., motors, antenna power, etc. For example, shows Fig. Figure 9 shows a functional block diagram of an autonomous battery monitoring control system 900 according to one or more embodiments of the disclosure. In one or more embodiments, the autonomous battery monitoring control system 900 can be configured to measure the current drawn from a battery, such as the current from battery 514, which is supplied through the auxiliary terminal 512 of Fig. 5 flows, and generates one or more control signals 916 in response to the measured current.

[0064] In one or more embodiments, the autonomous battery monitoring control system 900 can include the autonomous sensing unit 902 and the pulse width modulator (PWM) 914. The autonomous sensing unit 902 can be configured to communicate with the PWM 914 via one or more of the peripheral buses 912, the event system 910, and / or the interrupts 918. In one or more embodiments, the autonomous sensing unit 902 can include an autonomously adjustable ADC 904, an accumulator 906, and sensing logic 908. The accumulator 906 can include one or more registers and adders for summing a sequence of current measurements output by the autonomously adjustable ADC 904.In one or more embodiments, the input signal autonomously sampled by the autonomously adjustable ADC 904 can be received from one or more input / output (I / O) pins of a microcontroller, for example, from I / O pins configured for general-purpose I / O (GPIO), from pins configured as event system inputs, and combinations thereof.

[0065] The acquisition logic 908 can be configured to receive current measurements from the accumulator 906 and output one or more results in response to the received current measurements. In one embodiment, the acquisition logic 908 can be configured to compare current measurements with one or more threshold values ​​and generate acquisition results (e.g., results indicating that a current measurement is above or below a threshold value) as a result of the comparison. In another embodiment, the acquisition logic 908 can be configured to determine an average current measurement based on current measurements received over time intervals and generate acquisition results in response to this determination. The autonomous acquisition unit 902 can be configured to provide (or make available) the acquisition results 920 and 922 to one or more event systems 910 and / or peripheral buses 912, respectively.

[0066] In one or more embodiments, the event system 910 can be configured to generate one or more PWM events in response to the sensing results 922. For example, if the sensing results 922 indicate a high current (e.g., the current measurement was above an upper threshold), the event system 910 can be configured to reduce the amount of current drawn from a battery. If the sensing results 922 indicate a low current (e.g., the current measurement was below a lower threshold), the event system 910 can be configured to do nothing, send a normal state, etc. In one or more embodiments, PWM 914 can be configured to pulse-width modulate a control signal 916 that responds to control signals received by the event system 910.

[0067] In another embodiment, the autonomous sensing unit 902 can be configured to generate one or more interrupts 918 at PWM 914 in response to one or more sensing results 922. PWM 914 can be configured to adjust the control signals 916 in response to interrupts 918. In one embodiment, PWM 914 can adjust the control signal 916 in a manner configured to reduce the amount of current drawn from a battery.

[0068] Fig. Figure 10 shows a flowchart of a control procedure 1000 according to one or more embodiments of the disclosure. In operation 1002, an input signal is autonomously sampled by the autonomously adjustable ADC 904. In one or more embodiments, the input signal can be a current, a voltage, a frequency, or combinations thereof. The sampled values ​​can be accumulated in an accumulator 1004 and read by the acquisition logic 908. In operation 1004, one or more conditions can be acquired in response to the sampled values. As a non-limiting example, the one or more conditions can include exceeding a threshold value, an average sample value, etc. In operation 1006, one or more acquisition results can be generated in response to one or more of the acquired conditions.The acquisition results can include any suitable form for indicating a detected state that is known to those skilled in the art (e.g., an error signal, a digital value, etc.). In Operation 1008, a control signal is set in response to one or more acquisition results. The setting can be configured to result in a specific operational change or a specific range of changes in a device or process. In Operation 1010, a monitored operation can change in response to the set control signal.

[0069] One or more embodiments of the disclosure relate to a microcontroller that includes an ADC with autonomous gain adjustment, wherein the gain adjustment is implemented internally within a microcontroller package. This architecture is more compact than an architecture in which a gain stage is located outside the microcontroller package, wherein, for example, a gain stage receives a signal of interest at an input and an output of the gain stage is connected to a GPIO pin.

[0070] Fig.Figure 11 shows a block diagram of a microcontroller 1100 according to one or more embodiments of this disclosure. The microcontroller 1100 includes processing cores 1104, system memory 1106, interrupts 1108, peripheral device(s) 1110, and I / O ports 1118, each operationally coupled to the bus 1122. The processing cores 1104 can be configured to perform one or more operations based on software instructions stored in program memory 1102 and data stored in system memory 1106. The bus 1122 can be any suitable bus type, including I2C, SPI, USB, and CAN. The I / O ports 1118 can include any number of general-purpose I / O (GPIO) ports 1120 and special-purpose I / O ports (not shown).

[0071] The 1110 peripherals can include any number and type of peripherals, such as ADCs, timers, mathematical units, USARTs, and more. Specifically, the 1110 peripherals include an autonomous processing unit 1112, which incorporates an AA-ADC 1114 operationally coupled to an arithmetic unit 1116. The arithmetic unit 1116 can be configured to perform one or more operations and may include, for example, a comparator, an adder, and a register for storing a result.

[0072] In one or more of the operations under consideration, an analog signal of interest 1122 can be received at one of the pins of GPIO 1120. In one or more embodiments, the pin and the signals activated at it can be selectively monitored by the autonomous processing unit 1112. The ADC of the AA-ADC 1114 can be configured for a step size that is insufficient for the dynamic range of the computing unit 1116. For example, the computing unit 1116 may require 16-bit resolution for an analog signal of interest 1122 with a 10 V range (i.e., ±5 volts), and the ADC of the AA-ADC 1114 may provide a lower resolution, such as 8-bit resolution. In other words, the computing unit 1116 may require the ADC to resolve changes of 20 mV in the analog signal, but the ADC may only be able to resolve changes of 40 mV.

[0073] Accordingly, the AA-ADC 1114 can be configured to increase the amplitude of the analog input signal such that a change of 20 mV in the input signal of interest 1122 results in a change of at least 40 mV in the amplified input signal to the ADC of the AA-ADC 1114. Furthermore, if the signal level of the amplified input signal exceeds a gain setting threshold assigned to the AA-ADC 1114, the AA-ADC 1114 is configured to adjust the gain to decrease the gain of the input signal of interest so that any further increase in the amplified signal does not exceed the dynamic range of the ADC. If the signal level of the amplified input signal falls below a gain setting threshold assigned to the AA-ADC 1114, the AA-ADC 1114 is configured to adjust the gain to increase the gain of the input signal.The AA-ADC 1114 can be configured to scale a digital output signal to match the dynamic range of the computing unit 1116.

[0074] One or more descriptions of the embodiments of the present disclosure may include a data bus or, more generally, communication via a data bus or data path. One or more embodiments of the disclosure may include interfaces to enable different elements to provide data to a data bus and, more generally, to enable communication via a data bus. The data may be communicated as messages and using a suitable protocol.

[0075] Many of the functional units described in this specification can be illustrated, described, or referred to as modules, threads, or other segregations of the program code to more clearly emphasize their implementation independence. Modules can be implemented in hardware, at least partially, in one form or another. For example, a module can be implemented as a hardware circuit comprising user-defined VLSI circuits or gate arrays, commercially available semiconductors such as logic chips, transistors, or other discrete components. A module can also be implemented in programmable hardware devices such as field-programmable gate arrays, programmable array logic, programmable logic devices, or the like.

[0076] While the present disclosure has been described herein in relation to certain illustrated embodiments, those skilled in the art will recognize and acknowledge that the present invention is not limited thereto. Rather, many additions, deletions, and modifications can be made to the illustrated and described embodiments without departing from the scope of the invention, as claimed below together with their legal equivalents. In addition, features of one embodiment can be combined with features of another embodiment while still remaining within the scope of protection of the invention as envisaged by the inventor.

[0077] Additional, non-restrictive embodiments of the disclosure include: Embodiment 1: A microcontroller system comprising: a central processing unit; one or more input / output (I / O) ports configured to receive an input signal; an autonomously adjustable analog-to-digital converter (ADC) configured to: amplify the input signal in response to a desired number of resolution bits; monitor the signal level of the amplified input signal; adjust a gain parameter in response to the monitored signal level to keep the amplified signal within a predefined dynamic range of the autonomously adjustable ADC; sample the amplified input signal with the desired number of resolution bits; provide a digital output signal in response to the amplified signal; and an arithmetic unit configured to provide one or more computational results in response to the digital output signal. Embodiment 2: The microcontroller system according to embodiment 1, wherein the computing unit comprises a processing logic circuit configured to determine one or more computational results, wherein the processing logic circuit is configured to perform one or more threshold detection, arithmetic and comparison operations. Embodiment 3: The microcontroller system according to one of embodiments 1 and 2, wherein the processing logic circuit is a configurable state machine. Embodiment 4: The microcontroller system according to one of embodiments 1 to 3, wherein the computing unit comprises one or more comparators, a timer, a counter, if-then logic, arithmetic, addition, subtraction, multiplication, division and averaging. Embodiment 5: The microcontroller system according to one of embodiments 1 to 4, wherein the autonomously adjustable ADC is operationally coupled to at least one I / O port of the one or more I / O ports, so that the autonomously adjustable ADC receives the input signal directly from one or more I / O ports. Embodiment 6: The microcontroller system according to one of embodiments 1 to 5, wherein the at least one I / O port is a general-purpose input / output port. Embodiment 7: The microcontroller system according to any one of embodiments 1 to 6, wherein the autonomously adjustable analog-to-digital converter (ADC) comprises: a gain stage circuit; an ADC circuit having at least one input coupled to at least one output of the gain stage circuit; a scaler circuit coupled to at least one output of the ADC circuit; and a gain setting logic circuit configured to: measure a signal level of an ADC input signal; compare the measured signal level with a gain setting threshold and, in response to the comparison: configure a gain of the gain stage circuit; and configure a scaling component of the scaler circuit, wherein the scaling component is proportional to the gain of the gain stage circuit. Embodiment 8: The microcontroller system according to one of embodiments 1 to 7, further comprising one or more peripheral devices. Embodiment 9: The microcontroller system according to any one of embodiments 1 to 8, further comprising a peripheral bus configured to enable a first peripheral device of one or more peripheral devices to communicate with a second peripheral device. Embodiment 10: The microcontroller system according to any one of embodiments 1 to 9, wherein the computing unit comprises an interface configured to be coupled to the peripheral bus, and wherein the computing unit is configured to provide the one or more computing results to the interface. Embodiment 11: The microcontroller system according to any one of embodiments 1 to 10, further comprising an event system, wherein the event system is configured to provide one or more events in response to the one or more computation results. Embodiment 12: The microcontroller system according to any one of embodiments 1 to 11, wherein the event system comprises an event logic configured to trigger a capture event of one or more events in response to a computation result of one or more computation results, wherein the computation result indicates a threshold capture at the one or more peripheral devices. Embodiment 13: The microcontroller system according to any of embodiments 1 to 12, wherein the event system comprises an event logic configured to trigger a capture event of one or more events in response to a computation result of one or more computation results and a threshold state. Embodiment 14: The microcontroller system according to one of embodiments 1 to 13, wherein the event system comprises a configurable event system logic. Embodiment 15: The microcontroller system according to one of embodiments 1 to 14, wherein the central unit is configured to execute a main control loop, and a first peripheral device of one or more peripheral devices and the computing unit are configured to execute a second control loop. Embodiment 16: The microcontroller system according to any one of embodiments 1 to 15, wherein the first peripheral device and the computing unit are configured to execute the second control loop while the central unit executes the main control loop without interrupting the main control loop. Embodiment 17: The microcontroller system according to any of embodiments 1 to 16, wherein the first peripheral device is configured to perform one of pulse width modulation, single-frame generation, periodic interrupts, event-driven interrupts, input sensing, analog signal timing, analog signal frequency measurement, digital signal timing, digital signal frequency measurement and noise suppression. Embodiment 18: A method for performing a computation on a microcontroller, comprising: executing a main control loop on a central processing unit of a microcontroller; and, while the first control loop is executed on the central processing unit, which performs a second control loop, the second control loop comprises: receiving an input signal at an input / output (I / O) port of the microcontroller; amplifying the input signal in response to a desired number of resolution bits; observing a signal level of the amplified signal; adjusting, in response to the observed signal level, a gain parameter to keep the amplified signal within a predefined dynamic range of the autonomously adjustable ADC; providing a digital signal in response to the amplified signal; and providing one or more computational results in response to the digital signal. Embodiment 19: The method according to embodiment 18, wherein the second control loop further comprises generating one or more computational results in response to performing one or more threshold detection, arithmetic and comparison operations. Embodiment 20: The method according to one of embodiments 18 and 19, wherein the second control loop further comprises the detection of one or more threshold conditions in response to one or more calculation results. Embodiment 21: The method according to one of embodiments 18 to 20, wherein the second control loop further comprises sampling the amplified input signal with the desired number of resolution bits. Embodiment 22. The method according to one of embodiments 18 to 21, wherein the second control loop can be executed at least partially without interrupting the first control loop. Embodiment 23: The method according to one of embodiments 18 to 22, wherein the first control loop is related to an energy-saving mode of the microcontroller and the second control loop is related to monitoring the operation of a system outside the microcontroller. Embodiment 24: The method according to one of embodiments 18 to 23, wherein the second control loop further comprises interrupting the first control loop in response to one or more computational results of the second control loop. Embodiment 25: The method according to one of embodiments 18 to 24, wherein the second control loop further comprises changing a control signal to a monitored system without interrupting the first control loop. Embodiment 26: A battery monitoring system comprising: an autonomous monitoring unit comprising: a sampling circuit configured to: receive an input current indicating a battery current; sample the input current with a desired number of resolution bits; and provide one or more battery current samples in response to the sampling; and a processing circuit configured to generate one or more processing results in response to the one or more battery current samples; and a monitoring logic configured to control one or more battery management systems in response to the generated one or more processing results. Embodiment 27: The battery monitoring system according to embodiment 26, wherein the battery comprises a single battery and a series of batteries. Embodiment 28: The battery monitoring system according to one of embodiments 26 and 27, wherein the battery current comprises at least one of a battery output current and a battery charging current. Embodiment 29: The battery monitoring system according to one of embodiments 26 to 28, wherein the processing circuit comprises at least one detection circuit and one measurement circuit. Embodiment 30: The battery monitoring system according to one of embodiments 26 to 29, wherein the processing circuit further comprises a battery configured to receive the battery current sampling values ​​and to generate battery current measurements. Embodiment 31: The battery monitoring system according to any of embodiments 26 to 30, wherein the sensing circuit is configured to compare the battery current measurements with one or more threshold values ​​and to generate sensing results in response to the comparison. Embodiment 32: The battery monitoring system according to any of embodiments 26 to 31, wherein the sensing circuit is configured to determine an average battery current measurement in response to the battery current measurements over time intervals and to generate the sensing results in response to the determination. Embodiment 33: The battery monitoring system according to one of embodiments 26 to 32, wherein the processing circuit is configured to determine an available energy capacity of the battery. Embodiment 34: The battery monitoring system according to one of embodiments 26 to 33, wherein the processing circuit is configured to determine an available energy consumption rate of the battery. Embodiment 35: The battery monitoring system according to one of embodiments 26 to 34, wherein the processing circuit is configured to determine an operating time of the battery. Embodiment 36: The battery monitoring system according to any of embodiments 26 to 35, wherein the autonomous monitoring unit is configured to communicate with the monitoring logic via at least one peripheral bus, an event system and / or interrupts. Embodiment 37: The battery monitoring system according to one of embodiments 26 to 36, wherein the one or more battery management systems comprise at least one of the event system, a processor and a pulse width modulator. Embodiment 38: The battery monitoring system according to one of embodiments 26 to 37, wherein the event system is configured to generate one or more pulse width modulator events in response to the generated one or more processing results. Embodiment 39: The battery monitoring system according to one of embodiments 26 to 38, wherein the pulse width modulator is configured to pulse width modulate the control signals in response to signals received from the event system. Embodiment 40: The battery monitoring system according to one of embodiments 26 to 39, wherein the autonomous monitoring unit is configured to generate one or more interrupts at the pulse width modulator in response to the generated one or more processing results. Embodiment 41: The battery monitoring system according to one of embodiments 26 to 40, wherein the pulse width modulator is configured to adjust the control signals in response to the interrupts. Embodiment 42: The battery monitoring system according to any of embodiments 26 to 41, wherein the pulse width modulator is configured to adjust the control signals to reduce the amount of current drawn from the battery. Embodiment 43: A method for monitoring a battery, comprising: amplifying an input current indicating a battery current in response to a desired number of resolution bits; sampling the amplified input current with the desired number of resolution bits; providing one or more battery current samples; generating one or more processing results in response to the one or more battery current samples; and controlling one or more battery management systems in response to the generated one or more processing results. Embodiment 44: The method of embodiment 43, wherein the sampling of the input current comprises sampling at least one of a single battery and a series of batteries. Embodiment 45: The method according to one of embodiments 43 and 44, wherein the sampling of the input current comprises sampling at least one of a battery output current and a battery charging current. Embodiment 46: The method according to one of embodiments 43 to 45, further comprising generating battery current measurements using a rechargeable battery. Embodiment 47: The method according to one of embodiments 43 to 46, further comprising comparing the battery current measurements with one or more threshold values ​​and generating detection results in response to the comparison. Embodiment 48: The method according to one of embodiments 43 to 47, further comprising: determining an average current measurement in response to the battery current measurements over time intervals; and generating the acquisition results in response to the determination. Embodiment 49: The method according to one of embodiments 43 to 48, further comprising determining an available energy capacity of the battery. Embodiment 50: The method according to one of embodiments 43 to 49, further comprising determining an available energy consumption rate of the battery. Embodiment 51: The method according to one of embodiments 43 to 50, further comprising determining an operating time of the battery. Embodiment 52: The method according to one of embodiments 43 to 51, further comprising generating one or more pulse width modulator events in response to the generated one or more processing results using an event system. Embodiment 53: The method according to one of embodiments 43 to 52, further comprising pulse width modulation using a pulse width modulator of control signals in response to signals received at the event system. Embodiment 54: The method according to one of embodiments 43 to 53, further comprising generating one or more interrupts at the pulse width modulator in response to the generated one or more processing results. Embodiment 55: The method according to any one of embodiments 43 to 54, further comprising adjusting the control signals in response to interrupts. Embodiment 56: The method according to any one of embodiments 43 to 55, further comprising adjusting the control signals to reduce the amount of current drawn from the battery. Embodiment 57: A system comprising: an amplifier; an analog-to-digital converter having at least one input operationally coupled to at least one output of the amplifier; a scaler operationally coupled to at least one output of the analog-to-digital converter; and a control circuit, wherein the control circuit is configured to: configure a gain of the amplifier and a scaling component of the scaler to increase an effective resolution of the analog-to-digital converter; measure a signal level of an input signal at the analog-to-digital converter; detect that increasing the signal level of an analog-to-digital converter by a step size would reach or exceed a gain setting threshold;to configure the amplifier's gain in response to a set gain selected such that an input signal level set at the analog-to-digital converter is substantially at half a reference voltage of the analog-to-digital converter; and to configure the scaler's scaling component in response to a set scaling component proportional to the set gain. Embodiment 57: A method comprising: measuring a signal level of an amplified input signal at an analog-to-digital converter; detecting that increasing the signal level of an analog-to-digital converter by a step size would reach or exceed a gain setting threshold; configuring a gain of an amplifier operationally coupled to the input of the analog-to-digital converter in response to a first set gain selected such that an input signal level set at the analog-to-digital converter is substantially at half a reference voltage of the analog-to-digital converter; and configuring a scaling component of a scaler operationally coupled to an output of the analog-to-digital converter in response to a first set scaling component proportional to the first set gain.Embodiment 58: A microcontroller system comprising: a central processing unit; and one or more peripheral devices, wherein the one or more peripheral devices comprise: an analog-to-digital converter; an amplification stage operationally coupled to an input of the analog-to-digital converter, the amplification stage comprising a differential amplifier; a scaler operationally coupled to an output of the analog-to-digital converter; and a control unit configured to: change a gain setting of the differential amplifier in response to an indication that a change in the amplitude of an input signal to the analog-to-digital converter, substantially corresponding to a step size of the analog-to-digital converter, may be outside a dynamic range of the analog-to-digital converter; and change a scaling setting of the scaler in response to the changed gain setting. Embodiment 59: The microcontroller system according to embodiment 58, wherein the control unit is further configured to measure the input to the analog-to-digital converter from a reference point, wherein the reference point is 50% of the dynamic range of the analog-to-digital converter.

Claims

[1] Microcontroller system, comprising: a central processing unit of a microcontroller configured to execute a first control loop at the central processing unit while a second control loop is executed, wherein the second control loop can be executed at least partially without interrupting the first control loop; one or more input / output (I / O) ports configured to receive an input signal; an autonomously adjustable analog-to-digital converter (ADC) configured to: to amplify the input signal in response to a desired number of resolution bits; to observe a signal level of the amplified input signal; to adjust a gain parameter in response to the observed signal level in order to keep the amplified signal within a predefined dynamic range of the autonomously adjustable ADC; to sample the amplified input signal with the desired number of resolution bits; to provide a digital output signal in response to the amplified signal, and a computing unit configured to provide one or more computational results in response to the digital output signal. [2] Microcontroller system according to claim 1, wherein the computing unit comprises a processing logic circuit configured to determine one or more computational results, wherein the processing logic circuit is configured to perform one or more threshold detection, arithmetic and comparison operations. [3] Microcontroller system according to claim 2, wherein the processing logic circuit is a configurable state machine. [4] Microcontroller system according to claim 2, wherein the computing unit comprises one or more comparators, a timer, a counter, an if-then logic, arithmetic, addition, subtraction, multiplication, division and averaging. [5] Microcontroller system according to claim 1, wherein the autonomously adjustable ADC is operationally coupled to at least one I / O port of the one or more I / O ports, such that the autonomously adjustable ADC receives the input signal directly from the one or more I / O ports. [6] Microcontroller system according to claim 5, wherein the at least one I / O port is a general-purpose input / output port. [7] Microcontroller system according to claim 1, wherein the autonomously adjustable ADC comprises: a staged amplification circuit; an ADC circuit with at least one input coupled to at least one output of the amplification stage circuit; a scaling circuit coupled to at least one output of the ADC circuit; and a gain setting logic circuit configured to: to measure the signal level of an ADC input signal; to compare the measured signal level with a gain setting threshold and in response to the comparison: to configure an amplification of the amplification stage circuit; and to configure a scaling component of the scaler circuit, where the scaling component is proportional to the gain of the gain stage circuit. [8] Microcontroller system according to claim 1, further comprising one or more peripheral devices. [9] Microcontroller system according to claim 8, further comprising a peripheral bus configured to enable a first peripheral device of one or more peripheral devices to communicate with a second peripheral device. [10] Microcontroller system according to claim 9, wherein the computing unit comprises an interface configured to be coupled to the peripheral bus, and wherein the computing unit is configured to provide the one or more computing results to the interface. [11] Microcontroller system according to claim 10, further comprising an event system, wherein the event system is configured to provide one or more events in response to the one or more computation results. [12] Microcontroller system according to claim 11, wherein the event system comprises an event logic configured to trigger a detection event of one or more events in response to a computation result of one or more computation results, wherein the computation result indicates a threshold detection at the one or more peripheral devices. [13] Microcontroller system according to claim 11, wherein the event system comprises an event logic configured to trigger a detection event of one or more events in response to a computation result of one or more computation results and a threshold state. [14] Microcontroller system according to claim 11, wherein the event system comprises a configurable event system logic. [15] Microcontroller system according to claim 11, wherein the central unit is configured to execute a main control loop, and a first peripheral device of one or more peripheral devices and the computing unit are configured to execute a second control loop. [16] Microcontroller system according to claim 15, wherein the first peripheral device and the computing unit are configured to execute the second control loop while the central unit executes the main control loop without interrupting the main control loop. [17] Microcontroller system according to claim 15, wherein the first peripheral device is configured to perform one of pulse width modulation, single-frame generation, periodic interrupts, event-driven interrupts, input sensing, analog signal timing, analog signal frequency measurement, digital signal timing, digital signal frequency measurement and noise suppression. [18] Method for performing a calculation on a microcontroller, comprising: Executing a main control loop on a central processing unit of a microcontroller; and While the first control loop is being executed at the central unit, a second control loop is executed without interrupting the first loop, encompassing the second control loop: Receiving an input signal at an input / output (I / O) port of the microcontroller; Amplifying the input signal in response to a desired number of resolution bits; Observing the signal level of the amplified signal; Adjusting, in response to the observed signal level, a gain parameter to keep the amplified signal within a predefined dynamic range of the autonomously adjustable ADC; Providing a digital signal in response to the amplified signal; and Providing one or more computational results in response to the digital signal. [19] Method according to claim 18, wherein the second control loop further comprises generating one or more computational results in response to performing one or more threshold detection, arithmetic and comparison operations. [20] Method according to claim 18, wherein the second control loop further comprises detecting one or more threshold conditions in response to one or more calculation results. [21] Method according to claim 18, wherein the second control loop further comprises sampling the amplified input signal at the desired number of resolution bits. [22] Method according to claim 18, wherein the second control loop can be executed at least partially without interrupting the first control loop. [23] Method according to claim 22, wherein the first control loop is associated with an energy-saving mode of the microcontroller and the second control loop is associated with monitoring the operation of a system outside the microcontroller. [24] Method according to claim 23, wherein the second control loop further comprises interrupting the first control loop in response to one or more computational results of the second control loop. [25] Method according to claim 23, wherein the second control loop further comprises changing a control signal to a monitored system without interrupting the first control loop.

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