POWER CONVERTER

Abstract

Power converters (100, 200a, 200b, 300a, 300b, 300c, 400), which has the following: - a boost converter (20) for increasing the output voltage of a DC power supply unit (1); - a smoothing capacitor (30) for smoothing the output voltage of the boost converter (20); - an inverter (35) for converting the voltage of the smoothing capacitor (30) into an alternating voltage; and - a control unit (50, 250, 450) for controlling the boost converter (20) and the inverter (35), wherein the boost converter (20) comprises: an inductance (2) having a first end connected to the DC power supply unit (1), a branch region (8) having four semiconductor elements comprising a first semiconductor element (3), a second semiconductor element (4), a first semiconductor switching element (5) and a second semiconductor switching element (6), each of which controls the conduction and interruption of current, wherein the four semiconductor elements are connected in series between positive and negative terminals of the smoothing capacitor (30), wherein a second end of the inductance (2) is connected to a connection point between the second semiconductor element (4) and the first semiconductor switching element (5), and an intermediate capacitor (7) connected between a connection point of the first semiconductor element (3) and the second semiconductor element (4) and a connection point of the first semiconductor switching element (5) and the second semiconductor switching element (6), wherein the control unit (50, 250, 450) in a normal mode, performs ON / OFF control for the first semiconductor switching element (5) and the second semiconductor switching element (6) in each control cycle to cause the boost converter (20) to output multi-level voltages, and then, when the voltage of the smoothing capacitor (30) is equal to or greater than a reference voltage value, executes a protection mode to stop a switching operation of semiconductor elements of the inverter (35) and to fix the first semiconductor switching element (5) and the second semiconductor switching element (6) in the OFF state for a period longer than the control cycle.

Description

TECHNICAL FIELD

[0001] The present invention relates to a power converter. STATE OF THE ART

[0002] The following describes a known power converter which performs subsequent control to suppress the application of overvoltages to a semiconductor element in a power converter.

[0003] In a power conversion unit of a DC / DC power converter, switching elements S1, S2 and diodes D1, D2 are arranged in series, and resistors R4, R3, R2, and R1 are arranged in parallel with switching elements S1, S2 and diodes D1, D2, respectively. Switching elements S1, S2 are voltage-balancing resistors for adjusting the voltages applied to diodes D1, D2. When the input voltage of an input terminal of a DC power supply is zero or significantly reduced and switching elements S1, S2 are in a control-stop state, voltage-balancing resistors R1 to R4 maintain a voltage balance between switching elements S1, S2 and diodes D1, D2 (see, for example, Patent Document 1).

[0004] In addition, a power converter is known, for example, which carries out the control described below.

[0005] An overvoltage detector outputs a trigger signal to an inverter when the DC voltage of a smoothing capacitor exceeds a predetermined overvoltage value. A DC voltage monitor measures the time period during which the DC voltage of the smoothing capacitor is equal to or greater than an overvoltage threshold using a timer and issues an alarm when a predetermined time or longer has elapsed. Then, a voltage reduction measure is performed through a manual operation, such as opening a capacitor of a system (see, for example, Patent Document 2).

[0006] JP 2012-239324 A (Patent Document 3) describes a DC / DC power converter with a boost and buck converter.

[0007] US 2017 / 0 050 525 A1 (Patent Document 4) discloses a motor drive mechanism with a transducer capable of outputting an error signal.

[0008] US 2013 / 0 021 011 A1 (Patent Document 5) describes a DC / DC power converter that converts a DC voltage up or down. STATE OF THE ART Patent document 1: JP 2014- 033 553 A Patent document 2: JP 2007- 166 815 A Patent document 3: JP 2012- 239 324 A Patent document 4: US 2017 / 0 050 525 A1 Patent document 5: US 2013 / 0 021 011 A1 SUMMARY OF THE INVENTION Problems to be solved by the invention

[0009] The known power converter described in Patent Document 1 can suppress the overvoltage of each semiconductor element when the input voltage is zero or significantly reduced and the power converter is stopped. However, if a situation occurs during the operation of the power converter where an overvoltage is applied to each semiconductor element, the overvoltage cannot be suppressed.

[0010] In the known power converter described in Patent Document 2, when the smoothing capacitor overvoltage occurs, a voltage reduction action is performed by a manual operation, such as opening the capacitor. However, a manual operation requires a certain amount of time to perform the voltage reduction action from the time the overvoltage occurs, so rapid overvoltage elimination is not possible.

[0011] In particular, in a power converter that includes a boost converter and an inverter and converts the boosted DC voltage into an AC voltage and outputs the AC voltage to a load, the bus voltage may increase due to the regeneration power of the load, resulting in an increase in the voltage of the smoothing capacitor connected to the bus voltage, for example, when an abnormality in the power conversion device or an abnormality in a load operation has occurred.

[0012] Due to the voltage rise in the smoothing capacitor, excessive voltage may be applied to each semiconductor element in the power converter. Especially when using a multi-level boost converter capable of outputting multi-level voltages, the withstand voltage of the boost converter's semiconductor element is generally set lower than the withstand voltage of the inverter's semiconductor element. Therefore, excessive voltage is likely to be applied to each semiconductor element.

[0013] The present invention has been conceived to solve the above problem, and the object of the present invention is to provide a power converter capable of quickly suppressing overvoltages at a semiconductor element in the power converter during operation of the power converter. Means to solve the problems

[0014] The object underlying the invention is achieved by a power converter having the features of independent claim 1. Advantageous developments of the power converter according to the invention are specified in dependent claims 2 to 9. Effect of the invention

[0015] The power converter according to the present invention can suppress overvoltages at each semiconductor element in the power converter during operation. This makes it possible to provide a highly reliable power converter that suppresses deterioration of each semiconductor element. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing the schematic structure of a power converter system including a power converter according to Embodiment 1; Fig. 2 is a diagram showing the internal configuration of a control unit according to Embodiment 1; Fig. 3 shows the relationship between input and output of a gate block unit according to Embodiment 1; Fig. 4 is a waveform diagram showing the operation of the power converter according to Embodiment 1; Fig. 5 shows the voltages at several locations in the power converter according to embodiment 1; Fig. 6 shows the voltages at several locations in the power converter in a comparative example; Fig. 7 is a diagram showing the schematic structure of a power converter system including the power converter according to Embodiment 1; Fig. 8 is a diagram showing the schematic structure of a power converter system including a power converter according to Embodiment 2; Fig. 9 is a diagram showing the internal configuration of a control unit according to Embodiment 2; Fig. 10 shows the relationship between input and output of a gate block unit according to Embodiment 2; Fig. 11 is a diagram showing the schematic structure of a power converter system including the power converter according to Embodiment 2; Fig. 12 is a diagram showing the schematic structure of a power converter system including a power converter according to Embodiment 3; Fig. 13 is a diagram showing the schematic structure of a power converter system including a power converter according to Embodiment 3; Fig. 14 is a diagram showing the schematic structure of a power converter system including a power converter according to Embodiment 3; Fig. 15 is a diagram showing the schematic structure of a power converter system including a power converter according to Embodiment 4; Fig. 16 is a diagram showing the internal configuration of a control unit according to Embodiment 4, and Fig. 17 shows the relationship between input and output of a gate block unit according to Embodiment 4. DESCRIPTION OF THE EMBODIMENTS Embodiment 1

[0016] Hereinafter, a power converter 100 according to Embodiment 1 of the present invention will be described with reference to the drawings.

[0017] Fig. 1 is a diagram showing the schematic structure of a power converter system including the power converter 100 according to Embodiment 1.

[0018] Fig. 2 is a diagram showing the internal structure of a control unit 50 in the present embodiment 1.

[0019] Fig. 3 shows the relationship between the input and output of the gate block units 56, 57, 58 of the Fig. 2 shown control unit 50.

[0020] As in Fig. 1, the power converter 100 is provided between a DC power supply unit 1 and an AC motor 40 and converts the DC voltage from the DC power supply unit 1 to drive the AC motor 40.

[0021] The power converter 100 includes a multi-level booster circuit 20 serving as a boost converter for boosting the output voltage of the DC power supply unit 1, a smoothing capacitor 30 for smoothing the output voltage of the multi-level booster circuit 20, an inverter 35 that converts the voltage smoothed by the smoothing capacitor 30 into AC voltage and outputs the AC voltage to the AC motor 40, and a control unit 50 for controlling the multi-level booster circuit 20 and the inverter 35.

[0022] The power converter 100 configured as described above, the DC power supply unit 1, and the AC motor 40 constitute the power conversion system according to the present embodiment.

[0023] The multi-level booster circuit 20 of the power converter 100 has an inductance 2, a branch region 8 connected between the positive and negative poles of the smoothing capacitor 30, an intermediate capacitor 7, and trimming resistors 10 and 11.

[0024] The branch portion 8 of the multi-level booster circuit 20 includes a first diode 3 as a first semiconductor element, a second diode 4 as a second semiconductor element, a first switching element 5 as a first semiconductor switching element, and a second switching element 6 as a second semiconductor switching element, which are arranged in this order from the side connected to the positive terminal of the smoothing capacitor 30 and respectively control current conduction and current interruption, these four semiconductor elements being connected in series.

[0025] The first diode 3 and the second diode 4 are arranged so that current flows from an intermediate node n, which is the connection point between the second diode 4 and the first switching element 5, to the positive output end of the multi-level booster circuit 20. Furthermore, the first switching element 5 and the second switching element 6 are arranged so that current flows from the intermediate node n to the negative output end of the multi-level booster circuit 20.

[0026] The output side, ie the second end of the inductance 2 is connected to the intermediate node n, and the input side, ie the first end of the inductance 2 is connected to the DC power supply unit 1.

[0027] The positive terminal of the intermediate capacitor 7 is connected to the connection point between the first diode 3 and the second diode 4, and the negative terminal of the intermediate capacitor 7 is connected to the connection point between the first switching element 5 and the second switching element 6.

[0028] Furthermore, a trimming resistor 10 is connected in parallel with the first diode 3, and a trimming resistor 11 is connected in parallel with the second switching element 6. Thus, in the present embodiment, the trimming resistors 10 and 11 are connected only to the first diode 3 and the second switching element 6 among the four semiconductor elements included in the branch region 8. The trimming resistors 10 and 11 are provided to stabilize the ratio of the applied voltages distributed among the semiconductor elements of the branch region 8.

[0029] Although in Fig. 1, the inverter 35 contains a total of six switching elements 36, two of which are provided for each phase to convert direct current into three-phase current.

[0030] The power converter 100 includes the voltage detection device 30A for detecting the voltage Vdc of the smoothing capacitor 30. The detected smoothing capacitor voltage Vdc is input to the control unit 50.

[0031] The first switching element 5 and the second switching element 6 used in the branch region 8 of the multi-level booster circuit 20 are formed from semiconductor elements such as insulated gate bipolar transistors (IGBTs) or metal oxide semiconductor field-effect transistors (MOSFETs). The first switching element 5 and the second switching element 6 may include diodes connected in antiparallel thereto. Of course, the materials of the semiconductor elements (first diode 3, second diode 4, first switching element 5, second switching element 6) of the branch region 8 may be Si (silicon) or semiconductors such as SiC (silicon carbide) and GaN (gallium nitride).

[0032] The first diode 3 and the second diode 4 can be replaced by semiconductor elements, such as IGBTs or MOSFETs, which have switching functions and to which diodes are connected in antiparallel. However, in the present embodiment, the regeneration operation of the multi-level booster circuit 20 is not required, so diodes are used.

[0033] The AC motor 40 may be an induction motor or a synchronous motor.

[0034] Next, the operation of the multi-level booster circuit 20 is described in detail.

[0035] The multi-level booster circuit 20 has the function of increasing the voltage of the smoothing capacitor 30 and generates a DC voltage at the intermediate capacitor 7 that is equal to or less than the voltage of the smoothing capacitor 30. That is, the multi-level booster circuit 20 has the property that its output voltage level can be multi-level, ie, three-level.

[0036] When the voltage Vm of the intermediate capacitor 7 is controlled to 1 / 2 Vdc, which is half of the smoothing capacitor voltage Vdc, the multi-level booster circuit 20 can generate three-level outputs, namely 0, 1 / 2 Vdc, and Vdc. Such a multi-level booster circuit has the characteristic of reducing the switching loss of the switching elements and reducing the carrier ripple current of the inductor, thus achieving high efficiency.

[0037] Next, the configuration and control of the control unit 50 will be described with reference to Fig. 2 described.

[0038] As in Fig. 2, the control unit 50 includes a comparator 51, a buffer unit 52, gate block units 56, 57, 58, and gate signal generating units 53, 54, 55. The control unit 50 may be formed from an analog circuit or from an application-specific integrated circuit (ASIC), an FPGA (Field Programmable Gate Array), a microcomputer, or the like.

[0039] The details of each block in the control unit 50 are described below.

[0040] The smoothing capacitor voltage Vdc detected by the voltage detection device 30A is input to the plus side of the comparator 51, and a comparison signal Vdcref as a reference voltage value is input to the minus side of the comparator 51. A voltage serving as a reference for stopping the inverter 35 is input as the comparison signal Vdcref. Regarding the setting value of the comparison signal Vdcref, the comparison signal Vdcref is set to approximately 400 V in the case of the inverter of an AC 200 V system and approximately 800 V in the case of the inverter of an AC 400 V system.

[0041] The comparator 51 compares the input smoothing capacitor voltage Vdc and the comparison signal Vdcref. If the relation: “Smoothing capacitor voltage Vdc < comparison signal Vdcref” is fulfilled, the comparison device 51 outputs the value “0”, and if the relation: “Smoothing capacitor voltage Vdc ≥ comparison signal Vdcref” is fulfilled, the comparison device 51 outputs the value “1”.

[0042] That is, the comparator 51 outputs a value of "1" only in an abnormal case when the smoothing capacitor voltage Vdc is equal to or greater than the reference voltage value, and the comparator 51 outputs a value of "0" in other normal cases. Thus, the comparator 51 has an abnormality determination function for detecting an overvoltage of the smoothing capacitor 30. The output of the comparator 51 is output to the latch unit 52.

[0043] In a case where the comparison device 51 is implemented as an analog circuit, the comparison device 51 is typically formed using a comparator. Of course, the comparison device 51 can also be implemented using an ASIC or FPGA.

[0044] Next, the latch unit 52 will be described. The latch unit 52 is designed to hold "1," an abnormal case signal, when the comparator 51 detects an overvoltage, until an enable signal S1 is input.

[0045] In the case where the latch unit 52 is formed by a logic circuit, the latch unit 52 can be designed as an RS flip-flop with input terminals R (reset) and S (set). In this case, the output of the comparator 51 is input to the set input of the latch unit 52, and the enable signal S1 is input to the reset input.

[0046] After the smoothing capacitor voltage Vdc becomes equal to or greater than the reference voltage value and the output of the comparator 51 becomes "1" for an abnormal case, the output of the latch unit 52 is fixed at "1" even if the output of the comparator 51 changes to "0" for a normal case. When "1" is input as the enable signal S1, the output of the latch unit 52 changes from "1" to "0", so that the abnormality determination can be canceled.

[0047] The enable signal S1 can be input externally by an operator or, for example, generated in the control unit 50. When the enable signal S1 is generated in the control unit 50, the output of the comparison device 51 is inverted by an inverter and then delayed by a delay device for a predetermined period of time. Thus, after the predetermined time has elapsed, when the smoothing capacitor voltage Vdc has become smaller than the value of the reference voltage, the output of the buffer unit 52 normally becomes "0."

[0048] By providing the buffer unit 52 at the output stage of the comparison device 51 as described above, the control unit 50 is prevented from frequently repeating a protection mode for the exceptional case and a normal operation described later, so that damage to devices can be avoided.

[0049] Next, the gate signal generating units 53, 54, 55 will be described.

[0050] The gate signal generation unit 53 generates a gate signal G3a for each switching element 36 included in the inverter 35. Furthermore, the gate signal generation units 54, 55 each generate a gate signal G1a, G2a for the first switching element 5 and the second switching element 6 included in the multi-level booster circuit 20.

[0051] Finally, the gate block units 56, 57, 58 are described.

[0052] Gate block units 56, 57, 58 serve to set the gate signals G1, G2, G3 for the first switching element 5 and the second switching element 6 included in the multi-level booster circuit 20 and each switching element 36 included in the inverter 35 to "0" in an exceptional case where the smoothing capacitor voltage Vdc is overvoltage. Gate block units 56, 57, 58 can be formed by logic circuits.

[0053] Gate block unit 56 receives the output of latch unit 52 and gate signal G3a. Gate block unit 57 receives the output of latch unit 52 and gate signal G1a. Gate block unit 58 receives the output of latch unit 52 and gate signal G2a.

[0054] The output signals (gate signals G1, G2, G3) of the gate block units 56, 57, 58 are determined by the Fig. 3. That is, only when the gate signals G1a, G2a, G3a are equal to "1" and the output of the latch unit 52 is "0" in the normal case, the control unit 50 causes the gate block units 56, 57, 58 to output the gate signals G1, G2, G3 of "1." In an abnormal case, the control unit 50 executes a protection mode to output the gate signals G1, G2, G3 of "0."

[0055] That is, in a normal case where the smoothing capacitor voltage Vdc is lower than the reference voltage value, the control unit 50 operates in a normal mode to perform ON / OFF control for the first switching element 5 and the second switching element 6 of the multi-level booster circuit 20, so that the multi-level booster circuit 20 outputs multi-level voltages. Furthermore, the control unit 50 performs ON / OFF control for each switching element 36 of the inverter 35 to generate an AC voltage.

[0056] On the other hand, in the abnormal case where the smoothing capacitor voltage Vdc is equal to or greater than the reference voltage value, the control unit 50 operates in a protection mode to keep the first switching element 5 and the second switching element 6 of the multi-level booster circuit 20 in the OFF state and stop the switching operation of each switching element 36 of the inverter 35 so that gate blocking is performed.

[0057] In Fig. Figure 2 shows the configuration with three gate block units 56, 57, 58 for outputting the gate signal G1 for the first switching element 5, the gate signal G2 for the second switching element 6, and the gate signal G3 for the inverter 35. However, in reality, such as the gate signal G3 for the inverter 35, six signals corresponding to the number of switching elements 36 and thus six gate block units are required. A total of eight gate block units are therefore required, including the gate block units for the first switching element 5 and the second switching element 6 of the multi-level booster circuit 20. Fig. 2, some of the gate block units are omitted to avoid complicating the drawing.

[0058] Next, the effects of the protection mode executed by the control unit 50 of the power converter 100 according to the present embodiment will be described with reference to the drawings.

[0059] Fig. 4 is a waveform diagram showing the operation of the power converter 100 immediately after the execution of the protection mode during the operation of the power converter 100.

[0060] Fig. Figure 5 shows voltages across several components in power converter 100 when the protection mode is executed.

[0061] In Fig. 4, three waveforms are shown, and these waveforms represent, from top to bottom, the smoothing capacitor voltage Vdc, the current of the AC motor 40, and the speed of the AC motor 40.

[0062] During operation of the power converter 100, it is assumed that the smoothing capacitor voltage Vdc rises due to an abnormality and reaches an overvoltage level. Then, the control unit 50 of the power converter 100 detects the rise in the smoothing capacitor voltage Vdc and executes the protection mode. After the protection mode starts, the first switching element 5 and the second switching element 6 of the multi-level booster circuit 20 are fixed in the OFF state at time 5.5 s, and the inverter 35 is gate-locked and stopped.

[0063] When the control unit 50 stops the inverter 35, the regeneration operation occurs due to the inductance energy of the AC motor 40 and the electromotive force of the AC motor 40, so that the smoothing capacitor voltage Vdc continues to rise from 850 V and reaches about 1030 V.

[0064] The voltages applied to the semiconductor elements of the branch region 8 of the multi-level booster circuit 20 when the smoothing capacitor voltage Vdc is an overvoltage as described above are shown in Fig. 5 shown.

[0065] In Fig. 5, the smoothing capacitor voltage Vdc has a value of 1030 V and the intermediate capacitor voltage Vm has a value of 850 / 2 V = 425 V. The smoothing capacitor voltage Vdc corresponds to the Fig. The result shown in Figure 4 is that the rate of change of the intermediate capacitor voltage Vm is sufficiently slower than the rate of change of the smoothing capacitor voltage Vdc, so that the intermediate capacitor voltage Vm does not change compared to that before the inverter stops. Therefore, the intermediate capacitor voltage Vm is equal to the voltage before stopping, i.e., 425 V.

[0066] In the protection mode, the first switching element 5 and the second switching element 6 of the branch region 8 of the multi-level booster circuit 20 are fixed in the OFF state. Therefore, as shown in Fig. 6, the voltage applied to the first diode and the second switching element 6 of the branch region 8 of the multi-level booster circuit 20 is 302.5 V, which is obtained by subtracting the intermediate capacitor voltage Vm (425 V) from the smoothing capacitor voltage Vdc (1030 V) and then dividing the resulting value by 2. In addition, the voltages applied to the second diode 4 and the first switching element 5 are 212.5 V, which is obtained by dividing the intermediate capacitor voltage Vm (425 V) by 2.

[0067] Here, a comparative example will be described in which the first switching element 5 and the second switching element 6 of the multi-level booster circuit 20 are not fixed in the OFF state when the smoothing capacitor voltage Vdc is an overvoltage.

[0068] Fig. Figure 6 shows the voltages at several points in the power converter in the comparison example.

[0069] In the abnormal case where the smoothing capacitor voltage Vdc is an overvoltage and when the first switching element 5 and the second switching element 6 are not fixed in the OFF state as shown in Fig. 5, the voltage applied to each semiconductor element of the branch region 8 of the multi-level booster circuit 20 differs depending on the ON / OFF states of the gate signals G1, G2 for the first switching element 5 and the second switching element 6.

[0070] It has been found that when the gate signal G2 is ON (the second switching element 6 is ON), an overvoltage of 605 V, which is obtained by subtracting the intermediate capacitor voltage Vm (425 V) from the smoothing capacitor voltage Vdc (1030 V), is applied to the first diode 3. In the case of multilevel circuits, it is generally common to use a semiconductor element with a lower withstand voltage than the inverter. Therefore, if elements with a withstand voltage of 600 V are used, there is a possibility of deterioration of the multilevel booster circuit.

[0071] As described above, in the present embodiment, the control unit 50 of the power converter 100 executes the protection mode in an abnormal case where the smoothing capacitor voltage Vdc becomes an overvoltage during operation of the power converter 100. Then, in the protection mode, the control unit 50 fixes the first switching element 5 and the second switching element 6 of the multi-level booster circuit 20 in the OFF state and stops the inverter 35. Although the smoothing capacitor voltage Vdc may continue to rise when the inverter 35 is stopped, even in this case, excessive voltage can be prevented from being applied to the semiconductor elements in the multi-level booster circuit 20.

[0072] Therefore, when the power converter 100 is abnormal, the control unit 50 can stop the power converter 100 and simultaneously suppress overvoltages at each semiconductor element in the multi-level booster circuit 20.

[0073] The semiconductor elements that Fig. 5 and Fig. The components corresponding to 6, indicated by (*), are semiconductor elements to which the applied voltage is distributed in the branch region 8. In the case where the applied voltage is distributed among the semiconductor elements as described above, the applied voltage is not evenly distributed if the impedances of the semiconductor elements vary. Even in such a case, the applied voltage can be evenly distributed by connecting a resistor with a sufficiently smaller impedance than each semiconductor element in parallel with the semiconductor element.

[0074] In the power converter 100 according to the present embodiment, the applied voltages distributed between the first diode 3 and the second switching element 6 in the branch region 8 need to be balanced. Therefore, the trimming resistors 10 and 11 are connected in parallel only to the first diode 3 and the second switching element 6, respectively, among the four semiconductor elements (first diode 3, second diode 4, first switching element 5, second switching element) constituting the branch region 8.

[0075] In addition, the resistance values ​​of the trimming resistors 10 and 11 are determined taking into account the impedances of the first diode 3 and the second switching element 6 in the OFF state in order to balance the applied voltages across the first diode 3 and the second switching element 6.

[0076] In Fig. 5 and Fig. 6 is calculated with respect to the impedances of the first diode 3, the second diode 4, the first switching element 5, and the second switching element 6 in the OFF state under the condition that all semiconductor elements have the same impedance value. Furthermore, the calculation is performed under the assumption that the impedances of the first diode 3, the second diode 4, the first switching element 5, and the second switching element 6 in the ON state are zero.

[0077] The following describes a power conversion system in which the configuration of the DC power supply unit 1 is modified.

[0078] Fig. 7 shows the schematic structure of the power conversion system in which the configuration of the DC power supply unit 1 is modified.

[0079] In Fig. 1 shows the example in which a DC power supply is used for the DC power supply unit 1. However, without being limited to this configuration, the DC power supply unit 1 may consist of a three-phase AC power supply 1c as the AC power supply and a diode rectifier 1d that rectifies the output voltage of the three-phase AC power supply 1c.

[0080] Even in the case where the configuration of the DC power supply unit 1 is changed as described above, the power converter 100 according to the present embodiment can be used in the same manner.

[0081] The three-phase AC power supply 1c can be replaced as an AC power supply by a single-phase AC power supply.

[0082] In the above description, the case where the control unit 50 stops the inverter 35 through the protection mode after the smoothing capacitor voltage Vdc becomes an overvoltage is shown. However, even if the inverter 35 is first stopped due to an abnormality in the power converter 100, thereby causing the smoothing capacitor voltage Vdc to become equal to or greater than the reference voltage value, the control unit 50 can execute the protection mode in the same way.

[0083] In the power converter 100 according to the present embodiment configured as described above, in an abnormal case where the smoothing capacitor voltage Vdc is overvoltage, the control unit 50 executes the protection mode to fix the first switching element 5 and the second switching element 6 of the multi-level booster circuit 20 in the OFF state.

[0084] Thus, it is possible to provide the power converter 100 that quickly prevents the application of an overvoltage to each semiconductor element of the branch region 8 of the multi-level booster circuit 20 and suppresses deterioration of the semiconductor elements of the branch region 8, thereby achieving high reliability.

[0085] Furthermore, the trimming resistors 10 and 11 are each connected in parallel with the first diode 3 and the second switching element 6 of the multi-level booster circuit 20. This makes it possible to stabilize the ratio of the applied voltages distributed between the first diode 3 and the second switching element 6, even in the case of large impedance fluctuations of the first diode 3 and the second switching element 6 in the OFF state. This further suppresses deterioration of the semiconductor elements of the branch region 8.

[0086] Furthermore, since the trimming resistors are only provided to the first diode 3 and the second switching element 6, the number of trimming resistors used is small. This allows the size of the hardware device configuration to be reduced.

[0087] Furthermore, the resistance values ​​of the trimming resistors 10 and 11 are set to equalize the voltages applied to the first diode 3 and the second switching element 6. This makes it possible to further stabilize the ratio of the applied voltages distributed between the first diode 3 and the second switching element 6.

[0088] Furthermore, in the abnormal case where the smoothing capacitor voltage Vdc is an overvoltage, the control unit 50 executes the protection mode to stop the switching operations of the switching elements 36 included in the inverter 35, thereby stopping the inverter 35. In a case where the inverter 35 continues to operate when the power converter 100 is abnormal, the inverter 35 is quickly stopped so that the power converter 100 can be stopped. Moreover, even if the smoothing capacitor voltage Vdc continues to rise due to the stoppage of the inverter 35, the semiconductor elements in the multi-level booster circuit 20 are protected from overvoltages by the protection control.

[0089] Furthermore, if it is determined that the smoothing capacitor voltage Vdc has become lower than the reference voltage value after the execution of the protection mode, the control unit 50 cancels the protection mode after a predetermined period of time has elapsed since this determination. This prevents the exceptional protection mode and the normal operation from being repeated frequently, thus preventing deterioration of the components of the power converter 100.

[0090] In the case where the first diode 3 and the second diode 4 in the multi-level booster circuit 20 are replaced with semiconductor switching elements, the control unit 50 performs ON / OFF control for these semiconductor switching elements according to a power / regeneration mode of the multi-level booster circuit 20. Furthermore, in the protection mode, the control unit 50 fixes the first switching element 5 and the second switching element 6 in the OFF state and also fixes the aforementioned semiconductor switching elements in the OFF state. Embodiment 2

[0091] Hereinafter, the present embodiment 2 will be described with reference to the drawings, focusing on components different from the above embodiment 1. The same components as in the above embodiment 1 are denoted by the same reference numerals, and the description thereof will be omitted.

[0092] Fig. 8 is a diagram showing the schematic structure of a power converter system including a power converter 200a according to the present embodiment 2.

[0093] Fig. 9 is a diagram showing the internal configuration of a control unit 250 according to the present embodiment 2.

[0094] Fig. 10 shows the Fig. 9 shows the relationship between the input and output of the gate block units 56, 57, 58, 59.

[0095] In the present embodiment, a step-down circuit 60 is provided between the DC power supply unit 1 and the multi-level booster circuit 20. The step-down circuit 60 has a third switching element 61, the inductor 2, and a freewheeling diode 62.

[0096] The third switching element 61 is connected in series between the DC power supply unit 1 and the input side of the inductor 2 and is turned on and off by pulse width modulation (PWM) so that the DC voltage from the DC power supply unit 1 becomes the target voltage.

[0097] The freewheeling diode 62 is provided such that its cathode side is connected to the connection point between the DC power supply unit 1 and the inductor 2, so that the current output from the output end of the inductor 2 returns to the input end of the inductor 2.

[0098] The third switching element 61 may be formed from a semiconductor element such as an IGBT or MOSFET.

[0099] The step-down circuit 60 and the multi-level boost circuit 20 share the inductance 2.

[0100] By connecting the step-down circuit 60 to the DC power supply unit 1 as described above, the DC voltage can be stepped down. Thus, the step-down circuit 60 and the multi-level booster circuit 20 can form a buck / boost converter with both a step-down and a step-up function, allowing the regulation range of the smoothing capacitor voltage Vdc to be expanded.

[0101] Next, the configuration and control of the control unit 250 will be described with reference to Fig. 9 described.

[0102] The control unit 250 according to the present embodiment 2 further includes a gate signal generation unit 253 for generating a gate signal G4a for the third switching element 61 of the step-down circuit 60, and a gate block unit 259 to which the gate signal G4a is input. The operation of the control unit 250 is almost identical to that of the control unit 50 shown in embodiment 1, but the operation of the gate block unit 259 is different.

[0103] The output signal (gate signal G4) of the gate block unit 259 is determined by the Fig. 10 is determined. Two types of operation methods, i.e., Method A and Method B, can be adopted.

[0104] In method A, in an abnormal case where the smoothing capacitor voltage Vdc is equal to or greater than the reference voltage value (output of the latch unit 52 is 1), the control unit 250 executes the same protection mode as in Embodiment 1 and further fixes the third switching element 61 of the step-down circuit 60 always in the OFF state.

[0105] In method B, in an abnormal case where the smoothing capacitor voltage Vdc is equal to or greater than the reference voltage value, the control unit 250 executes the same protection mode as in Embodiment 1 and also keeps the third switching element 61 of the step-down circuit 60 constantly in the ON state.

[0106] In the case where the step-down circuit 60 is provided, when the smoothing capacitor voltage Vdc becomes an overvoltage, the switching operation of the third switching element 61 by PWM is not performed, and the third switching element 61 is placed in an ON or OFF state as described above.

[0107] Of course, the downshift 60 is not limited to the Fig. 8, but can be changed to another circuit configuration, e.g., a multi-stage circuit configuration.

[0108] The following describes a different configuration of a power converter, which differs from the one described above in Fig. 8 shows the configuration of the power converter 200a.

[0109] Fig. 11 is a diagram showing the schematic structure of a power converter 200b in the present embodiment 2.

[0110] The Fig. The power converter 200b shown in Figure 11 includes a DC power supply unit 1 consisting of the three-phase AC power supply 1c and the diode rectifier 1d of Fig. 7 of embodiment 1, as well as the down-circuit 60 of Fig. 8.

[0111] In the power converter 200a, 200b of the present embodiment configured as described above, the step-down circuit 60 is provided so that the regulation range of the smoothing capacitor voltage Vdc can be expanded. Furthermore, when the smoothing capacitor voltage Vdc is overvoltage, as in Embodiment 1, the control unit 250 fixes the first switching element 5 and the second switching element 6 of the multi-level booster circuit 20 in the OFF state and executes the protection mode to stop the switching operations of the switching elements 36 in the inverter 35. Furthermore, in the protection mode, the control unit 250 fixes the third switching element 61 of the step-down circuit 60 in an ON state or an OFF state, so that the power converter 100 can be stopped accordingly.

[0112] Thus, the power converter 200a, 200b can quickly prevent excessive voltage from being applied to the semiconductor elements in the power converter 200a, 200b, thus achieving high reliability. The three-phase AC power supply 1c can be replaced with a single-phase AC power supply as the AC power supply. Embodiment 3

[0113] Hereinafter, the present embodiment 3 will be described with reference to the drawings, focusing on components different from the above embodiment 1. The same components as in the above embodiment 1 are denoted by the same reference numerals, and their description will be omitted.

[0114] Fig. 12 is a diagram showing the schematic structure of a power converter system including a power converter 300a according to the present embodiment 3.

[0115] Fig. 13 is a diagram showing the schematic configuration of a power converter system including a power converter 300b having a different configuration from that shown in Fig. 12 has the power converter 300a shown.

[0116] Fig. 14 is a diagram showing the schematic configuration of a power converter system including a power converter 300c having a configuration different from the Fig. 12 and Fig. 13 shown power converters 300a, 300b.

[0117] The embodiment now described differs from Embodiment 1 in the number and arrangement of trimming resistors for stabilizing the ratio of applied voltages distributed among the semiconductor elements of the branch region 8 of the multi-level booster circuit 20.

[0118] In the Fig. In the power converter 300a shown in Figure 12, in addition to the trimming resistors 10 and 11 shown in embodiment 1, a trimming resistor 212 is connected in series and in parallel with the intermediate capacitor 7, ie connected in parallel with the second diode 4 and the first switching element 5.

[0119] Thus, regardless of the charge / discharge state of the intermediate capacitor 7, the ratio of the applied voltages distributed among the semiconductor elements of the branch region 8 can be reliably stabilized.

[0120] In the Fig. In the power converter 300b shown in Fig. 13, in addition to the trimming resistors 10 and 11 shown in Embodiment 1, the trimming resistors 213 and 214 are connected to the second diode 4 and the first switching element 5, respectively.

[0121] Thus, regardless of the impedances of the second diode 4 and the first switching element 5 in the OFF state, the ratio of the applied voltages distributed to the semiconductor elements of the branch region 8 can be reliably stabilized.

[0122] In the Fig. No trimming resistors are provided in the power converter 300c shown in Figure 14.

[0123] In the event that the impedances of the first diode 3 and the second switching element 6 fluctuate only slightly in the OFF state and therefore there is no risk of exceeding the dielectric strengths of the semiconductor elements, a configuration without trimming resistors, as described above, can be selected. This allows the size of the hardware device configuration to be reduced.

[0124] In each of the power converters 300a, 300b, 300c, the step-down circuit 60 may be added as in Embodiment 2, or the DC power supply unit 1 may be composed of the three-phase AC power supply 1c and the diode rectifier 1d.

[0125] In the power converter 300a of the present embodiment, with the configuration described above, the trimming resistor 212 is connected in parallel with the intermediate capacitor 7, so that the ratio of the applied voltages distributed to the semiconductor elements of the branch region 8 can be stabilized regardless of the discharge state of the intermediate capacitor 7. This further reliably prevents excessive voltage from being applied to the semiconductor elements of the branch region 8 of the multi-level booster circuit 20.

[0126] In the power converter 300b of the present embodiment, with the configuration described above, the trimming resistors 213, 214 are connected to the second diode 4 and the first switching element 5, respectively, so that the ratio of the applied voltages distributed to the semiconductor elements of the branch region 8 can be stabilized regardless of the impedances of the second diode 4 and the first switching element 5 in the OFF state. This further reliably prevents excessive voltage from being applied to the semiconductor elements of the branch region 8 of the multi-level booster circuit 20.

[0127] This demonstrates a power converter that quickly and safely prevents the application of overvoltages to the semiconductor elements in the power converter and thus achieves high reliability.

[0128] In the power converter 300c of the present embodiment configured as described above, no trimming resistors are provided, and thus the size of the hardware device configuration can be reduced. Embodiment 4

[0129] Hereinafter, the present embodiment 4 will be described with reference to the drawings, focusing on the components different from the above embodiment 2. The same components as in the above embodiment 2 are denoted by the same reference numerals, and their description will be omitted.

[0130] Fig. 15 is a diagram showing the schematic structure of a power converter system including a power converter 400 according to the present embodiment 3.

[0131] Fig. 16 is a diagram showing the internal configuration of a control unit 450 in the present embodiment 4.

[0132] Fig. 17 shows the Fig. 16 shows the relationship between the input and output of the gate block units 56, 57, 58, 259, 460.

[0133] The power converter 400 of the present embodiment differs in the configuration of a step-down circuit 460 and control in the control unit 450, compared to that in Fig. 8 shown power converter 200a of embodiment 2.

[0134] The step-down circuit 460 is achieved by replacing the freewheeling diode 62 in the step-down circuit 60 of Embodiment 2 with a fourth switching element 463 and causing synchronous rectification by the fourth switching element 63, so that the step-down circuit 460 is operated with high efficiency. As shown in Fig. As shown in Fig. 15, a MOSFET is used as the fourth switching element 463, which is turned on when the current flows back, so that the conduction loss can be reduced compared to the case of the freewheeling diode 62.

[0135] Next, the configuration and control of the control unit 450 will be described with reference to Fig. 16 and Fig. 17 described.

[0136] In the control unit 450 of the present embodiment 4, the gate signal generation unit 253 of the step-down circuit 460 generates the gate signal G4a for the third switching element 61 and additionally generates a gate signal G5a for the fourth switching element 463. The control unit 450 further includes the gate block unit 460 to which the gate signal G5a is input.

[0137] The operation of the control unit 450 is almost identical to the operation of the control unit 250 shown in Embodiment 2. The operation of the added gate block unit 460 will be described below.

[0138] The output signal (gate signal G5) of the gate block unit 460 is determined by the Fig. 17 is determined. As in Embodiment 2, two types of operation, namely, Method A and Method B, can be applied. In both Method A and Method B, the control unit 450 constantly fixes the switching state of the fourth switching element 463 in the OFF state when the output of the latch unit 52 is 1.

[0139] In the protection mode, i.e., when the smoothing capacitor voltage Vdc is an overvoltage, the control unit 450 constantly fixes the fourth switching element 463 in the OFF state without performing the synchronous rectification operation of the step-down circuit 460. In this way, it is possible to stop the power converter 400 accordingly when the smoothing capacitor voltage Vdc is overvoltage. List of reference symbols 1 DC power supply unit 2 Inductance 3 first diode 4 second diode 5 first switching element 6 second switching element 7 Intermediate capacitor 8 Branch area 30 smoothing capacitor 35 inverters 36 switching element 40 AC motor 51 Comparison facility 52 Buffer unit 61 third switching element 62 Diode 463 fourth switching element 10, 11, 212, 213, 214 trimming resistor 100, 200a, 200b, 300a, 300b, 300c, 400 power converters 1c AC power supply 1d diode rectifier 30A voltage detection device 50, 250, 450 control unit 53, 54, 55, 253 Gate signal generating unit 56, 57, 58, 460 Gateblock unit 60, 460 downshift G1, G2, G3 gate signal Vdc smoothing capacitor voltage Vdcref comparison signal Vm intermediate capacitor voltage

Claims

A power converter (100, 200a, 200b, 300a, 300b, 300c, 400) comprising:- a boost converter (20) for boosting the output voltage of a DC power supply unit (1);- a smoothing capacitor (30) for smoothing the output voltage of the boost converter (20);- an inverter (35) for converting the voltage of the smoothing capacitor (30) into an AC voltage; and- a control unit (50, 250, 450) for controlling the boost converter (20) and the inverter (35), wherein the boost converter (20) comprises: an inductor (2) having a first end connected to the DC power supply unit (1), a branch region (8) having four semiconductor elements comprising a first semiconductor element (3), a second semiconductor element (4), a first semiconductor switching element (5), and a second semiconductor switching element (6), each of which controls the conduction and interruption of current,wherein the four semiconductor elements are connected in series between positive and negative terminals of the smoothing capacitor (30), wherein a second end of the inductor (2) is connected to a connection point between the second semiconductor element (4) and the first semiconductor switching element (5), and an intermediate capacitor (7) connected between a connection point of the first semiconductor element (3) and the second semiconductor element (4) and a connection point of the first semiconductor switching element (5) and the second semiconductor switching element (6), wherein the control unit (50, 250, 450) in a normal mode performs ON / OFF control for the first semiconductor switching element (5) and the second semiconductor switching element (6) in each control cycle to cause the boost converter (20) to output multi-level voltages, and when the voltage of the smoothing capacitor (30) is equal to or greater than a reference voltage value,executes a protection mode to stop a switching operation of semiconductor elements of the inverter (35) and to fix the first semiconductor switching element (5) and the second semiconductor switching element (6) in the OFF state for a period longer than the control cycle., The power converter (100, 200a, 200b) according to claim 1, wherein the boost converter (20) includes a plurality of trimming resistors (10, 11) for stabilizing the ratio of applied voltages distributed among the semiconductor elements of the branch region (8), and wherein the trimming resistors (10, 11) are each connected in parallel only to the first semiconductor element (3) and the second semiconductor switching element (6) among the first semiconductor element (3), the second semiconductor element (4), the first semiconductor switching element (5), and the second semiconductor switching element (6) of the branch region (8). The power converter (300a) according to claim 1, wherein the boost converter (20) includes a plurality of trimming resistors (10, 11, 212) for stabilizing the ratio of applied voltages distributed among the semiconductor elements of the branch region (8), and wherein the trimming resistors (10, 11, 212) are each connected in parallel to the first semiconductor element (3), the second semiconductor switching element (6), and the intermediate capacitor (7). The power converter (300b) according to claim 1, wherein the boost converter (20) includes a plurality of trimming resistors (10, 11, 213, 214) for stabilizing a ratio of applied voltages distributed among the semiconductor elements of the branch region (8), and wherein the trimming resistors (10, 11, 213, 214) are each connected in parallel to the first semiconductor element (3), the second semiconductor element (4), the first semiconductor switching element (5), and the second semiconductor switching element (6). Power converter (100, 200a, 200b) according to one of claims 2 to 4, wherein the trimming resistors (10, 11), which are each connected in parallel to the first semiconductor element (3) and the second semiconductor switching element (6), have resistance values which are predetermined such that applied voltages to the first semiconductor element (3) and the second semiconductor switching element (6) are balanced. A power converter (200a, 200b, 400) according to any one of claims 1 to 5, further comprising:- a step-down circuit (60, 460) having a third switching element (61) provided between the DC power supply unit (1) and the step-up converter (20), wherein in the protection mode, the control unit (50, 250) fixes the third switching element (61) of the step-down circuit (60, 460) in an ON state or OFF state. The power converter (400) according to claim 6, wherein the step-down circuit (460) further includes a fourth switching element (463), the third switching element (61) is connected in series between the DC power supply unit (1) and the first end of the inductor (2), the fourth switching element (463) being arranged so that the current output from the second end of the inductor (2) returns to the first end of the inductor (2), and wherein in the protection mode, the control unit (450) fixes the third switching element (61) in an ON state or OFF state and fixes the fourth switching element (463) in an OFF state. Power converter (100, 200a, 200b, 300a, 300b, 300c, 400) according to one of claims 1 to 7, wherein in the protection mode the control unit (50, 250, 450) stops the switching operation of a switching element contained in the inverter (35). Power converter (100, 200a, 200b, 300a, 300b, 300c, 400) according to one of claims 1 to 8, wherein the control unit (50, 250, 450) cancels the protection mode after a predetermined period of time has elapsed after the voltage of the smoothing capacitor (30) has become smaller than the reference voltage value.

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