Semiconductor unit and power converter

Abstract

Semiconductor unit with a semiconductor region (40) having a first principal surface and a second principal surface opposite the first principal surface, wherein the semiconductor region has the following: - alternating first support layers (13) with a first conductivity type and second support layers (14) with a second conductivity type along the first main surface; - a first trough layer (21) with the second conductivity type, located within each of the first support layers (13) on an upper surface of the first support layer (13); - a first source layer (22) with the first conductivity type, which is located within the first trough layer (21) on an upper surface of the first trough layer (21); - a first dielectric layer (35) on a lateral surface, which is located on a lateral surface in a first trench (74) which is located at boundaries between the first support layers (13) and the second support layers (14), wherein the first dielectric layer on the lateral surface is in contact with the first trough layer (21) and the first source layer (22); - a first dielectric layer (36) on a soil surface located on a soil surface in the first trench, wherein the first dielectric layer (36) on the soil surface is at least partially in contact with one of the second support layers (14); and - a first gate electrode (71) located in the first trench, opposite the first trough layer (21) and the first source layer (22) by the first dielectric layer (35) on the lateral surface and opposite the second support layer (14) by the first dielectric layer (36) on the bottom surface, - wherein each of the second support layers (14) has a second source layer (27) of the first conductivity type located within the second support layer on an upper surface of the second support layer, - wherein the first dielectric layer (35) is located on opposite lateral surfaces in the first trench and is in contact with an area (26) with the second conductivity type within the second support layer (14) and the second source layer (27), - wherein the first dielectric layer on the bottom surface is in contact with the area with the second conductivity type within the second support layer (14) and - wherein a lower surface of the second source layer (27) is located closer to the second main surface than a lower surface of the first source layer (22) is located.

Description

TECHNICAL AREA

[0001] The present invention relates to semiconductor units, power converters and to methods for manufacturing semiconductor units. STATE OF THE ART

[0002] In power electronics, a switching element, such as a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT), is used to drive a motor load. Such a switching element is operated by switching it between a low-resistance on state and a high-resistance off state via a control signal. It is important for the switching element to exhibit a high breakdown voltage in the off state, as power electronics applications process high voltage inputs.

[0003] The high breakdown voltage is typically maintained by the propagation of a depletion layer up to a drift layer. A higher breakdown voltage can be achieved if the drift layer has a greater thickness, and a higher breakdown voltage can be achieved if the drift layer has a lower defect concentration, as the depletion layer becomes wider.

[0004] On the other hand, it is necessary for the switching element to have low resistance in the on-state to reduce conduction losses. The resistance of the drift layer is a component of the on-resistance and should ideally be as low as possible. The resistance of the drift layer can be reduced by decreasing the thickness of the drift layer or by increasing the impurity concentration within the drift layer.

[0005] As described above, a high breakdown voltage cannot be achieved if the drift layer has a small thickness and a high concentration of defects. Therefore, a compromise exists between the breakdown voltage in the off-state and the on-resistance in the on-state.

[0006] As a structure for improving the compromise between the breakdown voltage in the off-state and the on-state resistance, a superjunction structure has already been proposed, as disclosed in patent document 1. The superjunction structure has strip-shaped n-type support layers and strip-shaped p-type support layers alternating in a direction perpendicular to a direction of current flow, maintaining an equilibrium such that the effective amounts of defects in the respective support layers are equal.

[0007] The effective amount of impurities refers to the amount of impurities that effectively act as acceptors in a p-type semiconductor and the amount of impurities that effectively act as donors in an n-type semiconductor.

[0008] By using a superjunction structure, the trade-off between the off-state breakdown voltage and the on-state resistance, a problem inherent in conventional switching elements, can be improved. That is, compared to a conventional switching element, for example, a semiconductor device with a superjunction structure can reduce the on-state resistance while maintaining the breakdown voltage, and it can also improve the breakdown voltage while maintaining the on-state resistance.

[0009] Patent document 2 describes a superjunction layer comprising first pillars of a first conductivity type and second pillars of a second conductivity type. First wells are arranged on the second pillars such that they reach the first pillars and are of the second conductivity type. First doping regions are arranged on the first wells and belong to the first conductivity type. Second wells are arranged on the first pillars, spaced apart from the second pillars as seen in a cross-section through an active region perpendicular to a semiconductor layer, and belong to the second conductivity type. Second doping regions are arranged on the second wells and belong to the first conductivity type. State of the Art Document (Patent Document) Patent document 1: JP 2006 - 313 892 A Patent document 2: DE 11 2017 007 907 T5 SHORT DESCRIPTION Problem to be solved with the invention

[0010] A bottom surface in a trench of a semiconductor element according to patent document 1 is in contact with an n-type support layer. As a result, an electrical breakdown may occur due to the concentration of an electric field at the bottom of the trench.

[0011] One object of the present invention is to reduce the concentration of an electric field at the bottom of a trench in order to solve the aforementioned problem, thereby resulting in a highly reliable semiconductor unit. Means to solve the problem

[0012] The problem underlying the invention is solved by a semiconductor unit with the features of independent claim 1 or a power converter with the features of independent claim 16. Advantageous embodiments of the invention are specified in dependent claims 2 to 15. Effects of the invention

[0013] The semiconductor device according to the present invention comprises the first dielectric layer on the base surface, located in the first groove on the base surface, and the first gate electrode, located in the first groove. The first dielectric layer on the side surface is opposite the first trough layer and the first source layer, and the second support layer is opposite the first dielectric layer on the base surface. As a result, the electric field applied to the first dielectric layer on the base surface is reduced by the second support layer, which is depleted when the semiconductor device is off. This effect results in a highly reliable semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The figures show: Fig. 1 a cross-sectional view along a line AA' of a semiconductor unit according to embodiment 1 of the present invention; Fig. 2 a top view showing an upper surface of a semiconductor area of ​​the semiconductor unit according to embodiment 1 of the present invention; Fig. 3 a cross-sectional view along the line A-A' showing an operation of the semiconductor unit according to embodiment 1 of the present invention; Fig. 4 a method for manufacturing the semiconductor unit according to embodiment 1 of the present invention; Fig. 5 the method for manufacturing the semiconductor unit according to embodiment 1 of the present invention; Fig. 6 the method for manufacturing the semiconductor unit according to embodiment 1 of the present invention; Fig. 7 the method for manufacturing the semiconductor unit according to embodiment 1 of the present invention; Fig. 8 the method for manufacturing the semiconductor unit according to embodiment 1 of the present invention; Fig. 9 the method for manufacturing the semiconductor unit according to embodiment 1 of the present invention; Fig. 10 the method for manufacturing the semiconductor unit according to embodiment 1 of the present invention; Fig. 11 the method for manufacturing the semiconductor unit according to embodiment 1 of the present invention; Fig. 12 the method for manufacturing the semiconductor unit according to embodiment 1 of the present invention; Fig. 13 a cross-sectional view along a line BB' of a semiconductor unit according to embodiment 2 of the present invention; Fig. 14 a top view of the semiconductor unit according to embodiment 2 of the present invention; Fig. 15 a cross-sectional view along the line B-B' showing an operation of the semiconductor unit according to embodiment 2 of the present invention; Fig. 16 a cross-sectional view along a line CC' of a semiconductor unit according to embodiment 3 of the present invention; Fig. 17 a top view showing an upper surface of a semiconductor area of ​​the semiconductor unit according to embodiment 3 of the present invention; Fig. 18 a cross-sectional view along a line DD' of a semiconductor unit according to embodiment 4 of the present invention; Fig. 19 a top view showing an upper surface of a semiconductor area of ​​the semiconductor unit according to embodiment 4 of the present invention; Fig. 20 a cross-sectional view along a line EE' of a semiconductor unit according to embodiment 5 of the present invention; Fig. 21 a top view showing an upper surface of a semiconductor area of ​​the semiconductor unit according to embodiment 5 of the present invention; Fig. 22 a cross-sectional view along a line FF' of a semiconductor unit according to embodiment 6 of the present invention; Fig. 23 a top view showing an upper surface of a semiconductor area of ​​the semiconductor unit according to embodiment 6 of the present invention; Fig. 24 a cross-sectional view along a line GG' of a semiconductor unit according to embodiment 7 of the present invention; Fig. 25 a top view showing an upper surface of a semiconductor area of ​​the semiconductor unit according to embodiment 7 of the present invention; Fig. 26 a cross-sectional view along a line HH' of a semiconductor unit according to embodiment 8 of the present invention; Fig. 27 a top view showing an upper surface of a semiconductor area of ​​the semiconductor unit according to embodiment 8 of the present invention; Fig. 28 a cross-sectional view along a line II' of the semiconductor unit according to embodiment 8 of the present invention; Fig. 29 a cross-sectional view along line II' of the semiconductor unit according to embodiment 8 of the present invention; Fig. 30 a cross-sectional view along line JJ' of a semiconductor unit according to embodiment 9 of the present invention; Fig. 31 a top view showing an upper surface of a semiconductor area of ​​the semiconductor unit according to embodiment 9 of the present invention; Fig. 32 a cross-sectional view along a line KK' of a semiconductor unit according to embodiment 10 of the present invention; Fig. 33 a top view showing an upper surface of a semiconductor area of ​​the semiconductor unit according to embodiment 10 of the present invention; Fig. 34 a cross-sectional view along a line LL' of a semiconductor unit according to embodiment 11 of the present invention; Fig. 35 a top view showing an upper surface of a semiconductor area of ​​the semiconductor unit according to embodiment 11 of the present invention; Fig. 36 a cross-sectional view along a line MM' of the semiconductor unit according to embodiment 11 of the present invention; Fig. 37 a cross-sectional view along the line MM' of the semiconductor unit according to embodiment 11 of the present invention; Fig. 38 a cross-sectional view along a line NN' of a semiconductor unit according to embodiment 12 of the present invention; Fig. 39 a top view showing an upper surface of a semiconductor area of ​​the semiconductor unit according to embodiment 12 of the present invention; Fig. 40 a cross-sectional view along a line OO' of a semiconductor unit according to embodiment 13 of the present invention; Fig. 41 a top view showing an upper surface of a semiconductor area of ​​the semiconductor unit according to embodiment 13 of the present invention; Fig. 42 a cross-sectional view along a line PP' of a semiconductor unit according to embodiment 14 of the present invention; Fig. 43 a top view showing an upper surface of a semiconductor area of ​​the semiconductor unit according to embodiment 14 of the present invention; Fig. 44 a functional block diagram of a power converter according to embodiment 15 of the present invention. DESCRIPTION OF EXECUTION FORMS Execution form 1

[0015] The following describes a configuration according to the present embodiment using the Fig. 1 and Fig. 2. The present description is based on the assumption that the semiconductor unit is a silicon carbide MOSFET, that the first conductivity type is an n-type, and that the second conductivity type is a p-type. The use of silicon carbide as the material for the semiconductor unit allows for lower losses and a higher operating temperature.

[0016] Fig. Figure 1 is a cross-sectional view of a semiconductor unit according to the present embodiment along an auxiliary line AA' of Fig. 2. Fig. Figure 2 is a top view showing an upper surface of a semiconductor area of ​​the semiconductor unit according to the present embodiment.

[0017] As in Fig. As shown in Figure 1, the semiconductor unit according to the present embodiment comprises the following: a semiconductor region 40, dielectric intermediate layers 33, ohmic electrodes 81 on the front surface, a source electrode 82, an ohmic electrode 91 on the rear surface, and a drain electrode 92. The semiconductor region 40 comprises: an n-type silicon carbide substrate 11 with a lower resistance than a semiconductor substrate, an n-type epitaxial crystalline layer 12, and a superjunction layer 15, which includes n-type support layers 13 as first support layers and p-type support layers 14 as second support layers. Each of the n-type support layers 13 includes a first p-type well layer 21 and a first n-type source layer 22.+ -type as well as a first layer 23 of p+-type. Each of the support layers 14 of p-type has a second layer 52 of p+-type.

[0018] Semiconductor region 40 has a first principal surface and a second principal surface. The first principal surface is a surface of semiconductor region 40 on the upper side of the sheet of Fig. 1. The second main surface is a surface of semiconductor area 40 on the lower side of the sheet of Fig. 1. That is, the second main surface is located opposite the first main surface.

[0019] The silicon carbide substrate 11 exhibits an n +-type. The silicon carbide substrate 11 is located within the semiconductor region 40 on the second main surface. A surface of the silicon carbide substrate 11 on one side of the first main surface is, for example, inclined at an offset angle of 4° with respect to a (0001) plane in a [11-20] direction. The polytype of the silicon carbide substrate 11 is, for example, 4H. The n + -Type denotes a higher concentration of defects than that of the n-type.

[0020] The epitaxial crystalline layer 12 of n-type is formed on the upper surface of the silicon carbide substrate 11. The epitaxial crystalline layer 12 consists of silicon carbide, which, for example, has a concentration of n-type defects of 1 × 10 13 cm -3 up to 1 × 10 18 cm -3 and has a thickness of 5 µm to 150 µm.

[0021] The superjunction layer 15 is located on an upper surface of the epitaxial crystalline layer 12. The superjunction layer 15 has alternating strip-shaped n-type support layers 13 and strip-shaped p-type support layers 14 along the first major surface of the semiconductor region 40. An equilibrium is maintained such that the effective amount of n-type defects in a region of each of the n-type support layers 13, which is distinct from the first trough layer 21 described below, and the effective amount of p-type defects in each of the p-type support layers 14 are equal. As shown in Fig. As shown in Figure 2, the support layers 13 of n-type and the support layers 14 of p-type are formed in strips in a top view. That is, the superjunction layer 15 has a strip-like shape in a top view.

[0022] The first p-type trough layer 21 is selectively located within each of the n-type support layers 13 on an upper surface of the n-type support layers 13. The first trough layers 21 are formed in strips in a top view. Aluminum (Al) is used for p-type defects. The first n-type source layer 22 + The -type is selectively located within the first trough layer 21 on an upper surface of the first trough layer 21. As in Fig. As shown in Figure 2, the first source layers 22 according to the present embodiment are formed in strips in a top view. Nitrogen (N) is used for defects of the n type.

[0023] The first trough layer 21 has a depth of, for example, approximately 0.5 µm to 3 µm. The first trough layer 21 exhibits a higher defect concentration than the epitaxial crystalline layer 12 and, for example, has a defect concentration in the range of 1 × 10⁻⁶17 cm -3 up to 1 × 10 19 cm -3 The first source layer 22 exhibits a defect concentration, for example, in the range of 1 × 10 18 cm -3 up to 1 × 10 21 cm -3 and the n-type defects introduced by ion implantation have a concentration that exceeds the concentration of the p-type defects of the first trough layer 21.

[0024] The first trenches 74 are located at the boundaries between the n-type support layers 13 and the p-type support layers 14. Each of the first trenches 74 has a lateral surface and a bottom surface. The entirety of the first trench 74 lies within the p-type support layer 14. The bottom surface of the first trench 74 is located at a lower position than the first depression layer 21. As in Fig. As shown in Figure 2, the trenches 74 are formed in strips in a top view.

[0025] As in Fig. As shown in Figure 1, the lateral surface of each of the first trenches 74 runs perpendicular to the silicon carbide substrate 11, and the bottom surface of the first trench 74 is parallel to the silicon carbide substrate 11. However, the lateral surface of the first trench 74 does not necessarily have to be perpendicular to the silicon carbide substrate 11. The bottom surface of the first trench 74 does not necessarily have to be parallel to the silicon carbide substrate 11.

[0026] A first dielectric layer 35, consisting of silicon dioxide, is formed in its entirety on the lateral surface of the first trench 74. A first dielectric layer 36, also consisting of silicon dioxide, is formed in its entirety on the bottom surface of the first trench 74. The first dielectric layer 35 on the lateral surface is in contact with the first trough layer 21 and the first source layer 22. The first dielectric layer 36 on the bottom surface is in contact with the p-type support layer 14.

[0027] The first gate electrodes 71 are located in the first grooves 74. Each of the first gate electrodes 71 faces the first trough layer 21 and the first source layer 22 through the first dielectric layer 35 on its lateral surface. The first gate electrode 71 faces the p-type support layer 14 through the first dielectric layer 36 on its bottom surface. Doped polysilicon, for example, is used as a material for the first gate electrodes 71.

[0028] As in Fig. As shown in Figure 1, the first p+-type layer 23 is formed in a region of the upper part of the first trough layer 21 that is not in contact with the first dielectric layer 35 on the lateral surface. The first p+-type layer 23 is in contact with the first trough layer 21. The p+ type denotes a higher impurity concentration than that of the p type. As shown in Fig. As shown in Figure 2, the first layers 23 of the p+ type are formed in strips in a top view.

[0029] As in Fig. As shown in Figure 1, the second p+-type layer 52 is formed in a region of an upper area of ​​the p-type support layer 14, which is not in contact with the first dielectric layer 35 on the lateral surface. As shown in Fig. As shown in Figure 2, the second layers 52 of the p+ type are formed in strips in a top view.

[0030] The first p+-type layers 23 are located on the front surface, described below, to improve electrical contact between the first trough layers 21 and the ohmic electrodes 81. The second p+-type layers 52 are located on the front surface, described below, to improve electrical contact between the p-type support layers 14 and the ohmic electrodes 81.

[0031] Each of the first p+-type layers 23 and the second p+-type layers 52 desirablely has a higher impurity concentration than the first trough layer 21 and, for example, has an impurity concentration in the range of 1 × 10 19 cm -3 up to 1 × 10 21 cm -3 This is because each of the first layers 23 of the p+ type and the second layers 52 of the p+ type desirablely exhibits low resistance.

[0032] As in Fig. As shown in Figure 1, the ohmic electrodes 81 are located on the front surface of the first source layer 22, the first p+-type layer 23, and the second p+-type layer 52. Furthermore, the source electrode 82 is located on the ohmic electrodes 81 on the front surface. The source electrode 82 is electrically connected to the first source layer 22, the first p+-type layer 23, and the second p+-type layer 52 via the ohmic electrodes 81 on the front surface. The ohmic electrodes 81 on the front surface reduce the contact resistance between the source electrode 82 and the first source layer 22, the first p+-type layer 23, and the second p+-type layer 52.

[0033] As in Fig. As shown in Figure 1, the dielectric intermediate layers 33 are located between the source electrode 82 and the first gate electrodes 71, and between the source electrode 82 and the p-type support layers 14. The first gate electrodes 71 and the source electrode 82 are electrically insulated from each other by the dielectric intermediate layers 33.

[0034] According to Fig. 1. A region of each of the dielectric intermediate layers 33 is located on an upper surface of the first source layer 22. However, this region of each of the dielectric intermediate layers 33 need not be located on the upper surface of the first source layer 22. It is possible that a region of each of the dielectric intermediate layers 33 is located on an upper surface of the second p+-type layer 52, or it may not be.

[0035] As in Fig. As shown in Figure 1, the drain electrode 92 is formed by the ohmic electrode 91 on the rear surface on one side of the second main surface of the semiconductor region 40. Gold, other metals, or a stack thereof are used for the drain electrode 92.

[0036] Next, the operation of the semiconductor unit according to the present embodiment will be described. Fig. Figure 3 is a cross-sectional view along line A-A', showing the operation of the semiconductor unit according to the present embodiment. When a voltage higher than a specific voltage value (a first threshold voltage) is applied to each of the first gate electrodes 71, a channel forms in a region within the first trough layer 21, which is in contact with the first dielectric layer 35 on the lateral surface.

[0037] As a result, the resistance between the drain electrode 92 and the source electrode 82 has a lower value, and by applying a positive voltage to the drain electrode 92, a current flows between the drain electrode 92 and the source electrode 82 in the direction of an arrow 501 (on state).

[0038] The aforementioned channel disappears, however, when a voltage lower than the first threshold voltage is applied to each of the first gate electrodes 71. As a result, the resistance between the drain electrode 92 and the source electrode 82 of the semiconductor unit has a higher value, and a very small current flows (off state).

[0039] Next, a method for manufacturing the semiconductor unit according to the present embodiment is described. Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11 to Fig. Figure 12 describes the method for fabricating the semiconductor unit according to the present embodiment. There are essentially two types of methods for fabricating a superjunction structure: a multi-epitaxial concept and a trench-filling concept. The multi-epitaxial concept involves repeating the epitaxial growth of an n-type semiconductor layer and the ion implantation of p-type defects.

[0040] In the superjunction structure, increasing the depth of the p-type support layers effectively improves breakdown voltage. In the multi-epitaxial concept, the number of repetitions is determined by the depth to which ions can be implanted. For example, if a superjunction layer is formed with a depth of 10 µm, the epitaxial growth and ion implantation must be repeated ten times if ions can be implanted to a depth of 1 µm.

[0041] In contrast, the trench-filling concept involves growing a semiconductor layer with n-type conductivity epitaxially to the required thickness for the superjunction layer. Trenches are then formed by an anisotropic etching process, and p-type conductivity semiconductor layers are subsequently embedded in these trenches by epitaxial growth. The trench-filling concept requires fewer process steps than the multi-epitaxial concept mentioned above. The semiconductor device fabrication method described in the present embodiment is the fabrication method employing the trench-filling concept.

[0042] First, the silicon carbide substrate 11 is removed from the n + -Type manufactured as in Fig. 4. Next, the epitaxial crystalline layer 12 of n-type is epitaxially grown on the silicon carbide substrate 11 by chemical vapor deposition (CVD), as shown in Fig. Figure 5 illustrates this. As described below, the n-type support layers 13 are formed from the epitaxial crystalline layer 12. The thickness of the epitaxial crystalline layer 12 is predetermined as required by the thickness of the n-type support layers 13.

[0043] Next, an oxide layer 17 is deposited on the surface of the epitaxial crystalline layer 12. The oxide layer 17 is deposited to serve as a mask when an etching process is carried out in a subsequent step to form the p-type support layers 14. The thickness of the oxide layer 17 is predetermined according to the thickness of the p-type support layers 14.

[0044] After the deposition of the oxide layer 17, as in Fig. Figure 6 shows that p-type mask structures are produced using a photoresist to form the support layers 14, which are formed from the oxide layer 17.

[0045] Next, the epitaxial crystalline layer 12 is etched (first etching process). As in Fig. As shown in Figure 7, the mask structures formed from the oxide layer 17 are deposited on the surface of the epitaxial crystalline layer 12 with a spacing between them. Thus, a plurality of support-forming trenches 18 are formed in the epitaxial crystalline layer 12 with a spacing between them. The p-type support layers 14, which are formed in a subsequent process, have the shapes of the support-forming trenches 18, so it is desirable to etch the epitaxial crystalline layer 12 by means of a dry etching process, in which it is easier to control the shapes of the support-forming trenches 18.

[0046] Next, an epitaxial crystalline silicon carbide layer 19 of the p-type is grown in the support-forming trenches 18 by epitaxial growth (process for growing crystals), as shown in Fig. Figure 8 shows the impurity concentration of the epitaxial crystalline silicon carbide layer 19 of the p-type is specified such that the effective amount of impurities in the region of each of the support layers 13 of the n-type, which differs from the first trough layer 21, and the effective amount of impurities in each of the support layers 14 of the p-type are equal, i.e., that equilibrium is maintained.

[0047] As in Fig. As shown in Figure 9, a region of the p-type epitaxial crystalline layer 19 and a region of the n-type epitaxial crystalline layer 12 are removed by chemical-mechanical polishing (CMP) to expose the n-type epitaxial crystalline layer 12 on one side of the upper surface of the silicon carbide substrate 11. The n-type support layers 13 are formed from regions of the n-type epitaxial crystalline layer 12 exposed on the upper surface of the silicon carbide substrate 11. The p-type support layers 14 are formed from the p-type epitaxial crystalline layer 19. The superjunction layer 15 is formed from the n-type support layers 13 and the p-type support layers 14.

[0048] Next, an implantation mask is formed using a photoresist and the like, and Al ions are implanted as p-type defects into an upper region of each of the n-type support layers 13 to form the first trough layer 21 with the second conductivity type within the n-type support layer 13 on the upper surface of the n-type support layer 13, as in Fig. Figure 10 shows the first ion implantation process. After completion of the ion implantation, the implantation mask is removed.

[0049] Next, an implantation mask is formed using a photoresist and the like, and N ions are implanted as n-type defects into an upper region of the first well layer 21 to form the first source layer 22 with the first conductivity type within the first well layer 21 at the upper surface of the first well layer 21, as in Fig. Figure 10 shows the second ion implantation process. After completion of the ion implantation, the implantation mask is removed.

[0050] The first source layer 22 has a shallower depth than the first trough layer 21. The channel length is determined by a difference in depth between the first source layer 22 and the first trough layer 21, so it is only necessary to specify the depth of the first source layer 22 to achieve the desired electrical properties. Next, an implantation mask is formed using a photoresist and the like, and Al ions as p-type impurities are implanted into an upper region of each of the p-type support layers 14 and an upper region of the first source layer 22 to simultaneously form the first p+-type layer 23 and the second p+-type layer 52, as shown in Fig. Figure 10 is shown. After completion of the ion implantation, the implantation mask is removed.

[0051] The first trough layer 21, the first source layer 22, the first p+-type layer 23 and the second p+-type layer 52 can be formed in any order and do not necessarily have to be formed in the process sequence mentioned above.

[0052] Next, a tempering process is carried out in an inert gas atmosphere, such as an argon (Ar) gas atmosphere, or in a vacuum, for example for 30 seconds or one hour at 1500 °C to 2100 °C. The implanted Al and N ions are electrically activated by the tempering process.

[0053] As in Fig. As shown in Figure 11, the first trenches 74 are formed next (second etching process). In particular, an etching mask is first formed using a resist and the like, such that areas having at least the p-type support layers 14 are etched at the boundaries between the n-type support layers 13 and the p-type support layers 14. The first trenches 74 are then formed by means of an etching process, and finally the etching mask is removed.

[0054] It is not absolutely necessary to use the oxide layer 17 for the mask structures, and a resist mask or the like can be used. The tempering process and the process for producing the first trenches 74 can be carried out in any order, and the tempering process can be carried out after the formation of the first trenches 74.

[0055] Next, silicon oxide layers are formed on the lateral surface and the bottom surface of each of the first trenches 74 by means of thermal oxidation or CVD (process for producing dielectric layers). The first dielectric layer 35 on the lateral surface and the first dielectric layer 36 on the bottom surface are thereby formed on the lateral surface and on the bottom surface of the first trench 74, as shown in Fig. Figure 12 shows the first dielectric layer 35 on the side surface and the first dielectric layer 36 on the bottom surface each have a thickness of, for example, 30 nm to 150 nm.

[0056] Next, CVD-doped polysilicon is formed in a region surrounded by the first dielectric layer 35 on the lateral surface and the first dielectric layer 36 on the bottom surface (gate fabrication process). In this case, it is desirable to embed the doped polysilicon sufficiently in the first trench 74.

[0057] Next, doped polysilicon deposited on an upper surface of the superjunction layer 15 is removed by back-etching. In this case, doped polysilicon remains in the first trench 74. The first gate electrode 71 is formed from the doped polysilicon remaining in the first trench 74, as shown in Fig. Figure 12 illustrates this. There is no problem if an upper surface of the doped polysilicon in the first trench 74 is located below the upper surface of the superjunction layer 15. However, it is required that the upper surface of the doped polysilicon in the first trench 74 be located above a lower surface of the first source layer 22. This process completes the semiconductor region 40.

[0058] Next, a dielectric layer is deposited on the first main surface of the semiconductor region 40 using CVD and similar processes. The dielectric layer is then removed in an active region using a resist mask and similar techniques to form source contact holes extending to the first source layer 22, the first p+-type layer 23, and the second p+-type layer 52. The dielectric intermediate layers 33 are formed from the remaining areas of the dielectric layer. The active region is a semiconductor region in which a current flows when a voltage is applied to the semiconductor unit. A semiconductor region formed around the periphery of the active region is referred to as a terminal region.

[0059] Next, after the formation of a metal layer containing nickel (Ni) as a major component on the first main surface of the semiconductor region 40 by sputtering or similar processes, a heat treatment at 600 °C to 1100 °C is carried out to react the metal layer containing Ni as a major component with the upper surfaces of the first source layer 22, the first p+-type layer 23, and the second p+-type layer 52, thereby forming silicide layers between them. Subsequently, any remaining metal layer on the dielectric intermediate layers 33 is removed, except for the silicide layers formed by this reaction. This forms the ohmic electrodes 81 on the front surface.

[0060] Next, after the formation of a metal layer containing Ni as a main component on the second main surface of the semiconductor region 40 by means of sputtering and the like, a heat treatment is carried out on the second main surface of the semiconductor region 40 to form the ohmic electrode 91 on the back surface of the second main surface of the semiconductor region 40.

[0061] Next, an aluminum-containing metal layer is formed over the first main surface of the semiconductor region 40 by sputtering, vacuum deposition, or the like. In this case, it is desirable to completely embed the metal in each of the contact holes. An unnecessary area of ​​the metal layer is then removed by a wet etching process using a resist mask or the like to form the source electrode 82.

[0062] Next, a gold-containing metal layer is formed on the surface of the ohmic electrode 91 at the rear surface by sputtering and the like to form the drain electrode 92. The semiconductor unit is completed by the aforementioned series of processes according to the present embodiment, as described in Fig. 1 is shown.

[0063] A process for producing a semiconductor layer of the second conductivity type, usually referred to as a guard ring, in the terminal area; a process for producing a dielectric layer, usually referred to as a field dielectric layer, in the terminal area, for example below a gate wiring, a gate contact point and the like; and other processes may be added as necessary for the aforementioned series of processes.

[0064] In each of the processes for manufacturing the semiconductor device, the local shape of the semiconductor device typically influences the completion of the process. Thus, it is possible that the completion of the local shape is not constant in a case where the shape is, for example, non-periodic, causing local variations in properties. These local variations in properties can degrade the reliability of the device. According to the present embodiment, the spacing between the n-type support layers 13 and the spacing between the p-type support layers 14 are each designed to be constant in order to suppress local variations in properties, thereby preventing a deterioration in the reliability of the semiconductor device.

[0065] Areas formed from a semiconductor, such as the first trough layer 21 and the first source layer 22, as well as areas formed from a material other than the semiconductor, such as the first trenches 74, are preferably formed in strips, as in the present embodiment. In a case where the process for growing crystals is carried out using the silicon carbide substrate 11, which has the offset angle, an alignment mark for use in an exposure process for resist structuring can be shifted in a direction corresponding to the offset angle.

[0066] In this case, the areas formed from the semiconductor, such as the first trough layer 21 and the first source layer 22, as well as the areas formed from a material other than the semiconductor, such as the first trenches 74, are formed at positions that are shifted in the direction corresponding to the offset angle with respect to the n-type support layers 13.

[0067] In a case where the semiconductor-based regions, such as the first trough layer 21 and the first source layer 22, and the regions formed from a material other than the semiconductor, such as the first trenches 74, are arranged in a lattice, for example, a displacement of the alignment mark in any direction can cause a change in the properties. However, in a case where the semiconductor-based regions, such as the first trough layer 21 and the first source layer 22, and the regions formed from a material other than the semiconductor, such as the first trenches 74, are arranged in stripes, the change in properties can be prevented by aligning the direction of displacement of the alignment mark with the direction of stripe expansion. The extent of the displacement increases with increasing depth of the p-type support layers 14.

[0068] As described above, the semiconductor unit according to the present invention comprises the first dielectric layer 36 on the bottom surface, which is located on the bottom surface of each of the first trenches 74, and the first gate electrode, which is located in the first trench 74, opposite the first trough layer 21 and the first source layer 22 by the first dielectric layer 35 on the side surface and opposite the p-type support layer 14 by the first dielectric layer 36 on the bottom surface.

[0069] As a result, the electric field applied to the first dielectric layer 36 on the base surface is reduced by the p-type support layer 14, which is depleted in the off state of the semiconductor unit according to the present embodiment. This results in an effect that leads to a highly reliable semiconductor unit.

[0070] Furthermore, the addition of a process, such as a process for producing a p-type semiconductor layer, is not necessary for a reduction of the electric field in the present semiconductor unit having the super-junction structure.

[0071] In particular, when the first dielectric layer 36 on the base surface is in total contact with the p-type support layer 14, the effect of reducing the electric field increases further, and an effect is also produced that improves the reliability of the silicon carbide MOSFET.

[0072] As in the Fig. 1 and Fig. As shown in Figure 2, the first trenches 74 are located within each of the strip-like support layers 14 of p-type at the boundaries between the support layer 14 of p-type and the support layers 13 of n-type, which are located on both sides of the support layer 14 of p-type. However, a first trench 74 can also be located at a boundary on only one side. In the case where the first trenches 74 are located within each of the strip-like support layers 14 of p-type at the boundaries between the support layer 14 of p-type and the support layers 13 of n-type, which are located on both sides of the support layer 14 of p-type, the channel width density is higher than in the case where the first trench 74 is located at the boundary on only one side, and as a result, the one-way resistance can be reduced. Design 2

[0073] The following describes a configuration according to the present embodiment using the Fig. 13, Fig. 14 to Fig. 15 described. Fig. Figure 13 is a cross-sectional view of a semiconductor unit according to the present embodiment along an auxiliary line BB' of Fig. 14. Fig. Figure 14 is a top view showing an upper surface of a semiconductor region of the semiconductor unit according to the present embodiment. The semiconductor unit according to the present embodiment has many similarities to the semiconductor unit according to embodiment 1, and only the differences from the semiconductor unit according to embodiment 1 are described.

[0074] As in Fig. As shown in Figure 13, the semiconductor unit according to the present embodiment, in addition to the configuration of the semiconductor unit according to embodiment 1, has a second p-type well layer 26 located within each of the p-type support layers 14 on an upper surface of the p-type support layer 14. Furthermore, a second source layer 27 is located + -type within the second trough layer 26 on an upper surface of the second trough layer 26. Each of the p-type support layers 14 according to the present embodiment has the second trough layer 26 and the second source layer 27.

[0075] As in Fig. As shown in Figure 13, the first dielectric layer 35 is located on the lateral surface on opposite lateral surfaces in each of the first troughs 74. The first dielectric layer 35 on the lateral surface is in contact with the second trough layer 26 and the second source layer 27. The first dielectric layer 36 on the bottom surface is in contact with the second trough layer 26. That is, the first dielectric layer 36 on the bottom surface is in contact with a p-type region of each of the p-type support layers 14. The second trough layers 26 are arranged in strips in a top view.

[0076] The second trough layer 26 can have the same impurity concentration as a region of the p-type support layer 14 that differs from the second trough layer 26, or it can have an impurity concentration that differs from this region. The second trough layer 26 can have a distribution in which the impurity concentration varies in a direction perpendicular to the silicon carbide substrate 11. The second trough layer 26 can have a distribution in which a region of the second trough layer 26 that is in contact with the first dielectric layer 36 on the bottom surface has the same impurity concentration as the region of the p-type support layer 14 that differs from the second trough layer 26.

[0077] The threshold voltage of a MOSFET is typically dependent on the impurity concentration in a well region, and thus it is only necessary that the second well layer 26 has an impurity concentration suitable for achieving a desired threshold voltage. According to the present embodiment, the description assumes that the second well layer 26 has a higher impurity concentration than the p-type support layer 14, which differs from the second well layer 26, and that it has a constant impurity concentration.

[0078] As in Fig. As shown in Figure 13, the second source layer 27 is from n + -Type formed within the second trough layer 26 on the upper surface of the second trough layer 26. As in Fig. As shown in Figure 14, the second source layers 27 are formed in strips in a top view. The ohmic electrodes 81 on the front surface according to the present embodiment are in contact not only with the first source layer 22, the first p+-type layer 23 and the second p+-type layer 52, but also with the second source layer 27.

[0079] Next, the operation of the semiconductor unit according to the present embodiment will be described. Fig. Figure 15 is a cross-sectional view along the auxiliary line BB' of Fig. Figure 14 shows the operation of the semiconductor unit according to the present embodiment. When a voltage higher than a specific voltage value (first threshold voltage) is applied to each of the first gate electrodes 71, a channel forms in a region within the first well layer 21, which is in contact with the first dielectric layer 35 on the lateral surface. As a result, when a positive voltage is applied to the drain electrode 92, as in embodiment 1, a current flows between the drain electrode 92 and the source electrode 82 in the direction of arrow 501.

[0080] The semiconductor unit according to the present embodiment further comprises the second source layer 27, which is electrically connected to the source electrode 82 in the upper region of the p-type support layer 14. When a voltage higher than a specific voltage value (second threshold voltage) is applied to each of the first gate electrodes 71, a channel is formed in a region within the second well layer 26 that is in contact with the first dielectric layer 35 on the lateral surface. As a result, when a positive voltage is applied to the drain electrode 92, a current flows between the drain electrode 92 and the source electrode 82 in the direction of arrow 501 and also in the direction of arrow 502. The first threshold voltage and the second threshold voltage can be the same or different.

[0081] Next, a method for manufacturing the semiconductor unit according to the present embodiment is described. The method for manufacturing the semiconductor unit according to the present embodiment has many similarities to the method for manufacturing the semiconductor unit according to embodiment 1, and only the differences compared to the method for manufacturing the semiconductor unit according to embodiment 1 are described.

[0082] The method for fabricating the semiconductor unit according to the present embodiment includes a process for producing the second trough layer 26 on the upper surface of the p-type support layer 14. In the aforementioned process, Al (aluminum) ions are introduced as p-type defects into the upper surface of the support layer 14 using an implantation mask, such as a photoresist. Fig. 9, the p-type support layer 14 shown is implanted to form the second trough layer 26, as in Fig. Figure 13 shows the second trough layer 26, which has a depth of, for example, approximately 0.5 µm to 4 µm.

[0083] The second trough layer 26 is shallower than the p-type support layer 14. The second trough layer 26 has the same defect concentration as the region of the p-type support layer 14 that differs from the second trough layer 26, or a higher defect concentration than this region, for example, exhibiting a defect concentration in the range of 1 × 10 17 cm -3 up to 1 × 10 19 cm -3 The implantation mask is removed after the ion implantation procedure is complete.

[0084] The method for fabricating the semiconductor unit according to the present embodiment further comprises a process for producing the second source layer 27 on the upper surface of the second well layer 26, which has been formed as described above. In the aforementioned process, n-type nitrogen ions are implanted into the upper surface of the second well layer 26 formed as described above, using an implantation mask such as a photoresist, to form the second source layer 27. Fig. 13 shown.

[0085] The second source layer 27 has a shallower depth than the second trough layer 26. It is required that the second source layer 27 has a shallower depth than the p-type support layer 14. The second source layer 27 may have a higher or lower impurity concentration than the first source layer 22. The impurity concentration in the second source layer 27 may be distributed perpendicular to the silicon carbide substrate 11.

[0086] The second source layer 27, for example, exhibits a defect concentration in the range of 1 × 10 18 cm -3 up to 1 × 10 21 cm -3The n-type defects introduced during the ion implantation process exhibit a concentration exceeding that of the p-type defects in the second trough layer 26. After completion of the ion implantation, the implantation mask is removed.

[0087] The process for producing the second trough layer 26 on the upper surface of the p-type support layer 14 and the process for producing the second source layer 27 on the upper surface of the second trough layer 26, as described above, may be added during, before, or after the processes for producing the first trough layer 21, the first source layer 22, the first p+-type layer 23, and the second p+-type layer 52, and these processes may be carried out in any order and need not necessarily be carried out in the process sequence mentioned above.

[0088] As described above, the semiconductor unit according to the present embodiment has a second p-type trough layer 26 located within the p-type support layer 14 on the upper surface of the p-type support layer 14. As shown in Fig. As shown in Figure 13, the first dielectric layer 35 on the side surface is in contact with the second well layer 26 and the second source layer 27, and the first dielectric layer 36 on the bottom surface is in contact with the second well layer 26. As a result, in the on-state of the semiconductor unit, the channel also forms in the area within the second well layer 26 that is in contact with the first dielectric layer 35 on the side surface.

[0089] In contrast, the semiconductor element described in patent document 1 has a gate-type structure with a single groove within each of the n-type support layers. The semiconductor unit according to the present embodiment thus has a higher channel width density than the semiconductor element described in patent document 1. Furthermore, the semiconductor unit according to the present embodiment produces an effect that reduces the on-resistance compared to the semiconductor element described in patent document 1.

[0090] In the trench-filling concept, the width of the p-type support layer increases with the depth of the trench to be formed due to process constraints. For example, when silicon carbide is used as the semiconductor material, the p-type support layer must be approximately 40 µm deep to achieve a breakdown voltage of 6.5 kV. In the trench-filling concept, trenches are typically formed using a dry etching process with a structure consisting of a deposited oxide layer as a mask.

[0091] The structure formed by the deposited oxide layer is created after the oxide layer has been deposited over the entire surface of a wafer using a dry etching process with a structured resist mask. This means that the dry etching process is performed twice to create the grooves in the wafer.

[0092] In a dry etching process, the mask from an oxide layer or the resist mask is etched gradually not only from its upper surface but also from its end surface. In a case where a positive resist is used, the completed trench areas thus have greater widths and areas than photolithographically exposed areas of the resist mask. In a case where trenches are formed to a depth of approximately 40 µm to achieve a breakdown voltage of 6.5 kV, the trenches to be formed, due to the influence of the etching process at the end surface of the mask, each have a width of approximately 7 µm or more, even though the photolithographically exposed areas each have a sufficiently smaller width.

[0093] Conversely, the mask width cannot be excessively reduced in areas where no trenches are formed, i.e., in areas where the mask is located. This is because, if the resist has a narrow width, the intended structure may not form due to resist drop, mask separation from the wafer, or similar issues. In particular, when forming a superjunction structure, the mask structure has an extremely high aspect ratio in a top view, thus increasing the likelihood of structure formation defects.

[0094] For the formation of a stable trench structure, the n-type support layer must have a width of approximately 5 µm or more. Therefore, for the formation of a p-type support layer 14 with a depth of approximately 40 µm, the required support spacing is approximately 12 µm or more.

[0095] In a case where the semiconductor device according to the present embodiment is fabricated using the trench-filling concept, which is more suitable for mass production than the multi-epitaxial concept, the p-type support layer 14 has an extremely large width. In the case of the semiconductor element described in patent document 1, no trenches are formed within the p-type support layer, and thus the effect of a reduction in channel width density is significant. In the semiconductor device according to the present embodiment, the effect of a reduction in the on-resistance of the semiconductor device is highly significant compared to that of the semiconductor element described in patent document 1.

[0096] Furthermore, it is usually more difficult to epitaxially grow silicon carbide in trenches formed in silicon carbide than to embed silicon in trenches formed in silicon. In a case where the p-type support layer 14 is formed using the trench-filling concept, it may be necessary for the initial trenches 74 to each have a greater width than those formed in silicon. The effect of reducing the on-resistance of the semiconductor unit is therefore highly significant for silicon carbide.

[0097] In a case where the second trough layer 26 has a narrower width than the first trench 74 and the second trough layer 26 has the same defect concentration profile as the first trough layer 21, the second trough layer 26 and the first trough layer 21 can be formed simultaneously. In this case, a single implantation mask can be used, thus reducing the number of structuring and implantation procedures required and simplifying the manufacturing processes.

[0098] In a case where the second source layer 27 has the same defect concentration profile as the first source layer 22, the second source layer 27 and the first source layer 22 can be formed simultaneously. In this case, a single implantation mask can be used, thus reducing the number of structuring and implantation steps required and simplifying the manufacturing process. embodiment 3

[0099] The following describes a configuration according to the present embodiment using the Fig. 16 and Fig. 17 described. Fig. 16 is a cross-sectional view of a semiconductor unit according to the present embodiment along an auxiliary line CC' of Fig. 17. Fig. Figure 17 is a top view showing an upper surface of a semiconductor region of the semiconductor unit according to the present embodiment. The semiconductor unit according to the present embodiment has many similarities to the semiconductor unit according to embodiment 2, and only differences from the semiconductor unit according to embodiment 2 are described.

[0100] As in Fig. As shown in Figure 16, the semiconductor unit according to the present embodiment has a second source layer 27a instead of the second source layer 27 in the configuration of the semiconductor unit according to embodiment 2. The second source layer 27a is configured to have a greater depth than the first source layer 22. That is, a lower surface of the second source layer 27a is located closer to the second main surface of the semiconductor area 40 than the lower surface of the first source layer 22.

[0101] Next, a method for manufacturing the semiconductor unit according to the present embodiment is described. In the method for manufacturing the semiconductor unit according to the present embodiment, it is only necessary to perform an ion implantation during the process for manufacturing the second source layer 27 according to embodiment 2 such that the second source layer 27a has a greater depth than the first source layer 22.

[0102] As described above, in the semiconductor unit according to the present embodiment, the lower surface of the second source layer 27a is located closer to the silicon carbide substrate 11 than the lower surface of the first source layer 22. As a result, the channel that forms on one side of the second well layer 26 is shorter, and the channel resistance on the side of the second well layer 26 is lower than that of the semiconductor unit according to embodiment 2. This also results in a reduction of the on-resistance of the semiconductor unit compared to the semiconductor unit according to embodiment 2. Design 4

[0103] The following describes a configuration according to the present embodiment using the Fig. 18 and Fig. 19 described. Fig. Figure 18 is a cross-sectional view of a semiconductor unit according to the present embodiment along an auxiliary line DD' of Fig. 19. Fig. Figure 19 is a top view showing an upper surface of a semiconductor region of the semiconductor unit according to the present embodiment. The semiconductor unit according to the present embodiment has many similarities to the semiconductor unit according to embodiment 2, and only differences from the semiconductor unit according to embodiment 2 are described.

[0104] As in Fig. As shown in Figure 18, the semiconductor unit according to the present embodiment has a first dielectric layer 36a on the bottom surface instead of the first dielectric layer 36 on the bottom surface. The first dielectric layer 36a on the bottom surface is designed to have a lesser thickness than the first dielectric layer 35 on the side surface.

[0105] Next, a method for manufacturing the semiconductor unit according to the present embodiment is described. In the method for manufacturing the semiconductor unit according to the present embodiment, it is only necessary that the first dielectric layer 36a on the bottom surface is formed in the process for manufacturing the first dielectric layer 36 on the bottom surface according to embodiment 2 such that it has a lesser thickness than the first dielectric layer 35 on the side surface.

[0106] According to the present embodiment, the (0001) plane is used as the surface of the silicon carbide substrate 11 for the side of the first main surface. The (0001) plane is a plane that exhibits the lowest oxidation rate among crystalline planes of silicon carbide. By forming the first dielectric layer 35 on the side surface and the first dielectric layer 36a on the bottom surface by thermal oxidation, the first dielectric layer 36a on the bottom surface naturally has a smaller thickness than the first dielectric layer 35 on the side surface.

[0107] As described above, the first dielectric layer 36a on the bottom surface of the semiconductor unit according to the present embodiment has a smaller thickness than the first dielectric layer 35 on the side surface. Therefore, in the on-state of the semiconductor unit according to the present embodiment, the electric field in the vicinity of the first dielectric layer 36a on the bottom surface is higher than that present in the semiconductor unit according to embodiment 2.

[0108] This means that in the vicinity of the first dielectric layer 36a on the base surface, many inversion charge carriers are generated in the on-state of the semiconductor unit, thus reducing the channel resistance. As a result, the on-resistance of the semiconductor unit is also reduced compared to the semiconductor unit according to embodiment 2. Design 5

[0109] The following describes a configuration according to the present embodiment using the Fig. 20 and Fig. 21 described. Fig. Figure 20 is a cross-sectional view of a semiconductor unit according to the present embodiment along an auxiliary line EE' of Fig. 21. Fig. Figure 21 is a top view showing an upper surface of a semiconductor area of ​​the semiconductor unit according to the present embodiment.

[0110] The semiconductor unit according to the present embodiment has both the second source layer 27a according to embodiment 3 and the first dielectric layer 36a on the base surface according to embodiment 4. A method for manufacturing the semiconductor unit according to the present embodiment is a combination of the method for manufacturing the second source layer 27a according to embodiment 3 and the method for manufacturing the first dielectric layer 36a on the base surface according to embodiment 4, and therefore a detailed description thereof is omitted.

[0111] Since, as described above, both the second source layer 27a according to embodiment 3 and the first dielectric layer 36a are contained on the bottom surface according to embodiment 4, effects similar to those caused by the semiconductor unit according to embodiment 3 and the semiconductor unit according to embodiment 4 are produced. Design 6

[0112] The following describes a configuration according to the present embodiment using the Fig. 22 and Fig. 23 described. Fig. 22 is a cross-sectional view of a semiconductor unit according to the present embodiment along an auxiliary line FF' of Fig. 23. Fig. Figure 23 is a top view showing an upper surface of a semiconductor region of the semiconductor unit according to the present embodiment. The semiconductor unit according to the present embodiment has many similarities to the semiconductor unit according to embodiment 2, and only differences from the semiconductor unit according to embodiment 2 are described.

[0113] As in Fig. As shown in Figure 22, the semiconductor unit according to the present embodiment has first grooves 74a instead of first grooves 74. Each of the first grooves 74a is configured to bridge a boundary between the n-type support layer 13 and the p-type support layer 14. That is, the first dielectric layer 36 on the base surface according to the present embodiment is in contact with the n-type support layer 13 and the second trough layer 26 within the p-type support layer 14.

[0114] The concentration of the electric field at the first dielectric layer 36 on the ground surface according to the present embodiment is reduced by a depletion layer which is generated at a boundary layer between the support layer 13 of n-type and the second trough layer 26 and at a boundary layer between the support layer 13 of n-type and the support layer 14 of p-type in the vicinity of the bottom of the first trench 74.

[0115] Next, a method for manufacturing the semiconductor unit according to the present embodiment is described. In the method for manufacturing the semiconductor unit according to the present embodiment, it is only necessary to modify the process for manufacturing the Fig. The first trenches 74 shown in Figure 11 are to be etched in such a way that the first trenches 74a are each formed in such a way that they bridge the boundary between the n-type support layer 13 and the p-type support layer 14. That is, when the first trenches 74a are formed, it is only necessary that each of the opening structures of the mask is arranged so that it bridges the boundary between the n-type support layer 13 and the p-type support layer 14.

[0116] As described above, the first dielectric layer 36 on the base surface of the semiconductor unit according to the present embodiment is arranged such that it is in contact with the n-type support layer 13 and the second well layer 26 within the p-type support layer 14. A lateral channel generated within the second well layer 26 in the on-state of the semiconductor unit has a shorter length than that in the semiconductor unit according to embodiment 2. This also results in a reduction of the channel resistance of the semiconductor unit.

[0117] The semiconductor unit according to the present embodiment can have the second source layer 27a, which has a greater depth than the first source layer 22, instead of the second source layer 27 as in embodiment 3. In this case, an effect similar to that produced by the semiconductor unit according to embodiment 3 is produced. Model 7

[0118] The following describes a configuration according to the present embodiment using the Fig. 24 and Fig. 25 described. Fig. Figure 24 is a cross-sectional view of a semiconductor unit according to the present embodiment along an auxiliary line GG' of Fig. 25. Fig. Figure 25 is a top view showing an upper surface of a semiconductor area of ​​the semiconductor unit according to the present embodiment.

[0119] The cross-sectional view of the semiconductor unit according to the present embodiment along line GG' of Fig. 25 has a configuration that is similar to that of the one in Fig. The cross-sectional view of the semiconductor unit according to embodiment 5 shown in Figure 20 along line EE' is similar. The semiconductor unit according to the present embodiment has many similarities to the semiconductor unit according to embodiment 5, and only the differences from the semiconductor unit according to embodiment 5 are described.

[0120] As in Fig. As shown in Figure 25, the semiconductor unit according to the present embodiment has, in addition to the first grooves 74, which are formed in strips in a top view, second grooves 74b (areas which are in Fig. 25 (surrounded by dashed lines), which are arranged within the support layers 13 of n-type in a plan view in a direction perpendicular to the first trenches 74. A second dielectric layer 35b on a lateral surface is located on a lateral surface in each of the second trenches 74b.

[0121] A second dielectric layer on a bottom surface, not shown, is located on a bottom surface of each of the second trenches 74b. A second gate electrode 81b is located in each of the second trenches 74b such that it faces the first trough layer 21 and the first source layer 22 through the second dielectric layer 35b on the lateral surface. As shown in Fig. As shown in Figure 25, the second trenches 74b are connected to the first trenches 74 in a top view.

[0122] Next, a method for manufacturing the semiconductor unit according to the present embodiment is described. The method for manufacturing the semiconductor unit according to the present embodiment is similar to the method for manufacturing the semiconductor unit according to embodiment 5, except that the second grooves 74b are formed. The second grooves 74b can be manufactured using a manufacturing method similar to that used for the first grooves 74.

[0123] As described above, the semiconductor unit according to the present embodiment has the second grooves 74b, which are arranged within the n-type support layers 13 in a top view in a direction perpendicular to the first grooves 74, which are formed in strips in a top view. Due to the presence of the second grooves 74b, the channel width density is higher than that of the semiconductor unit according to embodiment 5. As a result, the channel resistance of the semiconductor unit is also reduced.

[0124] In the semiconductor unit according to the present embodiment, as in embodiment 1, an electric field acting on the first dielectric layer 36a on the base surface is reduced by the p-type support layer 14, which is depleted in the off state of the semiconductor unit according to the present embodiment. This results in an effect that produces a highly reliable semiconductor unit.

[0125] It is possible that, according to the present embodiment, the second well layer 26 and the second source layer 27 are not located within the p-type support layer 14. In this case, the addition of a process, such as the process for producing the p-type semiconductor layer to reduce the electric field, is not necessary for the present semiconductor unit having the superjunction structure.

[0126] It is possible that the first gate electrode 71 and the second gate electrode 71b are not directly connected. It is only necessary that the first gate electrode 71 and the second gate electrode 71b are electrically connected. In this case, a similar effect will be produced. Design 8

[0127] The following describes a configuration according to the present embodiment using the Fig. 26, Fig. 27, Fig. 28 to Fig. 29 described. Fig. Figure 26 is a cross-sectional view of a semiconductor unit according to the present embodiment along an auxiliary line HH' of Fig. 27. Fig. 27 is a top view of the semiconductor unit according to the present embodiment. The cross-sectional view of the semiconductor unit according to the present embodiment along line HH' of Fig. 27 has a similar configuration to that of the one in Fig. 20 shows a cross-sectional view of the semiconductor unit according to embodiment 5 along the line EE'.

[0128] As in Fig. As shown in Figure 27, the semiconductor unit according to the present embodiment has, in addition to the first grooves 74 formed in strips in a top view, second grooves 74b which, in a top view as in embodiment 7, are formed within the support layers 13 of the n-type in the vertical direction. Furthermore, third grooves 74c (areas which are in Fig. 27 surrounded by dashed lines) within the support layers 14 of the p-type on extensions of the second trenches 74b.

[0129] The third trenches 74c are arranged in a plan view in a direction perpendicular to the first trenches 74. A third dielectric layer 35c on a lateral surface is located on a lateral surface in each of the third trenches 74c. A third dielectric layer on a bottom surface, not shown, is located on a bottom surface of each of the third trenches 74c.

[0130] A third gate electrode 71c is located in each of the third grooves 74c such that it faces the second trough layer 26 and the second source layer 27a through the third dielectric layer 35c on the lateral surface. The first grooves 74 are connected to the second grooves 74b in a top view. The third grooves 74c are connected to the second grooves 74b in a top view.

[0131] The Fig. 28 and Fig. 29 are cross-sectional views of the semiconductor unit according to the present embodiment along an auxiliary line II' of Fig. 27. Fig. Figure 28 is a cross-sectional view along line II' when viewed from the top of the page. Fig. 27 out. Fig. Figure 29 is a cross-sectional view along line II' when viewed from the bottom of the page. Fig. 27 out. According to the Fig. 28 and Fig. 29 the third gate electrode 71c is arranged such that it is opposite the second trough layer 26 by the third dielectric layer 35c on the side surface and a third dielectric layer 36c on the bottom surface.

[0132] According to the Fig. 28 and Fig. 29 is a region of the second well layer 26, which is in contact with the first dielectric layer 35 on the side surface and the third dielectric layer 35c on the side surface, inverted in the on-state of the semiconductor unit, so that a channel is formed. As a result, when a positive voltage is applied to the drain electrode 92, a current flows in the direction of arrow 503, as shown in Fig. 28 is shown. This means that the channel width density can be increased. In the semiconductor unit according to the present embodiment, the channel resistance on the side of the second trough layer 26 is thus reduced, and the on-resistance of the semiconductor unit is reduced compared to the semiconductor unit according to embodiment 7.

[0133] Next, a method for manufacturing the semiconductor unit according to the present embodiment is described. The method for manufacturing the semiconductor unit according to the present embodiment is similar to the method for manufacturing the semiconductor unit according to embodiment 7, except that the third grooves 74c are formed. The third grooves 74c can be manufactured using a manufacturing method similar to that used for the first grooves 74 and the second grooves 74b.

[0134] As described above, the semiconductor unit according to the present embodiment has, in addition to the first grooves 74 and the second grooves 74b, third grooves 74c, which are formed within the p-type support layers 14 in the direction perpendicular to the first grooves 74. Due to the presence of the third grooves 74c, the channel width density is higher than that of the semiconductor unit according to embodiment 7. As a result, the channel resistance of the semiconductor unit is also reduced.

[0135] It is possible that the third gate electrode 71c is not directly connected to the first gate electrode 71 and the second gate electrode 71b. It is only necessary that the third gate electrode 71c is electrically connected to the first gate electrode 71 and the second gate electrode 71b. In this case, a similar effect will be produced.

[0136] It is possible that the semiconductor unit according to the present embodiment does not have the second grooves 74b. Even in this case, the channel width density is higher than that of the semiconductor unit according to embodiment 5 due to the presence of the third grooves 74c. As a result, the channel resistance of the semiconductor unit is also reduced. Design 9

[0137] The following describes a configuration according to the present embodiment using the Fig. 30 and Fig. 31 described. Fig. Figure 30 is a cross-sectional view of a semiconductor unit according to the present embodiment along an auxiliary line JJ' of Fig. 31. Fig. Figure 31 is a top view showing an upper surface of a semiconductor region of the semiconductor unit according to the present embodiment. The semiconductor unit according to the present embodiment has many similarities to the semiconductor unit according to embodiment 5, and only differences from the semiconductor unit according to embodiment 5 are described.

[0138] As in Fig. As shown in Figure 30, the semiconductor unit according to the present embodiment has, in addition to the first grooves 74, second grooves 74d located within the n-type support layers 13. As shown in Fig. As shown in Figure 31, the second trenches 74d are arranged parallel to the first trenches 74. A second dielectric layer 35d is located on a lateral surface in each of the second trenches 74d.

[0139] A second dielectric layer 36d on a bottom surface is located on a bottom surface of each of the second trenches 74d. A second gate electrode 71d is located in each of the second trenches such that it is opposite the first trough layer 21 and the first source layer 22 through the second dielectric layer 35d on the lateral surface.

[0140] Next, a method for manufacturing the semiconductor unit according to the present embodiment is described. The method for manufacturing the semiconductor unit according to the present embodiment is similar to the method for manufacturing the semiconductor unit according to embodiment 5, except that the second grooves 74d are formed. The second grooves 74d can be manufactured using a manufacturing method similar to that used for the first grooves 74.

[0141] As described above, the semiconductor unit according to the present embodiment has, in addition to the first grooves 74, second grooves 74d, which are arranged within the n-type support layers 13 in a direction parallel to the first grooves 74. Due to the presence of the second grooves 74d, the channel width density is higher than that of the semiconductor unit according to embodiment 5. As a result, the channel resistance of the semiconductor unit is also reduced. Design 10

[0142] The following describes a configuration according to the present embodiment using the Fig. 32 and Fig. 33 described. Fig. Figure 32 is a cross-sectional view of a semiconductor unit according to the present embodiment along an auxiliary line KK' of Fig. 33. Fig. Figure 33 is a top view showing an upper surface of a semiconductor area of ​​the semiconductor unit according to the present embodiment.

[0143] The in Fig. The cross-sectional view of the semiconductor unit shown in Figure 32, according to the present embodiment, along line KK', has a similar configuration to that shown in Figure 32. Fig. Figure 30 shows a cross-sectional view of the semiconductor unit according to embodiment 9 along line JJ'. The semiconductor unit according to the present embodiment has many similarities to the semiconductor unit according to embodiment 9, and only differences from the semiconductor unit according to embodiment 9 are described.

[0144] As in Fig. As shown in Figure 33, the semiconductor unit according to the present embodiment has the second grooves 74b, which in a top view are arranged in the direction perpendicular to the first grooves 74 and the second grooves 74d (areas which are shown in Fig. 33 (surrounded by dashed-dotted lines), which are formed in stripes in a top view. The second trenches 74b are located within the n-type support layers 13. The second gate electrode 71b is located in each of the second trenches 74b.

[0145] The second gate electrode 71b is arranged such that it faces the first trough layer 21 and the first source layer 22 through the second dielectric layer 35b on its lateral surface. The second grooves 74b are connected to the first grooves 74 in a top view. The second grooves 74b are connected to the second grooves 74d in a top view.

[0146] Next, a method for manufacturing the semiconductor unit according to the present embodiment is described. The method for manufacturing the semiconductor unit according to the present embodiment is similar to the method for manufacturing the semiconductor unit according to embodiment 9, except that the second grooves 74b are formed. The second grooves 74b can be manufactured using a manufacturing method similar to that used for the first grooves 74 and the second grooves 74d.

[0147] As described above, the semiconductor unit according to the present embodiment has the second grooves 74b, which, in a top view, are arranged in a direction perpendicular to the first grooves 74 and the second grooves 74d, which, in a top view, are formed in strips. Due to the presence of the second grooves 74b, the channel width density is higher than that of the semiconductor unit according to embodiment 9. As a result, the channel resistance of the semiconductor unit is also reduced.

[0148] It is possible that the first gate electrode 71, the second gate electrode 71d, and the second gate electrode 71b are not directly connected. It is only necessary that the first gate electrode 71, the second gate electrode 71d, and the second gate electrode 71b are electrically connected. In this case, a similar effect will be produced. Design 11

[0149] The following describes a configuration according to the present embodiment using the Fig. 34, Fig. 35, Fig. 36 to Fig. 37 described. Fig. Figure 34 is a cross-sectional view of a semiconductor unit according to the present embodiment along an auxiliary line LL' of Fig. 35. Fig. Figure 35 is a top view showing an upper surface of a semiconductor region of the semiconductor unit according to the present embodiment. The semiconductor unit according to the present embodiment has many similarities to the semiconductor unit according to embodiment 10, and only differences from the semiconductor unit according to embodiment 10 are described.

[0150] As in Fig. As shown in Figure 34, the semiconductor unit according to the present embodiment has, in addition to the first grooves 74 and the second grooves 74d, a fourth groove 74e (areas which are shown in Figure 34). Fig. 35 are surrounded by dash-dotted lines), which are located within the support layers 14 of p-type. As in Fig. As shown in Figure 35, the fourth trenches 74e are arranged in a top view parallel to the first trenches 74 and the second trenches 74d. A fourth gate electrode 71e is located in each of the fourth trenches 74e. A fourth dielectric layer 35e is located on a lateral surface in each of the fourth trenches 74e.

[0151] The fourth dielectric layer 35e on the lateral surface of the fourth trench 74e is in contact with the second trough layer and the second source layer. A fourth dielectric layer 36e is located on a bottom surface of each of the fourth trenches 74e. The fourth gate electrode 71e is located in each of the fourth trenches 74e such that it is opposite the second trough layer 26 and the second source layer 27a through the fourth dielectric layer 35e on the lateral surface.

[0152] As in Fig. As shown in Figure 35, the semiconductor unit according to the present embodiment has the second grooves 74b, which, as in embodiment 10, are arranged within the n-type support layers 13 in a top view in a direction perpendicular to the first grooves 74, which are formed in strips in a top view. Furthermore, the third grooves 74c are located on the extensions of the second grooves 74b. The third grooves 74c are located within the p-type support layers 14. The third gate electrode 71c is located in each of the third grooves 74c.

[0153] As in Fig. As shown in Figure 35, the semiconductor unit according to the present embodiment further comprises the second grooves 74d, which, in a top view, are arranged in the direction parallel to the first grooves 74, which, as in embodiment 10, are formed in strips. The second grooves 74d are located within the n-type support layers 13. The fourth grooves 74e are arranged, in a top view, in the direction parallel to the first grooves 74, which, in a top view, are formed in strips. The fourth grooves 74e are located within the p-type support layers 14.

[0154] The Fig. 36 and Fig. Figure 37 shows cross-sectional views of the semiconductor unit according to the present embodiment along an auxiliary line MM' of Fig. 35. Fig. Figure 36 is a cross-sectional view along the line MM' when viewed from the top of the page. Fig. 35 out. Fig. Figure 37 is a cross-sectional view along the line MM' when viewed from the bottom of the page. Fig. 35 out. According to the Fig. 37 and Fig. 38 the third gate electrode 71c is arranged such that it is opposite the second trough layer 26 by the third dielectric layer 35c on the side surface and the third dielectric layer 36c on the bottom surface.

[0155] According to the Fig. 36 and Fig. 37 is a region of the second well layer 26, which is in contact with the first dielectric layer 35 on the side surface, the third dielectric layer 35c on the side surface, and the fourth dielectric layer 35e on the side surface. In the on-state of the semiconductor unit, this region is inverted, thus forming a channel. As a result, when a positive voltage is applied to the drain electrode 92, a current flows in the direction of arrow 504, as shown in Fig. 36 shown.

[0156] This means that the channel width density can be increased. In the semiconductor unit according to the present embodiment, the channel resistance on the side of the second trough layer 26 is reduced, and the on-resistance of the semiconductor unit is reduced compared to the semiconductor unit according to embodiment 10.

[0157] Next, a method for manufacturing the semiconductor unit according to the present embodiment is described. The method for manufacturing the semiconductor unit according to the present embodiment is similar to the method for manufacturing the semiconductor unit according to embodiment 1, except that the third trenches 74c and the fourth trenches 74e are formed. The third trenches 74c and the fourth trenches 74e can be manufactured using a manufacturing method similar to that used for the first trenches 74, the second trenches 74b, and the second trenches 74d.

[0158] As described above, the semiconductor unit according to the present embodiment has, in addition to the first grooves 74 and the second grooves 74b, third grooves 74c, which are formed in a top view on the extents of the second grooves 74b. Furthermore, fourth grooves 74e are formed in a top view in the direction parallel to the first grooves 74, which are formed in strips in a top view. Due to the presence of the third grooves 74c and the fourth grooves 74e, the channel width density is higher than that of the semiconductor unit according to embodiment 10. As a result, a reduction in the channel resistance of the semiconductor unit is also achieved.

[0159] It is possible that the third gate electrode 71c and the fourth gate electrode 71e are not directly connected to the first gate electrode 71, the second gate electrode 71b, and the second gate electrode 71d. It is only necessary that the third gate electrode 71c and the fourth gate electrode 71e are electrically connected to the first gate electrode 71, the second gate electrode 71b, and the second gate electrode 71d. In this case, a similar effect will be produced.

[0160] It is possible that the semiconductor unit according to the present embodiment does not have the second grooves 74b and the second grooves 74d. Even in this case, the channel width density is higher than that of the semiconductor unit according to embodiment 5 due to the presence of the third grooves 74c and the fourth grooves 74e. As a result, the channel resistance of the semiconductor unit is also reduced. Design 12

[0161] The following describes a configuration according to the present embodiment using the Fig. 38 and Fig. 39 described. Fig. Figure 38 is a cross-sectional view of a semiconductor unit according to the present embodiment along an auxiliary line NN' of Fig. 39. Fig. Figure 39 is a top view showing an upper surface of a semiconductor area of ​​the semiconductor unit according to the present embodiment.

[0162] The in Fig. The cross-sectional view of the semiconductor unit shown in Figure 38, according to the present embodiment, along line NN', has a similar configuration to that shown in Figure 38. Fig. Figure 20 shows a cross-sectional view of the semiconductor unit according to embodiment 5 along line EE'. The semiconductor unit according to the present embodiment has many similarities to the semiconductor unit according to embodiment 7, and only the differences from the semiconductor unit according to embodiment 7 are described.

[0163] As in Fig. As shown in Figure 38, the semiconductor unit according to the present embodiment has a superjunction layer 15a instead of the superjunction layer 15. The superjunction layer 15a has n-type support layers 13a instead of the n-type support layers 13. The superjunction layer 15a has p-type support layers 14a instead of the p-type support layers 14. The n-type support layers 13a are arranged in a grid in a top view. The p-type support layers 14a are formed as points in areas separated by the n-type support layers 13a arranged in a grid in a top view.

[0164] The first trenches 74 are located at the boundaries between the n-type supporting layers 13a and the p-type supporting layers 14a. The first trenches 74 are entirely located within the p-type supporting layers 14a. As in Fig. As shown in Figure 39, the first ditches are 74, 74f and 74g.

[0165] As in Fig. As shown on page 39, the first ditches are located on pages 74f (areas that are in Fig. 39 (surrounded by dashed lines) at the boundaries between the support layers 13a of n-type and the support layers 14a of p-type. The first trenches 74f are located entirely within the support layers 14a of p-type. Each of the first trenches 74f has a lateral surface and a bottom surface. The bottom surface of the first trench 74f is located at a lower position than the first depression layer 21.

[0166] A first dielectric layer 35f, consisting of silicon dioxide, is formed on the lateral surface of the first trench 74f as a whole. A first dielectric layer, also consisting of silicon dioxide, is formed on the bottom surface of the first trench 74f as a whole, but this layer is not shown. The first dielectric layer 35f on the lateral surface is arranged to be in contact with the first trough layer 21 and the first source layer 22. The first dielectric layer on the bottom surface, which is not shown, is arranged to be in contact with the p-type support layer 14a.

[0167] The first grooves 74f contain the first gate electrodes 71f. Each of the first gate electrodes 71f faces the first trough layer 21 and the first source layer 22 through the first dielectric layer 35f on its lateral surface. The first gate electrode 71f faces the p-type support layer 14a through the first dielectric layer on the bottom surface, which is not shown. Doped polysilicon, for example, is used as a material for the first gate electrodes 71f.

[0168] As shown in FIG: 39, the first trenches are located 74g (areas that are in Fig. 39 (surrounded by dashed-dotted lines) at the boundaries between the support layers 13a of n-type and the support layers 14a of p-type. The first trenches 74g are located entirely within the support layers 14a of p-type. Each of the first trenches 74g has a lateral surface and a bottom surface. The bottom surface of the first trench 74g is located at a lower position than the first depression layer 21.

[0169] As in Fig. As shown in Figure 39, the first trenches 74g are arranged in a plan view in a direction perpendicular to the first trenches 74f. The first trenches 74f and the first trenches 74g are connected to each other and are arranged such that, in a plan view, they surround the outer peripheries of the point-formed support layers 14a of the p-type.

[0170] A first dielectric layer 35g, consisting of silicon dioxide, is formed on the lateral surface of each of the first trenches 74g. A first dielectric layer 36g, consisting of silicon dioxide, is formed on the bottom surface of the first trench 74g. The first dielectric layer 35g on the lateral surface is positioned in contact with the first trough layer 21 and the first source layer 22. The first dielectric layer 36g on the bottom surface is positioned in contact with the p-type support layer 14a.

[0171] The first grooves 74g contain the first gate electrodes 71g. Each of the first gate electrodes 71g faces the first trough layer 21 and the first source layer 22 through the first dielectric layer 35g on its lateral surface. The first gate electrode 71g faces the p-type support layer 14a through the first dielectric layer 36g on its bottom surface. Doped polysilicon, for example, is used as a material for the first gate electrodes 71g.

[0172] As in Fig. As shown on page 39, there are second trenches at 74h (areas that are in Fig. 39 (surrounded by double-dashed lines) within the n-type support layers 13a. The second trenches 74h are located in a plan view on extensions of the first trenches 74f. The second trenches 74h are arranged in a plan view in a direction perpendicular to the first trenches 74g. A second dielectric layer 35h on a lateral surface is located on a lateral surface in each of the second trenches 74h.

[0173] A second dielectric layer on a bottom surface, not shown, is located on a bottom surface of each of the second trenches 74h. A second gate electrode 71h is located in each of the second trenches 74h such that it faces the first trough layer 21 and the first source layer 22 through the second dielectric layer 35h on the lateral surface. As shown in Fig. Figure 39 shows the second trenches 74h connected to the first trenches 74g in a top view.

[0174] As in Fig. As shown in figure 39, there are second trenches 74i (areas which are in Fig. 39 (surrounded by double solid lines) within the n-type support layers 13a. The second trenches 74i are located in a plan view on extensions of the first trenches 74g. The second trenches 74i are arranged in a plan view in the direction perpendicular to the first trenches 74f. A second dielectric layer 35i on a lateral surface is located on a lateral surface in each of the second trenches 74i. A second dielectric layer on a bottom surface, not shown, is located on a bottom surface of each of the second trenches 74i.

[0175] A second gate electrode 71i is located in each of the second grooves 74i such that it faces the first trough layer 21 and the first source layer 22 through the second dielectric layer 35i on the lateral surface. As in Fig. Figure 39 shows the second trenches 74i connected to the first trenches 74g in a top view. The first trenches 74f, the first trenches 74g, the second trenches 74h and the second trenches 74i are arranged in a grid in a top view.

[0176] Next, a method for fabricating the semiconductor unit according to the present embodiment is described. In the method for fabricating the semiconductor unit according to the present embodiment, the n-type support layers 13a are formed in a lattice, and the p-type support layers 14a are formed as points in the fabrication method according to embodiment 7 in areas surrounded by the n-type support layers 13a. The first trenches 74f and the first trenches 74g are formed along the peripheries of the p-type support layers 14a formed as points, and it is only necessary that the first trenches 74f, the first trenches 74g, the second trenches 74h, and the second trenches 74i are formed in a lattice in a top view.

[0177] As described above, the semiconductor unit according to the present embodiment has the first dielectric layer (not shown) on the bottom surface, which is located on the bottom surface of each of the first trenches 74f, and the first gate electrode 71f, which is located in the first trench 74f, opposite the first trough layer 21 and the first source layer 22 by the first dielectric layer 35f on the side surface, and opposite the p-type support layer 14a formed at a point by the first dielectric layer on the bottom surface, which is not shown.

[0178] As with the semiconductor unit according to embodiment 1, the electric field acting on the first dielectric layer 36f on the base surface is reduced by the p-type support layer 14a, which is depleted in the off state of the semiconductor unit according to the present embodiment. This results in an effect that produces a highly reliable semiconductor unit.

[0179] The semiconductor unit according to the present embodiment also has the first dielectric layer 36g on the bottom surface, which is located on the bottom surface of each of the first trenches 74g, and the first gate electrode 71g, which is located in the first trench 74g, opposite the first trough layer 21 and the first source layer 22 by the first dielectric layer 35g on the lateral surface and opposite the p-type support layer 14a formed at a point by the first dielectric layer 36g on the bottom surface.

[0180] As with the semiconductor unit according to embodiment 1, the electric field acting on the first dielectric layer 36g on the base surface is reduced by the p-type support layer 14a, which is depleted in the off state of the semiconductor unit according to the present embodiment. This results in an effect that produces a highly reliable semiconductor unit.

[0181] The semiconductor unit according to the present embodiment has, in addition to the first grooves 74g, the second grooves 74h, and the second grooves 74i, first grooves 74f located at the boundaries between the n-type support layers 13a and the p-type support layers 14a. In a top view, the first grooves 74f are arranged perpendicular to the first grooves 74g. The entirety of the first grooves 74f lies within the p-type support layers 14a. Due to the presence of the first grooves 74f, the channel width density is higher than that of the semiconductor unit according to embodiment 7. This also results in a reduction of the channel resistance of the semiconductor unit.

[0182] It is possible that the second gate electrode 71h and the second gate electrode 71i are not directly connected to the first gate electrode 71g. It is only necessary that the second gate electrode 71h and the second gate electrode 71i are electrically connected to the first gate electrode 71g. In this case, a similar effect will occur.

[0183] It is possible that the semiconductor unit according to the present embodiment does not have the second grooves 74h and the second grooves 74i. As in embodiment 1, in this case too, an electric field acting on the first dielectric layer 36g on the base surface and on the first dielectric layer (not shown) on the base surface in each of the first grooves 74f is reduced by the p-type support layer 14a, which is depleted in the off state of the semiconductor unit according to the present embodiment. The result is an effect that produces a highly reliable semiconductor unit.

[0184] It is possible that, according to the present embodiment, the second well layer 26 and the second source layer 27 are not located within the p-type support layer 14a. In this case, the addition of a process, such as the process for forming the p-type semiconductor layer for reducing the electric field, is not necessary in the present semiconductor unit with the superjunction structure as in embodiment 1. embodiment 13

[0185] The following describes a configuration according to the present embodiment using the Fig. 40 and Fig. 41 described. Fig. Figure 40 is a cross-sectional view of a semiconductor unit according to the present embodiment along an auxiliary line OO' of Fig. 41. Fig. Figure 41 is a top view showing an upper surface of a semiconductor region of the semiconductor unit according to the present embodiment. The semiconductor unit according to the present embodiment has many similarities to the semiconductor unit according to embodiment 12, and only differences from the semiconductor unit according to embodiment 12 are described.

[0186] As in Fig. As shown in Figure 40, in addition to the first trenches 74 in the semiconductor unit according to embodiment 12, the second trenches 74d are located within the support layers 13 of the n-type in the semiconductor unit according to the present embodiment.

[0187] As in Fig. As shown in Figure 41, the second trenches 74d (areas which are located in the semiconductor unit according to the present embodiment) are located in the semiconductor unit. Fig. 41 surrounded by dashed-dotted lines) in a top view between the first trenches 74g and between the second trenches 74i in the semiconductor unit according to embodiment 12. The second trenches 74d are arranged parallel to the first trenches 74g in a top view. The number of second trenches 74d located between the first trenches 74g and between the second trenches 74i in a top view is shown in Figure 12. Fig. 41 equals one, but it can also be two or greater.

[0188] As in Fig. As shown on page 41, the second trenches are located 74b (areas that are in Fig. 41 (surrounded by dashed lines) in a plan view, furthermore between the first trenches 74f and between the second trenches 74h. The second trenches 74b are arranged parallel to the first trenches 74f in a plan view. The second trenches 74b are arranged parallel to the second trenches 74h in a plan view.

[0189] The number of second trenches 74b, which are located in a plan view between the first trenches 74f and between the second trenches 74h, is in Fig. 41 equals one, but it can also be two or greater. As in Fig. As shown in Figure 41, the second trenches 74b are connected to the second trenches 74d in a plan view. The second trenches 74b are also connected to the first trenches 74g or the second trenches 74i in a plan view.

[0190] As in the Fig. 40 and Fig. As shown in Figure 41, four second layers 52 of the p+ type are arranged within the second trough layer 26 such that they are in contact with the ohmic electrode 81 on the front surface. The number of second layers 52 of the p+ type is given above as four, but it can be any number.

[0191] Next, a method for manufacturing the semiconductor unit according to the present embodiment is described. In the method for manufacturing the semiconductor unit according to the present embodiment, it is only necessary that the second grooves 74d are arranged in a top view between the first grooves 74g and between the second grooves 74i in the manufacturing process according to embodiment 12. Furthermore, it is only necessary that the second grooves 74b are arranged in a top view between the first grooves 74f and between the second grooves 74h.

[0192] As described above, in the semiconductor unit according to the present embodiment, the second grooves 74d are located, in a top view, between the first grooves 74g and between the second grooves 74i in the semiconductor unit according to embodiment 12. The second grooves 74d, located between the aforementioned first grooves 74, are arranged parallel to the first grooves 74 in a top view. The second grooves 74b are also located, in a top view, between the first grooves 74f and between the second grooves 74h. As a result, the channel width density is higher than that of the semiconductor unit according to embodiment 12. This also results in a reduction of the channel resistance of the semiconductor unit.

[0193] It is possible that the second gate electrode 71b is not directly connected to the second gate electrode 71d, the first gate electrode 71g, and the second gate electrode 71i. It is only necessary that the second gate electrode 71b be electrically connected to the second gate electrode 71d, the first gate electrode 71g, and the second gate electrode 71i. In this case, a similar effect will be produced. embodiment 14

[0194] The following describes a configuration according to the present embodiment using the Fig. 42 and Fig. 43 described. Fig. 42 is a cross-sectional view of a semiconductor unit according to the present embodiment along an auxiliary line PP' of Fig. 43. Fig. Figure 43 is a top view showing an upper surface of a semiconductor region of the semiconductor unit according to the present embodiment. The semiconductor unit according to the present embodiment has many similarities to the semiconductor unit according to embodiment 5, and only differences from the semiconductor unit according to embodiment 5 are described.

[0195] As in Fig. As shown in Figure 42, the semiconductor unit according to the present embodiment has a superjunction layer 15b instead of the superjunction layer 15. The superjunction layer 15b has n-type support layers 13b instead of the n-type support layers 13. Each of the n-type support layers 13b has a smaller width than each of the p-type support layers 14. That is, the distance between the p-type support layers 14 is smaller than the distance between the n-type support layers.

[0196] Next, a method for fabricating the semiconductor unit according to the present embodiment is described. The method for fabricating the semiconductor unit according to the present embodiment is similar to the method for fabricating the semiconductor unit according to embodiment 5, except that each of the n-type support layers 13b is formed such that it has a smaller width than each of the p-type support layers 14.

[0197] As described above, each of the n-type support layers 13b in the semiconductor device according to the present embodiment has a smaller width than each of the p-type support layers 14. That is, the distance between the p-type support layers 14 is smaller than the distance between the n-type support layers. Due to the smaller width of each of the n-type support layers 13b, the channel width density of the semiconductor device is higher. This also results in a reduction of the channel resistance of the semiconductor device.

[0198] In the semiconductor unit according to the present embodiment, the support layers 13b of n-type can be formed in a grid in a top view, and the support layers 14 of p-type can be formed in points in areas surrounded by the support layers 13b of n-type formed in a grid in a top view, as in embodiment 12 and embodiment 13.

[0199] In this case as well, the channel width density of the semiconductor unit is higher due to the smaller width of each of the n-type support layers 13b. As a result, the channel resistance of the semiconductor unit is reduced, similar to the effect observed in the present embodiment. Design 15

[0200] A power converter according to the present embodiment is a power converter in which the semiconductor unit according to any of the embodiments 1 to 14 described above is used. With regard to the power converter according to the present invention, a case is described in which the present invention is used in a three-phase inverter.

[0201] Fig. Figure 44 is a functional block diagram showing a configuration of a power converter 301 in which the power converter is used according to the present embodiment. A power supply 321 and a load 331 are connected to the power converter shown in Figure 44. Fig. The power converter 301 shown in Figure 44 is connected. For example, the power supply 321 is a power supply that converts a commercial AC power supply into DC using an AC / DC converter and supplies the DC current to the power converter 301.

[0202] The power converter 301 is a three-phase inverter connected between the power supply 321 and the load 331. The power converter 301 converts the direct current supplied by the power supply 321 into alternating current and supplies the alternating current to the load 331. As shown in Fig. As shown in Figure 44, the power converter 301 comprises the following: a main converter 311 for converting direct current into alternating current and supplying the alternating current, a driver 312 for outputting driver signals for driving switching elements contained in the main converter 311, and a control unit 313 for outputting a control signal to the driver 312 for controlling the driver 312. The load 331 is a three-phase motor driven by the alternating current supplied by the power converter 301.

[0203] The main converter 311 receives the direct current supplied by the power supply 321 as input power. The main converter 311 comprises switching elements and freewheeling diodes. The main converter 311 converts the input power into alternating current by switching the switching elements and supplies the alternating current to the load 331. There are various special circuit configurations for the main converter 311. The main converter 311 according to the present embodiment, for example, is a two-stage three-phase full-bridge circuit. The main converter 311 according to the present embodiment can have six switching elements and six freewheeling diodes, which are connected antiparallel to the respective switching elements.

[0204] Each of the switching elements of the main converter 311 is a semiconductor unit 314 described according to any one of embodiments 1 to 14. Two switching elements of the six switching elements connected in series form upper and lower branches, and each upper and lower branch forms a U-phase, a V-phase, and a W-phase of the full bridge circuit. Output terminals of the respective upper and lower branches, that is, three output terminals of the main converter 311, are connected to the load 331.

[0205] The driver 312 generates the driver signals for driving the switching elements of the main converter 311 and outputs the driver signals to control electrodes of the switching elements of the main converter 311. In particular, the driver 312 outputs a driver signal to switch each of the switching elements to the ON state and a driver signal to switch the switching element to the OFF state in order to control an electrode of the switching element according to the control signal output by the control unit 313.

[0206] The control unit 313 controls the switching elements of the main converter 311 such that a desired current is supplied to the load 331. In particular, if the main converter 311 is operated, for example, by pulse width modulation (PWM) control, the control unit 313 calculates a circuit diagram of the switching elements based on the current to be supplied to the load 331 and outputs the control signal for implementing the circuit diagram to the driver 312. Based on the control signal, the driver 312 outputs an on signal or an off signal as the driver signal to the control electrode of each of the switching elements.

[0207] The power converter according to the present embodiment has a semiconductor unit according to any of embodiments 1 to 14 as each of the switching elements included in the main converter 311, so that an effect is produced by which a power converter is achieved which has low losses and enables fast switching operations.

[0208] The power supply is described as one that converts a commercial AC power supply into a DC power supply using the AC / DC converter according to the present embodiment; however, it can also be a power supply of another type. For example, the power supply could be a commercial DC power supply, a solar cell, a storage battery, a rectifier circuit connected to an AC power supply, an output of the AC / DC converter, or an output of a DC / DC converter.

[0209] The semiconductor substrate is described as a silicon carbide substrate 11 in the semiconductor unit according to each of embodiments 1 to 14, but it need not necessarily be a silicon carbide substrate and may also consist of silicon, diamond and other wide bandgap semiconductors, compound semiconductors and oxide semiconductors.

[0210] The first main surface of the silicon carbide substrate 11 is specified such that it is inclined at 4° with respect to the (0001) plane in the [11-20] direction in the semiconductor unit according to each of embodiments 1 to 14; however, another crystalline plane, such as a (000-1) plane, may also be used, and the inclination angle may also be a different angle, such as 0° to 8°. The polytype of the silicon carbide is specified as 4H; however, it may also be another polytype, such as 3C and 6H.

[0211] The first conductivity type and the second conductivity type are specified in the semiconductor unit according to each of embodiments 1 to 14 as n-type and p-type respectively, but the first conductivity type and the second conductivity type may also be p-type and n-type respectively.

[0212] In the semiconductor unit according to each of embodiments 1 to 14, aluminum is given as an example of p-type defects; however, p-type defects can also be other elements of Group III, such as boron (B) and gallium (Ga). Nitrogen (N) is given as an example of n-type defects; however, n-type defects can also be other elements of Group V, such as phosphorus (P) and arsenic (As).

[0213] When the first well layer 21 is formed in the semiconductor unit according to any of embodiments 1 to 14, ion implantation is used; however, the first well layer 21 can also be formed by a method in which, for example, after epitaxial growth of the p-type semiconductor layer, ions from n-type defects are implanted into a semiconductor region that is to become an n-type region, distinct from the first well layer 21. Any other semiconductor regions formed by ion implantation can be formed using epitaxial growth, provided this is carried out as a single fabrication process.

[0214] Silicon dioxide is used as a material for: the first dielectric layer 35 on the lateral surface, the first dielectric layer 36 on the bottom surface, the first dielectric layer 36a on the bottom surface, the second dielectric layer 35b on the lateral surface, the second dielectric layer 36b on the bottom surface, the third dielectric layer 35c on the lateral surface, the third dielectric layer 36c on the bottom surface, the second dielectric layer 35d on the lateral surface, the second dielectric layer 36d on the bottom surface, the fourth dielectric layer 35e on the lateral surface, the fourth dielectric layer 36e on the bottom surface, the first dielectric layer 35f on the lateral surface, the first dielectric layer on the bottom surface, which is not shown, in each of the first trenches 74f, the first dielectric layer 35g on the lateral surface,the first dielectric layer 36g on the bottom surface, the second dielectric layer 35h on the side surface, and the second dielectric layer on the bottom surface, which is not shown, in each of the second grooves 74i in the semiconductor unit according to each of embodiments 1 to 14, but these may also be thermal oxide layers formed by thermal oxidation, or they may be deposited layers formed by CVD.

[0215] Dielectric layers made of a material other than silicon dioxide can also be used, such as dielectric layers made of silicon nitride, dielectric layers made of aluminum oxide, and dielectric layers with a high dielectric constant.

[0216] Doped polysilicon is used as the material for: the first gate electrode 71, the second gate electrode 71b, the third gate electrode 71c, the second gate electrode 71d, the fourth gate electrode 71e, the first gate electrode 71f, the first gate electrode 71g, the second gate electrode 71h and the second gate electrode 71i in the semiconductor unit according to each of embodiments 1 to 14, the conductivity type of which may also be either the n-type or the p-type, and instead of doped polysilicon, aluminum, an aluminum alloy, and any other metals, metal silicide layers or a stack thereof may be used.

[0217] In the semiconductor unit according to each of embodiments 1 to 14, the source electrode 82 is made of aluminum, but it can also be made of other metals, alloys or a stack thereof.

[0218] In the semiconductor unit according to each of embodiments 1 to 14, the first p+-type layers 23 and the second p+-type layers 52 are described such that, in one case, they are formed in strips, as are the support layers 13 of n-type and the support layers 14 of p-type; however, they can also be formed in dots. It is only required that at least some region of each of the first p+-type layers 23 and some region of each of the second p+-type layers 52 overlap with the p-type semiconductor regions below them in a top view. However, in a case where the regions in contact with the p-type semiconductor regions below them are small, a problem may arise, such as an increase in switching losses and a deterioration in reliability.

[0219] In the semiconductor unit according to each of embodiments 1 to 11 and 14, the n-type support layers 13 or the n-type support layers 13b and the p-type support layers 14 are arranged in strips in a top view. However, it is only necessary in the active region for the n-type support layers 13 or the n-type support layers 13b and the p-type support layers 14 to be arranged in strips in a top view. In the termination region, it is not necessary for the n-type support layers 13 or the n-type support layers 13b and the p-type support layers 14 to be arranged in strips in a top view.

[0220] In the semiconductor unit according to each of embodiments 12 and 13, the n-type support layers 13a are arranged in a grid in a top view, and the p-type support layers 14a are arranged in a top view at points separated by the n-type support layers 13a. However, it is only required in the active region that the n-type support layers 13a are arranged in a grid in a top view and that the p-type support layers 14a are arranged in a top view at points separated by the n-type support layers 13a.

[0221] In the connection area, it is not necessary for the support layers 13a of n-type to be arranged in a grid in a plan view, and it is not necessary for the support layers 14a of p-type to be arranged in a plan view at points separated by the support layers 13a of n-type.

[0222] Dimensions, manufacturing processes, heat treatment conditions and the like for components of the semiconductor unit according to each of embodiments 1 to 14 are described using specific examples, but are not limited to those shown and may be modified as necessary.

[0223] As long as a semiconductor unit has the configuration of the semiconductor unit according to each of embodiments 1 to 14, the effect of the present invention is not dependent on the manufacturing process for the same, and in a case where the semiconductor unit is manufactured by means of a different manufacturing process, a similar effect can be achieved.

[0224] In the semiconductor device according to each of embodiments 2 to 14, a region with the second conductivity type within each of the p-type support layers 14 and the p-type support layers 14a has the second well layer 26. The second well layer 26 can have the same concentration of defects with the second conductivity type as a region with the second conductivity type that differs from the second well layer 26 within each of the p-type support layers 14 and the p-type support layers 14a. That is, the second well layer 26 need not be formed. Industrial applicability

[0225] The present invention can be used, for example, in power semiconductor units with a superjunction structure. EXPLANATION OF REFERENCE MARKS 11 Silicon carbide substrate 12 epitaxial crystalline layer 13 Support layer of n-type 14 p-type support layer 14a p-type support layer 15 Super-Junction Layer 17 Oxide layer 18 a supporting trench 19 epitaxial crystalline layer 21 first layer of depressions 22 first source layer 23 first layer of p+ type 26 second layer of depressions 27 second source layer 27a second source layer 33 dielectric intermediate layer 35 first dielectric layer on the side surface 36 first dielectric layer on the floor surface 36a first dielectric layer on the floor surface 35b second dielectric layer on the lateral surface 36b second dielectric layer on the floor surface 35c third dielectric layer on the side surface 36c third dielectric layer on the floor surface 35d second dielectric layer on the side surface 36d second dielectric layer on the floor surface 35e fourth dielectric layer on the side surface 36e fourth dielectric layer on the floor surface 35f first dielectric layer on the side surface 35g first dielectric layer on the side surface 36g first dielectric layer on the base surface 35h second dielectric layer on the side surface 35i second dielectric layer on the side surface 40 Semiconductor area 52 second layer of p+ type 71 first gate electrode 71b second gate electrode 71c third gate electrode 71d second gate electrode 71e fourth gate electrode 71f first gate electrode 71g first gate electrode 71h second gate electrode 71i second gate electrode 74 first trench 74a first trench 74b second trench 74c third trench 74d second trench 74e fourth trench 74f first trench 74g first trench 74h second trench 74i second trench 81 ohmic electrode on the front surface 82 Source electrode 91 ohmic electrode on the rear surface 92 Drain electrode 301 Power converters 311 Main Converter 312 drivers 313 Control unit 314 Semiconductor unit 321 Power supply 331 Last 501 Arrow 502 Arrow 503 Arrow and 504 Arrow

Claims

Semiconductor unit with a semiconductor region (40) having a first main surface and a second main surface opposite the first main surface, the semiconductor region comprising: - alternating first support layers (13) with a first conductivity type and second support layers (14) with a second conductivity type along the first main surface; - a first trough layer (21) with the second conductivity type located within each of the first support layers (13) on an upper surface of the first support layer (13); - a first source layer (22) with the first conductivity type located within the first trough layer (21) on an upper surface of the first trough layer (21); - a first dielectric layer (35) on a lateral surface located on a lateral surface in a first trench (74),which is located at the boundaries between the first support layers (13) and the second support layers (14), wherein the first dielectric layer on the lateral surface is in contact with the first trough layer (21) and the first source layer (22); - a first dielectric layer (36) on a bottom surface located on a bottom surface in the first trench, wherein the first dielectric layer (36) on the bottom surface is at least partially in contact with one of the second support layers (14); and - a first gate electrode (71) located in the first trench, which is opposite the first trough layer (21) and the first source layer (22) by means of the first dielectric layer (35) on the lateral surface and opposite the second support layer (14) by means of the first dielectric layer (36) on the bottom surface,- wherein each of the second support layers (14) has a second source layer (27) of the first conductivity type located within the second support layer at an upper surface of the second support layer, - wherein the first dielectric layer (35) is located on the lateral surface on opposite lateral surfaces in the first trench and is in contact with an area (26) of the second conductivity type within the second support layer (14) and the second source layer (27), - wherein the first dielectric layer is located on the bottom surface in contact with the area of ​​the second conductivity type within the second support layer (14), and - wherein a lower surface of the second source layer (27) is located closer to the second main surface than a lower surface of the first source layer (22). Semiconductor unit according to claim 1, wherein each of the second support layers (14) has a second well layer (26) with the second conductivity type located within the second support layer (14) on an upper surface of the second support layer (14), and wherein the second source layer (27) is located within the second well layer (26) on an upper surface of the second well layer (26). Semiconductor unit according to claim 1 or 2, wherein the first dielectric layer (36) on the bottom surface has a lesser thickness than the first dielectric layer (35) on the side surface. Semiconductor unit according to one of claims 1 to 3, wherein the first dielectric layer (36) on the bottom surface is in contact with the second support layer (14) and one of the first support layers (13). Semiconductor unit according to any one of claims 1 to 4, further comprising: - a third dielectric layer (35c) on a lateral surface, which is located on a lateral surface in a third trench (74c) which, in a top view, is arranged within each of the second support layers (14) in a direction perpendicular to the first trench; - a third dielectric layer (36c) on a bottom surface, which is located on a bottom surface of the third trench (74c); and - a third gate electrode (71c) which is located in the third trench (74c) and is opposite the region with the second conductivity type within the second support layer (14) and the second source layer (27) by the third dielectric layer (35c) on the lateral surface. Semiconductor unit according to claim 5, wherein the third gate electrode (71c) is connected to the first gate electrode (71). Semiconductor unit according to any one of claims 1 to 6, further comprising: - a fourth dielectric layer (35e) on a lateral surface, which is located on a lateral surface in a fourth trench (74e) which, in a top view, is arranged within each of the second support layers (14) in a direction parallel to the first trench, wherein opposing lateral surfaces of the fourth dielectric layer (35e) on the lateral surface are in contact with the area with the second conductivity type within the second support layer (14) and the second source layer (27); - a fourth dielectric layer (36e) on a bottom surface, which is located on a bottom surface of the fourth trench;and a fourth gate electrode (71e) located in the fourth trench and opposite the area with the second conductivity type within the second support layer (14) and the second source layer (27) by the fourth dielectric layer (35e) on the lateral surface. Semiconductor unit according to any one of claims 1 to 7, further comprising: - a second dielectric layer (35d) on a lateral surface, which is located on a lateral surface in a second trench which is located within each of the first support layers (13); - a second dielectric layer (36d) on a bottom surface which is located on a bottom surface in the second trench; and - a second gate electrode (71d) which is located in the second trench and is opposite the first trough layer (21) and the first source layer (22) by the second dielectric layer (35d) on the lateral surface. Semiconductor unit according to claim 8, wherein the second trench is arranged in a top view in a direction parallel to the first trench. Semiconductor unit according to claim 8 or 9, wherein the second gate electrode (71d) is connected to the first gate electrode (71). Semiconductor unit according to one of claims 1 to 10, wherein the first support layers (13) and the second support layers (14) are arranged in strips in an active region in a top view. Semiconductor unit according to one of claims 1 to 11, wherein in an active region the first support layers (13) are arranged in a grid in a top view and the second support layers (14) are arranged in a top view at points separated by the first support layers (13). Semiconductor unit according to claim 11 or 12, wherein the distance between the second support layers (14) is less than the distance between the first support layers (13). Semiconductor unit according to claim 11 or 12, wherein the distance between the first support layers (13) is constant and the distance between the second support layers (14) is constant. Semiconductor unit according to any one of claims 1 to 14, wherein the semiconductor area consists of silicon carbide. Power converter comprising: - a main converter (311) to convert an input power using a semiconductor unit according to any one of claims 1 to 15 as a switching element; - a driver (312) to output a driver signal to the semiconductor unit for driving the semiconductor unit; and - a control unit (313) to output a control signal to the driver (312) for controlling the driver (12).

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