Semiconductor unit and power converter

Abstract

Semiconductor unit (103) comprising the following: - a semiconductor substrate (50) consisting of a semiconductor having a higher linear expansion coefficient than silicon, wherein the semiconductor substrate comprises: a source region (4) having a first conductivity type, a base region (2) having a second conductivity type different from the first conductivity type, and a drift layer (1) separated from the source region (4) by the base region (2) and having the first conductivity type, wherein the semiconductor substrate has a main surface (S2) having a region formed from the source region (4); - a dielectric gate layer (5) covering the base region (2) of the semiconductor substrate (50); - a gate electrode (6) which is opposite the base region (2) of the semiconductor substrate (50) by the dielectric gate layer (5); - a first electrode layer (91) which is electrically connected to the source region (4) of the semiconductor substrate (50) and is arranged above the main surface (S2) of the semiconductor substrate (50); - a second electrode layer (92) which is electrically connected to the gate electrode (6) and is arranged above the main surface (S2) of the semiconductor substrate (50) at a distance from the first electrode layer (91); - a third electrode layer (93) arranged above the main surface (S2) of the semiconductor substrate (50) at a distance from the first electrode layer (91); and - a dielectric protective layer (20) arranged over the main surface (S2) of the semiconductor substrate (50), wherein the main surface is provided with the first electrode layer (91), the second electrode layer (92) and the third electrode layer (93), wherein the dielectric protective layer covers only a region of each of the first electrode layer (91) and the second electrode layer (92) and covers at least a region of the third electrode layer (93), wherein the dielectric protective layer (20) consists of a thermosetting resin, - wherein the main surface (S2) of the semiconductor substrate (50) has a peripheral substrate region (RA) and an inner substrate region (RB) enclosed by the peripheral substrate region (RA), and the dielectric protective layer (20) has a peripheral protective layer region (29) covering the peripheral substrate region (RA), and has a first inner protective layer region (21) covering at least a region of the third electrode layer (93) and intersecting the inner substrate region (RB), and - wherein the semiconductor unit further comprises at least one electrical element (60) which is connected to the third electrode layer (93) and is covered by the first inner protective layer region (21) of the dielectric protective layer (20), - wherein the dielectric protective layer (20) has an opening (OP) such that the dielectric protective layer (20) comprises less than half of the main surface area (S2) of the semiconductor substrate (50), - wherein the opening (OP) in a top view has a rim with a first corner region on the side of a corner of the main surface (S2) and the first corner region is curved, - wherein the edge of the opening (OP) in the top view has a second corner region formed from the peripheral protective layer region (29) and the first inner protective layer region (21) of the dielectric protective layer (20), and the first corner region is less curved than the second corner region, and wherein the at least one electrical element (60) is completely covered in the top view by the first inner protective layer region (21) of the dielectric protective layer (20), and is located in the inner substrate region (RB) closer to a center than to an edge of the semiconductor unit (103).

Description

TECHNICAL AREA

[0001] The present invention relates to semiconductor units and power converters, and in particular to a semiconductor unit having a dielectric protective layer consisting of a thermosetting resin, and to a power converter. STATE OF THE ART

[0002] Patent document 1 discloses a power converter comprising an inverter circuit. The power converter includes a semiconductor unit as a switching element. When the power converter is in a drive state, the semiconductor unit performs a switching operation. In this case, the semiconductor unit generates a significant amount of heat. When the power converter switches between a standby state and the drive state, the amount of heat generated by the semiconductor unit changes considerably.

[0003] The power converter is therefore subject to thermal cycling. To ensure long-term reliability of the power converter, it is necessary that the power converter has a module design that is resistant to thermal cycling.

[0004] Patent document 2 discloses a metal-oxide-semiconductor field-effect transistor (MOSFET) manufactured using silicon carbide (SiC), i.e., a SiC MOSFET. The on-resistance of the MOSFET can be significantly reduced by using SiC as a wide-bandgap semiconductor. Consequently, SiC MOSFETs are now being used in power converters. The MOSFET features a polyimide layer with an opening serving as a dielectric protective layer.

[0005] Patent document 3 discloses a MOSFET comprising a diode as a temperature sensor element, as well as an anode electrode and a cathode electrode connected to the diode. An increase in the MOSFET's temperature, caused by the aforementioned heat, can be detected by the temperature sensor element. Furthermore, the MOSFET's operation can be stabilized by referring to the detected information.

[0006] For further information on the state of the art, reference should be made to patent documents 4 to 8. DOCUMENTS ON THE STATE OF THE TECHNOLOGY Patent documents Patent document 1: Japanese patent application disclosure JP 2002 - 095 268 A Patent document 2: Japanese patent application disclosure JP 2017 - 168 602 A Patent document 3: Japanese patent application disclosure JP 2012 - 129 503 A Patent document 4: US 2017 / 0 110 545 A1 Patent document 5: US 2012 / 0 132 912 A1 Patent document 6: US 2017 / 0 111 037 A1 Patent document 7: US 2016 / 0 241 018 A1 Patent document 8: WO 2017 / 169 086 A1 SHORT DESCRIPTION Problems to be solved with the invention

[0007] The technology disclosed in patent document 1 and described above was designed to improve the reliability of the connection between the semiconductor unit and the elements mounted on it, and was not designed to improve the configuration of the semiconductor unit itself. Therefore, high reliability cannot be achieved if the semiconductor unit itself is susceptible to thermal cycling.

[0008] According to the technology described above, disclosed in patent document 2, the semiconductor unit comprises a polyimide layer with the opening serving as a dielectric protective layer. Due to the influence of thermal cycling, the dielectric layer can deteriorate, leading, for example, to the formation of cracks or wrinkles caused by differences in the layer's density, and the like.

[0009] In particular, when the coefficient of linear expansion (the coefficient of linear expansion) in a semiconductor region is high, the dielectric protective layer is likely to degrade as a result of an increase in the difference between the coefficient of linear expansion in the semiconductor region and the coefficient of linear expansion of the dielectric protective layer. The coefficient of linear expansion of SiC is 6.6 × 10 -6 / K, for example, is significantly higher than the linear coefficient of thermal expansion of silicon (Si) at 2.5 × 10 -6 / K.

[0010] Furthermore, SiC is a semiconductor material that is more suitable for high-temperature operation than Si, and therefore, semiconductor devices made using SiC are frequently employed at high temperatures. Stresses acting on the dielectric protective layer due to the difference in linear expansion coefficients can be much greater in the case of SiC than in the case of Si.

[0011] According to the technology disclosed in patent document 3, as described above, the semiconductor unit has a structure comprising a diode as a temperature sensor element, as well as an anode electrode and a cathode electrode connected to the diode. The document is silent regarding the protection of the structure by the use of a dielectric protective layer.

[0012] According to an investigation by the current inventors, it is desirable to protect the structure using a dielectric protective layer to ensure reliability. In this case, the shape of an opening in the dielectric protective layer is influenced by the arrangement of the structure. Depending on the shape of the opening, local deterioration of the dielectric protective layer is likely to occur.

[0013] The present invention was designed to solve the problems described above, and its object is to provide a semiconductor unit with which deterioration of a dielectric protective layer can be prevented. Means of solving the problems

[0014] The problem underlying the invention is solved by a semiconductor unit having the features of independent claim 1. Advantageous embodiments of the semiconductor unit according to the invention are specified in dependent claims 2 to 15. Furthermore, the problem underlying the invention is also solved by a power converter according to claim 16. Effects of the invention

[0015] According to the present invention, the dielectric protective layer has a first inner region that covers at least a region of the third electrode layer to protect a structure comprising the third electrode layer. The first inner region intersects the inner region enclosed by the peripheral region of the dielectric protective layer, such that one end and the other end of the first inner region are each connected to the peripheral region of the insulating protective layer. This prevents the propagation of local deterioration of the dielectric protective layer at both ends of the first inner region. Thus, deterioration of the dielectric protective layer can be prevented.

[0016] The objectives, features, aspects and advantages of the present invention will become even clearer from the following detailed description and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The figures show: Fig. 1 a top view schematically representing a configuration of a semiconductor unit according to embodiment 1 of the present invention; Fig. 2 a top view showing the configuration of the semiconductor unit according to Fig. 1 schematically represents, without depicting a dielectric protective layer; Fig. 3 a top view to describe a configuration of the dielectric protective layer of the semiconductor unit according to Fig. 1; Fig. 4 a schematic section view along a line IV-IV according to Fig. 1; Fig. 5 a schematic section view along a line VV according to Fig. 1; Fig. 6 a schematic section view along a line VI-VI according to Fig. 1; Fig. 7 a schematic section view along a line VII-VII according to Fig. 1; Fig. 8 a section view that schematically represents a configuration of a semiconductor unit according to a modification; Fig. 9 a top view showing a configuration of a semiconductor unit according to a comparative example; Fig. 10 a top view to describe a configuration of a dielectric protective layer of the semiconductor unit according to Fig. 9; Fig. 11 a top view schematically representing a configuration of a semiconductor unit according to embodiment 2 of the present invention; Fig. 12 a top view to describe a configuration of a dielectric protective layer of the semiconductor unit according to Fig. 11; Fig. 13 a top view schematically representing a configuration of a semiconductor unit according to embodiment 3 of the present invention; Fig. 14 a schematic section view along a line XIV-XIV according to Fig. 13; Fig. 15 an enlarged view of an area according to Fig. 14 and a section view, which provides a first example of a cross-sectional shape of a dielectric protective layer; Fig. 16 an enlarged view of an area according to Fig. 14 and a section view showing a second example of the cross-sectional shape of the dielectric protective layer; Fig. 17 an enlarged view of an area according to Fig. 14 and a section view showing a third example of the cross-sectional shape of the dielectric protective layer; Fig. 18 a section view showing an example of a cross-sectional shape of a first inner region of the dielectric protective layer; Fig. 19 a section view showing a configuration of a semiconductor unit according to a modification according to Fig. 14 schematically represents; Fig. 20 a section view schematically representing a configuration of a semiconductor unit according to embodiment 4 of the present invention; Fig. 21 a block diagram schematically representing a configuration of a power converter system in which a power converter according to embodiment 5 of the present invention is used. DESCRIPTION OF EXECUTION FORMS

[0018] The following describes embodiments of the present invention based on the drawings. The same or equivalent components in the drawings bear the same reference numeral, and a description of them is not repeated below. Design 1

[0019] Fig. Figure 1 is a top view schematically representing a configuration of a MOSFET 101 (a semiconductor unit) according to embodiment 1. Fig. Figure 2 is a top view showing the configuration of MOSFET 101 according to Fig. Figure 1 schematically represents the structure without depicting a polyimide layer 20 (a dielectric protective layer). Fig. Figure 3 is a top view to describe a configuration of the polyimide layer 20 ( Fig. 1). In Fig. For the sake of simplicity, the polyimide layer 20 is shown as a dashed line in 3.

[0020] The Fig. 4, Fig. 5, Fig. 6 and Fig. 7 are schematic section views along lines IV-IV, VV, VI-VI and VII-VII according to Fig. 1. Although described in detail below, it corresponds to Fig. 4 along line IV-IV ( Fig. 1) an area in which an outer edge of a source electrode contact point 91 (a first electrode layer) is covered with the polyimide layer 20. Fig. 5 along line VV ( Fig. 1) corresponds to an area in which a gate electrode contact point 92 (a second electrode layer) is covered with the polyimide layer 20. Fig. 6 along line VI-VI ( Fig. 1) and Fig. 7 along line VII-VII ( Fig. 1) correspond to an area in which a temperature sensor element 60 ( Fig. 6) is arranged, which is connected to an electrode layer 93 (a third electrode layer).

[0021] As in Fig. As shown in Figure 4, the MOSFET 101 comprises the following: a SiC substrate 50 (a semiconductor substrate), a dielectric gate layer 5, a gate electrode 6, a dielectric intermediate layer 7, a source contact electrode 8, the source electrode contact 91, the polyimide layer 20, and a back electrode 10. The MOSFET 101 may have a barrier layer 81.

[0022] The SiC substrate 50 consists of SiC, and SiC has a higher coefficient of linear expansion than Si, as described above. The SiC substrate 50 comprises: a source region 4 with an n-type (a first conductivity type), a base region 2 with a p-type (a second conductivity type, different from the first conductivity type), a drift layer 1 with the n-type, and a contact region 3 with the p-type.

[0023] The drift layer 1 is separated from the source region 4 by the base region 2. The SiC substrate 50 has a lower surface S1 and an upper surface S2 (a main surface) opposite the lower surface S1. The upper surface S2 has a region formed by the source region 4 and a region formed by the contact region 3.

[0024] The dielectric gate layer 5 covers the base region 2 of the SiC substrate 50. The gate electrode 6 is located opposite the base region 2 of the SiC substrate 50 through the dielectric gate layer 5. The gate electrode 6 consists of a conductive material, such as impurity-doped polysilicon. According to the present embodiment, the gate electrode 6 has a planar structure. In other words, the gate electrode 6 has a planar shape along its upper surface S2.

[0025] The source contact electrode 8 is in contact with the source region 4 and the contact region 3. A region of the source contact electrode 8 that is in contact with the source region 4 and the contact region 3 is preferably silicidicated. The source contact electrode 8 is, for example, a nickel (Ni) electrode with a silicidicated region that faces the upper surface S2 of the SiC substrate 50.

[0026] The source electrode junction 91 is a terminal electrode for supplying a source potential from the exterior of the MOSFET 101. The source electrode junction 91 is positioned above the upper surface S2, on which the source contact electrode 8 is located. The source electrode junction 91 is in contact with the source contact electrode 8, thus electrically connecting it to the source region 4 and the contact region 3 of the SiC substrate 50. This electrical connection can extend through the barrier layer 81.

[0027] The source electrode junction 91 and the gate electrode 6 are insulated from each other by the dielectric intermediate layer 7. The dielectric intermediate layer 7 typically consists of an inorganic material. The source electrode junction 91 consists of a metal, such as aluminum (Al) or an alloy thereof.

[0028] The barrier layer 81 consists of a metal that has a high capacity to occlude hydrogen atoms or hydrogen ions, such as titanium (Ti). A process for manufacturing the MOSFET 101 sometimes involves the generation of hydrogen atoms or hydrogen ions, and the barrier layer 81 prevents the penetration of hydrogen atoms or hydrogen ions into the dielectric intermediate layer 7. The barrier layer 81 can also prevent the penetration of hydrogen atoms or hydrogen ions from the outside.

[0029] The back electrode 10 is located on the lower surface S1 of the SiC substrate 50. The back electrode 10 functions as a drain electrode of the MOSFET 101.

[0030] As in Fig. As shown in Figure 5, the MOSFET 101 has the gate electrode contact 92 and a silicon oxide layer 11 (a dielectric layer) and may have a barrier layer 82 made of a metal. The barrier layer 82 is made of a similar material to the barrier layer 81 and thus has a similar function.

[0031] Barrier layer 82 is separated from barrier layer 81.

[0032] The gate electrode contact point 92 is a connection electrode for obtaining a gate potential from the outside of the MOSFET 101. The gate electrode contact point 92 is shown in a top view ( Fig. 2) arranged at a distance from the source electrode contact point 91. The gate electrode contact point 92 is preferably located approximately 1 µm or more away from the source electrode contact point 91. The gate electrode contact point 92 is positioned above the upper surface S2 above which the gate electrode 6 is arranged. The gate electrode contact point 92 is electrically connected to the gate electrode 6. They can be electrically connected through the barrier layer 82.

[0033] In the vicinity of the gate electrode junction 92, the gate electrode 6 and the upper surface S2 are insulated from each other by the silicon oxide layer 11. The gate electrode junction 92 consists of a metal, such as A1 and an alloy thereof. The gate electrode junction 92 preferably consists of the same material as the source electrode junction 91.

[0034] As in the Fig. 6 and Fig. As shown in Figure 7, the MOSFET 101 has the electrode layer 93 and the temperature sensor element 60 (an electrical element) connected to the electrode layer 93. The MOSFET 101 can have an oxide layer 41 (a dielectric layer) and a dielectric intermediate layer 42.

[0035] The electrode layer 93 is shown in a top view ( Fig. 2) arranged remotely from the source electrode contact point 91. The electrode layer 93 is preferably located approximately 1 µm or more away from the source electrode contact point 91. According to the present embodiment, the electrode layer 93 is shown in a top view ( Fig. 2) arranged away from the gate electrode contact point 92.

[0036] The electrode layer 93 is preferably located approximately 1 µm or more away from the gate-electrode contact point 92. The electrode layer 93 consists of a metal, such as A1 and an alloy thereof. The electrode layer 93 preferably consists of the same material as at least one of the source-electrode contact point 91 and the gate-electrode contact point 92, and more preferably consists of the same material as these two.

[0037] The electrode layer 93 is positioned above the upper surface S2, on which the silicon oxide layer 11 is arranged. According to the present embodiment, the electrode layer 93 is thus insulated from the SiC substrate 50. It is possible that the electrode layer 93 extends not only through the silicon oxide layer 11, but also through the dielectric intermediate layer 42 and the oxide layer 41 above the upper surface S2, as shown.

[0038] The electrode layer 93 comprises an anode electrode layer 93a and a cathode electrode layer 93c. The temperature sensor element 60 is a pn diode and has a p-type anode region 61 and an n-type cathode region 62. The anode electrode layer 93a and the cathode electrode layer 93c are each connected to the anode region 61 and the cathode region 62, respectively.

[0039] Each of the anode electrode layer 93a and the cathode electrode layer 93c has a contact area (in Fig. 2 a substantially rectangular area) as well as a wiring area (an area extending such that it has a narrower width than the contact area in Fig. 2), which extends from the contact point area. The contact point area is a region of the electrode layer 93 for an electrical connection with the exterior of the MOSFET 101.

[0040] According to the present embodiment, the temperature sensor element 60 is connected to the wiring area. The wiring area is arranged such that it electrically connects the temperature sensor element 60, which is located remotely from the contact point area, to the contact point area.

[0041] Referring to the Fig. 1 and Fig. In Figure 2, the polyimide layer 20 is arranged above the upper surface S2 of the SiC substrate 50, above which the source electrode contact 91, the gate electrode contact 92, and the electrode layer 93 are arranged. The polyimide layer 20 serves as a dielectric protective layer for the MOSFET 101. The polyimide layer 20 is particularly necessary in a semiconductor device that handles a high current, i.e., in a power semiconductor device.

[0042] The polyimide layer 20 is arranged such that the source electrode contact point 91 and the gate electrode contact point 92 are each at least partially exposed. In other words, the polyimide layer 20 is arranged such that it covers only a portion of each of the source electrode contact point 91 and the gate electrode contact point 92.

[0043] The polyimide layer 20 is also arranged such that it covers at least a region of the electrode layer 93. According to the present embodiments, the polyimide layer 20 is arranged such that the contact area of ​​each of the anode electrode layer 93a and the cathode electrode layer 93c is at least partially exposed.

[0044] In other words, the polyimide layer 20 is arranged such that only a portion of each of the anode electrode layer 93a and the cathode electrode layer 93c is covered. According to the present embodiment, the polyimide layer 20 is arranged such that the wiring area of ​​each of the anode electrode layer 93a and the cathode electrode layer 93c is covered.

[0045] To achieve an arrangement as described above, the polyimide layer 20 has an opening OP ( Fig. 3) The opening OP preferably exposes at least half of the upper surface S2 of the SiC substrate 50 in a top view. In other words, the opening OP preferably exposes less than half of the upper surface S2 of the SiC substrate 50 in a top view. In other words, the opening OP preferably exposes directly or indirectly a region of the upper surface S2 of the SiC substrate 50, but does not directly or indirectly expose at least half of the upper surface S2.

[0046] In the present description, terms such as "exposed" and "uncovered" in connection with the polyimide layer 20 mean that a certain area is exposed with respect to the polyimide layer 20. In other words, these terms mean that the area is not covered by the polyimide layer 20. These terms do not imply that covering the area with an element other than the polyimide layer 20 is excluded.

[0047] The polyimide layer 20 has an area covering the source electrode contact point 91, the gate electrode contact point 92, and the electrode layer 93, and has the remaining area. The remaining area may include: an area covering the barrier layer 81 ( Fig. 4), an area covering the barrier layer 82 ( Fig. 5), a (not shown area) that directly covers the dielectric intermediate layer 7 between the barrier layers 81 and 82, an area that directly covers the upper surface S2 of the SiC substrate 50, and the like.

[0048] The polyimide layer 20 consists of a thermosetting resin. That is, the dielectric protective layer 20, according to the present embodiment, consists of a polyimide resin. The polyimide layer 20 preferably has a large thickness with respect to its function of protecting an area to be covered. On the other hand, an extremely large thickness makes it difficult to structure the polyimide layer 20.

[0049] The polyimide layer 20 thus preferably has a thickness of about 1 µm or a greater thickness, and of about 20 µm or a lesser thickness, more preferably has a thickness of about 5 µm or a greater thickness and of about 20 µm or a lesser thickness, and more preferably has a thickness of about 10 µm or a greater thickness and of about 20 µm or a lesser thickness.

[0050] The polyimide layer 20 can be formed by applying a liquid material, curing, and structuring. Structuring can be carried out using a photomechanical process. Alternatively, a dielectric protective layer consisting of a thermosetting resin different from the polyimide resin can be used. Specifically, a thermosetting resin layer consisting of at least one polyimide resin, a silicone resin, an epoxy resin, and a polyurethane resin can be used as the dielectric protective layer.

[0051] Referring to Fig. 3 The upper surface S2 of the SiC substrate 50 has a peripheral region RA and an inner region RB enclosed by the peripheral region RA. The polyimide layer 20 has a peripheral region 29 covering the peripheral region RA and a first inner region 21 covering at least a region of the electrode layer 93. The first inner region 21 intersects the inner region RB. In other words, the first inner region 21 intersects an opening of the peripheral region 29.

[0052] In this configuration, the opening OP of the polyimide layer 20 has a first opening OP1 and a second opening OP2, and these are separated from each other by the first inner region 21. The temperature sensor element 60 ( Fig. 6 and Fig. 7) is preferably covered with the polyimide layer 20. The temperature sensor element 60 is preferably covered with the first inner region 21 of the polyimide layer 20, and in this case the temperature sensor element 60 is arranged in the inner region RB of the SiC substrate 50.

[0053] In addition to the source electrode contact point 91, the gate electrode contact point 92 and the electrode layer 93 ( Fig. 2) can a (in Fig. 2 electrode layer 94 (not shown) arranged as shown in Fig. Figure 8 shows the electrode layer 94, for example, as gate wiring to connect the gate electrode 6 and the gate electrode contact point 92.

[0054] According to the present embodiment, a temperature sensor element is arranged as at least one electrical element covered by the first inner region 21 of the polyimide layer 20. However, instead of a temperature sensor element, at least one electrical element may be arranged comprising at least one diode element, one bipolar transistor element, one resistor element, and one capacitive element. This allows an electrical element covered by the polyimide layer 20, and which is not a unipolar transistor, to be arranged in the inner region RB of the SiC substrate 50.

[0055] In a case where not just one electrical element, but a plurality of electrical elements are arranged, the semiconductor unit can be extended to include a complex function. In particular, in a case where a plurality of semiconductor elements are arranged as a plurality of electrical elements, the semiconductor unit can be extended to include a more complex function, such as a signal processing function.

[0056] In a case where it is not preferred to configure the shape of the opening of the dielectric protective layer only by a simple square, a simple circle or a simple ellipse or the like, it is necessary, due to the aforementioned arrangement of at least one electrical element, that the dielectric protective layer has a shape like the shape of the polyimide layer 20. Comparative example

[0057] Fig. Figure 9 is a top view showing a configuration of a MOSFET 100 according to a comparative example. Fig. Figure 10 is a top view to describe a configuration of the polyimide layer 20 of the MOSFET 100 ( Fig. 9).

[0058] The MOSFET 100 according to the comparative example and the MOSFET 101 according to the present embodiment differ from each other only with respect to the shape of the opening of the polyimide layer 20. In particular, the MOSFET 100 has an inner region 21C ( Fig. 10) instead of the first inner area 21 ( Fig. 3) of the MOSFET 101. The inner region 21C does not intersect the inner region RB of the SiC substrate 50. Assuming that the shape of the polyimide layer 20 is solely for the purpose of ensuring a wider area for electrical contact between the source-electrode junction 91 ( Fig. 2) and is designed for the outside, the first inner area 21 should not be used, but rather the inner area 21C.

[0059] In the configuration mentioned above, one end (the upper end in Fig. 10) The inner region 21C is separated from the peripheral region 29, as indicated by an arrow DF. It is likely that thermal cycling will cause a concentration of stresses at this end, leading to cracking and the like. As a result, local deterioration of the polyimide layer 20 is likely to progress at this end of the inner region 21C. Thus, deterioration of the polyimide layer 20 is likely to occur. Effects

[0060] According to the MOSFET 101 of the present embodiment, the polyimide layer 20, in contrast to that of the aforementioned comparative example, has the first inner region 21 ( Fig. 3) The first inner region 21 intersects the inner region RB, which is enclosed by the peripheral region 29 of the polyimide layer 20, such that one end and the other end of the first inner region 21 are each connected to the peripheral region 29 of the polyimide layer 20. This prevents the progression of local deterioration of the polyimide layer 20 at both ends of the first inner region 21. Deterioration of the polyimide layer 20 is thus prevented.

[0061] The polyimide layer 20 preferably has the opening OP ( Fig. 3) so that at least half of the upper surface S2 of the SiC substrate 50 is exposed. In other words, the opening OP, viewed from above, comprises less than half of the upper surface S2 of the SiC substrate 50. This ensures that the area for an electrical connection between the MOSFET 101 and the outside is sufficient to handle a high current at the opening OP of the polyimide layer 20.

[0062] The electrode layer 93 can be located remotely from the gate-electrode contact point 92. This allows a configuration to be achieved in which the electrode layer 93 is not electrically short-circuited with the gate-electrode contact point 92.

[0063] The temperature sensor element 60 ( Fig. 6 and Fig. 7) is preferably covered with the first inner region 21 of the polyimide layer 20. The temperature sensor element 60 can therefore not be arranged in the peripheral region RA, but is arranged in the inner region RB of the SiC substrate 50 ( Fig. 3) The temperature sensor element 60 is thus positioned near the center of the SiC substrate 50. This places the temperature sensor element 60 at a location that is representative of the temperature of the SiC substrate 50. This increases the accuracy of the temperature measurement. Design 2

[0064] Fig. Figure 11 is a top view schematically representing a configuration of a MOSFET 102 (a semiconductor unit) according to embodiment 2. Fig. Figure 12 is a top view to describe a configuration of the polyimide layer 20 ( Fig. 11) In MOSFET 102, the polyimide layer 20 has at least one second inner region 22 in addition to the peripheral region 29 and the first inner region 21. Every second inner region 22 intersects between the peripheral region 29 and the first inner region 21. This is described in more detail below.

[0065] The inner area RB ( Fig. 3) The SiC substrate 50 has a first region RBa and a second region RBb, which are separated from each other by the first inner region 21. According to the present embodiment, a second inner region 22a and a second inner region 22b of the polyimide layer 20 are each arranged in the first region RBa and the second region RBb of the SiC substrate 50, respectively. The number of second inner regions 22 is two according to the present embodiment, but it can be any number.

[0066] The configuration, with the exception of the configuration mentioned above, is essentially the same as the configuration mentioned above according to embodiment 1, so that the same or corresponding components bear the same reference numeral and a description of the same is not repeated.

[0067] According to the present embodiment, the polyimide layer 20 has the second inner region 22 ( Fig. 12), which crosses between the peripheral region 29 and the first inner region 21. The first inner region 21 is thereby connected at a point between one end and the other end of the first inner region 21 to the other region (i.e., the second inner region 22) of the polyimide layer 20. This prevents deterioration of the long-extending first inner region 21, which is subject to local stresses between its two ends.

[0068] The second inner region 22 intersects here between the peripheral region 29 and the first inner region 21. One end and the other end of the second inner region 22 are thus connected to the other region of the polyimide layer 20. This prevents the progression of local deterioration of the polyimide layer 20 at one end and the other end of the second inner region 22.

[0069] As described above, the arrangement of the second inner region 22 further prevents deterioration of the first inner region 21, and makes it less likely that the second inner region 22 itself will deteriorate. This further prevents deterioration of the polyimide layer 20. embodiment 3

[0070] Fig. Figure 13 is a top view schematically representing a configuration of a MOSFET 103 (a semiconductor unit) according to embodiment 3. Fig. 14 is a schematic section view along a line XIV-XIV according to Fig. 13. According to the present embodiment, an edge of the opening OP of the polyimide layer 20 does not have a right angle, but is angled at the sides of the chip corners OPc ( Fig. 13) slightly bent. This prevents cracking in the polyimide layer 20 at the sides of the chip corners OPc. The cause is described below.

[0071] Stresses caused by a difference in the coefficient of thermal expansion of the SiC substrate 50 and an insulating or metal element placed on it lead to expansion and contraction of the chip in a planar direction. This expansion and contraction are particularly noticeable at the chip's corners. As a result, cracks tend to form in the polyimide layer 20, typically at the sides of the chip corners. According to the configuration described above, this expansion and contraction are reduced, thus preventing cracking in the polyimide layer 20 at the sides of the chip corners.

[0072] As in Fig. As shown in Figure 13, the polyimide layer 20 preferably covers one edge at a time (see the dashed lines in Figure 13). Fig. 13) the source electrode contact point 91, the gate electrode contact point 92 and the electrode layer 93. This allows an area, with the exception of the source electrode contact point 91, the gate electrode contact point 92 and the electrode layer 93, to be completely protected by the polyimide layer 20 in a top view.

[0073] Both Fig. 15, Fig. 16 to Fig. 17 each represents an enlarged view of an area according to Fig. 14 and section views, which represent a first to third example of a cross-sectional shape of the polyimide layer 20. The polyimide layer 20 exhibits in the Fig. 15 and Fig. 16 a tapered or inversely tapered cross-sectional shape. Such cross-sectional shapes can be achieved by structuring the polyimide layer 20 using a wet etching process. Compared to a dry etching process, the use of a wet etching process can increase the etching speed and reduce process costs.

[0074] In Fig. In contrast, the polyimide layer 20 has a cross-sectional shape with a sidewall that extends essentially along its thickness. It is likely that such a cross-sectional shape is achieved when the polyimide layer 20 is structured by a dry etching process. In this case, a corner region is formed (an upper left region in Fig. 17), which has a side wall that is steeper than that in the case according to Fig. 15, and which has an angle of approximately 90°.

[0075] In such a corner area, it is likely that a concentration of layer stresses caused by heat shrinkage will occur, and thus it is likely that cracking will occur in the polyimide layer 20 due to the layer stresses.

[0076] In contrast, in a case where a tapered form is used, as in Fig. As shown in Figure 15, the corner area has an angle of more than 90°, so that there is a probability that layer stresses will be reduced and cracking caused by layer stresses in the polyimide layer 20 will be prevented.

[0077] In a case where the polyimide layer 20 is used with a cross-sectional shape, as in Fig. As shown in 15, the first inner area 21 (see Fig. 3) the dielectric protective layer 20 also has a tapered cross-sectional shape, as in Fig. 18. One edge of the cross-sectional shape can be curved overall, as shown in Fig. 18 shown, so that the concentration of layer stresses is further reduced.

[0078] As in Fig. 14 is preferably located below the polyimide layer 20 at one end of the main surface (the upper surface in Fig. 14) of the SiC substrate 50, a connection structure 30 is arranged. The connection structure 30 is arranged to ensure a suitable breakdown voltage. A specific configuration of the connection structure 30 is not expressly restricted in the case of a Fig. However, in the 14 examples shown, a trough area 31 of the p-type, an area 32 of the n-type formed on it, and a protective ring area 33 of the p-type are formed.

[0079] The configuration, with the exception of the configuration mentioned above, is essentially similar to the configuration mentioned above according to embodiment 1, such that the same or corresponding components bear the same reference numeral and their description is not repeated. Features of the polyimide layer 20 described in the present embodiment apply to each of embodiments 1 and 2. modification

[0080] Fig. Figure 19 is a sectional view showing a configuration of a MOSFET 103V (a semiconductor unit) according to a modification of the MOSFET 103 ( Fig. Figure 14) schematically represents the MOSFET 103V. The MOSFET 103V has a plated layer 96 (a metal layer) on the source electrode junction 91 and the gate electrode junction 92. The plated layer 96 is particularly desirable in cases where the source electrode junction 91 and the gate electrode junction 92 are made of A1 or an Al alloy.

[0081] A similar plated layer can be arranged on the electrode layer 93. The plated layer 96 is in contact with an inner edge of the polyimide layer 20. The plated layer 96 is preferably an electroless plated layer and, for example, an electroless plated nickel-phosphorus layer.

[0082] In a case where electroless plating is used, it is easy to form the plated layer 96, after the formation of the polyimide layer 20 with the opening OP, simply within the opening OP of the polyimide layer 20. The plated layer 96 can be located anywhere within the opening OP in a top view. The plated layer 96 preferably only partially fills a gap formed by the opening OP of the polyimide layer 20 along its thickness.

[0083] A similar clad layer (a metal layer) can be arranged on the rear electrode 10. Such a clad layer is desirable in a case where the rear electrode 10 consists of A1 or an Al alloy. Design 4

[0084] Fig. Figure 20 is a sectional view schematically representing a configuration of a MOSFET 104 according to embodiment 4. While the gate electrode 6 of the MOSFET 101 ( Fig. 4: In embodiment 1) which has a planar structure, the gate electrode 6 in the present embodiment has a trench structure. This is described in more detail below.

[0085] In MOSFET 104, the upper surface S2 of the SiC substrate 50 has a groove TR. The groove TR penetrates the source region 4 and the base region 2 and extends into the drift layer 1. The gate electrode 6 is positioned within the groove TR by the dielectric gate layer 5. This creates the groove structure. As with the planar structure mentioned above, the groove structure is suitable for a power semiconductor device, which is a semiconductor device capable of handling high currents. In particular, in a case where high currents are handled, as described above, a dielectric protection layer, such as the polyimide layer 20, is required.

[0086] The configuration, with the exception of the configuration mentioned above, is essentially the same as the configuration mentioned above according to any of embodiments 1 to 3, so that the same or corresponding components bear the same reference numeral and their description is not repeated. According to the present embodiment, effects similar to those achieved according to embodiments 1 to 3 described above can be achieved. Design 5

[0087] Fig. Figure 21 is a block diagram that schematically represents a configuration of a power converter system in which a power converter 700 according to embodiment 5 is used.

[0088] In embodiment 5, the aforementioned semiconductor unit according to any one of embodiments 1 to 4 or according to modifications thereof is used in a power converter. The present invention is not limited to any particular power converter; however, embodiment 5, as described below, is a case in which the present invention is used in a three-phase inverter.

[0089] Fig. Figure 21 is a block diagram that schematically represents the configuration of the power converter system in which the power converter 700 is used according to embodiment 6 of the present invention.

[0090] The power converter 700 is a three-phase inverter connected between a power supply 600 and a load 800. It converts direct current supplied by the power supply 600 into alternating current and supplies the alternating current to the load 800. The power converter 700 comprises a main converter circuit 701, a driver circuit 702, and a control circuit 703.

[0091] The main converter circuit 701 comprises at least one of the semiconductor units (e.g., one of the MOSFETs 101 to 104) according to embodiments 1 to 4 and their modifications as a switching element and converts the input direct current into an alternating current and outputs it. To drive each semiconductor unit as a switching element, the driver circuit 702 outputs a driver signal to the semiconductor unit. The control circuit 703 outputs a control signal to the driver circuit 702 to control the driver circuit 702.

[0092] The 600 power supply is a DC power supply that provides a DC current to the 700 power converter. The 600 power supply can be configured in various ways, for example, using a DC system, a solar cell, or a storage battery. It can also be configured with a rectifier circuit or an AC / DC converter connected to an AC system. The 600 power supply can be configured with a DC / DC converter that converts the DC current supplied by a DC system into a specified DC current.

[0093] The Last 800 is a three-phase motor driven by alternating current supplied by the Power Converter 700. The Last 800 is not limited to a single application and is a motor that can be mounted on various types of electrical equipment, such as hybrid vehicles, electric vehicles, rail vehicles, elevators, or air conditioning systems.

[0094] The power converter 700 is described in detail below. The main converter circuit 701 includes the switching element and a freewheeling diode (not shown). When the switching element is activated, the main converter circuit 701 converts the direct current supplied by the power supply 600 into alternating current and supplies the alternating current to the load 800.

[0095] The main converter circuit 701 can have various special circuit configurations, and the main converter circuit 701 according to the present embodiment is a two-stage three-phase full bridge circuit, and it can be configured by six switching elements and six freewheeling diodes connected antiparallel to the respective switching elements.

[0096] Two of the six switching elements are connected in series to form upper and lower branches, and the upper and lower branches form the respective phases (a U-phase, a V-phase, and a W-phase) of the full bridge circuit. The output terminals of the respective upper and lower arms, that is, three output terminals of the main converter circuit 701, are connected to the load 800.

[0097] The driver circuit 702 generates a driver signal to drive each of the switching elements of the main converter circuit 701 and supplies the driver signal to a control electrode of the switching element of the main converter circuit 701. In particular, the driver circuit 702 outputs, according to the control signal from the control circuit 703, which is described below, a driver signal to switch the switching element to an ON state and a driver signal to switch the switching element to an OFF state to the control electrode of each of the switching elements.

[0098] The driver signal is a voltage signal (an ON signal) which, in a case where the switching element is held in the ON state, is equal to or higher than the threshold voltage of the switching element, and in a case where the switching element is held in the OFF state, is a voltage signal (an OFF signal) which is equal to or lower than the threshold voltage of the switching element.

[0099] The control circuit 703 controls the switching element of the main converter circuit 701 such that a desired power is supplied to the load 800. In particular, the control circuit 703 calculates, based on the power to be supplied to the load 800, a duration (an ON duration) during which the switching elements of the main converter circuit 701 should be in the ON state. The main converter circuit 701 can be controlled, for example, by pulse width modulation (PWM) control, which modulates the ON duration of the switching element according to a voltage to be output.

[0100] The control circuit 703 outputs a control command (a control signal) to the driver circuit 702 at specific times, such that the ON signal is output to a switching element that is to be in the ON state, and the OFF signal is output to a switching element that is to be in the OFF state. The driver circuit 702 outputs the ON signal or the OFF signal, according to the control signal, as the driver signal to the control electrode of each of the switching elements.

[0101] According to embodiment 5, the main converter circuit 701 comprises, as a switching element, at least one of the semiconductor units (e.g., one of the MOSFETs 101 to 104) according to embodiments 1 to 4 and their modifications. These semiconductor units prevent the progression of local deterioration of the polyimide layer 20, as described above.

[0102] This prevents deterioration of the polyimide layer 20 due to thermal cycling caused by the operation of the power converter 700. Thus, the reliability of the power converter 700, which performs the operation associated with thermal cycling, can be improved.

[0103] According to embodiment 5, a case is described in which the present invention is used with a two-stage three-phase inverter; however, the present invention is not limited to being applied to the two-stage three-phase inverter and can be used with various power converters. Although the power converter according to embodiment 5 is a two-stage power converter, the power converter can also be a multi-stage power converter, such as a three-stage power converter.

[0104] The present invention can also be used with a single-phase inverter in cases where power is supplied to a single-phase load. The present invention can also be used with a DC / DC converter or an AC / DC converter in cases where power is supplied to a DC load or the like.

[0105] The power converter to which the present invention is applied is not limited to the one in the aforementioned case where the load is a motor, and it can, for example, be used as a power supply device for an electric discharge machine, a laser processing machine, an induction cooktop and a contactless power supply system, and can furthermore be used as a power conditioner of a photovoltaic system, a storage system or the like.

[0106] While each of the aforementioned embodiments describes in detail a case in which the semiconductor unit is a MOSFET, the semiconductor unit can also be a metal-insulator-semiconductor field-effect transistor (MISFET), which is not a MOSFET. The semiconductor unit can be a transistor other than a MISFET, and it can, for example, be an insulated-gate bipolar transistor (IGBT).

[0107] To obtain an IGBT, it is only necessary to add a collector region with the second conductivity type between the aforementioned back electrode 10 and the drift layer 1 with the first conductivity type. In this case, the aforementioned source acts as an emitter of the IGBT, and the back electrode 10 acts as a collector electrode.

[0108] Although each of the embodiments mentioned above describes in detail a case in which the semiconductor substrate consists of SiC, the semiconductor substrate can also consist of a semiconductor other than SiC that has a higher coefficient of linear expansion than Si. For example, a semiconductor substrate consisting of gallium arsenide (GaAs) or gallium nitride (GaN) can be used.

[0109] Although each of the aforementioned embodiments describes a case in which the first conductivity type is the n-type and the second conductivity type is the p-type, the first conductivity type can also be of the p-type and the second conductivity type of the n-type. EXPLANATION OF REFERENCE MARKS S1 lower surface S2 upper surface (main surface), RA peripheral area RB inner area Surgical opening OP1 first opening OP2 second opening TR Trench RBa first area RBb second area 1 Drift layer 2 Basic Area 3 Contact area 4 Source area 5 dielectric gate layer 6 Gate electrode 7, 42 dielectric intermediate layer 8 Source contact electrode 10 rear electrode 11 Silicon oxide layer 20 Polyimide layer (dielectric protective layer) 21 first inner area 22, 22a, 22b second inner area 29 peripheral area 41 Oxide layer 50 SiC substrate (semiconductor substrate) 60 Temperature sensor element (electrical element) 61 Anode area 62 Cathode area 81, 82 Barrier layer 91 Source-electrode contact point (first electrode layer) 92 Gate electrode contact point (second electrode layer) 93 Electrode layer (third electrode layer) 93a Anode electrode layer 93c Cathode electrode layer 94 Electrode layer 101 to 104 MOSFET (semiconductor unit) 600 Power supply 700 power converters 701 Main converter circuit 702 Driver Circuit 703 Control circuit 800 Last

Claims

[1] Semiconductor unit (103) comprising the following: - a semiconductor substrate (50) consisting of a semiconductor having a higher linear expansion coefficient than silicon, wherein the semiconductor substrate comprises: a source region (4) having a first conductivity type, a base region (2) having a second conductivity type different from the first conductivity type, and a drift layer (1) separated from the source region (4) by the base region (2) and having the first conductivity type, wherein the semiconductor substrate has a main surface (S2) having a region formed from the source region (4); - a dielectric gate layer (5) covering the base region (2) of the semiconductor substrate (50); - a gate electrode (6) which is opposite the base region (2) of the semiconductor substrate (50) by the dielectric gate layer (5); - a first electrode layer (91) which is electrically connected to the source region (4) of the semiconductor substrate (50) and is arranged above the main surface (S2) of the semiconductor substrate (50); - a second electrode layer (92) which is electrically connected to the gate electrode (6) and is arranged above the main surface (S2) of the semiconductor substrate (50) at a distance from the first electrode layer (91); - a third electrode layer (93) arranged above the main surface (S2) of the semiconductor substrate (50) at a distance from the first electrode layer (91); and - a dielectric protective layer (20) arranged over the main surface (S2) of the semiconductor substrate (50), wherein the main surface is provided with the first electrode layer (91), the second electrode layer (92) and the third electrode layer (93), wherein the dielectric protective layer covers only a region of each of the first electrode layer (91) and the second electrode layer (92) and covers at least a region of the third electrode layer (93), wherein the dielectric protective layer (20) consists of a thermosetting resin, - wherein the main surface (S2) of the semiconductor substrate (50) has a peripheral substrate region (RA) and an inner substrate region (RB) enclosed by the peripheral substrate region (RA), and the dielectric protective layer (20) has a peripheral protective layer region (29) covering the peripheral substrate region (RA), and has a first inner protective layer region (21) covering at least a region of the third electrode layer (93) and intersecting the inner substrate region (RB), and - wherein the semiconductor unit further comprises at least one electrical element (60) which is connected to the third electrode layer (93) and is covered by the first inner protective layer region (21) of the dielectric protective layer (20), - wherein the dielectric protective layer (20) has an opening (OP) such that the dielectric protective layer (20) comprises less than half of the main surface area (S2) of the semiconductor substrate (50), - wherein the opening (OP) in a top view has a rim with a first corner region on the side of a corner of the main surface (S2) and the first corner region is curved, - wherein the edge of the opening (OP) in the top view has a second corner region formed from the peripheral protective layer region (29) and the first inner protective layer region (21) of the dielectric protective layer (20), and the first corner region is less curved than the second corner region, and wherein the at least one electrical element (60) is completely covered in the top view by the first inner protective layer region (21) of the dielectric protective layer (20), and is located in the inner substrate region (RB) closer to a center than to an edge of the semiconductor unit (103). [2] Semiconductor unit (103) according to claim 1, wherein a region of the dielectric protective layer (20) covering the at least one electrical element (60) has a thickness of 1 µm or more and of 20 µm or less. [3] Semiconductor unit (103) according to claim 1 or 2, wherein the third electrode layer (93) comprises: - a contact point area for an electrical connection with an exterior area of ​​the semiconductor unit (103); and - a wiring area with a first end connected to the contact point area and a second end connected to the at least one electrical element (60). [4] Semiconductor unit (103) according to claim 3, wherein the second end of the wiring area is an end of the third electrode layer (93) and is arranged away from the peripheral substrate area (RA) of the main surface (S2). [5] Semiconductor unit (103) according to claim 3 or 4, wherein the third electrode layer (93) does not cross the inner substrate region (RB) of the main surface (S2). [6] Semiconductor unit (103) according to one of claims 3 to 5, wherein the contact area is at least partially contained in the peripheral substrate area (RA) of the main surface (S2). [7] Semiconductor unit (103) according to any one of claims 3 to 6, wherein the at least one electrical element (60) comprises a temperature sensor element. [8] Semiconductor unit (103) according to any one of claims 1 to 7, wherein the at least one electrical element (60) has an electrical element (60) that is arranged in the center of the main surface (S2). [9] Semiconductor unit (102) according to any one of claims 1 to 8, wherein the dielectric protective layer (20) has a second inner region (22) that intersects between the peripheral protective layer region (29) and the first inner protective layer region (21). [10] Semiconductor unit (103) according to any one of claims 1 to 9, wherein the third electrode layer (93) is arranged remotely from the second electrode layer (92). [11] Semiconductor unit (103) according to any one of claims 1 to 10, wherein the at least one electrical element (60) comprises at least one of a diode element, a bipolar transistor element, a resistor element and a capacitive element. [12] Semiconductor unit (103) according to any one of claims 1 to 11, wherein the gate electrode (6) has a planar structure. [13] Semiconductor unit (103) according to any one of claims 1 to 11, wherein the gate electrode (6) has a trench structure. [14] Semiconductor unit (103) according to any one of claims 1 to 13, wherein the first inner protective layer region (21) of the dielectric protective layer (20) has a tapered cross-sectional shape. [15] Semiconductor unit (103) according to any one of claims 1 to 14, wherein the dielectric protective layer (20) consists of at least one of a polyimide resin, a silicone resin, an epoxy resin and a polyurethane resin. [16] Power converter (700) which has the following features: - a main converter circuit (701) to convert and output an input power, wherein the main converter circuit comprises a semiconductor unit (103) according to any one of claims 1 to 15; - a driver circuit (702) to output a driver signal to drive the semiconductor unit (103) to the semiconductor unit (103); and - a control circuit (703) to output a control signal to the driver circuit (702) for controlling the driver circuit (702).

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