METHOD FOR VERIFYING THE ERASE PHASE OF A STORAGE DEVICE

Abstract

A non-volatile storage device (100), comprising: - at least one array (90) of memory cells with associated decoding and reading circuitry, wherein the array (90) comprises memory cells: - a large number of memory blocks; - at least one dummy line (300) corresponding to a corresponding memory block (160) of the plurality of memory blocks, wherein each dummy line of the at least one dummy line (300): - is assigned to a first address space which is located outside a second address space of the corresponding memory block (160); and - is configured to store internal block variables of a deletion phase and a known pattern; and - a controller (101) which is connected to the array (90) of memory cells, and is configured for each dummy row of at least one dummy row (300): - during each power-up phase of at least one array (90) of memory cells to determine whether a known pattern is stored in the corresponding dummy row, wherein a determination that the known pattern is not stored in the corresponding dummy row indicates an incomplete erasure of the corresponding memory block; and - to delete the corresponding memory block each time it is determined that the known pattern is not stored in the corresponding dummy line.

Description

TECHNICAL AREA

[0001] The present disclosure relates generally to storage devices and in particular to methods for setting operating parameters of an integrated storage circuit.

[0002] In particular, the present disclosure relates to a method for self-trimming the operating parameters of a storage device and for checking the erasure phase of the storage device. STATE OF THE ART

[0003] Storage devices are well-known in the field of electronics for storing and accessing digital information. Generally, various types of semiconductor storage devices can be incorporated into more complex systems that include either non-volatile or volatile memory components, such as in so-called system-on-chips (SoCs), where the aforementioned memory components are embedded.

[0004] However, nowadays the need for real-time operating systems for automotive applications requires SoCs with ever greater performance and efficiency, and the known solutions no longer meet these requirements.

[0005] Non-volatile memory can provide persistent data by retaining stored data when it is not powered on, and can include, among other types, NAND flash memory or NOR flash memory. NAND flash has shorter erase and write times and requires less chip area per cell, enabling higher storage density and lower cost per bit than NOR flash.

[0006] A key feature of flash memory is its ability to erase blocks of data rather than bytes at a time. However, a significant drawback of flash memory is its limited capacity for a relatively small number of write and erase cycles within a given block.

[0007] Flash storage devices can comprise large arrays of memory cells for storing data, often organized in rows and columns. Individual memory cells and / or ranges of memory cells can be addressed by their row and column. When addressing a memory array, there may be one or more layers of address translation to translate, for example, between a logical address used by a host device (i.e., the SoC) and a physical address corresponding to a position in the memory array.

[0008] US 2016 / 0322108A1 discloses a non-volatile storage system with NAND architecture in which one or more word lines at the ends of a memory block are designated as dummy word lines that are not used for storing user data. These dummy word lines serve to store metadata about the block's state, trim parameters, error statistics, and other status information. Based on this metadata, the memory controller can adjust read parameters or perform block reshuffles.

[0009] US Patent 2016 / 0342494A1 discloses a storage system with non-volatile memory in which each memory block can be monitored with regard to its state and behavior. For this purpose, one or more dummy word lines are used within each block, which are not accessible for normal data storage. These dummy word lines are programmed with a known data pattern that can be read and analyzed to detect potential errors and represent the health of the memory block. Based on this analysis, the operating parameters, such as read voltages, can be adjusted to optimize the performance of each memory block.

[0010] US Patent 2018 / 0293029A1 discloses a storage system comprising non-volatile memory and a controller that responds to temperature differences between data writing and reading. The controller can measure the threshold values ​​(Vt) of memory cells under varying parameters and determine correction values ​​to adjust the read threshold accordingly. Additionally, data written at unusual write temperatures is marked as requiring a refresh or stored with increased reliability. In this way, read parameters are adjusted based on temperature to enhance data integrity and storage reliability.

[0011] Although unusual, it is possible that the address information provided to a storage device on a command / address bus may be corrupted by an error, so that an internal operation of the storage device (e.g., a read operation, a write operation, an erase operation, etc.) may be performed at a different physical address than the one used as the target by a host device or a controller of the storage device.

[0012] Accordingly, a way to verify that a storage operation was performed at the intended address is required, and the present disclosure focuses on methods for verifying the correctness of the deletion phase. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 shows a schematic view of a system with a storage component associated with a controller that exchanges data, address and control signals with the storage device; Fig. Figure 2 is a schematic view of the storage component according to the present disclosure; Fig. Figure 3 is a schematic view of the storage component according to the present disclosure; Fig. Figure 4 is a schematic view of a memory block formed by a plurality of rows of a memory array according to an embodiment of the present disclosure; Fig. Figure 5 is a schematic view of a group of address registers for a memory page in the memory section of the present disclosure; Fig. Figure 6 shows in a schematic diagram the distribution of a good deleted / programmed cell (1 bit / cell); Fig. Figure 7 shows a diagram accordingly Fig. 6, which shows an enlarged distribution shifted towards the depletion state (negative Vth) due to aging, temperature and stress; Fig. Figure 8 shows an example of the procedural steps of the present disclosure in a block diagram. DETAILED DESCRIPTION

[0013] The preceding detailed description refers to the accompanying drawings, which form part of this document and contain specific examples for illustration. In the drawings, the same reference numerals in the different views describe essentially similar components. Other embodiments may also be disclosed, and structural, logical, and electrical modifications may be made without departing from the scope of this disclosure. The following detailed description should therefore not be interpreted as limiting.

[0014] Several embodiments of the present disclosure relate to memory devices, systems with memory devices and methods for operating memory devices that avoid the potential problems of aging, temperature and process drift during memory operation.

[0015] In one embodiment of the present disclosure, a new storage architecture is provided for improved security and performance of the data erasure phase in the non-volatile storage device.

[0016] More precisely, the present disclosure relates to a non-volatile storage device comprising at least one array of memory cells with associated decoding and reading circuitry and a memory controller, wherein the memory array comprises: - a large number of memory blocks; - at least one dummy line for each block outside the address space of - each block for storing at least internal block variables of the deletion phase and at least one known pattern.

[0017] The internal block variables mentioned above are parameters that are also used during the erasure phase of the memory block.

[0018] More precisely, the internal block variables are parameters such as the erase pulses and / or the target voltages that are applied to the memory block during the erase phase.

[0019] Furthermore, the internal block variables of a previous erase phase are retrieved from the dummy line before the erase algorithm is started on the memory block.

[0020] For a better understanding of the present disclosure, it should be noted that flash memory has become a popular source of non-volatile memory for a wide range of electronic applications.

[0021] Flash memory typically uses a single-transistor memory cell, enabling high storage densities, high reliability, and low power consumption. Changes in the cell's threshold voltage, achieved through programming a charge storage structure such as floating gates or trap layers, or other physical phenomena, determine the data state of each cell. Single-level cells (SLC) use a single binary digit (e.g., a logical 0 or a logical 1); multi-level cells (MLC) store more bits in the same physical cell. For example, triple-level cells (TLC) store 3 bits of information using 8 threshold voltage levels.

[0022] When addressing a memory array, there can be one or more levels of address translation, such as a translation between a logical address used by a host device and a physical address corresponding to a memory location within the array. Such a mechanism is very useful for implementing advanced features like block wear leveling and / or factory / on-field block redundancy.

[0023] Although unusual, incomplete deletions can occur during a deletion operation. In such a scenario, it is crucial to have a mechanism for detecting blocks that have not been properly or completely deleted. Since a poorly deleted block cannot be read or programmed, it is essential to avoid any unexplained errors during the read or program phase of a block where an incomplete deletion has occurred.

[0024] In some embodiments, during each power-on and / or reset phase and / or at the user's request, all blocks in the array are verified to determine if any of them are in an incompletely erased state. This can be done by verifying the presence of the pattern in the aforementioned dummy array.

[0025] In case of incomplete deletion detection: - A warning message is sent to the host device; and / or - Deleting such a block is performed to restore the block. This can happen automatically or on command from the host.

[0026] For example, a warning and / or recovery is triggered by detecting that one of the blocks did not complete the deletion process correctly.

[0027] Furthermore, temperature fluctuations within a device can lead to measurement drifts, which are referred to as the ghost temperature problem.

[0028] The disadvantage associated with such temperature fluctuations affects the actual bit distribution, which is detected by the read amplifiers as shifted relative to the ideal center value for which they were programmed. Under certain circumstances, such drifted and / or enlarged threshold voltage distributions during reading can cause the same problems as an incomplete erase operation, as described below.

[0029] To give just one practical example: If the programming phase was performed at -40°C, the read results may contain many errors at 120°C. This is a real problem for all chips installed in automotive devices, where temperature increases during vehicle operation must be taken into account.

[0030] Therefore, the read phase of the storage device is never performed under environmental conditions similar to the original programming phase; this also applies to the erase phase.

[0031] A storage device can be defined as a kind of "real-time" device in the sense that it must release reliable data in all environmental operating conditions, regardless of whether it has been tested in the factory that reports approval based on positive test results.

[0032] Furthermore, temperature-related drift is further increased by the age of the device, and this problem could be particularly critical for storage devices integrated into system-on-chip autonomous vehicles.

[0033] Fig. Figure 1 illustrates a schematic example of a system 10 that includes a flash memory device or component 100. The system also includes a memory controller 101 that is coupled to the memory device 100.

[0034] The controller 101 is shown coupled to the storage device 100 via a data bus 105, a control bus 106, and an address bus 107. In one embodiment, the data bus could be a 64-bit and / or 128-bit wide double data rate (DDR) bus.

[0035] The in Fig. The system device 10 shown in Figure 1 can be a host device or a system-on-chip coupled with the memory component 100, as will be apparent from the description of other embodiments of the present disclosure, which is made with reference to other figures. In each case, the system-on-chip 10 and the memory component 100 are implemented on a corresponding chip, which is manufactured by different lithography and fabrication processes.

[0036] Fig. Figure 2 is a schematic view of the memory component according to the present disclosure; the memory component 100 is an independent structure, but it is strictly associated with the host device or the SoC structure. In particular, the memory device 100 is connected to and linked with the SoC structure, partially overlapping such a structure, while the corresponding semiconductor area of ​​the SoC structure has been used for other logic circuits, and the partially overlapping, structurally independent memory device 100 is connected, for example, by a plurality of pillars or similar alternative connections such as bumping balls or with a flip-chip-like technology.

[0037] More precisely, this non-volatile memory component 100 comprises an array 90 of flash memory cells and circuitry arranged around the memory array. The coupling between the SoC structure 10 and the memory component 100 is achieved by connecting a multitude of corresponding pads or pin connectors facing each other in a circuit layout that maintains the orientation of the pads even if the size of the memory component is changed.

[0038] In one embodiment of the present disclosure, the pads of the memory component are arranged on a surface of the memory component 100, in practice on the top of the array. More precisely, the pads are arranged above the array so that, when the memory component 100 is inverted, its pads face the corresponding pads of the host of the SoC structure 10. Signals from data (105), command (106), and address (107) buses are transmitted through the pads described above; the pads can also be used for supply voltages as well as other signals and / or voltages.

[0039] Ultimately, the storage device 100 will be manufactured according to the user's needs, with a capacity ranging from at least 128 Mbit to 512 Mbit or even more. More precisely, the proposed external architecture allows for exceeding the limitations of current eFlash technology (i.e., embedded flash technology), enabling the integration of larger storage capacities, which, depending on the storage technology and technology nodes, can reach 512 Mbit and / or 1 Gbit and / or even more.

[0040] Now, with more specific reference to the example of Fig. 2 the main structure of the memory component 100 according to an embodiment of the present disclosure.

[0041] The memory component 100 contains at least: an I / O circuit 5, a microsequencer 3, an array of memory cells 90, voltage and current reference generators 7, charge pumps 2 and decoding circuits 8 located at the periphery of the array or under the array, read amplifiers 9 and corresponding latches, a command user interface, for example a CUI block 4.

[0042] The array of memory cells 90 contains non-volatile flash memory cells. The cells can be erased in blocks instead of bytes at a time. Each erasable memory block comprises a multitude of non-volatile memory cells arranged in a matrix of rows and columns. Each cell is coupled to an access line and / or a data line. The cells are programmed and erased by manipulating the voltages and timing on the access and data lines.

[0043] A special logic circuit section is provided for writing and erasing the memory cells of the array 90, which contains a simplified RISC controller (Reduced Instruction Set Computer) or a Modify Finite State Machine, i.e. the logic circuit for handling the programming and erasing algorithms.

[0044] To read the array's memory cells, a dedicated circuit section 90 is provided, containing an optimized read finite-state machine. This machine ensures high read performance, including features such as branch prediction, fetch / pre-fetch, interrupt management, and so on. Error correction is handled by the SoC 10; the additional bits are allocated to the controller 101 to store any possible ECC syndrome associated with the page. The ECC cells allow the host controller to understand whether data corruption, including address content, has occurred.

[0045] Errors affecting address information provided to the storage device on a command or address bus can cause a memory operation to be performed at a memory address other than the intended address.

[0046] In this respect, the controller is configured to receive a data word to be stored at an address in the array of memory cells. The controller is further configured to instruct the array to read the data word from the address, receive response data from the array, and verify that the location of the response data corresponds to the desired address.

[0047] If the location data does not match the address, the controller is configured to display an error. This error is detected in the metadata, including ECC information.

[0048] ECC information is stored alongside the data for which it provides error correction capabilities.

[0049] Upon closer examination of the internal structure of the storage component 100, it can be seen that the architecture of the array 90 is structured as a collection of subarrays 120, as shown in Fig. 3 shown schematically.

[0050] The read amplifiers SA at the output of each subarray 120 are directly connected to modified JTAG cells 140 to integrate a JTAG structure and the read amplifiers into a single circuit component. This makes it possible to minimize the delay in passing the output of the memory array to the SoC.

[0051] Each subarray 120 contains several memory blocks 160, which will later be referred to as Fig. 4 will be revealed.

[0052] In this way, with smaller sectors compared to known solutions, the access time is significantly reduced and the overall throughput of the memory component is improved.

[0053] Each subarray 120 within the storage device 100 is independently addressable. Furthermore, the storage array 90 is structured, for example, with at least four storage subarrays 120, one for each communication channel with a corresponding core of the host device or SoC 10. A different number of cores and / or subarrays can be used. The host device or system-on-chip 10 typically includes more than one core, and each core is connected to a corresponding bus or channel for receiving and transmitting data to the storage component 100.

[0054] Therefore, in the present implementation, each subarray 120 has access to a corresponding channel to communicate with a corresponding core of the system-on-chip 10.

[0055] It should also be noted that each subarray comprises 120 address registers connected to data buffer registers, similar to an architecture used in a DRAM storage device.

[0056] Furthermore, according to one embodiment of the present disclosure, each block 160 of the storage subarray 120 is assigned at least one dummy row 300.

[0057] This dummy line 300 is located outside the address space of the memory array 90 and is used to optimize the read, write and erase parameters.

[0058] Furthermore, this dummy series is used to monitor extinguishing robustness in order to successfully complete modification operations and other purposes.

[0059] According to another embodiment, the dummy row of a block 160 is provided in another block of the memory subarray 120; this can make it possible to keep a single dummy row updated for a multitude of memory blocks that may be subject to the same environmental conditions.

[0060] An expert will recognize that such a dummy line can also reside in a dedicated section of the memory array (e.g., not in one of the subarrays coupled to the SoC). If the content of this "external" line becomes invalid, it must be updated, i.e., rewritten, which means it must be erased. However, such an operation means that the entire block containing such an "external" line in a NAND flash memory must be erased.

[0061] The dummy line 300 may contain information useful for tracking parameters that can be used during the read and erase phases of the memory component 100, and / or for storing some parameters to detect a possible incomplete erase.

[0062] The dummy line 300 contains a pattern known to the controller 101 of the storage device 100.

[0063] Let's assume we record a known pattern value like 0x55 or 0xAA in hexadecimal form in dummy line 300. This value is particularly suitable because it contains the same number of logical values ​​of "0" and logical values ​​of "1", which are stored within the array in two different flash memory cells with two different thresholds.

[0064] In another embodiment, the above well-known pattern is not limited to a value in hexadecimal form such as 0x55 or 0xAA, but also includes an update of the erase parameters such as: amplitude / number of pulses in steps and / or erase / depletion verification levels.

[0065] Since these values ​​are also known a priori to the memory controller, the system performs several read cycles in each case, modifying the read trim parameters until the value is read correctly. The modified trim parameter of the correct measurement corresponds to a set temperature value recorded in the programmable register. In the case of a multi-level cell memory (N levels), the values ​​to be stored can be chosen to cover all N levels present in the memory matrix. For example, the known pattern can include cells programmed in all available levels of the multi-level cell memory device.

[0066] Only if the trim parameters set for the read phase perfectly allow the correct known value to be retrieved, can the read phase of the other memory blocks of subarray 120 be carried out.

[0067] In one embodiment of the present disclosure, the output of a generic subarray 120 is formed by an extended page that combines data cells, address cells, and ECC cells. In this example, the total number of bits would comprise 168 pads per channel, as shown in Fig. 5 shown.

[0068] The combined string of data cells + address cells + ECC cells enables the implementation of the entire bus security coverage according to the standard requirements of the ISO26262 regulation, since the ECC covers all bus communication (data cells + address cells), while the presence of the address cells ensures that the data comes exactly from the addressed point of the responsible party.

[0069] Furthermore, each memory subarray 120 is structured within a memory block 160. The architecture of a memory block encompassing every location of the memory array can be defined as an extended page 150. An extended page comprises 128-bit I / O required for the SoC and a 16-bit ECC with 24-bit addressing (up to 2 GB of available memory).

[0070] A schematic view of the output of the SA read amplifiers through the modified JTAG cells 140 is shown in Fig. 5 shown, where the composition of an extended page 150 with 168 bits can be recognized as a non-restrictive example.

[0071] In other words, the atomic 128-bit page used in each subarray 120 to fill the communication channel with the SoC device 10 has been enlarged in the present implementation to contain the stored address and the ECC, forming an extended 168-bit page. Two extended 150-bit pages form a "super page".

[0072] Each memory block 160 contains 256 lines, and each line 135 contains sixteen extended pages of the above size. Each superpage contains a pair of 168 bits as a combination of data, addressing, and ECC bits. Therefore, each line 135 of the memory array 90 can contain up to sixteen double pages of 128 bits each, plus the address and ECC syndrome replacement bits per page.

[0073] To specify only a numerical value, an extended page is formed from 128 + 16 + 24 = 168 bits, and sixteen extended pages per line 135 comprise 168 * 16 = 2688 bits.

[0074] Therefore, each line of a memory block contains at least sixteen pages, comprising a memory word plus the corresponding address bits and ECC bits. Obviously, a different size can be chosen, and the reported value serves only to illustrate a non-restrictive example. The resulting blocks are passed directly to the host device or SoC 10 without using high-performance buffers or optimizing the path.

[0075] The idea underlying the present disclosure is based on the consideration that the temperature and aging drift affecting the storage array 90 can be detected by the storage component 100 itself using a stored reference.

[0076] By using the drift information of the stored known pattern, it is possible to set the optimal parameters to be used in the next erasure process. Such information can be used to correctly trim all voltage values ​​and timing (i.e., the waveform) to be used in each stage of the erasure algorithm.

[0077] In general, the correct voltage level and timing in each erase phase must conform to technological guidelines. These guidelines are provided by flash cell technologists as a chart that maps the aging stage to the corresponding voltage / time values ​​to be used. Based on these guidelines, several well-known or predefined parameters can be defined a priori for the given technology. These parameters can be further adjusted during electrical testing of the chip to account for process variations, for example.

[0078] In a further embodiment of the present disclosure, even the parameters or the known patterns, adapted or not, can be stored in the dummy series 300, and in some embodiments updated during electrical wafer sorting or electrical testing and / or during the operational lifetime in the field, for example after the erasure process has been correctly completed.

[0079] Let's now look at the deletion process using this method:

[0080] The well-known patterns are read from the dummy series 300 and processed by the internal control system to determine the best parameters to use in the next steps. Then the deletion algorithm can start.

[0081] If the parameters in dummy line 300 are missing, this means that an incomplete delete has occurred. This event must be rectified by deleting the entire block. Otherwise, the block cannot be programmed or read correctly. The absence of parameters in the dummy line can be confirmed by a mismatch between a pattern (which is usually also present in dummy line 300, as explained in more detail below) and an expected known pattern.

[0082] Under normal operating conditions, a pre-programming phase, also known as program a110, is generally provided for erasing this type of storage device.

[0083] Normally, before the deletion phase begins, the threshold values ​​of the cells to be deleted are moved towards the programmed state. This is done by issuing some blind (i.e., without validation) program pulses.

[0084] In this procedure, the number of pre-program pulses to be output and / or the voltage to be used is selected according to the previous reading step of the dummy series.

[0085] During an erasure pulse phase, voltage and pulse duration can be adjusted so that the cells in the block are erased quickly and safely (corresponding to the previous erasure phase).

[0086] When the block is cyclically processed (many program-erase cycles, estimated using drift information), several suitable high voltages and pulse durations are used. Typically, a block is erased by applying multiple erase pulses at different values ​​(negative for the gate voltage and / or positive for the body source). This sequence is called a staircase.

[0087] Once a delete pulse is issued (as above), the delete cell status is verified by applying a suitable cell gate voltage value, which is used to perform a delete verification with sufficient margin to guarantee a properly deleted cell distribution.

[0088] In other words, the first step (#1) is based on extinguishing pulses in the staircase, while the second step (#2) is based on extinguishing verification. The drift information can be used to select the correct extinguishing test values.

[0089] Fig. Figure 6, for example, shows in a schematic diagram the distribution of a correctly erased / programmed (1 bit / cell) cell. The entire cell threshold population is correctly restricted to the assigned limit (i.e., programmed '0' or erased '1'). Steps #1 and #2 (erasure pulse and erasure verification) are repeated until all cells meet the erasure verification criteria.

[0090] Once all cells have been correctly verified (deleted), the system also checks for cells with a threshold that is too low. Fig. 6 shows this through the Label Depletion Verification (DV).

[0091] In the event of cell exhaustion, a soft program operation is executed for the cells that require it. The parameters used to perform a soft drift of the cells, in order to correctly position the thresholds within the deletion cell distribution, can be chosen according to the age of the cells.

[0092] An incorrect selection of such a parameter can cause the threshold of cells to be placed outside the deleted distribution (above the deletion check value), and this would mean that the block would have to be deleted again, starting from step #1 above of providing the deletion pulses (this would be time-consuming).

[0093] Once the erasure process is complete (the above phases are finished), the known pattern or even the erasure parameters (i.e., amplitude / number of pulses in steps and / or erasure / depletion verification levels, etc.) are written to line 300 to be used in the next erasure cycle. Specifically, the pattern selected by storing the set values ​​(0x55, 0xAA, etc.) is programmed and verified accordingly (see the PV phase of...). Fig. 6) using a suitable programming pulse, the voltage and timing of which depends on the current aging level of the block.

[0094] By using the drift information and the number of erase pulses provided in the erase phase (step #1 above), it is possible to infer that a block is nearing the end of its life.

[0095] This information could be used as a warning to the customer or as a flag for an internal algorithm to trigger potential block wear leveling or on-field block redundancy (OFBR) operation, if implemented. OFBR involves replacing the affected block with a spare block.

[0096] Fig. Figure 7 shows a diagram accordingly Fig. Figure 6, however, shows an increased distribution due to aging, temperature, and / or stress. With aging, temperature, and / or stress, the threshold voltage distributions tend to increase. According to the methodology of this disclosure, it is possible to use this increase in distribution to track cell degradation and to use this information to correct subsequent quenching pulses. This makes it possible to improve the reliability and performance of the quenching phase.

[0097] The trim sequence for performing a read phase of the memory array at different temperatures or different aging of the memory devices can be recorded in a laboratory during the technology development phase and / or product testing and stored in a programmable register of the memory controller 101.

[0098] Similarly, the parameters used during the extinguishing phase can be regulated in the same way during operation in the field.

[0099] The content of a correct reading phase does not depend on the actual temperature at which the reading phase is performed. Such a temperature could be higher (even much higher) or lower compared to the temperature at which the programming phase of the known value was performed.

[0100] The system is automatically protected against any thermal drift, as the read trim parameters are selected after the correct reading of the known sequence stored in the dummy series 300 has been performed and the trim parameter has been set accordingly to correctly read this known value.

[0101] This method allows for the identification of more suitable read trim parameters for a correct read operation at a specific temperature value. It is not necessary to repeat this process for every read operation or access. On the contrary, such a procedure can be performed periodically or in a more appropriate manner when potential problems are detected, for example, an abnormal increase in the number of ECC bits.

[0102] For example, an increased number of ECC bits might indicate an excessive number of erroneous reads from the storage device. In such a case, the system can automatically initiate a procedure to detect potential thermal drift and the resulting need to adjust the trim parameters.

[0103] The dummy line 300 can also be used as a clue to verify a possible error in the deletion process.

[0104] The method of the present disclosure makes it possible to correctly verify the erasure phase of the memory component 1 or better of a memory block 160.

[0105] The method for erasing a non-volatile storage device comprising at least one array of memory cells with associated decoding and reading circuitry and a memory controller comprises at least the following steps: - Performing a deletion operation on a memory block 160; - Storing at least internal block variables of the erase phase and at least one known pattern in a dummy line 300 of memory block 160.

[0106] The above process phases are illustrated in the example of Fig. Figure 8 illustrates that a flowchart 800 shows, as a first phase 810, a dynamic deletion process of at least one memory block 160.

[0107] Then, in a subsequent phase 820, at least the internal block variables of the deletion process are stored in the dummy line 300.

[0108] Finally, in phase 830, at least the known pattern is also stored in the dummy series 300.

[0109] The first step of the deletion algorithm is to invalidate the contents of dummy line 300, which stores the new delete variable, at the end of the deletion phase. To invalidate the contents of dummy line 300, a flag or an invalid pattern can be programmed, or the entire line can be overwritten.

[0110] The content of dummy line 300 includes at least internal block variables, which means the parameters used during the erasure phase of the block, for example: the erasure pulses, the target voltages, etc.

[0111] Furthermore, the content of dummy line 300 also contains at least the known pattern, i.e., the previously mentioned known hexadecimal value. Alternatively, an example of a known pattern is: 0x0, 0x1, 0x2, ... 0xF, or any other sequence comprising a number of bits set to zero and a similar number set to one, such as: 0x55, 0xAA, 0x33, etc. As mentioned previously, in the case of multi-level cells that store more than a single bit in a physical cell, a suitable known pattern should be chosen to ensure the correct capture of all possible threshold voltage levels.

[0112] The method of the present disclosure provides for the execution of the deletion algorithm using the specific parameters. In other words, the internal block variables of a previous deletion phase are retrieved from the dummy line 300 before the deletion algorithm is started for memory block 160.

[0113] The deletion algorithm is completed by storing the deletion-critical parameters and the known pattern.

[0114] Storing the critical parameters can provide feedback on the condition of the block and also determine how wear compensation must be applied to block 160 of subarray 220.

[0115] The presence of the known pattern at the end of the dummy series ensures the correctness of the operation.

[0116] If it is not possible to correctly read the block variables and / or the known pattern when accessing dummy line 300, for example, if the retrieval is unsuccessful (as can happen if an incomplete erase event occurred during a previous erase operation before the erase operation was correctly completed), a block recovery is triggered. The block recovery can include an erase procedure according to predefined (e.g., factory-defined) parameters. Accordingly, a blind pre-programming phase is executed (to ensure all bits are in an A110 state before the actual erase pulse sequence).A step-down algorithm is then applied to the bits of the block of interest with increasing voltage steps, interspersed with erase check steps (using the predefined erase check level). Finally, a check against the predefined depletion check level is performed, possibly followed by a software program of consumed bits. The recovery erase procedure is completed by programming the known pattern for future use in dummy line 300 of the block. The erase parameters can also be stored in dummy line 300.

[0117] The method of the present invention enables the obtaining of a dynamic extinguishing verification of the extinguishing phase, since it is possible to obtain reliable feedback on the correctness of the extinguishing process even under different operating environment conditions.

Claims

[1] A non-volatile storage device (100) comprising: - at least one array (90) of memory cells with associated decoding and reading circuitry, wherein the array (90) comprises memory cells: - a large number of memory blocks; - at least one dummy line (300) corresponding to a corresponding memory block (160) of the plurality of memory blocks, wherein each dummy line of the at least one dummy line (300): - is assigned to a first address space which is located outside a second address space of the corresponding memory block (160); and - is configured to store internal block variables of a deletion phase and a known pattern; and - a controller (101) which is connected to the array (90) of memory cells, and is configured for each dummy row of at least one dummy row (300): - during each power-up phase of at least one array (90) of memory cells to determine whether a known pattern is stored in the corresponding dummy row, wherein a determination that the known pattern is not stored in the corresponding dummy row indicates an incomplete erasure of the corresponding memory block; and - to delete the corresponding memory block each time it is determined that the known pattern is not stored in the corresponding dummy line. [2] Non-volatile storage device (100) according to claim 1, wherein the internal block variables comprise parameters that are usable during the erase phase of the corresponding storage block (160). [3] Non-volatile storage device (100) according to claim 1, wherein the internal block variables comprise erase pulses and / or target voltages which are applied to the corresponding storage block (160) during the erase phase. [4] Non-volatile storage device (100) according to any one of claims 1 to 3, wherein the plurality of storage blocks is contained in at least one subarray (220) of the array (90) of memory cells. [5] Having a system: - a host device; - a non-volatile storage device (100) coupled to the host device and comprising at least one array (90) of memory cells with associated decoding and reading circuitry, - a multitude of memory blocks in the array (90) of memory cells; - at least one dummy line (300) corresponding to a corresponding memory block (160) of the plurality of memory blocks, wherein each dummy line of the at least one dummy line (300): - is assigned to a first address space which is located outside a second address space of the corresponding memory block (160); and - is configured to store internal block variables of a deletion phase and a known pattern; and - a controller (101) which is connected to the array (90) of memory cells, and is configured for each dummy row of at least one dummy row (300): - during each power-up phase of the at least one array (90) of memory cells, to determine whether a known pattern is stored in the corresponding dummy row, wherein a determination that the known pattern is not stored in the corresponding dummy row indicates an incomplete erasure of the corresponding memory block; and - during each determination that the known pattern is not stored in the corresponding dummy row, to erase the corresponding memory block. [6] System according to claim 5, configured to attempt to retrieve previous internal block variables of a previous erase phase from the at least one dummy line (300) for the corresponding memory block (160). [7] System according to claim 6, which is configured to start the erase phase for the corresponding memory block (160) at least partially on the basis of a successful attempt to retrieve the previous internal block variables. [8] System according to claim 6, wherein the at least one dummy row (300) is provided in another block (160) of the plurality of memory blocks or in a dedicated memory section of the array (90) of memory cells. [9] System according to claim 5, wherein the internal block variables comprise parameters that are usable during the erase phase of the corresponding memory block (160). [10] System according to claim 5, wherein the internal block variables comprise erase pulses and target voltages which are applied to the corresponding memory block (160) during the erase phase. [11] System according to claim 5, wherein the plurality of memory blocks is contained in at least one subarray (220) of the array (90) of memory cells. [12] Method for checking a deletion process of a non-volatile storage device (100) comprising at least an array (90) of memory cells and with associated decoding and reading circuitry and a controller (101), wherein the method comprises: - Performing (810) a deletion phase on a memory block (160) in which at least one array (90) of memory cells of the non-volatile storage device (100) - Storing (820, 830) internal block variables of the erase phase and a known pattern in a dummy line (300) of the memory block (160) before switching on the at least one array (90) of memory cells, wherein the dummy line (300) is assigned to a first address space which is outside a second address space of the corresponding memory block (160); - Determine whether the known pattern is stored in the corresponding dummy row (300) after switching on the at least one array (90) of memory cells, wherein a determination that the known pattern is not stored in the corresponding dummy row indicates an incomplete erasure of the corresponding memory block; and - Performing a delete operation on the corresponding memory block if it has been determined that the known pattern is not stored in the corresponding dummy line (300). [13] Method according to claim 12, wherein the execution of the deletion phase comprises performing a dynamic deletion operation on the storage block (160). [14] Method according to claim 12, wherein the method comprises invalidating the content of the dummy line (300) before performing the deletion operation. [15] Method according to claim 12, wherein storing the internal block variables includes storing parameters to be used during the erasure phase of the memory block (160). [16] Method according to claim 12, wherein storing the internal block variables includes storing erase pulses and target voltages that are applied to the storage block (160) during the erase phase. [17] Method according to claim 12, wherein the start of the erase phase on the memory block (160) is based partly on an unsuccessful attempt to retrieve the previous internal block variables. [18] Method according to claim 12, wherein starting the erase phase comprises restoring the memory block (160) at least partially based on an unsuccessful attempt to retrieve the previous internal block variables. [19] Method for erasing a non-volatile storage device (100) comprising at least one array (90) of memory cells and with associated decoding and reading circuitry and a controller, wherein the method comprises: - Performing a dynamic erase operation on a memory block (160) in which at least one array (90) of memory cells of the non-volatile storage device (100) - Storing internal block variables of the dynamic erase operation in a dummy line (300) of the memory block (160) before switching on the at least one array (90) of memory cells, wherein the dummy line (300) is assigned to a first address space which is located outside a second address space of the corresponding memory block (160); - Storing a known pattern in the dummy row (300) before switching on the at least one array (90) of memory cells; - Determine whether the known pattern is stored in the corresponding dummy row (300) after switching on the at least one array (90) of memory cells, wherein a determination that the known pattern is not stored in the corresponding dummy row (300) indicates an incomplete erasure of the corresponding memory block (160); and - Performing a deletion of the corresponding memory block (160) if it has been determined that the known pattern is not stored in the corresponding dummy line (300). [20] Method according to claim 19, further comprising invalidating the content of the dummy line (300) before performing a dynamic deletion operation. [21] Method according to claim 19, wherein the internal block variables comprise erase pulses and / or target voltages that are applied to the memory block (160) during the erase process. [22] Method according to claim 19, wherein restoring the memory block (160) comprises deleting the memory block (160) according to predefined parameters.

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