SEMICONDUCTOR DEVICE

Abstract

Semiconductor device comprising: a first insulating substrate (20); and a first semiconductor element (12) configured to be connected to the first insulating substrate via a first conductive spacer (16); wherein the first insulating substrate includes a first insulating layer (22) and a first inner conductive layer (24) disposed on one side of the first insulating layer, wherein the first inner conductive layer includes a surface having a first region (NR1) and a second region (RG1), and the second region surrounds the first region and has a greater surface roughness than the first region, and wherein the first conductive spacer is connected to the first region of the first inner conductive layer by a first connecting layer, wherein an edge of the first region is partially enlarged with respect to the first conductive spacer in a plan view of the first inner conductive layer, and wherein a distance between the first conductive spacer and a peripheral edge of the first inner conductive layer is larger in a portion where the edge is larger compared to another portion where the edge is smaller.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device. STATE OF THE ART

[0002] A semiconductor device is disclosed in JP 2008-166626 A. The semiconductor device includes a semiconductor element and a pair of conductive plates facing each other, with the semiconductor element disposed between the conductive plates. A conductive spacer is interposed between one of the conductive plates and the semiconductor element. The conductive spacer is connected to the conductive plate by a solder layer. A groove is provided on the conductive plate surrounding the solder layer. The groove prevents excessive wetting of the molten solder when soldering is performed between the conductive spacer and the conductive plate.

[0003] For such a semiconductor device as described above, it is considered to employ an insulating substrate in at least one of the conductive plates. The insulating substrate refers to a substrate for a power circuit in which a conductive layer, such as a metal plate, is provided on one or both surfaces of an insulating layer, such as a ceramic substrate. Typical examples of the insulating substrate include, for example, a direct bonded copper (DBC) substrate, a direct bonded aluminum (DBA) substrate, and an active metal brazed copper (AMB) substrate, but the insulating substrate is not limited to these examples. It is possible to maintain the heat dissipation characteristics of the semiconductor device while improving the insulation characteristics by using the insulating substrate. However, the conductive layer of the insulating substrate is relatively thin.Therefore, it is difficult to provide the above-described groove on the conductive layer of the insulating substrate.

[0004] Further semiconductor devices are also known from DE 11 2009 000 447 T5 and US 2013 / 0 313 711 A1.

[0005] It is an object of the present invention to control the spread of wetting of connecting material, such as solder material, in the conductive layer of the insulating substrate.

[0006] This object is achieved by the semiconductor device having the features according to the independent claim. Advantageous embodiments are the subject of the dependent claims.

[0007] A semiconductor device according to one aspect includes a first insulating substrate and a first semiconductor element connected to the first insulating substrate through a first conductive spacer. The first insulating substrate includes a first insulating layer and a first inner conductive layer disposed on one side of the first insulating layer. The first inner conductive layer includes a surface having a first region and a second region. The second region surrounds the first region and has a greater surface roughness than the first region. The first conductive spacer is connected to the first region of the first inner conductive layer through a first connecting layer. An edge of the first region is partially enlarged with respect to the first conductive spacer in a plan view of the first inner conductive layer.A distance between the first conductive spacer and a peripheral edge of the first inner conductive layer is larger in a portion where the edge is larger compared to another portion where the edge is smaller.

[0008] In the semiconductor device, the first region and the second region having a larger surface roughness than the first region are arranged on the surface of the first inner conductive layer, and the first region is surrounded by the second region. The first region with relatively low surface roughness has a relatively high wettability for the molten joining material. In contrast, the second region has a relatively large surface roughness and has a relatively low wettability for the molten joining material. When the first conductive spacer is joined to the first region by applying the joining material such as the solder material, the molten joining material has an improved wetting spread in the first region, and the wetting spread to the second region is inhibited.Therefore, it is possible to control the propagation of wetting in the connecting material at the first inner conductive layer by appropriately designing the boundary between the first region and the second region. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view showing a semiconductor device 10 according to an embodiment. Fig. 2 is a cross-sectional view along the line II-II in Fig. 1. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 1. Fig. 4 is a perspective view showing an internal structure of the semiconductor device 10 by omitting a seal 52. Fig. 5 is a perspective view showing the internal structure of the semiconductor device 10 by omitting the seal 52 and a first insulating substrate 20. Fig. 6 is a circuit diagram of the semiconductor device 10. Fig. 7 illustrates a first inner conductive layer 24 of the first insulating substrate 20. Fig. 8 illustrates a second inner conductive layer 34 of a second insulating substrate 30. DETAILED DESCRIPTION OF EMBODIMENTS

[0009] In one embodiment of the present invention, the area of ​​a first region of a first inner conductive layer may be larger than the area of ​​a surface of a first conductive spacer facing the first region of the first inner conductive layer. According to such a configuration, a first conductive block and the first inner conductive layer are firmly bonded to each other when a first bonding layer contacts the first region over a sufficient area. Specifically, in a step of roughening a second region, foreign matters scattered from the second region are adhered to the first region. Even in such a case, if the first region is set wider than the size of the first conductive spacer, it is possible to suppress a decrease in the bonding force exerted by the foreign matters.

[0010] In the embodiment, the area where the first interconnection layer is in contact with the first inner conductive layer may be larger than the area where the first interconnection layer is in contact with the surface of the first conductive spacer. With such a configuration, since the first interconnection layer has a suitable fillet shape, the thermal stress generated inside the semiconductor device, particularly in the first barrier layer and its surroundings, is suppressed. However, in another embodiment, the area where the first interconnection layer is in contact with the first inner conductive layer may be smaller than the area where the first interconnection layer is in contact with the surface of the first conductive spacer.

[0011] In the embodiment of the present invention, the first interconnection layer may reach at least part of the boundary between the first region and the second region at a surface of the first inner conductive layer. With such a configuration, the size of the first region may be determined to be substantially suitable for the size of the first conductive spacer. However, in another embodiment, the first region may be configured to be sufficiently larger than the size of the first conductive spacer. As a result, the first interconnection layer may not be required to reach the boundary between the first region and the second region.

[0012] In the embodiment, the first interconnect layer may cover the entire first region on the surface of the first inner conductor layer. With such a configuration, the size of the first region is considered to be more suitable for the size of the first conductive spacer, and it can be determined that the wetting spread of the first interconnect layer is accurately controlled by the second region.

[0013] In the embodiment, the first bonding layer on the surface of the first inner conductive layer may extend to the second region, and need not necessarily extend to the second region. That is, the second region can completely prevent the spread of wetting of the molten bonding material, and can only suppress the spread of wetting of the molten bonding material.

[0014] In the embodiment, the first interconnection layer may include solder material. However, the material included in the first interconnection layer is not limited to only the solder material, but may also be a conductive interconnection material other than the solder material.

[0015] In the embodiment of the present invention, the first insulating substrate may further include a first outer conductive layer on the other side of the first insulating layer, in other words, on a side opposite to the first inner conductive layer. According to such a configuration, it is possible to improve the heat dissipation properties of the first insulating substrate. When the symmetry of the structure of the two sides of the first insulating layer is improved, it is possible to suppress deformation due to thermal deformation of the first insulating substrate. In this regard, the first inner conductive layer and the first outer conductive layer are not particularly limited. However, they may be formed with mutually identical patterns.

[0016] In the embodiment of the present invention, the semiconductor device may further include a seal or a sealing agent for sealing the first semiconductor element. In this case, the seal may be in contact with the second region of the first inner conductive layer. Since the second region of the first inner conductive layer has a relatively large surface roughness, it is possible to adhere to the seal, for example, through an anchor effect. When the semiconductor device includes the seal, the second region of the first inner conductive layer not only controls the wetting spread of the bonding material but can also improve the sealing properties of the first semiconductor element through the seal.

[0017] In the embodiment of the present invention, the second region of the first inner conductive layer may be a region roughened by at least one of laser irradiation, electron beam irradiation, sputtering, chemical etching, and short-time irradiation. According to such a configuration, it is possible to uniformly form the second region on the surface of the first inner conductive layer. The second region has low roughness. The surface roughness of the second region is not particularly limited. As described above, the wettability of the molten joining material, that is, the material contained in the first joining layer, may be lower in the second region than in the first region. In other words, the contact angle in the second region of the molten joining material may be smaller than the contact angle in the first region.For example, the contact angle in the second region may be 90 degrees or more, whereas the contact angle in the first region is less than 90 degrees.

[0018] In the embodiment of the present invention, the semiconductor device may further include a second insulating substrate opposed to the first insulating substrate via the first semiconductor element. In this case, the second insulating substrate may include a second insulating layer and a second inner conductive layer disposed on one side of the second insulating layer. The surface of the second inner conductive layer may include a third region and a fourth region. The fourth region has a larger surface roughness than the third region and surrounds the third region. The first semiconductor element may be connected to the third region of the second inner conductive layer via the second connection layer.In a case where the semiconductor device further includes the second insulating substrate, it is possible to similarly adopt the configuration of the first insulating substrate for the second insulating substrate.

[0019] In the embodiment of the present invention, the second insulating substrate may further include a second outer conductive layer disposed on the other side of the second insulating layer. According to such a configuration, similar to the first insulating substrate described above, it is possible to improve the heat dissipation properties of the second insulating substrate and suppress deformation caused by thermal deformation of the second insulating substrate.

[0020] In the embodiment of the present invention, the semiconductor device may further include a second semiconductor element connected to the first insulating substrate through a second conductive spacer. In this case, the first inner conductive layer of the first insulating substrate may include a fifth region and a sixth region. The sixth region has a greater surface roughness than the fifth region and surrounds the fifth region. The second conductive spacer may be connected to the fifth region of the first inner conductive layer through the third interconnection layer. The fifth region may be separate from the first region or continuous with the first region. The fifth region may be separate from the first region or continuous with the first region.

[0021] In the embodiment, the first inner conductive layer of the first insulating substrate may have a first portion and a second portion separated from each other above the first insulating layer. In this case, the first region and the second region may be disposed in and on the first portion of the first inner conductive layer, respectively, and the fifth region and the sixth region may be disposed in and on the second portion of the first inner conductive layer, respectively. According to such a configuration, the first semiconductor element and the second semiconductor element may be electrically insulated on the common first insulating substrate.

[0022] In the embodiment of the present invention, the semiconductor device may further include the second insulating substrate opposing the first insulating substrate via or through the second semiconductor element. In this case, the second insulating substrate may include a second insulating layer, with a second inner conductive layer disposed on or on a side of the second insulating layer. The surface of the second inner conductive layer may include a seventh region and an eighth region. The eighth region has a larger surface roughness than the seventh region and surrounds the seventh region. The second semiconductor element may be connected to the seventh region of the second inner conductive layer through the fourth interconnection layer. With respect to the second semiconductor element, it is possible to similarly adopt the configuration of the first insulating substrate for the second insulating substrate.

[0023] In the embodiment of the present invention, the first semiconductor element and / or the second semiconductor element may be a switching element having an upper surface electrode and a lower surface electrode. The switching element conducts or blocks electricity between the upper surface electrode and the lower surface electrode. In this case, the switching element may be an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field-effect transistor (MOSFET), but is not limited to these examples. (Embodiment)

[0024] A semiconductor device 10 according to the embodiment will be described with reference to the drawings. The semiconductor device 10 is used, for example, in a power control device for an electric vehicle and may form part of a power conversion circuit such as a converter or an inverter. An electric vehicle is generally understood herein to mean a vehicle having a motor for driving wheels, and includes, for example, an electric vehicle charged by an external electric power source, a hybrid vehicle having an internal combustion engine in addition to the motor, a fuel cell vehicle having a fuel cell as a power source, and the like.

[0025] As in Fig. As shown in Figures 1 to 6, the semiconductor device 10 includes a first semiconductor element 12, a second semiconductor element 14, and a seal 52. The first semiconductor element 12 and the second semiconductor element 14 are sealed within the seal 52. The seal 52 includes an insulating material. Although not particularly limited, in the present embodiment, the seal 52 includes a thermosetting resin such as epoxy resin. The seal 52 has a plate-like shape. The seal 52 has an upper surface 52a and a lower surface 52b. The lower surface 52b is located on a side opposite the upper surface 52a.

[0026] The first semiconductor element 12 includes a semiconductor substrate 12a, an upper surface electrode 12b, a lower surface electrode 12c, and signal electrodes 12d. The upper surface electrodes 12b and the signal electrodes 12d are located on the upper surface of the semiconductor substrate 12a, and the lower surface electrode 12c is located on the lower surface of the semiconductor substrate 12a. Although not particularly limited, the first semiconductor element 12 is a switching element that conducts and blocks electricity between the upper surface electrode 12b and the lower surface electrode 12c, and is specifically an RC-IGBT. That is, the first semiconductor element 12 has a built-in freewheeling diode in addition to the IGBT. In another embodiment, the first semiconductor device 12 may be a MOSFET.

[0027] Similarly, the second semiconductor element 14 includes a semiconductor substrate 14a, an upper surface electrode 14b, a lower surface electrode 14c, and a plurality of signal electrodes 14d. The upper surface electrodes 14b and the signal electrodes 14d are located on the upper surface of the semiconductor substrate 14a, and the lower surface electrode 14c is located on the lower surface of the semiconductor substrate 14a. Although not particularly limited, the second semiconductor element 14 is a switching element that conducts and blocks electricity between the upper surface electrode 14b and the lower surface electrode 14c, and is specifically an RC-IGBT. That is, the second semiconductor element 14 has a built-in freewheeling diode in addition to the IGBT. In another embodiment, the first semiconductor device 14 may be a MOSFET.

[0028] Although not particularly limited, semiconductor elements having the same structure are used in the first semiconductor element 12 and the second semiconductor element 14. However, in another embodiment, semiconductor elements having different structures may be used for the first semiconductor element 12 and the second semiconductor element 14, respectively. For example, switching elements having different structures may be used for the first semiconductor element 12 and the second semiconductor element 14. Alternatively, the first semiconductor element 12 may be a switching element, and the second semiconductor element 14 may be a diode element. The first semiconductor element 12 and the second semiconductor element 14 are not limited to only the switching elements; various types of power semiconductor elements may also be used.Although the semiconductor substrate 12a of the first semiconductor element 12 and the semiconductor substrate 14a of the second semiconductor element 14 are not particularly limited, each of the semiconductor substrates 12a and 14a may be, for example, a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate.

[0029] The semiconductor device 10 further includes a first insulating substrate 20 and a second insulating substrate 30. The first insulating substrate 20 faces the second insulating substrate 30 via the first semiconductor element 12 and the second semiconductor element 14. The first insulating substrate 20 and the second insulating substrate 30 are held together by the sealant 52, and the space between the first insulating substrate 20 and the second insulating substrate 30 is filled by the sealant 52. The first insulating substrate 20 is not limited to a single insulating substrate, but may include two or more insulating substrates. The second insulating substrate 30 is not limited to a single insulating substrate, but may include two or more insulating substrates.

[0030] The first insulating substrate 20 includes a first insulating layer 22, a first inner conductive layer 24, and a first outer conductive layer 26. The first inner conductive layer 24 is disposed on one side of the first insulating layer 22, and the first outer conductive layer 26 is disposed on the other side of the first insulating layer 22. The first inner semiconductor layer 24 is electrically connected to the first semiconductor element 12 and the second semiconductor element 14 within the seal 52. On the other hand, the first outer conductive layer 26 is exposed to the outside at an upper surface 52a of the seal 52. Therefore, the first insulating substrate 20 is not only included in a part of an electrical circuit, but the first insulating substrate 20 also functions as a heat radiation plate that dissipates the heat of the first semiconductor element 12 and the second semiconductor element 14 to the outside.

[0031] The first inner conductive layer 24 of the first insulating substrate 20 includes a first portion 24X and a second portion 24Y. The first portion 24X and the second portion 24Y are separated from each other and are electrically insulated above the first insulating layer 22. The first portion 24X of the first inner conductive layer 24 is electrically connected to the upper surface electrode 12b of the first semiconductor element 12 via a first conductive spacer 16. Specifically, the first portion 24X of the first inner conductive layer 24 is connected to the first conductive spacer 16 by an interconnect layer 60A, and the first conductive spacer 16 is connected to the upper surface electrode 12b of the first semiconductor element 12 by an interconnect layer 60B.On the other hand, the second portion 24Y of the first inner conductive layer 24 is electrically connected to the upper electrode 14b of the second semiconductor element 14 via a second conductive spacer 18. Specifically, the second portion 24Y of the first inner conductive layer 24 is connected to the second conductive spacer 18 by an interconnect layer 60D, and the second conductive spacer 18 is connected to the upper surface electrode 14b of the second semiconductor element 14 by an interconnect layer 60E. Although the interconnect layers 60A, 60B, 60C, 60D are not particularly limited, they may include solder material.

[0032] The first outer conductive layer 26 of the first insulating substrate 20 includes a first portion 26X and a second portion 26Y. The first portion 26X of the first outer conductive layer 26 and the first portion 24X of the first inner conductive layer 24 have identical shapes, and the two first portions 26X, 24X face each other, with the first insulating layer 22 disposed between the two first portions 26X, 24X. Similarly, the second portion 26Y of the first outer conductive layer 26 and the second portion 24Y of the first inner conductive layer 24 have identical shapes, and both second portions 26Y, 24Y face each other, with the first insulating layer 22 disposed between the two second portions 26Y, 24Y.As described above, when the first insulating substrate 20 has a symmetrical structure on both sides of the first insulating layer 22, warpage due to thermal deformation of the first insulating substrate 20 is effectively suppressed. However, in another embodiment, the first outer conductive layer 26 of the first insulating substrate 20 does not need to be divided into sections 26X, 26Y. The first outer conductive layer may include a single section.

[0033] The second insulating substrate 30 includes a second insulating layer 32, a second inner conductive layer 34, and a second outer conductive layer 36. The second inner conductive layer 34 is disposed on one side of the second insulating layer 32, and the second outer conductive layer 36 is disposed on the other side of the second insulating layer 32. The second inner semiconductor layer 34 is electrically connected to the first semiconductor element 12 and the second semiconductor element 14 within the seal 52. On the other hand, the second outer conductive layer 36 is exposed to the outside at a lower surface 52b of the seal 52. Therefore, the second insulating substrate 30 is not only included in a part of an electrical circuit, but the second insulating substrate 30 also functions as a heat radiation plate that dissipates the heat of the first semiconductor element 12 and the second semiconductor element 14 to the outside.

[0034] The second inner conductive layer 34 of the second insulating substrate 30 includes a first portion 34X, a second portion 34Y, and a third portion 34Z. The first portion 34X, the second portion 34Y, and the third portion 34Z are separated from each other and are electrically insulated via the second insulating layer 32. The first portion 34X of the second inner conductive layer 34 is connected to the lower surface electrode 12c of the first semiconductor element 12 via the interconnection layer 60C and is electrically connected to the lower surface electrode 14c. On the other hand, the second portion 34Y of the second inner conductive layer 34 is connected to the lower surface electrode 14c of the second semiconductor element 14 via the interconnection layer 60F and is electrically connected to the lower surface electrode 14c. Although the interconnection layers 60E, 60F are not particularly limited, they may include solder material.

[0035] The second outer conductive layer 36 of the second insulating substrate 30 includes a first portion 36X, a second portion 36Y, and a third portion 36Z. The first portion 36X of the second outer conductive layer 36 and the first portion 34X of the second inner conductive layer 34 have identical shapes, and the two first portions 34X, 36X face each other, with the second insulating layer 32 being disposed between the two first portions 34X, 36X. Similarly, the second portion 26Y of the second outer conductive layer 36 and the second portion 34Y of the second inner conductive layer 34 have identical shapes, and the two second portions 34Y, 36Y face each other, with the second insulating layer 32 being disposed between the two second portions 34Y, 36Y.Similarly, the third portion 36Z of the second outer conductive layer 36 and the third portion 34Z of the second inner conductive layer 34 have identical shapes, and both third portions 34Z, 36Z face each other, with the second insulating layer 32 disposed between the two third portions 34Z, 36Z. As described above, when the second insulating substrate 30 has a symmetrical structure on both sides of the second insulating layer 32, warpage due to thermal deformation of the second insulating substrate 30 is effectively suppressed. However, in another embodiment, the second outer conductive layer 36 of the second insulating substrate 30 need not be divided into portions 36X, 36Y, 36Z. The second outer conductive layer 36 may include a single portion.

[0036] As one of several examples, each of the first insulating substrate 20 and the second insulating substrate 30 in the present embodiment is an active metal brazed copper (AMB) substrate. Each of the first insulating layer 22 and the second insulating layer 32 is made of ceramics such as alumina, silicon nitride, and aluminum nitride, respectively. The first inner conductive layer 24, the second inner conductive layer 34, the first outer conductive layer 26, and the second outer conductive layer 36, however, are made of copper. The respective surfaces of the first inner conductive layer 24 and the second inner conductive layer 34 are nickel-plated and gold-plated.However, the first insulating substrate 20 and the second insulating substrate 30 are not limited to the AMB substrate, but may also be a direct bonded copper (DBC) substrate or a direct bonded aluminum (DBA) substrate. The specific configuration of the first insulating substrate 20 and the second insulating substrate 30 is not particularly limited. The first insulating substrate 20 and the second insulating substrate 30 may each include at least the first insulating layer 22, the second insulating layer 32, the first conductive layer 24, and the second conductive layer 34, but may not necessarily include the first outer conductive layer 26 and the second outer conductive layer 36.

[0037] The semiconductor device 10 further includes an interconnect element 40. The interconnect element 40 is located within the seal 52 between the first insulating substrate 20 and the second insulating substrate 30. The upper surface of the interconnect element 40 is connected to the first portion 24X of the first inner conductive layer 24 via an interconnect layer 60G. The lower surface of the interconnect element 40 is connected to the second portion 34Y of the second inner conductive layer 34. The interconnect element 40 is made of metal, such as copper or a conductor other than metal, and electrically connects the first portion 24X of the first inner conductive layer 24 and the second portion 34Y of the second inner conductive layer 34. The first semiconductor element 12 and the second semiconductor element 14 are electrically connected in series within the seal 52.

[0038] The semiconductor device 10 further includes a first power terminal 42, a second power terminal 44, and a third power terminal 46. The first power terminal 42, the second power terminal 44, and the third power terminal 46 each protrude from the seal 52 in the same direction and extend parallel to each other. The first power terminal 42, the second power terminal 44, and the third power terminal 46 are made of a conductor such as copper or another metal. Although not particularly limited, during the manufacturing stage of the semiconductor device 10, the first power terminal 42, the second power terminal 44, and the third power terminal 46 may be formed by a single lead frame together with a first signal terminal 48 and a second signal terminal 50, which will be described below.

[0039] The first power terminal 42 is connected to the second insulating substrate 30 within the seal 52. In particular, the first power terminal 42 is connected to the first portion 34X of the second inner conductive layer 34 through an interconnect layer (not shown). Thus, the first power terminal 42 is electrically connected to the lower surface electrode 12c of the first semiconductor element 12. The second power terminal 44 is connected to the first insulating substrate 20 within the seal 52. In particular, the second power terminal 44 is connected to the second portion 24Y of the first inner conductive layer 24 via an interconnect layer 60I. Thus, the second power terminal 44 is electrically connected to the upper surface electrode 12b of the second semiconductor element 14. The third power terminal 46 is connected to the second insulating substrate 30 within the seal 52.In particular, the third power terminal 46 is connected to the second portion 34Y of the second inner conductive layer 34 through a connecting layer (not shown). Consequently, the third power terminal 46 is electrically connected to the upper surface electrode 12b of the first semiconductor element 12 and the lower surface electrode 14c of the second semiconductor element 14.

[0040] The semiconductor device 10 includes a plurality of first signal terminals 48 and a plurality of second signal terminals 50. The first signal terminals 48 and the second signal terminals 50 each protrude from the seal 52 in the same direction and extend parallel to each other. Each of the first signal terminals 48 and the second signal terminals 50 is made of a conductor such as copper or another metal. The first signal terminals 48 are each connected to signal electrodes 12d of the first semiconductor element 12 within the seal 52. The second signal terminals 50 are each electrically connected to signal electrodes 14d within the seal 52.Although not particularly limited, in the present embodiment, the first signal terminals 48 and the second signal terminals 50 are each connected to the corresponding signal electrodes 12d via a bonding wire (not shown) made of metal such as aluminum or copper. However, the connection between the corresponding one of the signal terminals 48, 50 and the corresponding one of the signal electrodes 12d, 14d is not limited to only the bonding wire, but may also use the first inner conductive layer 24 of the first insulating substrate 20 or the second inner conductive layer 34 of the second insulating substrate 30 for the connection.

[0041] In the following, the configuration of the first inner conductive layer 24 of the first insulating substrate 20 and the configuration of the second inner conductive layer 34 of the second insulating substrate 30 will be described with reference to Fig. 7, Fig. 8. As described in Fig. As shown in Fig. 7, in the first insulating substrate 20, the surface of the first inner conductive layer 24 is partially roughened. As a result, unroughened regions NR1, NR2 and a roughened region RG1 are formed at the first portion 24X of the first inner conductive layer 24. The roughened region RG1 surrounds the unroughened regions NR1, NR2. The roughened region RG1 is a region roughened, for example, by laser irradiation, and the surface roughness of the roughened region RG1, RG2 is greater than the surface roughness of the unroughened regions NR1, NR2. The first conductive spacer 16 is connected to the unroughened region NR1 via the interconnection layer 60A, and the interconnection element 40 is connected to the unroughened region NR2 via the interconnection layer 60G.The non-roughened regions NR3, NR4 and the roughened region RG2 are formed on the second portion 24Y of the first inner conductive layer 24. The roughened region RG2 surrounds the non-roughened regions NR3, NR4. The second conductive spacer 18 is connected to the non-roughened region NR3 via the interconnect layer 60D, and the second power terminal 44 is connected to the non-roughened region NR4 via the interconnect layer 60I.

[0042] As in Fig. As shown in Figure 8, the surface of the second inner conductive layer 34 is partially roughened on the second insulating substrate 30. As a result, non-roughened regions NR5, NR6 and a roughened region RG1 are formed on the first portion 34X of the second inner conductive layer 34. The roughened region RG3 surrounds the non-roughened regions NR5, NR6. The first semiconductor element 12 is connected to the non-roughened region NR5 via the interconnection layer 60C, and the first power terminal 42 is connected to the non-roughened region NR6 via the interconnection layer (not shown). Non-roughened regions NR7, NR8, NR9 and a roughened region RG4 are formed on the second portion 34Y of the second inner conductive layer 34. The roughened region RG4 surrounds the non-roughened regions NR7, NR8, NR9. The second semiconductor element 14 is connected to the non-roughened region NR7 via a connecting layer 60F.The connecting element 40 is connected to another non-roughened region NR8 via a connecting layer 60H. The third power terminal 46 is connected to another non-roughened region NR9 via a connecting layer (not shown).

[0043] As described above, in the semiconductor device 10 of the present embodiment, the non-roughened region NR1 and the roughened region RG1 are arranged, for example, on the surface of the first inner conductive layer 24 of the first insulating substrate 20. The non-roughened region NR1 corresponds to a first region, and the roughened region RG1 corresponds to a second region. The non-roughened region NR1 is surrounded by the roughened region RA1. The non-roughened region NR1 with relatively low surface roughness has a relatively high wettability for the molten joining material. In contrast, the roughened region RG1 with relatively large surface roughness has a relatively low wettability for the molten joining material. Therefore, when the first conductive spacer 16 is bonded to the non-roughened region NR1 by applying the joining material, such asSolder material, the molten joining material satisfactorily wets and spreads in the non-roughened region NR1 and is prevented from being wetted and spreading in the roughened region RG1. By appropriately designing the boundary between the non-roughened region NR1 and the roughened region RG1, it is therefore possible to specifically control the spread of wetting of the joining material in the first inner conductive layer 24.

[0044] In the semiconductor device 10 of the present embodiment, the area of ​​the non-roughened region NR1 of the first portion 24X of the first inner conductive layer 24 is larger than the area of ​​the upper surface 16a facing the non-roughened region NR1 of the first conductive spacer 16. According to such a configuration, the interconnection layer 60A between the first inner conductive layer 24 and the first conductive spacer 16 can be in contact with the non-roughened region NR1 of the first inner conductive layer 24 over a sufficient area. Hereinafter, the interconnection layer 60A will be referred to as the first interconnection layer 60A. As a result, the first conductive spacer 16 and the first inner conductive layer 24 are firmly bonded to each other. Specifically, during the formation of the roughened region RG1, impurities scattered from the roughened region RG1 are adhered to the non-roughened region NR1.Even in such a case, if the non-roughened region NR1 is set wider than the size of the first conductive spacer 16, it is possible to suppress a reduction in the joining force caused by the foreign matter.

[0045] With the above configuration, in the semiconductor device 10 according to the present embodiment, the area where the first interconnection layer 60A is in contact with the first inner conductive layer 24 is larger than the area where the first interconnection layer 60A is in contact with the upper surface 16a of the first conductive spacer 16. As a result, the first interconnection layer 60A has a suitable groove shape, and the thermal stress generated inside the semiconductor device 10, particularly the interconnection layer 60A or its surroundings, is suppressed. The first interconnection layer 60A extends over the entire non-roughened region NR1 on the surface of the first inner conductive layer 24. However, it is not limited to the above example.The first bonding layer 60A may also reach only a part of the boundary between the non-roughened region NR1 and the roughened region RG1 on the surface of the first inner conductive layer 24. In the embodiment, the first bonding layer 60A may extend to the roughened region RG1 on the surface of the first inner conductive layer 24, and it is not necessary to extend to the roughened region RG1. That is, the roughened region RG1 can completely prevent the spread of wetting of the molten bonding material and can only suppress the spread of wetting of the molten bonding material.

[0046] As can be seen from Fig.7, the margin may be partially enlarged as a dimensional difference of the non-roughened region NR1 with respect to the first conductive spacer 16. In this case, although not particularly limited, in the portion where the distance from the first conductive spacer 16 to the outer peripheral edge of the first inner conductive layer 24 is relatively large, the margin of the non-roughened region NR1 with respect to the first conductive spacer 16 may be enlarged. In other words, in the portion where the distance from the first conductive spacer 16 to the outer peripheral edge of the first inner conductive layer 24 is relatively small, the margin of the non-roughened region NR1 with respect to the first conductive spacer 16 may be reduced.As a result, the roughened region RG1 having a sufficient width can be formed outside the non-roughened region NR1 even in the portion where the clearance is small.

[0047] In the semiconductor device 10 according to the present embodiment, each of the interconnection layers 60A to 60I may be made of solder material. However, the material included in each of the interconnection layers 60A to 60I is not limited to only the solder material, but may also be another conductive interconnection material. Regardless of the type of interconnection material, the surface roughness required for the roughened regions RG1 to RG4 may be designed to suppress the wetting spread of the molten interconnection material. Furthermore, the technique for forming the roughened regions RG1 to RG4 is not limited to laser irradiation, but may be performed by, for example, electron beam irradiation, sputtering, chemical etching, or shot peening.

[0048] The above-described functional effects associated with the non-roughened region NR1 are similar to the effects occurring in each of the other non-roughened regions NR2 to NR9. For example, in the second portion 24Y of the first inner conductive layer 24, when the second conductive spacer 18 is bonded to the non-roughened region NR2, the molten bonding material is satisfactorily wetted and spread in the non-roughened region NR2 and prevented from being wetted and spreading in the roughened region RG2. The non-roughened region NR2 corresponds to a fifth region, and the roughened region RG2 corresponds to a sixth region.In the first portion 24Y of the second inner conductive layer 34, when the first semiconductor element 12 is bonded to the non-roughened region NR5, the molten bonding material is satisfactorily wetted and spread in the non-roughened region NR5 and prevented from wetting and spreading into the roughened region RG3. The non-roughened region NR5 corresponds to a third region, and the roughened region RG3 corresponds to a fourth region. When the second semiconductor element 14 is bonded to the non-roughened region NR7 in the second portion 24Y of the second inner conductive layer 34, the molten bonding material is satisfactorily wetted and spread in the non-roughened region NR7 and prevented from wetting and spreading into the roughened region RG4. The non-roughened region NR7 corresponds to a seventh region, and the roughened region RG4 corresponds to an eighth region.When the corresponding connecting element 40 or the power terminals 42, 44, 46 are connected to each of the remaining non-roughened regions NR2, NR4, NR6, NR8, NR9, the excessive spread of wetting of the molten connecting material through the roughened regions RG1 to RG4 can be suppressed.

[0049] The remaining non-roughened regions NR2, NR4, NR6, NR8, NR9 are located near the outer peripheral edge of each of the first inner conductive layer 24 and the second inner conductive layer 34. A portion of each of the non-roughened regions NR2, NR4, NR6, NR8, NR9 reaches the outer peripheral edge of the corresponding one of the first inner conductive layer 24 and the second inner conductive layer 34 at a location that may not necessarily be surrounded by the roughened regions NG1 to NG4. Even with such a configuration, the wetting spread of the molten solder material through the edge of the outer periphery of each of the first inner conductive layer 24 and the second inner conductive layer 34 can be prevented.However, in such an embodiment, it is also effective to suppress the wettability on the side surface of each of the first inner conductive layer 24 and the second inner conductive layer 34 by omitting the gold plating of the first inner conductive layer 24 and the second inner conductive layer 34. The side surface of each of the first inner conductive layer 24 and the second inner conductive layer 34 corresponds to an outer peripheral surface. DESCRIPTION OF REFERENCE SYMBOLS 10 semiconductor device 12 First semiconductor element 14 Second semiconductor element 16 First conductive spacer 18 Second conductive spacer 20 First Insulating Substrate 22 First insulating layer 24 First inner conductive layer 24X First section of the first inner conductive layer 24Y Second section of the first inner conductive layer 26 First outer conductive layer 26X First section of the first outer conductive layer 26Y Second section of the first outer conductive layer 30 Second insulating substrate 32 Second insulating layer 34 Second inner conductive layer 34X First section of the second inner conductive layer 34Y Second section of the second inner conductive layer 36 Second outer conductive layer 36X First section of the second outer conductive layer 36Y Second section of the second outer conductive layer 40 connecting element 42 First power connection 44 Second power connection 46 Third power connection 48 First signal connection 50 Second signal connection 52 Sealing 60A - 60I connection layer

Claims

[1] A semiconductor device comprising: a first insulating substrate (20); and a first semiconductor element (12) configured to be connected to the first insulating substrate via a first conductive spacer (16); wherein the first insulating substrate includes a first insulating layer (22) and a first inner conductive layer (24) disposed on one side of the first insulating layer, wherein the first inner conductive layer includes a surface having a first region (NR1) and a second region (RG1), and the second region surrounds the first region and has a greater surface roughness than the first region, and wherein the first conductive spacer is connected to the first region of the first inner conductive layer by a first connecting layer, wherein an edge of the first region is partially enlarged with respect to the first conductive spacer in a plan view of the first inner conductive layer, and wherein a distance between the first conductive spacer and a peripheral edge of the first inner conductive layer is larger in a portion where the edge is larger compared to another portion where the edge is smaller. [2] The semiconductor device according to claim 1, wherein an area of ​​the first region of the first inner conductive layer is larger than an area of ​​a surface of the first conductive spacer facing the first region. [3] The semiconductor device according to claim 2, wherein an area where the first interconnection layer is in contact with the first inner conductive layer is larger than an area where the first interconnection layer is in contact with the surface of the first conductive spacer. [4] A semiconductor device according to any one of claims 1 to 3, wherein the first interconnection layer reaches at least a part of a boundary between the first region and the second region at the surface of the first inner conductive layer. [5] The semiconductor device according to claim 4, wherein the first interconnection layer completely covers the first region on the surface of the first inner conductive layer. [6] A semiconductor device according to any one of claims 1 to 5, wherein the first interconnection layer does not cover the second region on the surface of the first inner conductive layer. [7] A semiconductor device according to any one of claims 1 to 6, wherein the first interconnection layer is made of solder material. [8] A semiconductor device according to any one of claims 1 to 7, wherein the first insulating substrate further includes a first outer conductive layer (26) disposed on another side of the first insulating layer. [9] A semiconductor device according to any one of claims 1 to 8, further comprising: a seal (52) configured to seal the first semiconductor element, wherein the seal is in contact with the second region of the first inner conductive layer. [10] The semiconductor device according to any one of claims 1 to 9, wherein the second region of the first inner conductive layer is a region roughened by at least one of laser irradiation, electron beam irradiation, sputtering, chemical etching, and short blasting. [11] A semiconductor device according to any one of claims 1 to 10, further comprising: a second insulating substrate (30) opposite to the first insulating substrate, wherein the first semiconductor element is arranged between the second insulating substrate and the first insulating substrate, wherein the second insulating substrate includes a second insulating layer (32) and a second inner conductive layer (34) disposed on one side of the second insulating layer, wherein the second inner conductive layer includes a surface having a third region (NR5) and a fourth region (RG4), and the fourth region surrounds the third region and has a greater surface roughness than the third region, and wherein the first semiconductor element is connected to the third region of the second inner conductive layer by a second connection layer (60C). [12] The semiconductor device according to claim 11, wherein the second insulating substrate further includes a second outer conductive layer (36) disposed on another side of the second insulating layer. [13] A semiconductor device according to any one of claims 1 to 12, further comprising: A second semiconductor element (14) configured to be connected to the first insulating substrate through the second conductive spacer (18), wherein the first inner conductive layer of the first insulating substrate includes a fifth region (NR2) and a sixth region (RG2), and the sixth region surrounds the fifth region and has a greater surface roughness than the fifth region, and wherein the second conductive spacer is connected to the fifth region of the first inner conductive layer by a third connecting layer (60D). [14] A semiconductor device according to claim 13, wherein the first inner conductive layer of the first insulating substrate includes a first region (24X) and a second region (24Y) separated from each other above the first insulating layer, wherein the first region and the second region are arranged on the first portion of the first inner conductive layer, and wherein the fifth region and the sixth region are arranged on the second portion of the first inner conductive layer. [15] A semiconductor device according to claim 13 or 14, further comprising: a second insulating substrate (30) opposite to the first insulating substrate, wherein the second semiconductor element is arranged between the first insulating substrate and the second insulating substrate, wherein the second insulating substrate includes a second insulating layer (32) and a second inner conductive layer (34) disposed on one side of the second insulating layer, wherein the second inner conductive layer includes a surface having a seventh region (NR7) and an eighth region (RG4), and the eighth region surrounds the seventh region and has a greater surface roughness than the seventh region, and wherein the second semiconductor element is connected to the seventh region of the second inner conductive layer by a fourth connection layer (60F).

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