LOW LEAKAGE CURRENT ELECTRICAL OVERLOAD PROTECTION FOR HIGH-VOLTAGE TOLERANT HIGH-SPEED INTERFACES

Abstract

A semiconductor die with electrical overload protection with low leakage current and high voltage tolerance, the semiconductor die comprising: a signal pad (1); an internal circuit (2) electrically connected to the signal pad (1); a power terminal (9) electrically connected between an isolated node (11) and a reference node; and one or more isolation blocking voltage devices (3; 4) electrically connected between the signal pad (1) and the isolated node (11), the one or more isolation blocking voltage devices (3; 4) operative to isolate the signal pad (1) from a capacitance of the power terminal (9); a first reverse protection diode (6) connected in parallel with the power terminal (9) and having its anode connected to the reference node and its cathode connected to the isolated node (11);anda second reverse protection diode (7) whose anode is connected to the separated node (11) and whose cathode is connected to the signal pad (1);

Description

FIELD OF DISCLOSUREEmbodiments of the invention relate to electronic systems and, more particularly, to electrical overload protection with low leakage, low capacitance, and / or high voltage tolerance.BACKGROUNDCertain electronic systems may be subject to electrical overload events or short duration electrical signals with rapidly changing voltage and high power. Electrical overload events include, for example, electrical overload (EOS) and electrostatic discharge (ESD) resulting from the sudden release of charge from an object or person to an electronic system.Electrical overload events can damage or destroy integrated circuits (IC) by creating overvoltage conditions and high levels of power dissipation in relatively small areas of the IC. High power dissipation can increase the IC temperature and lead to numerous problems such as gate oxide breakdown, junction damage, metal damage, and surface charge accumulation.US 2014 / 0 167 104 A1 relates to protection circuit architectures with integrated supply terminals and methods for their production. In a particular implementation, an integrated circuit interface protection device includes a first diode protection structure and a first thyristor protection structure electrically connected in parallel between a signal pin and a high voltage supply. Moreover, the protection device comprises a second diode protection structure and a second thyristor protection structure electrically connected in parallel between the signal pin and a low power supply. In addition, the protection device comprises a third diode protection structure and a third thyristor protection structure which are electrically connected in parallel between the power high supply and the power low supply. The third thyristor protection structure and the third diode protection structure are synthesized as part of the integrated circuit interface and may share at least a portion of the wells and / or diffusion regions connected to the first and second thyristor protection structures.US 2015 / 0 263 505 A1 relates to an open drain output circuit which outputs a signal of an internal circuit. The output circuit includes a first signal output terminal, a first signal line, a first floating line, a first rectifying element, and a first ESD protection circuit. The first signal line connects the first signal output terminal and the internal circuit. The potential of the first floating line is not fixed. The first rectifier element is connected between the first signal output terminal and the first floating line. The first ESD protection circuit is connected between the first floating line and the ground potential.SUMMARY OF THE DISCLOSURELow leakage and low capacitance electrical overload protection is provided. In certain embodiments, a semiconductor chip comprises a power clamp for protecting against electrical overloading at a contact surface of the electrical interface of the chip. The power terminal is separated from the contact surface by at least one isolation blocking voltage device. By inserting the isolation blocking voltage device between the contact pad and the power terminal, the contact pad is shielded from a capacitance of the power terminal and / or a leakage current amount at the contact pad is reduced. In this way, the electrical interface may operate at high speed, fast signaling and / or low static power dissipation while maintaining robustness in the event of electrical overload that could otherwise damage the semiconductor die.In one aspect, there is provided a semiconductor die with low leakage current electrical overload protection and high voltage tolerance having the features of claim 1.In a further aspect, an electrical interface for a semiconductor chip is provided having the features of claim 11.In another aspect, there is provided a method of providing low capacitance, low leakage current electrical overload protection having the features of claim 13.In another aspect, a semiconductor die with bidirectional protection against electrical overload is provided. The semiconductor die includes a first pad, a second pad, a forward protection SCR electrically connected between the first pad and the second pad and configured to become active in response to electrical overload that increases a voltage of the first pad relative to a voltage of the second pad, and a reverse protection SCR electrically connected in parallel to the forward protection SCR between the first pad and the second pad and configured to become active in response to electrical overload that decreases the voltage of the first pad relative to the voltage of the second pad. In certain embodiments, the forward protection SCR and / or the reverse protection SCR includes one or more gated diodes.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1A is a schematic illustration of a chip interface according to an example embodiment. FIG. 1B is a schematic illustration of a chip interface according to an example embodiment. FIG. 1C is a schematic illustration of a chip interface according to an example embodiment. FIG. 1D is a schematic illustration of a chip interface according to another embodiment. FIG. 1E is a schematic illustration of a chip interface according to an example embodiment. FIG. 2A is a schematic illustration of a chip interface according to an example embodiment. FIG. 2B is a top view of one embodiment of a layout for a protection circuit. FIG. 3A is a top view of an embodiment of a layout for a gated diode. FIG. 3B is a top view of another embodiment of a layout for a gated diode. FIG. 3C is a cross-section of a gated diode according to another embodiment. FIG. 3D is a cross-section of a gated diode according to another embodiment. FIG. 3E is a top view of an embodiment of a gate and first metal layer layout for a gate controlled diode. FIG. 3F is a top view of an embodiment of a layout of gate, first metal and second metal layers for a gate controlled diode. FIG. 3G is a top view of an embodiment of a layout of gate, second metal and third metal layers for a gate controlled diode. FIG. 3H is a top view of an embodiment of a layout of gate, third metal and fourth metal layers for a gate controlled diode. FIG. 3I is a top view of an embodiment of a gate, fourth metal, and fifth metal layer layout for a gated diode. FIG. 3J is a top view of an embodiment of a layout of gate, fifth metal and sixth metal layers for a gated diode. FIG. 3K is a top view of an embodiment of a layout of gate, sixth metal and seventh metal layers for a gated diode. FIG. 4 is a top view of an embodiment of a layout for reverse protection diodes. FIG. 5 is a schematic illustration of a power clamp according to an embodiment. FIG. 6 is a schematic illustration of a power clamp according to another embodiment. FIG. 7 is a graph of an example of a 1-kV human body model (HBM) simulation over time for the power clamp of FIG. 6. FIG. 8 is a diagram of an example of leakage current versus temperature for an implementation of the chip interface of FIG. 2A. FIG. 9 is a diagram of an example of parasitic capacitance versus temperature for an implementation of the chip interface of FIG. 2A. FIG. 10A is a top view of one embodiment of a layout for a protection circuit. FIG. 10B is a top view of another embodiment of a layout for a protection circuit. FIG. 11 is a schematic diagram of a bidirectional protection circuit according to an example embodiment. FIG. 12 is a cross-section of a forward protection SCR according to an example embodiment. FIG. 13A is a cross-section of a reverse protection SCR according to an example embodiment. FIG. 13B is a circuit diagram of a portion of the reverse protection SCR of FIG. 13A. FIG. 13C is a schematic illustration of a chip interface according to an example embodiment. FIG. 14A is a top view of an example embodiment of a layout of a bidirectional protection circuit. FIG. 14B is a top view of an example embodiment of a layout of a forward protection SCR. FIG. 14C is a top view of an example embodiment of a layout of a reverse protection SCR. FIG. 15A is a plot of current versus voltage for various temperatures for an implementation of the bidirectional protection circuit of FIG. 11. FIG. 15B is a plot of TLP characteristics of current versus voltage for an implementation of the bidirectional protection circuit of FIG. 11. FIG. 15C is a graph of capacitance versus frequency characteristics for an implementation of the bidirectional protection circuit of FIG. 11. FIG. 15D is a plot of TLP characteristics of current versus voltage for an implementation of the bidirectional protection circuit of FIG. 11.DETAILED DESCRIPTIONThe following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention may be embodied in a variety of different ways. In this specification, reference is made to the drawings in which like reference numerals may designate identical or functionally similar elements. It will be understood that the elements depicted in the figures are not necessarily drawn to scale. It will also be appreciated that certain embodiments may include more elements than those shown in a drawing and / or a subset of the elements shown in a drawing. Further, some embodiments may include any suitable combination of features from two or more drawings.Certain electronic systems include overload protection circuits to protect circuits or components from electrical overload events. To help ensure that an electronic system is reliable, manufacturers may test the electronic system under defined load conditions that may be described by standards set by various organizations such as the Joint Electronic Device Engineering Council (JEDEC), the International Electrotechnical Commission (IEC), and the Automotive Engineering Council (AEC). The standards may cover a variety of electrical overload events, including electrical overload (EOS) and / or electrostatic discharge (ESD).A power terminal separated from the contact surface by one or more isolation blocking voltage devicesLow leakage and low capacitance electrical overload protection is provided. In certain embodiments, a semiconductor chip comprises a power clamp for protecting against electrical overloading at a contact surface of the electrical interface of the chip. The power terminal is separated from the contact surface by at least one isolation blocking voltage device. By inserting the isolation blocking voltage device between the contact pad and the power terminal, the contact pad is shielded from a capacitance of the power terminal and / or a leakage current amount at the contact pad is reduced. In this way, the electrical interface may operate at high speed, fast signaling and / or low static power dissipation while maintaining robustness in the event of electrical overload that could otherwise damage the semiconductor die.Such electrical overload protection schemes are suitable for a variety of pads including, but not limited to, pads that operate with tight leakage current and / or capacitance constraints. For example, the teachings herein may be used to provide protection to a consumer electronics control (CEC) pad of a high-definition multimedia interface (HDMI) interface.Examples of isolation blocking voltage devices include, but are not limited to, isolation diodes, isolation thyristors, and / or other devices that conduct little to no conduction below a blocking voltage while conducting at voltages above the blocking voltage.FIG. 1A is a schematic illustration of a chip interface 10 according to an example embodiment. The chip interface 10 comprises a chip pin or pad 1, an internal circuit 2, a separating diode 3 and a power terminal 9.In the illustrated embodiment, the isolation diode 3 has been incorporated to reduce the effect of the parasitic capacitance of the power terminal 9 on the operation of the internal circuit 2. As shown in FIG. 1A, the isolation diode 3 is electrically connected in series with the power terminal 9 between the pad 1 and a reference voltage such as ground. In certain implementations, the reference voltage is connected to another pad of the chip, e.g., a ground pad.Although an embodiment with an isolation diode is shown, the teachings herein are applicable to other types of isolation blocking voltage devices. For example, isolation diodes, isolation thyristors, and / or other isolation blocking voltage devices may be used. In addition, the teachings herein are applicable to implementations using a combination of two or more isolation blocking voltage devices of different types. For example, one or more isolation diodes may be electrically connected in series with one or more isolation thyristors between a signal pad and a separate node.The power terminal 9 provides electrical overload protection for the internal circuit 2. For example, the power terminal 9 for providing forward protection becomes active when an electrical overload causes the voltage of the contact pad 1 (relative to the reference voltage) to increase and reach a trigger voltage. Although not shown in FIG. 1A, in certain implementations, the chip interface 10 further includes reverse protection circuitry for electrical overload protection that causes the voltage of the pad 1 to decrease relative to the reference voltage.The node between the power terminal 9 and the isolation diode 3 corresponds to a isolated node 11 that is not directly connected to a contact pad or pin of the semiconductor die. Rather, the isolated node 11 is electrically isolated from the pad 1 by the isolation diode 3 and electrically isolated from the reference voltage by the power terminal 9 (e.g., in implementations where the reference voltage is provided by a ground pad). The separate node 11 is also referred to herein as a virtual utility.Certain circuits for electrical overload protection have a relatively high degree of snapback corresponding to a difference between a trip voltage of the protection circuit and a hold voltage of the protection circuit. High snap-back protection circuits may have certain desirable properties, but may be unsuitable for certain applications. For example, the high level of snapback and / or the low hold voltage of such protection circuits may be unacceptable for the protection of certain types of internal circuits and / or pads.The inclusion of the isolation diode 3 not only shields or isolates the internal circuit 2 from a parasitic capacitance of the power terminal 9, but the isolation diode 3 also increases a sustain voltage for overload protection, thereby a larger range of protection circuits being suitable for the protection of the internal circuit 2. The isolation diode 3 may also help reduce the leakage current of the power terminal 9 and thereby increase the performance.In certain implementations, the isolation diode 3 is implemented as a gated diode. For example, a gate controlled diode may include a p-type region (e.g., a P+ region) formed in a semiconductor region (e.g., a p-type or n-type semiconductor well) and an n-type region (e.g., an N+ region) formed in the semiconductor region. In addition, a field plate or gate (e.g., a metal gate of a field effect transistor) is included between the p-type region and the n-type region over a surface of the semiconductor region. A diode having a gate is referred to herein as a gate controlled diode.Implementing the isolation diode 3 using a gated diode provides a number of advantages, such as increased control over the low capacitance characteristics with process, temperature and / or voltage (PVT) variation.FIG. 1B is a schematic illustration of a chip interface 15 according to an example embodiment. The chip interface 15 of FIG. 1B is similar to the chip interface 10 of FIG. 1A, except that the chip interface 15 further includes a second isolation diode 4 in series with the first isolation diode 3.In certain implementations, two or more isolation diodes are included in series with a power terminal. The inclusion of two or more isolation diodes may result in further reductions in parasitic capacitance and / or leakage current. Moreover, the inclusion of two or more isolation diodes may increase the hold voltage for overload protection and / or reduce the adverse effects of snap-back of the power terminal 9. Although an example with two isolation diodes is shown, three or more isolation diodes may be included in series.FIG. 1C is a schematic illustration of a chip interface 20 according to an example embodiment. The chip interface 20 of FIG. 1C is similar to the chip interface 10 of FIG. 1A, except that the chip interface 20 also includes a reverse protection circuit 12. As shown in FIG. 1C, the reverse protection circuit 12 is electrically connected between the pad 1 and a reference voltage such as ground.The reference voltage of the reverse protection circuit 12 may be equal to or different from the reference voltage of the power terminal 9. Thus, in one example, the reference voltage of the reverse protection circuit 12 and the reference voltage of the power terminal 9 are provided by a common pad, such as a shared ground pad. In another example, the reference voltage of the reverse protection circuit 12 and the reference voltage of the power terminal 9 are provided by separate pads. In implementations with separate pads, the reference voltages may have the same voltage level or different voltage levels.In certain implementations, a reverse protection circuit for providing electrical overload protection is included that reduces a voltage of the contact pad. Examples of reverse protection circuits include, but are not limited to, diodes and / or controlled silicon rectifiers (SCR). An SCR is also referred to herein as a thyristor.FIG. 1D is a schematic illustration of a chip interface 25 according to an embodiment. The chip interface 25 of FIG. 1D is similar to the chip interface 10 of FIG. 1A, except that the chip interface 25 further includes a first reverse protection diode 6 and a second reverse protection diode 7.As shown in FIG. 1D, the first reverse protection diode 6 is electrically connected in parallel with the power terminal 9, an anode of the first reverse protection diode 6 is electrically connected to the reference voltage, and a cathode of the first reverse protection diode 6 is electrically connected to the disconnected node 11. In addition, the second reverse protection diode 7 is electrically connected in series with the first reverse protection diode 6, an anode of the second reverse protection diode 7 is electrically connected to the disconnected node 11, and a cathode of the second reverse protection diode 7 is electrically connected to the pad 1.The chip interface 25 of Figure 1D shows another embodiment of electrical overload protection circuitry that is bi-directional. For example, when an electrical overload event having negative polarity causes the voltage of the pad 1 to decrease relative to the reference voltage, current flows through the first reverse protection diode 6 and the second reverse protection diode 7 to mitigate the electrical overload.FIG. 1E is a schematic illustration of a chip interface 30 according to an example embodiment. The chip interface 30 of FIG. 1E is similar to the chip interface 15 of FIG. 1B, except that the chip interface 30 further includes a first reverse protection diode 6, a second reverse protection diode 7, and a third reverse protection diode 8.As shown in FIG. 1E, the first reverse protection diode 6, the second reverse protection diode 7 and the third reverse protection diode 8 are electrically connected in series between the reference voltage and the pad 1. Although an example with three diodes in series is shown, more or fewer reverse protection diodes may also be included.The chip interface 30 of FIG. 1E illustrates another embodiment of electrical overload protection circuitry that is bi-directional.FIG. 2A is a schematic illustration of a chip interface 50 according to an example embodiment. The chip interface 50 comprises a signal pad 21 (in this example a CEC pin of an HDMI interface), a ground pad 23, an isolation diode 3, a first reverse protection diode 13, a second reverse protection diode 14, a power terminal 29 (with a trigger voltage of about 3.3 V in this example) and an internal circuit 22.The chip interface 50 comprises a reverse protection circuit realized as the first reverse protection diode 13 and the second reverse protection diode 14 in series between the signal pad 21 and the ground pad 23. Although an example of a reverse protection circuit is shown, other implementations of reverse protection are possible. Moreover, although an example with two reverse protection diodes is illustrated, more or fewer reverse protection diodes may be included.In the illustrated embodiment, the internal circuit 22 includes a CEC receiving portion (CEC RX) including an n-type first receiving field effect transistor (NFET) 31, a second receiving NFET 32, a receiver 33, a receiving protection and control circuit 34, a first receiving resistor 35, and a second receiving resistor 36.The internal circuit 22 further includes a CEC transmission part (CEC TX) including a first transmission NFET 41, a second transmission NFET 42, and a transmission protection and control circuit 43. As shown in FIG. 2A, the transmission protection and control circuit 43 receives an enable signal (en) and controls the gate voltages of the first transmission NFET 41 and the second transmission NFET 42. The internal circuit 22 further includes a CEC protection part (CEC PROT) including a first sensing resistor 45 and a second sensing resistor 46 that operate as a voltage divider that provides a divided voltage to the reception protection and control circuit 34 and the transmission protection and control circuit 43. The divided voltage varies depending on the voltage of the signal pad 21.FIG. 2B is a top view of one embodiment of a layout 70 for a protection circuit. Layout 70 corresponds to one implementation of the protection circuit layout for electrical interface 50 of FIG. 2A. The layout includes a low-leakage power clamping portion 61 (corresponding to a layout of the power clamp 29), an upper diode portion 62 (corresponding to a layout of the isolation diode 3), and a lower diode portion 63 (corresponding to a layout of the first reverse protection diode 13 and the second reverse protection diode 14). In this example, layout 70 has a footprint of about 100 μm by 140 μm.FIG. 3A is a top view of one embodiment of a layout for a gated diode 110.The gate controlled diode 110 includes a semiconductor region 100 that may correspond to a doped well or substrate. When the semiconductor region 100 has a p-type doping, the gate controlled diode 110 is referred to as a p-type gate controlled diode. In addition, when the semiconductor region 100 has n-type doping, the gate controlled diode 110 is referred to as an n-type gate controlled diode.With continued reference to FIG. 3A, the gated diode 110 further includes a P+ anode region 101, an N+ cathode region 102, and a metal gate 103 extending across the semiconductor region 100 between the P+ anode region 101 and the N+ cathode region 102.Implementing an isolation diode (e.g., the first isolation diode 3 and / or the second isolation diode 4 of FIGS. 1A-2A ) using a gated diode provides a number of advantages, such as reduced leakage current, lower parasitic capacitance, and / or higher hold voltage. Moreover, a gate controlled diode can have superior low capacitance properties in the presence of PVT variation. In certain implementations listed herein, the gate of a gated diode is electrically floating during operation.FIG. 3B is a top view of another embodiment of a layout for a gated diode 120. The gated diode 120 includes P+ anode regions 101, N+ cathode regions 102, metal gates 103, n-type well (NW) 112, and P+ ring 115. The gate controlled diode 120 is fabricated in a p-type substrate (PSUB) 111 in this example.As shown in FIG. 3B, the P+ anode regions 101 and the N+ cathode regions 102 are formed in the NW 112. Thus, as shown in FIG. 3B, the gate controlled diode 120 is an n-type gate controlled diode. The P+ anode regions 101 may be electrically connected to each other using metallization (e.g., metallization associated with back-end processing of a semiconductor die) to form an anode terminal of the gated diode 120. In addition, N+ cathode regions 102 may be electrically connected to each other by metallization to form a cathode terminal of the gated diode 120.In the illustrated embodiment, the gated diode 120 includes a plurality of portions or legs electrically interconnected by metallization. Implementing the gated diode 120 using multiple sections helps achieve a compact area and / or desired operating characteristics, such as current handling capability.FIG. 3C is a cross-section of a gated diode 130 according to another embodiment. The gate controlled diode 130 is formed in the PSUB 111 and includes a P+ anode region 101, N+ cathode regions 102, metal gates 103, an NW 112, and a P+ guard ring 115.Referring to FIG. 3C, a cross-section of the gated diode 130 is shown. In the top plan view, the gated diode 130 may have a layout that may be implemented in a variety of ways, such as a planar layout configuration or an annular configuration. For example, the gate controlled diode 130 may be implemented using a planar layout configuration as shown in FIG. 3B.In the illustrated embodiment, the gated diode 130 is formed directly in the PSUB 111. However, the teachings herein are also applicable to other configurations, such as implementations in which a substrate includes a p-type epitaxial layer over a doped or undoped carrier substrate and the gate controlled diode 130 is fabricated in the p-type epitaxial layer. Although not shown in FIG. 3B, the PSUB 111 typically includes other devices or structures formed therein. For example, any of the circuitry of the chip interfaces herein may be fabricated on a common substrate of a semiconductor die.A gate controlled diode may include various wells (e.g., n-type wells (NW) and / or p-type wells (PW) regions), various active regions (e.g., n-type active (N+) and / or p-type active (P+) regions), gate structures (e.g., metal gates), and / or other structures. Those of ordinary skill in the art will understand that P+ regions have a higher doping concentration than the PW, which in turn have a higher doping concentration than the p-type substrate. In addition, N+ regions have a higher doping concentration than NW. One of ordinary skill in the art will understand different dopant concentrations in the ranges.It should be understood that since regions within a semiconductor device are defined by doping different portions of a semiconductor material with different impurities or different concentrations of impurities, discrete physical boundaries between different regions may not actually exist in the completed device, but the regions may instead merge with one another. Some boundaries as depicted in the figures of this type are depicted as abrupt structures merely to aid the reader. Those of ordinary skill in the art will understand that p-type regions may include a p-type semiconductor material, such as boron, as a dopant. In addition, n-type regions may include an n-type semiconductor material such as phosphorus as a dopant.Although electrical connections are schematically represented by lines, one of ordinary skill in the art will understand that the discussed electrical connections may be partially made by metallization via back-end processing. Additionally, in certain implementations, bond pads or other structures may be included that may correspond to certain nodes. Such details are omitted for the sake of clarity of the figures.As shown in FIG. 3C, the gate controlled diode 130 includes an anode terminal (ANODE) and a cathode terminal (CATHODE). In addition, a substrate terminal (SUB) for connection to the PSUB 111 is shown.FIG. 3D is a cross-section of a gated diode 135 according to another embodiment. The gated diode 135 is formed in the PSUB 111 and includes anode P+ regions 101, cathode N+ region 102, metal gates 103, PW 114, P+ guard ring 115, PW guard ring 116, N+ isolation ring 117, NW isolation ring 118, and DNW 119. The N+ separation ring 117, the NW separation ring 118, and the DNW 119 function as an n-type separation well that electrically separates the PW 114 from the PSUB 111. In addition, the P+ guard ring 115 and the PW guard ring 116 function as a p-type guard ring.In the illustrated embodiment, the gate controlled diode 135 is implemented using a bipolar transistor structure in which the base-emitter junction of the bipolar transistor structure serves as the gate controlled diode. The gated diode 135 may provide a lower capacitance, separation, and / or reverse leakage current relative to the gated diode 130 of FIG. 3C.Electrical connections are schematically shown with lines across the cross section. As shown in FIG. 3D, the gate controlled diode 135 includes an anode / base terminal (ANODE / BASE) and a cathode / emitter terminal (CATHODE / EMITTER). In addition, there are shown a separation / collector terminal (SEPARATION / COLLECTOR) for connecting to the n-type separation well and a substrate terminal (SUB) for connecting to the PSUB 111 / p-type guard ring.FIGS. 3E-3K show a top view of gate and metallization layers for an embodiment of a gated diode. The top views show an example die metallization for a p-type gated diode according to the configuration in FIG. 3D for a multi-finger implementation with forty-two metal gates.FIG. 3E is a top view of an embodiment of a gate and first metal layer layout for a gate controlled diode. As shown in FIG. 3E, the first metal layer is used for inter-finger routing of the gated diode and for providing connection to the n-type isolation well and the p-type guard ring.FIG. 3F is a top view of an embodiment of a layout of gate, first metal and second metal layers for a gate controlled diode. As shown in FIG. 3F, the first metal layer and the second metal layer superimpose the fingers of the gated diode to provide an improved capability to handle the density of transient current.FIG. 3G is a top view of an embodiment of a layout of gate, second metal and third metal layers for a gate controlled diode. As shown in FIG. 3G, the third metal layer provides a low resistance for the anode terminal and the cathode terminal while having a relatively large separation to reduce parasitic capacitances between the metals.FIG. 3H is a top view of an embodiment of a layout of gate, third metal and fourth metal layers for a gate controlled diode. As shown in FIG. 3H, the fourth metal layer overlaps the third metal layer to provide low terminal resistance and reduced parasitic capacitances between the metals.FIG. 3I is a top view of an embodiment of a gate, fourth metal, and fifth metal layer layout for a gated diode. As shown in FIG. 3I, the fifth metal layer overlaps the fourth metal layer to provide low terminal resistance and reduced parasitic capacitances between the metals.FIG. 3J is a top view of an embodiment of an array of gate, fifth metal and sixth metal layers for a gate controlled diode. As shown in FIG. 3J, the sixth metal layer overlaps the fifth metal layer to provide low terminal resistance and reduced parasitic capacitances between the metals.FIG. 3K is a top view of an embodiment of a gate, sixth, and seventh metal layer layout for a gated diode. As shown in FIG. 3K, the seventh metal layer serves to current distribution and mitigate bias reduction effects by connecting to the anode and cathode terminals near opposing corners of the layout. By implementing this type of metallization, a low capacitance, a uniform current density and / or a low on-state resistance is achieved. As shown in FIG. 3K, a current path through the gated diode has been shown.FIG. 4 is a top view of one embodiment of a layout for reverse protection diodes 190. The reverse protection diodes 190 are fabricated in the PSUB 111 and include P+ regions, N+ regions, metal gates 103, PW 114, NW 118, DNW 119, and a p-type guard ring 133.The reverse protection diodes 190 represent an embodiment of the reverse protection circuitry for an electrical interface according to the teachings herein. For example, the reverse protection diodes 190 may be used to implement the first reverse protection diode 13 and the second reverse protection diode 14 according to FIG. 2A. Although the reverse protection diodes 190 provide an example of suitable reverse protection circuitry for an electrical interface, other implementations of reverse protection circuitry in accordance with the teachings herein may also be used.The reverse protection diodes 190 include a pair of series-connected gated diodes present between P+ anode regions 121 and N+ cathode regions 122. The P+ anode regions 121 may be electrically connected to each other by metallization to form an anode terminal of a first gated diode. In addition, the N+ cathode regions 122 may be electrically connected to each other by metallization to form a cathode terminal of a second gated diode. In addition, metallization may be used to connect a cathode of the first gated diode to an anode of the second gated diode, thereby connecting the pair of gated diodes in series.Thus, the layout of FIG. 4 includes two series-connected gate controlled reverse protection diodes. In addition, the layout includes a plurality of portions that operate in parallel with each other and that are connected to each other using metallization. As will be understood by one of ordinary skill in the art, the layout of FIG. 4 further includes an SCR protection component.The guard ring 133 can be implemented in a variety of ways. For example, the guard ring 133 may include a PW 134 and a P+ region 135 formed therein. In certain embodiments, the P+ region 135 is electrically connected to ground.FIG. 5 is a schematic illustration of a power clamp 210 according to an embodiment. The power terminal 210 includes a detection circuit 201, a bias circuit 202, and a terminal 203 electrically connected in parallel between a first terminal 205 and a second terminal 206.Power clamp 210 represents an embodiment of a power clamp for a chip interface implemented in accordance with the teachings herein. The power terminal 210 represents, for example, an embodiment of the power terminal 9 of FIGS. 1A-1E and 13C and / or the power terminal 29 of FIG. 2A.An actively controlled power terminal is a type of power terminal that detects the presence of an electrical overload event by monitoring electrical conditions associated with an overload. By implementing a power clamp with active control, relatively fast activation times, a relatively low static dissipation, and / or a relatively compact area may be achieved compared to an implementation that relies on the native junction breakdown to provide clamping.The illustrated power clamp 210 is actively controlled. For example, the detection circuit 201 activates a detection signal in response to detecting the presence of an electrical overload event between the first terminal 205 and the second terminal 206. The detection circuit 201 may include, for example, a resistor-capacitor (RC) network that detects the presence of electrical overload based on monitoring a change in voltage difference between the first terminal 205 and the second terminal 206 over time.With continued reference to FIG. 5, the bias circuit 202 biases the terminal 203 to control the terminal 203 between a high impedance or off state and a low impedance or on state. In addition, the bias circuit 202 turns on the terminal 203 in response to the activation of the detection signal, thereby turning on the terminal 203 when electric overload is detected.FIG. 6 is a schematic illustration of a power clamp 300 according to another embodiment. The power terminal 300 includes a detection circuit 251, a bias circuit, and a terminal 253. The bias circuit includes a first bias circuit portion 252 aand a second bias circuit portion 252 b, collectively referred to as the bias circuit 252 a / 252 b. As shown in FIG. 6, the detection circuit 251, the bias circuit 252 a / 252 b, and the terminal 253 are electrically connected in parallel to each other between a first terminal 241 and a second terminal 242.Although an embodiment of an actively controlled power terminal is illustrated, the teachings herein are applicable to power terminals that may be implemented in a variety of ways. For example, an actively controlled power terminal may include a detection circuit, a bias circuit, and / or a terminal implemented in some other manner.In the illustrated embodiment, the detection circuit 251 includes a first capacitor 261, a second capacitor 262, a first diode-connected PFET 263, and a second diode-connected PFET 264. The first capacitor 261 may be bypassed with a metallization 265 and / or the metallization 265 may be omitted to electrically connect the first capacitor 261 and the second capacitor 262 in series. As shown in FIG. 6, the bodies of the first diode-connected PFET 263 and the second diode-connected PFET 264 are biased by a medium voltage (VMID) from the second bias circuit portion 252 bto extend the operating voltage range and / or to prevent parasitic body diodes from accidentally becoming active under certain bias conditions.The first bias circuit portion 252 aincludes a first bipolar transistor 271, a second bipolar transistor 272, a third bipolar transistor 273, a capacitor 274, a first resistor 275, and a second resistor 276. The second bias circuit part 252 bincludes a first diode-connected PFET 281, a second diode-connected PFET 282, a third diode-connected PFET 283, a fourth diode-connected PFET 284, a fifth diode-connected PFET 285, and a sixth diode-connected PFET 286.The clamp 253 includes a first clamp NFET 291 and a second clamp NFET 292 in this embodiment. The clamp NFET 291 and the second clamp 292 are connected in series to increase voltage handling capability and, in certain embodiments, have channel lengths greater than a minimum channel length (L min) for process technology, thereby reducing leakage current. In an embodiment, a channel length L 1 of the first clamp NFET 291 is greater than L min, and a channel length L 2 of the second clamp NFET 292 is greater than both L min and L 1. Thus, in this embodiment, L 2 > L 1 > L min. In another embodiment, at least one of L 2 or L 1 is greater than L min.In embodiments where the power terminal 300 is used to implement the power terminal 9 of FIGS. 1A-2A and / or 13C, the leakage current of the power terminal 300 may dominate the total leakage current of the contact pad 1. For example, during normal operation of the contact pad 1, a relatively small portion of the voltage of the contact pad over the isolation blocking voltage device(s) (e.g. isolation diode 3) is exhibited, while a relatively large portion of the voltage of the contact pad over the power terminal is exhibited.To aid in reducing leakage current of a power terminal, such as power terminal 300 of FIG. 6, the power terminal may be implemented with one or more leakage current reducing features.In a first example, the power clamp is implemented with stacked clamping devices (e.g., stacking the first clamping NFET 291 and the second clamping NFET 292).In a second example, the power clamp is implemented with one or more clamp FETs having transistor lengths greater than a smallest channel length allowed by the fabrication process. For example, with respect to the power clamp 300 of FIG. 6, the first clamp NFET 291 and / or the second clamp NFET 292 may be implemented with channel lengths greater than the minimum channel length. In one implementation, the first NFET 291 has a channel length in the range of 160 nm to 200 nm, e.g., 170 nm, and a width in the range of 600 μm to 800 μm, e.g., 750 μm (implemented with multiple parallel cells, e.g., 4). Also, in one implementation, the second NFET 292 has a channel length in the range of 200 nm to 500 nm, e.g., 350 nm, and a width in the range of 600 μm to 800 μm, e.g., 750 μm (implemented using multiple parallel cells, e.g., 4).In a third example, biasing circuitry used to bias a clamping device may be implemented to reduce leakage current. With respect to the power terminal 300 of FIG. 6, the second bias circuit part 252 bmay be implemented with channel lengths greater than the minimum channel length, for example. In one implementation, diode-connected PFETs 281-283 may have channel lengths in the range of 1.5 μm to 2.5 μm, for example 2 μm, and device widths in the range of 250 nm to 500 nm, for example 300 nm, while diode-connected PFETs 284-286 may have channel lengths in the range of 0.85 μm to 1.5 μm, for example 1 μm, and device widths in the range of 250 nm to 500 nm, for example 300 nm.In a fourth example, various capacitors of a power clamp may be implemented to provide coupling that may reduce the size (and thus leakage current) of active devices. For example, with respect to power terminal 300 of FIG. 6, in one implementation, capacitor 274 has a capacitance in the range of 400 fF to 500 fF, e.g., 450 fF, while capacitor 261 and capacitor 262 have capacitances in the range of 500 fF to 700 fF, e.g., 550 fF.In a fifth example, a detection resistor is implemented as a long channel length active transistor to reduce leakage current. For example, with respect to the power terminal 300 of FIG. 6, in one implementation, the diode-connected PFETs 263- 264 have channel lengths in the range of 1.5 μm to 2.5 μm, e.g., 2 μm, and widths in the range of 250 nm to 500 nm, e.g., 300 nm.In a sixth example, transistor areas of biasing devices used to amplify a detection signal are implemented with device areas selected to reduce leakage current. With respect to the power terminal 300 of FIG. 6, for example, in one implementation, the bipolar transistors 271- 273 are implemented with emitter areas in the range of 50 μm 2 to 300 μm 2 such as 100 μm 2.In a seventh example, resistors of a bias circuit with relatively high resistance are implemented to reduce leakage current. For example, with respect to power terminal 300 of FIG. 6, in one implementation, resistors 275-276 have a resistance of about 50 kilo-ohms or greater.FIG. 7 is a graph of an example of a 1 kV human body model (HBM) simulation over time for the power terminal 300 of FIG. 6. The simulation of the voltage as a function of time comprises a graph 1302 of the voltage of the first terminal 241.As shown in FIG. 7, in this example, the power terminal 300 limits the peak current to less than 650 mA and the peak voltage to less than 5.5 V.FIG. 8 is a diagram of an example of leakage current versus temperature for an implementation of the chip interface 50 of FIG. 2A operating with a signal pad input voltage of 3.6V.The diagram includes graphs for various simulation process corners, including fast N / fast P (FF) 1311, fast N / slow P (FS) 1312, nominal N / nominal P (TT) 1313, slow N / fast P 1314 (SF) 1314, and slow N / slow P (SS) 1315.FIG. 9 is a diagram of an example of parasitic capacitance versus temperature for an implementation of the chip interface of FIG. 2A.The diagram includes graphs for various simulation process corners including FF 1321, FS 1322, TT 1323, SF 1324, and SS 1325.Although FIGS. 7-9 show various examples of simulation results for a protection circuit, other simulation results are also possible, including results that depend on implementation, application, and / or processing technology.FIG. 10A is a top view of one embodiment of a layout for a protection circuit. The layout of FIG. 10A is implemented with a general positioning of the power clamping portion, the upper diode portion, and the lower diode portion, as discussed above with reference to layout 70 of FIG. 2B.The layout includes, for example, a low-leakage power clamping portion 1401 (corresponding to a layout of the power clamp 29), an upper diode portion 1402 (corresponding to a layout of the separation diode 3), and a lower diode portion 1403 (corresponding to a layout of the first reverse protection diode 13 and the second reverse protection diode 14). In this example, the layout has a footprint of about 96 μm by 131 μm.FIG. 10B is a top view of another embodiment of a layout for a protection circuit. The layout of FIG. 10B is similar to the layout of FIG. 10A, except that the upper metal layers of the layout are illustrated in FIG. 10B and the lower metal layers and doped semiconductor regions are omitted.Bidirectional Protection Circuit with Forward Protection and Reverse Protection SCRFIG. 11 is a schematic illustration of a bidirectional protection circuit 305 according to an embodiment. The bidirectional protection circuit 305 includes a forward protection SCR 301 and a reverse protection SCR 302. An SCR is also referred to as a thyristor. In the illustrated embodiment, the bidirectional protection circuit 305 is electrically connected between a first pad 303 (i.e., power-low or VSS in this example) and a second pad 304 (i.e., power-low or VSS in this example).As shown in FIG. 11, the forward protection SCR 301 includes an anode electrically connected to the first contact surface 303 and a cathode electrically connected to the second contact surface 304. Additionally, the reverse protection SCR 302 includes an anode electrically connected to the second contact surface 304 and a cathode electrically connected to the first contact surface 303. Thus, the forward protection SCR 301 and the reverse protection SCR 302 are electrically connected in antiparallel with each other.The forward protection SCR 301 becomes active to provide protection against positive polarity electrical overload that causes the voltage of the first contact pad 303 to increase relative to the voltage of the second contact pad 304. The forward protection SCR 301 has a forward trigger voltage and a forward hold voltage that controls a forward protection characteristic of the bidirectional protection circuit 305.With continued reference to FIG. 11, the reverse protection SCR 302 becomes active to provide protection from negative polarity electrical overload that causes the voltage of the first contact pad 303 to decrease relative to the voltage of the second contact pad 304. The reverse protection SCR 302 has a reverse trigger voltage and a reverse hold voltage that controls a reverse protection characteristic of the bidirectional protection circuit 305.In certain implementations herein, the forward protection SCR 301 and the reverse protection SCR 302 are implemented in a common layout with a common guard ring to improve integration.FIG. 12 is a cross-section of a forward protection SCR 350, according to an example embodiment. The forward protection SCR 350 represents an embodiment of the forward protection SCR 301 of FIG. 11.Referring now to FIG. 12, a cross-section of the forward protection SCR 350 is shown. In the top plan view, the forward guard SCR 350 may have a layout realized in a wide variety of ways, e.g., a planar layout configuration or an annular configuration.In the illustrated embodiment, the forward protection SCR 350 is formed directly in the PSUB 306. However, the teachings herein are also applicable to other configurations, such as implementations in which a substrate includes a p-type epitaxial layer over a doped or undoped carrier substrate and the forward protection SCR 350 is fabricated in the p-type epitaxial layer. Although not shown in FIG. 12, the PSUB 306 typically includes other devices or structures formed therein. For example, a forward protection SCR, a reverse protection SCR, and an internal circuit protected by the SCR may be fabricated in a common substrate.The forward protection SCR 350 includes various NW and PW regions, such as NW 313, PW 314, and PW guard ring 318. Additionally, various N+ regions and P+ regions are illustrated, such as anode P+ regions 312 / 322, cathode N+ region 315, auxiliary N+ input / output (IO_aux) regions 316 / 326, first ring P+ region 317, and second ring P+ region 319. The P+ regions have a higher doping concentration than the PW, which in turn have a higher doping concentration than the p-type substrate. In addition, the N+ regions have a higher doping concentration than the NW. Those of ordinary skill in the art will understand various dopant concentrations in the ranges.The forward protection SCR 350 also includes additional structures including field plates or gates, such as metal gates 311 / 321. Additionally, isolation regions 310 (e.g., shallow trench isolation regions) are shown. The isolation regions 310 may be formed in various ways, e.g., by etching trenches into the p-type substrate, filling the trenches with a dielectric, e.g., silicon dioxide (SiO 2), and removing the excess dielectric by any suitable method, e.g., chemical mechanical planarization.It should be understood that since regions within a semiconductor device are defined by doping different portions of a semiconductor material with different impurities or different concentrations of impurities, discrete physical boundaries between different regions may not actually exist in the completed device, but the regions may instead merge with one another. Some boundaries as depicted in the figures of this type are depicted as abrupt structures merely to aid the reader. As will be understood by those of ordinary skill in the art, p-type regions may include a p-type semiconductor material, such as boron, as a dopant. In addition, n-type regions may include an n-type semiconductor material such as phosphorus as a dopant.Although electrical connections are schematically represented by lines, one of ordinary skill in the art will understand that the discussed electrical connections may be partially made by metallization via back-end processing. Additionally, in certain implementations, bond pads or other structures may be included that may correspond to particular nodes, including, but not limited to, signal input / output (IO), power-low or VSS, substrate VSS, and / or IO_aux. Such details are omitted for the sake of clarity of the figures.The forward protection SCR 350 has been schematically illustrated to show certain electrical connections and devices, including a PNP bipolar transistor 341, an NPN bipolar transistor 342, and a gated diode 343. Although certain devices have been discussed in the left half of the forward protection SCR 350, it will be understood by those of ordinary skill in the art that the right half may include similar devices that operate in combination with those on the left half to achieve the overall operating characteristics of the forward protection SCR 350.The PNP bipolar transistor 341 includes an emitter associated with the P+ region 312, a base associated with the NW 313, and a collector associated with the PW 314. In addition, NPN bipolar transistor 342 includes an emitter associated with N+ region 315, a base associated with PW 314, and a collector associated with NW 313 and N+ region 316. In addition, the gated diode 343 includes an anode associated with the P+ region 312 and a cathode associated with the NW 313 and the N+ region 316. As shown in FIG. 12, a metal gate 311 is formed over the NW 313 between the P+ region 312 and the N+ region 316.In certain implementations, the P+ region 317 is embodied as a ring that is connected to a voltage for power-low via metallization. In addition, a second ring (PW 318 / P+ region 319) may be used for Kelvin connection. In the illustrated embodiment, the P+ region 317 is formed in a native (NTN) region.In certain implementations, a substrate may be connected to a separate contact surface to improve separation and / or reduce the risk of snap-in. In certain implementations, a VSS pad and a SUB pad are connected to the same electrical potential by off-chip metallization.In an embodiment, a distance or distance D 1 between the N+ region 315 and the P+ region 322 is selected to be in the range of about 0.2 μm and about 2 μm.FIG. 13A is a cross-section of a reverse protection SCR 450, according to an example embodiment. The reverse protection SCR 450 illustrates an embodiment of the reverse protection SCR 302 of FIG. 11.The reverse protection SCR 450 is formed in the PSUB 306. The reverse protection SCR 450 includes various NW and PW regions, such as the first PW 412, the second PW 414, the third PW 474, the first NW 413, the second NW 422, the deep NW (DNW) 423, and the PW guard ring 466. Additionally, various N+ regions and P+ regions are illustrated, e.g., P+ anode regions 411 / 471, N+ cathode region 416 / 476, N+ diode cathode region 417, P+ diode anode regions 415 / 475, first P+ ring region 421, and second P+ ring region 467. The reverse protection SCR 450 also includes gate regions 418 / 419 / 420 / 478 / 479 / 480.The reverse protection SCR 450 has been schematically illustrated to show certain electrical connections and devices, including a PNP bipolar transistor 441, an NPN bipolar transistor 442, a first gated diode 443, a second gated diode 444, a first resistor 445, a second resistor 446, and a diode 447. Those of ordinary skill in the art will understand that the left and right halves of the reverse protection SCR 450 may comprise similar devices.The PNP bipolar transistor 441 includes an emitter associated with the P+ region 411 and the PW 412, a base associated with the NW 413, and a collector associated with the PW 414 and the P+ region 415. In addition, NPN bipolar transistor 442 includes an emitter associated with N+ region 416, a base associated with PW 414 and P+ region 415, and a collector associated with NW 413. In addition, the first gated diode 443 includes an anode associated with the P+ region 411 and the PW 412, a cathode associated with the N+ region 417, and a metal gate 418. Additionally, the second gated diode 444 includes an anode associated with the P+ region 415 and the PW 414, a cathode associated with the N+ region 416, and a metal gate 419. Diode 447 also includes an anode associated with P+ region 421 and a cathode associated with NW 422 and deep NW 423. The first resistor 445 corresponds to a resistance of the PW 414, and the second resistor 446 corresponds to a resistance of the NW 422 and low NW 423.In the illustrated exemplary embodiment, the reverse protection SCR 450 includes the metal gate 420 that extends across a boundary between the PW 414 and the NW 413 and across a boundary between the NW 413 and the PW 412.The reverse protection SCR 450 includes a gated diode-induced SCR line and thus operates with improved performance characteristics, such as a faster turn-on speed.In an embodiment, the P+ region 421 is electrically connected to a power-high supply voltage, e.g., to a VDD pad. However, other implementations are also possible, e.g., implementations in which the P+ region 421 is electrically connected to an IO pad or is electrically floating.In certain implementations, the N+ regions 416 / 476 are electrically connected to an IO pad (e.g., the aio pad 303 in FIG. 11 ), and the P+ regions 411 / 471 are electrically connected to one or more power-low pads (e.g., the VSS pad 304 in FIG. 11 ).FIG. 13B is a circuit diagram of a portion of the reverse protection SCR 450 of FIG. 13A. As shown in FIG. 13B, the circuit diagram includes the PNP bipolar transistor 441, the NPN bipolar transistor 442, the first gated diode 443, the second gated diode 444, the first resistor 445, the second resistor 446, and the diode 447.The first gated diode 443 helps provide a diode-induced SCR line by injecting current into a base of the NPN bipolar transistor 442 in response to an electrical overload that reduces the voltage of the IO pad low relative to the voltage of the power pad.In certain embodiments, a bidirectional protection circuit includes a forward protection SCR implemented according to one or more features of FIGS. 12 and / or a reverse protection SCR implemented according to one or more features of FIGS. 13A-13B. Implementing the bidirectional protection circuit in this manner may provide a number of advantages.In one example, such an example embodiment may serve as a low-triggering ESD ground reference protection terminal for low-capacitance, low leakage current, and / or high voltage tolerance operation for signal pads (IO) operating at, for example, a rated signaling of up to about 3.5V. Such a terminal may serve, for example, as a high voltage tolerant cell of more than 1.8V and less than 6V. In addition, the clamp includes a pair of SCRs that operate in parallel and may be modeled as a single component. Such embodiments may include, for example, gate controlled diodes with field plates implemented with metal transistor gates. Such terminals may be fabricated in a variety of manufacturing technologies, including processes with small transistor geometries, such as 28 nm processes.FIG. 13C is a schematic illustration of a chip interface 455 according to an example embodiment. The chip interface 455 of FIG. 13C is similar to the chip interface 10 of FIG. 1A, except that the chip interface 455 omits the isolation diode 3 in favor of a first isolation thyristor 450 aand a second isolation thyristor 450 b.As shown in FIG. 13C, the first separation thyristor 450 aincludes an anode electrically connected to the contact pad 1 and a cathode electrically connected to the separated node 11. In addition, the second separation thyristor 450 bis electrically connected in antiparallel to the first separation thyristor 450 aand includes an anode electrically connected to the separated node 11 and a cathode electrically connected to the contact pad 1.In some implementations, the power terminal 9 may be configured to provide the capability of reverse conduction incorporated as part of the power terminal configuration, e.g., by forming a dedicated p-n junction as a ring surrounding the power terminal and being correspondingly connected (e.g., to serve as a reverse protection p-n junction diode). However, this can result in a large scale device and increase capacitance and leakage to a level that may not be suitable for some high speed interface applications. Additionally or alternatively, according to the teachings of FIGS. 1D and 1E, the power supply terminal may be configured to have a separate low-capacitance diode (e.g., a p-n junction diode optimized for a given low-capacitance current handling capability) formed in parallel with the reverse current line supply terminal not shown in this figure. This reverse conducting device can be connected in parallel with the supply terminal. In an embodiment, the reverse conducting diode is implemented according to the example embodiments of FIG. 3C and / or FIG. 3D.The teachings herein are applicable to a variety of types of isolation blocking voltage devices, including isolation diodes and / or isolation thyristors. For example, any of the embodiments described herein (e.g., any of the chip interfaces of FIGS. 1A to 2A ) may be implemented using one or more isolation diodes, one or more isolation thyristors, or any suitable combination thereof.In an embodiment, the first isolation thyristor 450 aand / or the second isolation thyristor 450 bare implemented using the embodiment of FIGS. 13A and 13B. In such an embodiment, the connections of FIGS. 13A and 13B depicted to the IO pad may be connected to the pad 1 of FIG. 13C, while the connections of FIGS. 13A and 13B depicted to power-low may instead be connected to the separate node 11 of FIG. 13C. In this configuration, the two terminals of the embodiment in FIGS. 13A and 13B are arranged anti-parallel. The inherent connection of the anode of the DNW diode 447 in each anti-parallel thyristor embodiment (not shown in the figure) may be configured floating.FIG. 14A is a top view of an example embodiment of a bidirectional protection circuit layout 510. Layout 510 illustrates one embodiment of a layout for bidirectional protection circuit 305 of FIG. 11.The layout 510 includes a first portion 501 corresponding to a layout of the forward protection SCR, a second portion 502 corresponding to a layout of the reverse protection SCR, and a guard ring 503. In certain implementations, the layouts of the forward protection SCR and the reverse protection SCR are implemented such that currents flowing through the forward protection SCR are substantially orthogonal to currents flowing through the reverse protection SCR.Thus, the reverse protection current may flow substantially in one direction (e.g., along an x-axis), while the forward protection current may flow substantially in another direction (e.g., along a y-axis). In one example, the metals that conduct current through the first portion 501 are orthogonal to metals that conduct current through the second portion 502. In another example, the layouts of the metal gates in the first portion 501 and the metal gates in the second portion 502 are orthogonal to each other.FIG. 14B is a top view of an example embodiment of a layout 511 of a forward protection SCR. Layout 511 of FIG. 14B illustrates an embodiment of the top view of forward protection circuit 350 of FIG. 12. In one embodiment, layout 511 is included in first portion 501 of the bidirectional protection circuit of FIG. 14A.FIG. 14C is a top view of another example embodiment of a reverse protection SCR layout 512. Layout 512 of FIG. 14C illustrates an embodiment of the top view of reverse protection circuit 450 of FIG. 13A. In one embodiment, layout 512 is included in second portion 502 of the bidirectional protection circuit of FIG. 14A.FIG. 15A is a plot of current versus voltage for various temperatures for an implementation of the bidirectional protection circuit 305 of FIG. 11 ; the plot corresponds to an example of a DC characteristic of a 2.5 V-SCR cell over temperature.FIG. 15B is a plot of TLP characteristics of current versus voltage for an implementation of the bidirectional protection circuit of FIG. 11 ; the plot corresponds to an example of TLP characteristics of a 2.5 V-SCR cell.FIG. 15C is a graph of capacitance versus frequency characteristics for an implementation of the bidirectional protection circuit of FIG. 11 corresponding to an example of C-V characteristics versus frequency of a 2.5 V-SCR cell. The diagram includes graphs for different DC bias voltages across the bidirectional protection circuit.FIG. 15D is a plot of TLP characteristics of voltage versus time for implementation of the bidirectional protection circuit 305 of FIG. 11 The plot corresponds to an example of VFTLP characteristics of a 2.5 V-SCR cell at 1 A.Although FIGS. 15A-15D show an example of simulation results for a bidirectional protection circuit, other simulation results are also possible, including results that depend on implementation, application, and / or processing technology.Applications Using ApplicationsDevices using the schemes described above may be implemented in various electronic systems. Examples of the electronic systems may include, but are not limited to, consumer electronics products, portions of the consumer electronics products, electronic test equipment, communication infrastructure applications, etc. Furthermore, the electronic systems may include unfinished products including those for communication, industrial, medical and automotive applications.A FaziteThe foregoing description may refer to elements or features that are "connected" or "coupled" together. Unless expressly stated otherwise, "connected" means that one element / feature is directly or indirectly connected to another element / feature, not necessarily mechanically. Similarly, unless expressly stated otherwise, "coupled" means that one element / feature is directly or indirectly coupled to another element / feature, not necessarily mechanically. Thus, while the various schemes shown in the figures depict example arrangements of elements and components, in an actual embodiment, additional intervening elements, devices, features, or components may be present (provided that the functionality of the depicted circuits is not adversely affected).Although the claims set forth herein are presented in a single dependency format for filing on the USPTO, it should be understood that any claim may depend on any preceding claim of the same type, unless clearly not technically feasible.

Claims

A semiconductor die with low leakage current electrical overload protection and high voltage tolerance, the semiconductor die comprising: a signal pad (1); an internal circuit (2) electrically connected to the signal pad (1); a power terminal (9) electrically connected between a separate node (11) and a reference node; and one or more isolation blocking voltage devices (3; 4) electrically connected between the signal pad (1) and the separate node (11), wherein the one or more isolation blocking voltage devices (3; 4) are operative to isolate the signal pad (1) from a capacitance of the power terminal (9); a first reverse protection diode (6) connected in parallel to the power terminal (9) and having an anode connected to the reference node and a cathode connected to the separate node (11); and a second reverse protection diode (7) whose anode is connected to the separate node (11) and whose cathode is connected to the signal contact pad (1).The semiconductor die of claim 1, wherein the one or more isolation blocking voltage devices (3; 4) comprise at least one gate controlled diode.The semiconductor die of claim 2, wherein the at least one gate controlled diode comprises a semiconductor region, a p-type (P+) anode active region formed in the semiconductor region, an n-type (N+) cathode active region formed in the semiconductor region, and a metal gate over the semiconductor region between the P+ anode region and the N+ cathode region.The semiconductor die of claim 2, wherein the at least one gated diode comprises an n-type well, a P+ anode region formed in the n-type well, an N+ cathode region formed in the n-type well, a metal gate over the n-type well between the P+ anode region and the N+ cathode region, and a P+ ring surrounding a perimeter of the n-type well.The semiconductor die according to any one of the preceding claims 1 to 4, wherein the one or more cut-off blocking voltage devices (3; 4) comprise at least two cut-off diodes in series.The semiconductor die according to any one of the preceding claims 1 to 4, wherein the power terminal (9) is actively controlled.The semiconductor die of claim 6, wherein the power terminal (9; 210) comprises a detection circuit (201), a bias circuit (202), and a terminal (203), wherein the detection circuit (201) activates a detection signal in response to detecting an electrical overload event at the disconnected node, and wherein the bias circuit (202) switches on the terminal (203) in response to activating the detection signal.The semiconductor die of any of the preceding claims 1 to 4, wherein the signal pad is a consumer electronics control (CEC) pad of a high definition multimedia interface (HDMI) interface.The semiconductor die according to any one of the preceding claims 1 to 4, wherein the power terminal (9; 210) includes a first terminal field effect transistor (FET) and a second terminal field effect transistor (FET) connected in series between the disconnected node (11) and the reference node.An electrical interface (50) for a semiconductor chip, the electrical interface (50) comprising: a signal pad (1); an internal circuit (2) electrically connected to the signal pad (1); a power terminal (9) electrically connected to a separate node (11) and a reference node; and means for separating the signal pad (1) from a capacitance of the power terminal (9), wherein the means for separating is electrically connected between the signal pad (1) and the separate node (11); a first reverse protection diode (6) connected in parallel to the power terminal (9) and having an anode connected to the reference node and a cathode connected to the separate node (11); and a second reverse protection diode (7) having an anode connected to the separate node (11) and a cathode connected to the signal pad (1).The electrical interface of claim 10, wherein the signal pad is a consumer electronics control (CEC) pad of a high definition multimedia interface (HDMI) interface.A method of providing low capacitance, low leakage current electrical overload protection, the method comprising: receiving an electrical overload event at a signal pad (1) of a semiconductor die; discharging the electrical overload event using a power terminal (9) electrically connected between a separate node (11) and a reference node; and separating the signal pad (1) from a capacitance of the power terminal (9) using at least one reverse bias device disposed between the signal pad (1) and the separate node (11); and providing a bypass path for the power terminal (9) using a first reverse protection diode (6) and a second reverse protection diode (7), wherein the first reverse protection diode (6) is connected in parallel with the power terminal (9) and has an anode coupled to the reference node (11) and a cathode coupled to the separated node (11), and wherein the second reverse protection diode (7) has an anode coupled to the separated node (11) and a cathode coupled to the signal contact surface (1).The method of claim 12, wherein disconnecting the signal pad (1) from the capacitance of the power terminal comprises providing disconnection using at least one gated diode.The method of any of claims 12 or 13, further comprising protecting a signal using a reverse protection circuit comprising two or more gate controlled diodes (7, 8) in series than the second reverse protection diode.

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