Dynamic switching between memory copy and memory image data transfer technology to improve I / O performance

Abstract

Method (500) for dynamically switching between a memory copy and a memory image data transmission technique to improve I / O performance, the method (500) comprising: receiving (502) an I / O request; calculating (504) the cost of executing the I / O request using a memory copy data transmission technique, wherein the memory copy data transmission technique copies cache segments (300) associated with the I / O request from the cache memory (216) into a permanently mapped memory (400), wherein the permanently mapped memory (400) is permanently mapped to a bus address window (304); calculating (506) the cost of executing the I / O request using a memory image data transmission technique, wherein the memory image data transmission technique temporarily copies cache segments (300) associated with the I / O request from the Cache memory (216) maps to the bus address window (304);Use (510) the memory copy data transfer technique to transfer cache segments (300) belonging to the I / O request if using the memory copy data transfer technique is less costly than using the memory image data transfer technique; and use (512) the memory image data transfer technique to transfer cache segments (300) belonging to the I / O request if using the memory image data transfer technique is less costly than using the memory copy data transfer technique.;

Description

FIELD OF THE INVENTIONThis invention relates to systems and methods for dynamically switching between a storage copy data transfer (memory copy) technique and a storage image data transfer (memory mapping) technique to improve I / O performance in storage systems, and to a corresponding computer program and computer program product.BACKGROUND OF THE INVENTIONA PCI Peripheral Component Interconnect (PCI) north bridge may enable data transfer between a processor and an input / output (I / O) subsystem within a data processing system. The PCI north bridge provides data buffering functions to allow data to be transferred between the processor and the I / O subsystem for read and write operations. The I / O subsystem may be a group of PCI devices coupled to a PCI bus. When a PCI device on the PCI bus causes a read or write operation from or to a system memory via a direct memory access (DMA), the PCI north bridge translates a PCI address of the DMA into a system memory address of the system memory.Each PCI device on the PCI bus may be associated with a corresponding translation control entry (TCE) table in system memory. The TCE table may be used to perform TCE translations from PCI addresses to system memory addresses. In response to a DMA read or write operation, a corresponding TCE table is read from the PCI northbridge to provide a TCE translation.In memory systems such as the IBM ® DS8000™ enterprise memory system, it is required that a cache of the memory system be mapped one or more times each I / O operation processed by the memory system. For example, a read access to the cache requires creating a TCE image in order for a host adapter to read the cache via a DMA. This TCE image is then deleted again after the execution of the DMA. In the event of a read error, two TCE images are required: one image between the cache memory and a device adapter to fetch the read data from storage drives, and a second image between the cache memory and a host adapter to return the read data to a host system. After the DMAs are executed, the TCE images can be de-imaged. IBM and DS / 8000 are trademarks of the International Business Machines Corporation, registered in many jurisdictions worldwide.In view of the above, alternative techniques for data transfer are needed to transfer data within storage systems such as the IBM DS8000™ enterprise storage system. Moreover, systems and methods are needed to dynamically transition between different techniques for data transfer to optimize I / O performance in storage systems such as the IBM DS8000™ enterprise storage system.Accordingly, there is a need in the art to solve the above problem.U.S. Pat. No. 8,966,133 B2 describes methods, computer-readable storage media and a computer system for determining a mapping mode for a DMA data transmission. The method may include receiving a request for a DMA data transfer within a computer system. The method may also include determining a mapping mode for the DMA data transfer based on available system profile data in response to receiving the request. The method may also include mapping the memory using the determined mapping mode.US 2018 / 0 081 568 A1 describes a method and system for implementing fast full synchronization for remote disk mirroring in a computer system. A source backup copy is made locally available to a target for remote disk mirroring. The sectors are identified that differ between the source and the target. A hash function is used for a block to be compared, wherein the number of sectors to be tracked per block can be adapted from a minimum block size.SUMMARYViewed from a first aspect, the present invention provides a method of dynamically switching between a storage copy and a storage map data transfer technique to improve I / O performance, the method comprising: receiving an I / O request; calculating a cost of executing the I / O request using a storage copy data transfer technique, the storage copy data transfer technique copying cache segments associated with the I / O request from the cache memory to a permanently mapped memory, the permanently mapped memory permanently mapped to a bus address window; calculating a cost of executing the I / O request using a memory map data transfer technique, the memory map data transfer technique temporarily mapping cache segments associated with the I / O request from the cache memory to the bus address window; using the memory copy data transfer technique to transfer cache segments associated with the I / O request if using the memory copy data transfer technique is less costly than using the memory map data transfer technique; and using the memory map data transfer technique to transfer cache segments associated with the I / O request if using the memory map data transfer technique is less costly than using the memory copy data transfer technique.Viewed from another aspect, the present invention provides a system for dynamically switching between a hard copy and a memory map data transfer technique to improve I / O performance, the system comprising: at least one processor; at least one memory unit coupled to the at least one processor and storing instructions for execution on the at least one processor, the instructions causing the at least one processor to: receive an I / O request; calculating a cost of executing the I / O request using a memory copy communication technique, the memory copy communication technique copying cache segments associated with the I / O request from the cache memory to a permanently mapped memory, the permanently mapped memory permanently mapped to a bus address window; calculating a cost of executing the I / O request using a memory map communication technique, the memory map communication technique temporarily mapping cache segments associated with the I / O request from the cache memory to the bus address window; Using the memory copy data transfer technique to transfer cache segments associated with the I / O request if using the memory copy data transfer technique is less costly than using the memory map data transfer technique; and using the memory map data transfer technique to transfer cache segments associated with the I / O request if using the memory map data transfer technique is less costly than using the memory copy data transfer technique.Viewed from a further aspect, the present invention provides a computer program product for dynamically switching between hard copy and mapped data transmission techniques to improve I / O performance, the computer program product comprising: a computer readable storage medium readable by processing circuitry and storing instructions for execution by the processing circuitry to perform a method of performing the steps of the invention.Viewed from a further aspect, the present invention provides a computer program stored on a computer readable medium and loadable into the internal memory of a digital computer, comprising software code portions, when said program is executed on a computer, for performing the steps of the invention.Viewed from a further aspect, the present invention provides a computer program product for dynamically transitioning between hard copy and mapped data transmission techniques to improve I / O performance, the computer program product comprising: a computer readable medium having computer usable program code embodied therein, the computer usable program code configured to, when executed by at least one processor: receive an I / O request; calculating a cost of executing the I / O request using a memory copy communication technique, the memory copy communication technique copying cache segments associated with the I / O request from the cache memory to a permanently mapped memory, the permanently mapped memory permanently mapped to a bus address window; calculating a cost of executing the I / O request using a memory map communication technique, the memory map communication technique temporarily mapping cache segments associated with the I / O request from the cache memory to the bus address window; Using the memory copy data transfer technique to transfer cache segments associated with the I / O request if using the memory copy data transfer technique is less costly than using the memory map data transfer technique; and using the memory map data transfer technique to transfer cache segments associated with the I / O request if using the memory map data transfer technique is less costly than using the memory copy data transfer technique.The invention has been developed in response to the present state of the art, and more particularly, in response to the problems and needs of the art that have not yet been fully solved by the presently available systems and methods. Accordingly, embodiments of the invention have been developed to dynamically switch between hard copy and memory map communications techniques to improve I / O performance. The functions and advantages of the invention will become more apparent from the following description and the appended claims, or may be learned by practice of the invention as set forth below.In accordance with the foregoing, a method is disclosed that dynamically switches between a hard copy and a memory map data transfer technique to improve I / O performance. In the method, an I / O request is received and a cost for executing the I / O request is calculated using a storage copy data transfer technique. In the memory copy data transfer technique, cache segments associated with the I / O request are copied from the cache memory into a permanently mapped memory that is permanently mapped to a bus address window. In the method, cost for executing the I / O request is further calculated using a memory image data transfer technique. In the map data transfer technique, cache segments associated with the I / O request are temporarily mapped from the cache to the bus address window. In the method, either the copy memory data transfer technique or the map data transfer technique is used to transfer the cache segments associated with the I / O request, depending on which technique is less costly.A corresponding system and computer program product are further disclosed and claimed herein.BRIEF DESCRIPTION OF THE DRAWINGSFor a better understanding of the advantages of the invention, a more detailed description of the invention briefly described above will be given by referring to specific embodiments shown in the accompanying drawings. In understanding that these drawings illustrate only typical embodiments of the invention and are therefore not to be considered as limiting the scope of the invention, the invention will be described and explained with additional accuracy and detail using the accompanying drawings, in which: FIG. 1 is a high-level block diagram illustrating an example of a networking environment in which systems and methods according to the invention may be implemented; FIG. 2 is a high-level block diagram illustrating one embodiment of a storage system that may be used in the networking environment of FIG. 1 ; FIG. 3 is a high-level block diagram illustrating an example of a memory map data transfer technique; FIG. 4 is a high-level block diagram illustrating an example of a hard copy data transfer technique; FIG. 5 shows a flow chart illustrating one embodiment of a method for determining which data transfer technique to use for a particular I / O request; FIG. 6 is a high-level block diagram illustrating "image" windows associated with use with a storage image communications technique and "copy" windows associated with use with a storage copy communications technique; FIG. 7 shows a high-level block diagram illustrating dynamically adjusting a number of "image" windows and a number of "copy" windows to increase efficiency in processing I / O requests; FIG. 8 is a flow chart illustrating one embodiment of a method for optimizing a number of "image" windows used in connection with a storage image communication technique and a number of "copy" windows used in connection with a storage copy communication technique; FIG. 9 is a flow chart illustrating another embodiment of a method for optimizing a number of "image" windows used in connection with a storage image communication technique and a number of "copy" windows used in connection with a storage copy communication technique; and FIG. 10 is a flow chart illustrating one embodiment of a method for determining whether to use a memory map data transfer technique or a hard copy data transfer technique to process an I / O request.DETAILED DESCRIPTIONIt will be understood that the components of the present invention, as generally described and shown in the figures herein, may be arranged and designed in a wide variety of different configurations. The following more detailed description of the embodiments of the invention as illustrated in the figures is therefore not intended to limit the scope of the invention as claimed, but is merely representative of specific examples of presently contemplated embodiments according to the invention. The embodiments described herein may best be understood with reference to the drawings, wherein like parts are designated by like numerals throughout.The present invention may be embodied as a system, method, and / or computer program product. The computer program product may comprise computer readable storage medium(s) on / on which computer readable program instructions are / are stored for causing a processor to carry out aspects of the present invention.The computer readable storage medium may be a physical device that can retain and store instructions for use by a system for executing instructions. The computer readable storage medium may be, for example, but is not limited to, an electronic storage system, a magnetic storage system, an optical storage system, an electromagnetic storage system, a semiconductor storage system, or any suitable combination thereof. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions stored thereon, and any suitable combination thereof. A computer readable storage medium, as used herein, is not intended to be transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through an optical fiber cable), or electrical signals transmitted through a wire.Computer readable program instructions described herein may be downloaded from a computer readable storage medium to respective data processing / processing units or via a network such as the Internet, a local area network, a wide area network, and / or a wireless network to an external computer or storage system. The network may include copper transmission cables, lightwave transmission conductors, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing unit receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the corresponding computing / processing unit.Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including object oriented programming languages such as Smalltalk, C++, or the like, as well as conventional procedural programming languages, such as the "C" programming language or similar programming languages.The computer readable program instructions may execute entirely on a user's computer, partly on a user's computer, as a stand-alone software package, partly on a user's computer and partly on a remote computer or entirely on a remote computer or server. In the latter case, a remote computer may be connected to a user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, via the Internet using an Internet Service Provider). In some embodiments, electronic circuits, including, for example, programmable logic circuits, field programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuits to perform aspects of the present invention.Aspects of the present invention may be described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It is to be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, may be executed using computer readable program instructions.These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, executed via the processor of the computer or other programmable data processing apparatus, produce a means for implementing the functions / steps specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions may also be stored on a computer readable storage medium that can control a computer, programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored thereon comprises an article of manufacture including instructions that implement aspects of the function / step specified in the flowchart and / or block diagram block or blocks.The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of process steps to be performed on the computer or other programmable apparatus or device to produce a computer executed process, such that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / steps specified in the flowchart and / or block diagram block or blocks.Referring to FIG. 1, an example of a network environment 100 is shown. Network environment 100 is shown to illustrate an example of an environment in which systems and methods according to the invention may be implemented. The network environment 100 is shown to name an example and is not limited thereto. Rather, the systems and methods disclosed herein can be applied to a wide variety of other network environments in addition to the illustrated network environment 100.As shown, the network environment 100 includes one or more computers 102, 106 interconnected via a network 104. The network 104 may include, for example, a local area network (LAN) 104, a wide area network (WAN) 104, the Internet 104, an intranet 104, or the like. In certain embodiments, the computers 102, 106 may include both client computers 102 and server computers 106 (also referred to herein as "hosts" 106 or "host systems" 106). In general, the client computers 102 initiate communication sessions while the server computers 106 are waiting for and responding to requests from the client computers 102. In certain embodiments, the computers 102 and / or servers 106 may be connected to one or more internal or external direct-connected storage systems 112 (e.g., arrays of hard disk drives, solid state data carriers, tape drives, etc.). These computers 102, 106 and direct-coupled storage systems 112 may communicate using protocols such as ATA, SATA, SCSI, SAS, Fibre Channel, or the like.The network environment 100, in certain embodiments, may include a storage network 108 behind the servers 106, for example, a storage area network (SAN) 108 or a LAN 108 (e.g., when network-connected storage is deployed). This network 108 may connect the servers 106 to one or more storage systems 110, for example, arrays 110 aof hard disk drives or semiconductor disks, tape libraries 110 b, single hard disk drives 110 cor semiconductor disks 110 c, tape drives 110 d, CD-ROM libraries, or the like. To access a storage system 110, a host system 106 may communicate, via physical connections, from one or more ports of the host 106 to one or more ports of the storage system 110. A connection can be made via a switching unit, a fabric (fabric), a direct connection or the like. In certain embodiments, the servers 106 and storage systems 110 may exchange data using a network standard such as Fibre Channel (FC) or iSC.Referring to FIG. 2, an example of a storage system 110 ais shown that includes an array of hard disk drives 204 and / or semiconductor media 204. The internal components of the storage system 110a are illustrated as systems and methods according to the invention may be implemented within such a storage system 110a. As shown, storage system 110 aincludes a storage controller 200, one or more switching units 202, and one or more storage drives 204, for example, hard disk drives 204 and / or solid state storage media 204 (e.g., flash memory-based storage media 204). The memory controller 200 may enable one or more host systems 106 (e.g., open system and / or mainframe servers 106 executing operating systems such as z / OS ®, z / VM ® or the like) to access data in the one or more storage drives 204. z / OS and z / VM** are trademarks of International Business Machines Corporation, which are registered in many jurisdictions worldwide.In selected embodiments, the memory controller 200 includes one or more servers 206 a, 206 b. The storage controller 200 may also include host adapters 208 and device adapters 210 to connect the storage controller 200 to the host systems 106 and the storage drives 204, respectively. Multiple servers 206 a, 206 bmay provide redundancy to ensure that data is always available to the connected host systems 106. Thus, upon failure of one server 206 a, the other server 206 bmay take over the I / O load of the failed server 206 ato ensure that I / O continues to be possible between the host systems 106 and the storage drives 204. This process can be referred to as "failover" (switching on failure).In selected embodiments, each server 206 includes one or more processors 212 and memory 214. The memory 214 may include both volatile memory (e.g., RAM) and nonvolatile memory (e.g., ROM, EPROM, EEPROM, hard drives, flash memory, etc.). The volatile and nonvolatile memories, in certain embodiments, may store software modules executing on the processor(s) 212 that access data in the storage drives 204. These software modules may manage all write and read requests from / to logical volume(s) in the storage drives 204.In certain embodiments, the memory 214 includes a cache 216, for example, a DRAM cache 216. When a host 106 (e.g., an open system or mainframe server) performs a read operation for data that is not in cache 216, the server 206 performing the read operation may retrieve data from the storage drives 204 and store it in its cache 216 in the event they are needed again. If the data is requested again by a host system 106, the server 206 may retrieve the data from the cache 216 rather than retrieving it from the storage drives 204, which saves both time and resources. Accordingly, when a host system 106 performs a write operation, the server 206 receiving the write request may store the modified data in its cache 216 and offload the modified data to the storage drives 204 at a later time.An example of a storage system 110a having an architecture similar to that shown in FIG. 2 is the IBM DS8000™ enterprise storage system. DS8000™ is a high performance, high capacity memory controller that provides hard disk and semiconductor memory and is designed for continuous operation. However, the techniques disclosed herein are not limited to the IBM DS8000™ enterprise storage system 110 a, but may be implemented in any comparable or analogous storage system 110, regardless of the manufacturer, product name, or components or component names associated with the system 110. Any storage system that may be supported by one or more embodiments of the invention is considered to fall within the scope of the invention. The IBM DS8000™ is therefore shown only to name an example and not limited thereto.Referring to FIG. 3, a peripheral component interconnect (PCI) north bridge may generally enable data transfer between a processor and an input / output (I / O) subsystem within a data processing system. The PCI north bridge may provide data buffering functions to allow data to be transferred between the processor and the I / O subsystem for read and write operations. The I / O subsystem may be a group of PCI devices (host adapters and / or device adapters) coupled to a PCI bus. When a PCI device on the PCI bus causes a read or write operation from / to a system memory via a direct memory access (DMA), the PCI north bridge may translate a PCI address of the DMA into a system memory address of the system memory.Each PCI device on a PCI bus may have associated with it a corresponding translation control entry (TCE) image 302 in system memory 214. The TCE images 302 may be used to perform TCE translations from PCI addresses to system memory addresses. In response to a DMA read or write operation, a corresponding TCE image is read from the PCI northbridge to provide a TCE translation.In memory systems such as the IBM DS8000™ enterprise storage system, it is required that each I / O operation processed by the memory system 110 maps the cache memory 216 of the memory system 110 one or more times. For example, a read access to cache memory 216 requires creating a TCE image 302 for a host adapter 208 to read cache memory 216 via a DMA. This TCE image 302 is then canceled again after the execution of the DMA. In the event of a read error, two TCE images are required: one image 302 between cache memory 216 and a device adapter 210 to fetch the read data from storage drives 204, and a second image 302 between cache memory 216 and a host adapter 208 to return the read data to a host system 106. After the DMAs are executed, the TCE images 302 may be de-mapped.A TCE image and removal of the TCE image may be time consuming, particularly at high I / O rates. One way to bypass the need for TCE images 302 is to keep certain portions of cache memory 216 permanently mapped (i.e., using dedicated permanently mapped memories). When an I / O occurs, the requested data may be copied from cache memory 216 into this persistently mapped memory 400. DMA can then be performed from this permanently mapped memory 400 without having to perform a TCE map / a TCE map release. This technique eliminates the cost (e.g., the time required) for the TCE image / the TCE image removal, but eliminates the cost (e.g., the time required) for copying data from one storage location to another. This cost may depend on where the two storage locations are relative to each other. In some cases, the cost of performing a TCE image / de-mapping may be lower, in other cases, the cost of copying data to the permanently-mapped memory 400 may be lower.In view of the above, systems and methods are needed to dynamically transition between hard copy and memory map communications techniques to optimize I / O performance in memory systems such as the IBM DS8000™ enterprise storage system. Ideally, such systems and methods use the most efficient data transfer technique (i.e., hard copy or storage image) depending on the I / O operation involved.FIG. 3 is a high-level block diagram illustrating an example of a storage image communication technique, such as a TCE image. As shown, a cache 216 may include one or more cache segments 300, for example four kilobyte cache segments 300. In certain embodiments, a data element, for example a "track", may consist of multiple cache segments 300, for example seventeen cache segments 300. Thus, if a track consists of seventeen cache segments 300 of four kilobytes each, the track may contain sixty eight kilobytes of data. In many cases, the cache segments 300 associated with a track may not be contiguous in the cache 216. This means that the cache segments 300 of the track may be singulated or randomly arranged at different locations in the cache 216. Thus, to read or write a track (i.e., a contiguous sequence of cache segments 300) from or to the cache 216, the track may need to be mapped to corresponding cache segments 300. In certain embodiments, an image 302 (e.g., a TCE image 302) may map cache segments 300 associated with the track to a bus address window 304, such that a host adapter 208 and / or a device adapter 210 may transfer the track to / from the cache 216 via DMA. In certain embodiments, the mapping 302 may arrange the cache segments 300 in the order in which they are arranged in the lane, as shown in FIG. 3.FIG. 4 is a high-level block diagram illustrating an example of a hard copy data transfer technique. As shown, rather than mapping cache segments 300 to a bus address window 304, a memory copy communication technique may first copy cache segments 300 associated with a data element (e.g., a track) to a permanently mapped memory 400. The permanently mapped memory 400 may reside in the same memory 214 (e.g., a memory chip) as the cache 216, or in another memory 214 (e.g., a memory chip). Copying the cache segments 300 from the cache 216 to the persistently mapped memory 400 may therefore involve some cost, the amount of which depends on the locations where the cache 216 and persistently mapped memory 400 are located, as well as the amount of time required to copy the data between those two memories. In certain embodiments, the copied cache segments 300 may be ordered in the persistently mapped memory 400 in the same manner as they are in the lane, thereby providing a contiguous ordered set of cache segments 300 that may be transferred via DMA through a host adapter 208 and / or a device adapter 210.Referring to FIG. 5, a flow chart depicting an embodiment of a method 500 for determining which data transfer technique to use for a particular I / O request is shown; this method 500 may be performed each time an I / O request is received from the storage system 110. As shown, in the method 500, an I / O request is first received 502. The method 500 then calculates 504 a cost associated with executing the I / O request using a memory map data transfer technique, for example, the memory map data transfer technique described in FIG. 3. In certain embodiments, cost may be calculated 504 by analyzing past statistics to determine how long it typically takes to map a particular data track and de-map it again.In the method 500, the cost of executing the I / O request is then calculated 506 using a hard copy data transfer technique, for example the hard copy data transfer technique described in connection with FIG. 4. In certain embodiments, the cost associated with using the memory copy communication technique is calculated by determining a number of cache segments 300 to be copied to the permanently mapped memory 400. In certain embodiments, the memory copy data transfer technique may be used to copy less than one complete track of data, while the memory map data transfer technique may need to map one complete track of cache segments 300. Therefore, the hard copy data transfer technique may be more efficient at smaller transfers (e.g., at less than a complete track of data) than the memory map data transfer technique. The cost associated with the hard copy data transfer technique may also depend on the locations where cache 216 and permanently mapped memory 400 are located relative to each other. For example, if cache 216 and persistently mapped memory 400 are on the same memory chip, cost may be lower because copying the data may take less time. On the other hand, if cache 216 and persistently mapped memory 400 are on different memory chips, cost may be higher as data copying may take more time.The method 500 then compares 508 the cost of the storage image data transfer technique to the cost of the storage copy data transfer technique. If the cost of the storage image communication technique is greater, then in the method 500, the storage copy communication technique may be used 510 to transmit data associated with the I / O request to / from the cache 216 from / to a host adapter 208 and / or device adapter 210. On the other hand, if the cost of the hard copy communication technique is greater, then in the method 500, if possible, the map communication technique may be used 512 to transfer data associated with the I / O request to / from the cache 216 from / to a host adapter 208 and / or device adapter 210. As will be discussed in more detail in connection with Figure 10, use of the storage image data transfer technique or the storage copy data transfer technique may depend on whether "image" windows or "copy" windows are available for transferring the data. A more detailed embodiment of a method for performing steps 510 and 512 of FIG. 5 is described in conjunction with FIG. 10.Referring to FIG. 6, in certain embodiments, a particular number of "image" windows 600 may be associated with transferring data using the storage image communication technique and a particular number of "copy" windows 602 may be associated with transferring data using the storage copy communication technique. Each "map" window may provide a bus address window 304 for transferring data using the memory map data transfer technique, and each "copy" window may provide a bus address window 304 for transferring data using the memory copy data transfer technique. As mentioned above, a bus address window 304 may provide a method to a host adapter 208 and / or a device adapter 210 to read or write a particular amount of contiguous memory space (e.g., a track) from an address bus.For example, assume that a total of two thousand windows are initially assigned to a data transmission and that these two thousand windows are one thousand "image" windows and one thousand "copy" windows. The "image" windows may be used to handle I / O requests for which the storage image communication technique is deemed more efficient, and the "copy" windows may be used to handle I / O requests for which the storage copy communication technique is deemed more efficient. Initially, when a certain number of "copy" windows and "image" windows are assigned to the transmission of data, systems and methods according to the invention may dynamically adjust the respective number of windows assigned to the respective data transmission technique according to the incoming I / O requests. For example, if there are not enough "copy" windows available to handle incoming I / O requests identified for using the storage copy communication technique, a larger portion of the total windows may be associated with the "copy" windows 602 and a smaller portion of the total windows may be associated with the "image" windows 600, as shown in FIG. 7. In this manner, the number of "copy" windows and the number of "image" windows can be dynamically changed to meet the incoming I / O requests.Referring to FIG. 8, an embodiment of a method 800 for mapping windows and dynamically changing the mapping of windows is shown. As shown, in method 800, first a first number of "copy" windows are assigned 802 to use with the storage copy communication technique and a second number of "image" windows are assigned 802 to use with the storage image communication technique. In certain embodiments, the mapping of the windows may include mapping a particular amount of memory 214 to implement the windows. For example, the windows may be allocated two gigabytes of memory 214, one gigabyte being allocated to images 302 associated with the storage map communications technique and one gigabyte being allocated to permanently mapped memory 400 associated with the storage copy communications technique.In other embodiments, the mapping may include a total number of windows, with a particular portion of the total windows being "image" windows and the remaining portion of the total windows being "copy" windows. In certain embodiments, the total number of windows or the total amount of memory 214 associated with the windows is fixed. In other embodiments, the total number of windows or the total amount of memory 214 associated with the windows is adjusted as needed. The initial mapping of windows may be based on an estimate or a guess about the number needed or based on statistical data, for example, the type of I / O that has occurred in the past.Once a first number of "copy" windows and a second number of "image" windows are allocated, the method 800 processes 804 I / O requests over a period of time, possibly using the most efficient communication technique to process the I / O requests. That is, if the map data transfer technique is considered more efficient for processing an I / O request, then ideally, the map data transfer technique and an associated "image" window is used in the method 800 to process the I / O request. Accordingly, if the storage copy data transfer technique is considered more efficient for processing an I / O request, then ideally the storage copy data transfer technique and an associated "copy" window is used in the method 800 to process the I / O request.In processing the I / O requests, the method 800 tracks 806 the number of instances in which the storage copy data transfer technique would ideally have been used but was unavailable due to the lack of associated "copy" windows. Also, in method 800, the number of instances in which the memory map data transfer technique would ideally have been used but was not available due to the lack of associated "map" windows is tracked 810. Based on the number of instances in which the respective window type was not available, in the method 800, the mapping of "copy" windows and "image" windows is dynamically changed 812 (e.g., the number of "copy" windows is changed relative to the number of "image" windows, or the number of "copy" windows and / or "image" windows is increased / decreased). This can be done with the aim of minimizing the number of cases in which windows of a certain type are needed but are not available.Referring to FIG. 9, another embodiment of a method 900 for mapping windows and dynamically changing the mapping of windows is shown. As shown, in method 900, first a first number of "copy" windows are assigned 902 to use with the storage copy communications technique and a second number of "image" windows are assigned 902 to use with the storage image communications technique. Once a first number of "copy" windows and a second number of "image" windows are allocated, I / O requests are processed 904 over a period of time in method 900, possibly using the most efficient communication technique to process the I / O requests.While the I / O requests are being processed, in the method 900, the portion of the I / O requests belonging to particular types is tracked 906. For example, in method 900, how high the fraction of sequential I / O requests, large random I / O requests, and small random I / O requests is may be tracked 906. Sequential I / O requests and large random I / O requests are typically complete track accesses, which can therefore be processed more efficiently using the memory map data transfer technique. Small random I / O requests, on the other hand, comprise less than complete track accesses and can therefore be processed more efficiently using the hard copy data transfer technique. As discussed above, the memory copy data transfer technique may be used to copy less than one complete track of data, while the memory map data transfer technique may need to map one complete track of cache segments 300.According to the portion of the I / O requests of the respective type, method 900 may dynamically adjust the number of "copy" windows and the number of "image" windows to match the composition and type of the incoming I / O requests. This ensures as much as possible that the most efficient data transmission technique is selected and used for each incoming I / O request.FIG. 10 shows a flow chart illustrating one embodiment of a method 1000 for determining whether to use a memory map data transfer technique or a hard copy data transfer technique to process an I / O request. In certain embodiments, this method 1000 is used in place of steps 510, 512 shown in FIG. 5. As shown, in the method 1000, first, for a received I / O request, it is determined 1002 whether using the storage copy data transfer technique causes less cost than using the storage map data transfer technique. If so, then the method 1000 determines whether an available number of "copy" windows is below a threshold (e.g., 100), an available number of "image" windows is above a threshold (e.g., 100), and a difference in cost between using the storage copy communication technique and using the storage image communication technique is below a threshold (e.g., 5 microseconds). If these conditions are met, then the map data transfer technique is used 1004 in the method 1000 to transfer the data associated with the I / O request. Essentially, in this step 1004, the map data transfer technique is used to transfer the data associated with the I / O request if "copy" windows are not present in sufficient number, "image" windows are present in sufficient number, and the cost difference between the data transfer techniques is not too great. Otherwise, the method 1000 continues with the next step 1006.If no "copy" windows are available in step 1006, but at least one "image" window is available, then the map data transfer technique is used 1006 in the method 1000 to transfer the data associated with the I / O request regardless of the difference in cost between using the map data transfer technique and using the map data transfer technique. Essentially, in this step 1006, the storage map data transfer technique is used to transfer the data associated with the I / O request if this is the only option available, even if using the storage copy data transfer technique were most efficient. Otherwise, the method 1000 continues with the next step 1008.If no "copy" windows and no "image" windows are available in step 1008, the next available window ("copy" window or "image" window) is waited 1008 in the method 1000, and this window is used together with the corresponding data transmission technique to transmit the data associated with the I / O request. This is performed regardless of the difference in cost between using the copy memory data transfer technique and using the map data transfer technique. Otherwise, the method 1000 continues with the next step 1010. In step 1010, in method 1000, the storage copy data transfer technique is used to transfer the data associated with the I / O request because "copy" windows are available and using the storage copy data transfer technique is less costly than using the storage image data transfer technique.If, in step 1002, the storage copy data transfer technique is not less costly than the storage map data transfer technique (i.e., the storage map data transfer technique is less costly than the storage copy data transfer technique), the method 1000 continues with step 1012. In step 1012, in method 1000, it is determined 1012 whether an available number of "image" windows is below a threshold (e.g., 100), an available number of "copy" windows is above a threshold (e.g., 100), and a difference in cost between using the storage image communication technique and using the storage copy communication technique is below a threshold (e.g., 5 microseconds). If these conditions are met, then the copy memory data transfer technique is used 1012 in the method 1000 to transfer the data associated with the I / O request. Essentially, in this step 1012, the storage copy data transfer technique is used to transfer the data associated with the I / O request if "image" windows are not present in sufficient number, "copy" windows are present in sufficient number, and the cost difference between the data transfer techniques is not too great. Otherwise, the method 1000 continues with the next step 1014.If no "image" windows are available in step 1014, but at least one "copy" window is available, then in the method 1000, the storage copy data transfer technique is used 1014 to transfer the data associated with the I / O request regardless of the difference in cost between using the storage image data transfer technique and using the storage copy data transfer technique. Essentially, in this step 1014, the hard copy data transfer technique is used to transfer the data associated with the I / O request if this is the only option available, even though using the memory map data transfer technique would be more efficient. Otherwise, the method 1000 continues with the next step 1016.If no "image" windows or "copy" windows are available in step 1016, the next available window ("copy" window or "image" window) is waited 1016 in the method 1000 and this window is used together with the corresponding data transmission technique to transmit the data. This is done regardless of the difference in cost between the map data transfer technique and the hard copy data transfer technique. Otherwise, method 1000 continues with next step 1018. In step 1018, in method 1000, the map data transfer technique is used 1018 to transfer the data associated with the I / O request, as "image" windows are available and using the map data transfer technique is less costly than using the hard copy data transfer technique.The flowcharts and / or the block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer usable media according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, including one or more executable instructions for executing the particular logical function(s). It should also be appreciated that in some alternative implementations, the functions indicated in the block may occur in a different order than shown in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may sometimes be executed in the reverse order depending on the appropriate functionality. It is further noted that each block of the block diagrams and / or flowchart illustrations, as well as combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented by special purpose hardware-based systems that perform the specified functions or steps, or combinations of special purpose hardware and computer instructions.

Claims

A method (500) of dynamically transitioning between a storage copy and a map data transfer technique to improve I / O performance, the method (500) comprising: receiving (502) an I / O request; calculating (504) a cost for executing the I / O request using a storage copy data transfer technique, the storage copy data transfer technique copying cache segments (300) associated with the I / O request from the cache memory (216) to a persistently mapped memory (400), the persistently mapped memory (400) persistently mapped to a bus address window (304); computing (506) a cost of executing the I / O request using a memory map data transfer technique, the memory map data transfer technique temporarily mapping cache segments (300) associated with the I / O request from the cache memory (216) to the bus address window (304); using (510) the memory copy data transfer technique to transfer cache segments (300) associated with the I / O request if using the memory copy data transfer technique is less costly than using the memory map data transfer technique; and using (512) the memory map data transfer technique to transfer cache segments (300) associated with the I / O request if using the memory map data transfer technique is less costly than using the hard copy data transfer technique.The method (500) of claim 1, wherein the bus address window (304) is a peripheral component interconnect (PCI) bus address window.The method (500) of any preceding claim, wherein calculating (506) the cost of executing the I / O request using the memory copy communication technique comprises calculating a number of cache segments (300) to be copied to the permanently mapped memory (400).The method (500) of any preceding claim, wherein calculating (506) the cost of executing the I / O request using the memory copy communication technique comprises determining a copy latency between the cache memory (216) and the permanently mapped memory (400).The method (500) of claim 4, wherein determining the copy latency between the cache memory (216) and the persistently mapped memory (400) comprises determining the locations of the cache memory (216) and the persistently mapped memory (400).The method (500) of any preceding claim, wherein calculating (504) the cost of executing the I / O request using the memory map data transfer technique comprises estimating a required amount of time for mapping and / or de-mapping cache segments (300) associated with the I / O request from the cache memory (216) to the bus address window (304).The method (500) of any preceding claim, wherein the cache segments (300) in the cache memory (216) are not all contiguous.A computer program product for dynamically transitioning between a hard copy and a memory image communication technique to improve I / O performance, the computer program product comprising: a computer (106) readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit to perform a method (500) according to any one of claims 1 to 7.A computer program stored on a medium readable by a computer (106) and loadable into the internal memory of a digital computer (106), comprising software code portions, when said program is executed on a computer (106), for performing the method (500) of any one of claims 1 to 7.A system (206) for dynamically transitioning between a hard copy and a memory map communication technique to improve I / O performance, the system (206) comprising: at least one processor (212); at least one memory unit (214) coupled to the at least one processor (212) and storing instructions for execution on the at least one processor (212), the instructions causing the at least one processor (212) to: receive (502) an I / O request; calculating (504) a cost of executing the I / O request using a memory copy communication technique, the memory copy communication technique copying cache segments (300) associated with the I / O request from the cache memory (216) to a permanently mapped memory (400), the permanently mapped memory (400) permanently mapped to a bus address window (304); calculating (506) a cost of executing the I / O request using a memory map communication technique, the memory map communication technique temporarily mapping cache segments (300) associated with the I / O request from the cache memory (216) to the bus address window (304); Using (510) the storage copy data transfer technique to transfer cache segments (300) associated with the I / O request if using the storage copy data transfer technique is less costly than using the storage map data transfer technique; and using (512) the storage map data transfer technique to transfer cache segments (300) associated with the I / O request if using the storage map data transfer technique is less costly than using the storage copy data transfer technique.The system (206) of claim 10, wherein the bus address window (304) is a Peripheral Component Interconnect (PCI) bus address window.The system (206) of claim 10 or 11, wherein calculating (506) the cost of executing the I / O request using the memory copy communication technique comprises calculating a number of cache segments (300) to be copied to the permanently mapped memory (400).The system (206) of any of claims 10 to 12, wherein calculating (506) the cost of executing the I / O request using the storage copy communication technique comprises determining a copy latency between the cache memory (216) and the persistently mapped memory (400).The system (206) of claim 13, wherein determining the copy latency between the cache memory (216) and the persistently mapped memory (400) comprises determining the locations of the cache memory (216) and the persistently mapped memory (400).The system (206) of any of claims 10 to 14, wherein calculating (504) the cost of executing the I / O request using the memory map data transfer technique comprises estimating a required amount of time for mapping and / or de-mapping cache segments (300) associated with the I / O request from the cache memory (216) to the bus address window (304).

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