Arranging upper vias at line ends by selectively growing a via mask from a line-cut dielectric

Abstract

A method (1200) for forming a semiconductor device, the method (1200) comprising: Forming (1202) a conductive element (102) in a metallization layer of an interconnect assembly, the conductive element (102) comprising a conductive hard mask (104); Forming (1204) a trench (106) in the conductive element (102) to expose conductive ends of the conductive element (102); Filling (1206) the trench (106) with a host material (202); Forming (1208) a growth inhibitor (402) over a first lead end of the lead element; Forming (1210) a via mask (602) over a second line end of the line element (102), wherein the via mask (602) is grown on an exposed surface of the host material (202); and Resetting (1212) portions of the conductive element (202) that are not covered with the via mask (602) to form a self-aligned upper via at the second conductive end, wherein the via mask (602) is grown using a number of growth cycles selected to target a predetermined dimension of the upper via.

Description

BACKGROUND

[0001] The present invention relates generally to manufacturing methods and resulting assemblies for semiconductor devices, and more specifically to a manufacturing method and resulting structures for disposing self-aligned top vias at line ends of an interconnect assembly by selectively growing a via mask from a line-cut dielectric.

[0002] The fabrication of very large scale integrated (VLSI) or ultra large scale integrated (ULSI) circuits requires the creation of complex interconnect assemblies comprising metallic wiring that connects individual devices within a semiconductor chip. Typically, the wiring interconnect network consists of two types of elements that serve as electrical conductors: line elements that traverse a distance across the chip, and via elements that connect lines at different levels. The conductive metal lines and vias are made of a conductive material, such as aluminum or copper, and are electrically insulated by interlayer dielectrics (ILDs). In a multilayer interconnect assembly, the metallization layers are referred to as "M" layers (e.g., M1 layer, M2 layer, etc.).), while “V” layers refer to the vias located between adjacent M layers (e.g., V1 is located between the M1 and M2 layers).

[0003] To increase the number of circuits that can be provided on a chip, the semiconductor industry has repeatedly reduced the gate length of transistors and the chip size. As a result, the interconnection array that forms the metallic circuitry has also been reduced. As the dimensions of integrated circuit (IC) elements continue to shrink, the aspect ratio (i.e., the ratio of height / depth to width) of elements such as vias generally increases, so the manufacturing process becomes more complicated. Fabricating complex arrays of conductive interconnect layers and vias with a high aspect ratio on increasingly smaller wafer footprints is one of the most process-intensive and cost-sensitive parts of semiconductor IC manufacturing.

[0004] There are already published documents in this context. Document US 2017 / 0 062 275 A1 describes chamferless via structures in semiconductor structures and methods for their fabrication. The method comprises at least the following: forming at least one self-aligned via within at least one dielectric material; plugging the at least one self-aligned via with material; and forming a protective sacrificial mask over the material that plugs the at least one self-aligned via. Furthermore, document US 2018 / 0 086 627 A1 describes integrated micromechanical structures with interconnects and contact vias. A conductive layer is applied in a trench of a sacrificial layer on a substrate. An etch stop layer is applied over the conductive layer. The sacrificial layer is then removed to form a trench. The result is a beam structure above the substrate.

[0005] Despite these advances, there is still a need to provide manufacturing processes for better vias within semiconductor structures. SUMMARY

[0006] This object is achieved by the subject matter of the independent patent claims. Further embodiments emerge from the respective dependent patent claims. Embodiments of the invention are directed to a method for forming self-aligned upper vias at line ends of an interconnect arrangement. A non-limiting example of the method comprises forming a line element in a metallization layer of the interconnect arrangement. The line element may comprise a line hard mask. A trench is formed in the line element to expose the line ends of the line element. The trench is filled with a host material, and a growth inhibitor is formed over a first line end of the line element. A via mask is formed over a second line end of the line element.The via mask can be selectively grown on an exposed surface of the host material. Portions of the conductive element not covered by the via mask are recessed to define a self-aligned top via at the second conductive end.

[0007] Embodiments of the invention are directed to a method for forming self-aligned top vias at line ends of an interconnect assembly. A non-limiting example of the method comprises forming a line element in a metallization layer. The line element may have two or more line ends. A region between a first line end and a second line end is filled with a host material, and a growth inhibitor is formed over the first line end. A via mask is selectively grown over an exposed surface of the host material. Portions of the line element not covered by the via mask are recessed to define a self-aligned top via at the second line end.

[0008] Embodiments of the invention are directed to a semiconductor device. A non-limiting example of the semiconductor device includes a conductive element in a metallization layer of an interconnect device. A plurality of self-aligned upper vias are formed at conductive ends of the conductive element. The self-aligned upper vias have the same critical dimension. The critical dimension is not subject to lithographic variation.

[0009] Embodiments of the invention are directed to a semiconductor device. A non-limiting example of the semiconductor device includes a conductive element in a metallization layer of an interconnect device. The conductive element has a first conductive end and a second conductive end. A trench is located adjacent to the first conductive end of the conductive element. The trench includes a host material. A first upper via is formed at the first conductive end of the conductive element. The first upper via has a first critical dimension. A second upper via is formed at the second conductive end of the conductive element. The second upper via has the first critical dimension. The first critical dimension is not subject to lithographic variation.

[0010] Other technical features and advantages are realized through the techniques of the present invention. Embodiments and aspects of the invention are described in detail herein and are considered part of the claimed subject matter. For a better understanding, reference is made to the detailed description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The specifics of the exclusive rights described herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of embodiments of the invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: Fig. 1 illustrates a cross-sectional view of a semiconductor device after an initial set of processing operations in accordance with one or more embodiments of the invention; Fig. 2 illustrates a cross-sectional view of the semiconductor device after further processing operations in accordance with one or more embodiments of the invention; Fig. 3 illustrates a cross-sectional view of the semiconductor device after further processing operations in accordance with one or more embodiments of the invention; Fig. 4 illustrates a cross-sectional view of the semiconductor device after further processing operations in accordance with one or more embodiments of the invention; Fig. 5 illustrates a cross-sectional view of the semiconductor device after further processing operations in accordance with one or more embodiments of the invention; Fig. 6 illustrates a cross-sectional view of the semiconductor device after further processing operations in accordance with one or more embodiments of the invention; Fig. 7 illustrates a cross-sectional view of the semiconductor device after further processing operations in accordance with one or more embodiments of the invention; Fig. 8 illustrates a cross-sectional view of the semiconductor device after further processing operations in accordance with one or more embodiments of the invention; Fig. 9 illustrates a cross-sectional view of the semiconductor device after further processing operations in accordance with one or more embodiments of the invention; Fig. 10 illustrates a cross-sectional view of the semiconductor device after further processing operations in accordance with one or more embodiments of the invention; Fig. 11 illustrates a cross-sectional view of the semiconductor device after further processing operations in accordance with one or more embodiments of the invention; Fig. 12 is a flowchart illustrating a method according to one or more embodiments of the invention; and Fig. 13 is a flowchart illustrating a method according to one or more embodiments of the invention.

[0012] The diagrams presented herein are illustrative. Many variations may be made to the diagram or the processes described herein without departing from the spirit of the invention. For example, the steps may be performed in a different order, or steps may be added, eliminated, or modified.

[0013] In the accompanying figures and the following detailed description of the disclosed embodiments of the invention, the various elements illustrated in the figures are designated by two- or three-digit reference numerals. With few exceptions, the leftmost digit(s) of each reference numeral corresponds to the figure in which the element is first illustrated. DETAILED DESCRIPTION

[0014] It should be understood in advance that, although exemplary embodiments of the invention are described in connection with a specific transistor architecture, embodiments of the invention are not limited to the specific transistor architectures or materials set forth in this description. Rather, embodiments of the present invention may be implemented in connection with any other type of transistor architecture or any other type of materials now known or later developed.

[0015] For the sake of brevity, conventional techniques related to fabrication of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Furthermore, the various acts and process steps described herein may be incorporated into a more comprehensive method or process with additional steps or functionality not described in detail herein. In particular, various steps in the fabrication of semiconductor devices and semiconductor-based ICs are well known, and thus, in the interest of brevity, many conventional steps are only briefly mentioned herein or are omitted altogether without providing the well-known process details.

[0016] Turning now to an overview of technologies more specifically relevant to aspects of the present invention, ICs are manufactured in a series of stages including a front-end-of-line (FEOL) stage, a middle-of-line (MOL) stage, and a back-end-of-line (BEOL) stage. The process flows for manufacturing modern ICs are often referred to based on whether the process flows fall into the FEOL stage, the MOL stage, or the BEOL stage. Generally, the FEOL stage is a stage in which device elements (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate / wafer. The processes of the FEOL stage include wafer fabrication, separation, gate patterning, and the formation of wells, source / drain (S / D) regions, extension junctions, silicide regions, and overcoats. The MOL stage usually includes process sequences for forming the contacts (e.g.CA) and other arrangements that communicatively couple active areas (e.g., gate, source, and drain) of the device. The silicidedization of source / drain regions as well as the deposition of metal contacts can, for example, take place during the MOL stage to connect the elements patterned during the FEOL stage. Over these logical and functional layers, layers of interconnections (e.g., metallization layers) are formed during the BEOL stage to complete the IC. Most ICs require more than one layer of wires to form all the necessary connections, and up to 5 to 12 layers are added in the BEOL process. The different BEOL layers are connected by means of vias that establish a coupling from one layer to another.

[0017] Insulating dielectric materials are used throughout the layers of an IC to perform a variety of functions, including stabilizing the IC structure and providing electrical isolation between the IC elements. For example, the metal interconnect wires in the BEOL region of the IC are separated by dielectric layers to prevent the wires from shorting to other metal layers.

[0018] The ongoing scaling of semiconductor devices has led to challenging manufacturing requirements, particularly when fabricating ever-smaller metallization layers. In an effort to meet these scaling demands, sophisticated masks incorporating phase shifting and optical proximity correction have been employed. However, these techniques are subject to overlay errors between elements in the interconnect array, which can lead to reliability issues in the final device. Overlay errors result from misalignment during the lithography process, when the mask becomes invariably misaligned with the underlying structure. Although overlay errors can be mitigated by refining the lithography processes, some degree of overlay error is unavoidable, resulting in misalignment of elements between metallization layers.

[0019] One of the challenges in fabricating advanced metallization layers is the difficulty of forming uniform vias at the end of lines (so-called top vias) without any variation in the critical dimension (CD) of the vias. The CD of an element (an interconnect line, a contact, a via, a trench, etc.) refers to the smallest geometric dimension for that element that can be formed (e.g., the CD for a via refers to the width of the via). Uniformity of the CD of a via is particularly difficult to achieve when via alignment is performed using lithography due to the limitations of lithography discussed previously.In particular, limited interference displacement (misalignment) can cause a via to either be moved away from a target line end or clipped by the line end, resulting in a reduction in the CD of the via. Because interference displacement is not exactly the same from via to via (some are moved away from their respective target lines while others are clipped by different amounts), variations in the CD of vias are common.

[0020] Turning now to an overview of aspects of the present invention, one or more embodiments of the invention address the above-described shortcomings of the prior art by providing a novel semiconductor device and method for disposing self-aligned top vias at line ends by assisting in the selective growth of a via mask from a line trench dielectric.

[0021] In some embodiments of the invention, line elements (metal lines and line hard masks) are first cut using lithography and etching. The cuts are then filled with a host material selected for a subsequent selective growth process. The host material is further selected to be non-dielectric and wet-removable (e.g., TiN or TiO x). As used herein, a "wet-removable" material refers to a material that can be removed using a wet etching process. A lithographically patterned mask is used to cover lines that will have a via at one or both ends of the line, and a growth inhibitor is applied to the lines exposed by the mask. The growth inhibitor adheres to exposed dielectrics but not to the host material (e.g., a metal containing a trench fill material), leaving a surface of the host material exposed. A selectively grown via mask is formed (deposited) on the exposed host material.

[0022] The via mask can be a metal or a dielectric (depending on the host material, e.g., TaN, TiN, Ta, Ti, W, etc.) grown using a precise number of growth cycles selected to target a specific via dimension. The growth inhibitor prevents the via mask material from growing at line ends where a via is not needed. The growth inhibitor is removed, and the lines are selectively recessed (e.g., etched) with respect to the via mask to form self-aligned top vias at one or more line ends. The via mask, line hardmask, and host material are then removed and replaced with dielectrics.

[0023] Advantageously, vias formed using selective growth of a via mask in this manner can be self-aligned with respect to one or both ends of the metal lines. The CD variations of the vias that otherwise arise from lithographic alignment of the via with respect to a previously formed line trench are avoided. Instead, the CD of the via at each line end is controlled by the amount of lateral growth of the via mask, which can be well controlled using a precise number of growth cycles to target a specific via dimension. This significantly improves the manufacturing precision for top vias, even enabling top vias at the very ends of lines (which is not possible using conventional lithography).In other words, the present invention provides top vias having invariant via widths (an invariant critical dimension that is not subject to lithographic variations).

[0024] Turning now to a more detailed description of aspects of the present invention, the Fig. 1 to 11 illustrate cross-sectional views of an interconnect assembly 100 after an initial set of manufacturing operations in accordance with one or more embodiments of the invention. Fig. 1, known manufacturing processes were used to form the interconnect assembly 100 to include a conductive element 102, a conductive hardmask 104, and trenches 106 configured and arranged as shown. Although not shown for simplicity of discussion, the conductive element 102 may be one of many conductive lines in a metallization layer of an interconnect assembly. The processes described herein with respect to the conductive element 102 may be used to create self-aligned vias in any of these metallization layers.

[0025] In some embodiments of the invention, the conductive element 102 comprises a conductive material formed or deposited using known BEOL processes in a trench of a metallization layer. In some embodiments of the invention, the conductive element 102 is overfilled (not shown) beyond a surface of the trench, forming overcharges that can be removed using, for example, a chemical mechanical planarization (CMP) process. The conductive element 102 may be made of any suitable conductive material, such as a metal (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, platinum), alloys thereof (such as AlCu, CuMn, CuTi, or the like), a conductive metallic interconnect material (e.g.,Tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium aluminum carbide, tungsten silicide, tungsten nitride, cobalt silicide, nickel silicide), a conductive carbon, or any combination of these materials. In some embodiments of the invention, the conductive element 102 is a ruthenium conductive element. The conductive element 102 may be formed or deposited using, for example, CVD, PECVD, PVD, sputtering, plating, chemical solution deposition, and electroless plating.

[0026] In some embodiments of the invention, the conductive hardmask 104 is deposited or formed on a top surface of the conductive element 102. The conductive hardmask 104 may be formed using any suitable process, such as using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), metal organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), limited reaction CVD (LRPCVD), atomic layer deposition (ALD), flowable CVD, spin-on dielectrics, physical vapor deposition (PVD), molecular beam epitaxy (MBE), chemical solution deposition, or another similar process.The line hardmask 104 may be formed from any suitable dielectric material, such as a low-k dielectric, a nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN. In some embodiments of the invention, the line hardmask 104 is a silicon nitride or silicon oxide hardmask. In some embodiments of the invention, the line hardmask 104 is formed to a thickness of about 10 nm to about 60 nm, for example, 30 nm, although other thicknesses are within the contemplated scope of the invention.

[0027] In some embodiments of the invention, the line hardmask 104 is formed over a plurality of line elements (including the line element 102). In some embodiments of the invention, the line hardmask 104 is formed from a same material on all of the line elements. In some embodiments of the invention, even-numbered or odd-numbered line elements may have the same or different material for the line hardmask 104. For example, an even-numbered line may have SiN, and an odd-numbered line may have SiO x / SoG, or vice versa.

[0028] As further stated in Fig. 1, portions of the conductive element 102 and the conductive hard mask 104 may be removed (cut or patterned) using a lithographic process to form one or more trenches 106. In some embodiments of the invention, portions of the conductive element 102 and the conductive hard mask 104 are removed using a wet etch, a dry etch, or a combination of sequential wet and / or dry etch processes. In some embodiments of the invention, portions of the conductive element 102 and the conductive hard mask 104 are removed using reactive ion etching (RIE). The positioning of the trenches 106 (the conductive cuts) defines one or more conductive ends of the conductive element 102.As used herein, a conduit end refers to the portion (sidewall) of a conduit element that is directly adjacent to a cut (e.g., trenches 106).

[0029] Fig. 2 illustrates a cross-sectional view of the interconnect assembly 100 after a processing operation in accordance with one or more embodiments of the invention. In some embodiments of the invention, the trenches 106 are filled with a host material 202. As previously discussed, the host material may be selected to provide a suitable surface for a subsequent selective growth process ( Fig. 6).

[0030] In some embodiments of the invention, the host material 202 is further selected to be non-dielectric and wet removable. In some embodiments of the invention, the host material 202 comprises TiN, TiO x, TaN, etc. In some embodiments of the invention, the host material 202 is overfilled beyond a surface of the conductive hard mask 104, forming overburdens that can be removed using, for example, CMP. The host material 202 can be formed or deposited in the trench 106 using, for example, CVD, PECVD, PVD, sputtering, plating, chemical solution deposition, and electroless plating.

[0031] Fig. 3 illustrates a cross-sectional view of the interconnect assembly 100 after a processing operation in accordance with one or more embodiments of the invention. In some embodiments of the invention, a lithographically patterned mask 302 is formed over the line hard mask 104. In some embodiments of the invention, the lithographically patterned mask 302 is patterned to cover only portions of the line element 102 proximate a line end where a via is desired.

[0032] Fig. 4 illustrates a cross-sectional view of the interconnect assembly 100 after a processing operation in accordance with one or more embodiments of the invention. In some embodiments of the invention, a growth inhibitor 402 is formed on portions of the conductive hardmask 104 exposed by the lithographically patterned mask 302. In some embodiments of the invention, the growth inhibitor material is selected such that the growth inhibitor 402 forms only on exposed dielectrics. In other words, the growth inhibitor 402 may be selectively formed on exposed portions of the conductive hardmask 104. In some embodiments of the invention, the host material 202 is a non-dielectric material, and the growth inhibitor 402 leaves a surface of the host material 202 exposed.

[0033] In some embodiments of the invention, the growth inhibitor 402 will build up on a surface of the conductive hardmask 104 during a spin-coating process. Examples of materials that do not bond to metal surfaces but can be deposited on dielectrics include self-assembled monolayers (e.g., a C6-C18 carbon chain) or polymer brush materials (with a molecular weight of 1 k to 10 k) designed with hydroxyl or amine functionality.

[0034] Fig. 5 illustrates a cross-sectional view of the interconnect assembly 100 after a processing operation in accordance with one or more embodiments of the invention. In some embodiments of the invention, the lithographically patterned mask 302 is removed to expose a surface of the conductive hard mask 104.

[0035] In some embodiments of the invention, the lithographically patterned mask 302 is removed using a wet etching process, a dry etching process, a combination of sequential wet and / or dry etching processes, or a lithographic stripping process. In some embodiments of the invention, the lithographically patterned mask 302 is removed selectively with respect to the growth inhibitor 402, the conductive hard mask 104, and / or the host material 202.

[0036] Fig. 6 illustrates a cross-sectional view of the interconnect assembly 100 after a processing operation in accordance with one or more embodiments of the invention. In some embodiments of the invention, a via mask 602 is formed (deposited) on an exposed surface of the host material 202. In some embodiments of the invention, the via mask 602 may be a metal or dielectric material grown using a precise number of growth cycles selected to target a specific via dimension.

[0037] In some embodiments of the invention, the via mask 602 may comprise a material that does not grow on the growth inhibitor 402. In some embodiments of the invention, the via mask 602 may comprise a material such that the via mask 602 grows on the host material 202, but not on the growth inhibitor 402. Such materials may include TaN, TiN, Ta, Ti, W, etc., depending on the host material 202. In this way, the growth inhibitor 402 prevents the via mask 602 from forming at line ends where a via is not needed.

[0038] Fig. 7 illustrates a cross-sectional view of the interconnect assembly 100 after a processing operation in accordance with one or more embodiments of the invention. In some embodiments of the invention, the growth inhibitor 402 is removed to expose a surface of the conductive hard mask 104.

[0039] In some embodiments of the invention, the growth inhibitor 402 is removed using a wet etching process, a dry etching process, a combination of sequential wet and / or dry etching processes, a stripping process, or an ashing process. In some embodiments of the invention, the growth inhibitor 402 is selectively removed with respect to the via mask 602, the line hard mask 104, and / or the host material 202. In some embodiments of the invention, the growth inhibitor 402 is selectively removed using O2 / N2-H2 ashing.

[0040] Fig. 8 illustrates a cross-sectional view of the interconnect assembly 100 after a processing operation in accordance with one or more embodiments of the invention. In some embodiments of the invention, portions of the conductive element 102 and the conductive hard mask 104 that are not covered by the via mask 602 are recessed to form one or more self-aligned top vias 802 at the conductive ends where the via mask 602 was allowed to form (i.e., where no blocking by the growth inhibitor 402 occurred, as described with reference to FIG. Fig. 5 and Fig. 6).

[0041] Advantageously, the upper vias 802 are formed by selectively recessing the surface of the conduction element 102 relative to the via mask 602. As a result, upper vias with an arbitrarily high aspect ratio (defined as height to width, or H / W) can be formed at the line ends without causing variations in the critical dimension. The aspect ratio can range from nearly zero (very wide vias) to 5 or even 10 or more (very tall vias to extremely tall vias with relatively narrow widths).

[0042] Fig. 9 illustrates a cross-sectional view of the interconnect assembly 100 after a processing operation in accordance with one or more embodiments of the invention. In some embodiments of the invention, the via mask 602 is removed to expose a surface of the conductive hardmask 104 and a surface of the host material 202. In some embodiments of the invention, the via mask 602 is removed using a wet etch process, a dry etch process, a combination of sequential wet and / or dry etch processes, a stripping process, or an ashing process. In some embodiments of the invention, the via mask 602 is removed selectively with respect to the conductive hardmask 104, the conductive element 102, and / or the host material 202.

[0043] Fig. 10 illustrates a cross-sectional view of the interconnect assembly 100 after a processing operation according to one or more embodiments of the invention. In some embodiments of the invention, the conductive hardmask 104 is removed to expose a surface of the upper vias 802. In some embodiments of the invention, the conductive hardmask 104 is removed using a wet etch, a dry etch, or a combination of sequential wet and / or dry etch operations. In some embodiments of the invention, the conductive hardmask 104 is removed selectively with respect to the conductive element 102.

[0044] In some embodiments of the invention, the host material 202 remains in the interconnect assembly 100. As in Fig. However, as shown in Figure 10, in some embodiments of the invention, the host material 202 is incompatible with the final product and is optionally removed. In some embodiments of the invention, the host material 202 is removed using a wet etching process, a dry etching process, a combination of sequential wet and / or dry etching processes, a stripping process, or an ashing process. In some embodiments of the invention, the host material 202 is removed selectively with respect to the conductive element 102.

[0045] Fig. 11 illustrates a cross-sectional view of the interconnect assembly 100 after a processing operation in accordance with one or more embodiments of the invention. In some embodiments of the invention, an interlayer dielectric 1102 may be formed over the interconnect assembly 100. The interlayer dielectric 1102 serves as an isolation structure for the lines and vias of the interconnect assembly 100. The interlayer dielectric 1102 may be formed from any suitable dielectric material, such as low-k dielectrics (materials having a low dielectric constant with respect to silicon dioxide, i.e.lower than about 3.9), ultra-low-k dielectrics (materials having a dielectric constant of less than 3), porous silicates, carbon-doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, silicon carbide (SiC), or other dielectric materials. Any known manner may be used for forming the interlayer dielectric 1102, such as CVD, PECVD, ALD, flowable CVD, spin-on dielectrics, or PVD. In some embodiments of the invention, the interlayer dielectric 1102 is formed over a top surface of the upper vias 802 and thereafter planarized down to a surface of the upper vias 802, for example, using CMP.

[0046] Fig. 12 illustrates a flowchart 1200 illustrating a method for forming a semiconductor device according to one or more embodiments of the invention. As shown in block 1202, a conductive element is formed in a metallization layer of an interconnect arrangement. In some embodiments of the invention, the conductive element comprises a conductive hardmask. In some embodiments of the invention, the conductive element comprises a metal line.

[0047] In block 1204, a trench is formed in the conductive element to expose conductive ends of the conductive element. In some embodiments of the invention, forming the trench includes removing portions of the conductive element using an etching process.

[0048] In block 1206, the trench is filled with a host material. In some embodiments of the invention, the material is selected based on the via mask (step 1210) to ensure that the via mask can be selectively grown on a surface of the host material. In some embodiments of the invention, the host material is further selected to comprise a wet-removable non-dielectric material. In some embodiments of the invention, the host material comprises titanium nitride or titanium oxide.

[0049] In block 1208, a growth inhibitor is formed over a first line end of the line element. In some embodiments of the invention, the growth inhibitor prevents growth of the via mask at the first line end.

[0050] In block 1210, a via mask is formed over a second conductive end of the conductive element. In some embodiments of the invention, the via mask is selectively grown on an exposed surface of the host material. In some embodiments of the invention, the via mask is grown using a number of growth cycles selected to target a predetermined dimension of the upper via.

[0051] In block 1212, portions of the conductive element not covered by the via mask are recessed to define a self-aligned top via at the second conductive end. In some embodiments of the invention, the conductive element is recessed such that a sidewall of the top via is coplanar with a sidewall of the second conductive end. In some embodiments of the invention, a plurality of top vias are formed on a respective plurality of conductive ends of the conductive element. In some embodiments of the invention, each of the top vias has a sidewall that is coplanar with a respective conductive end. In some embodiments of the invention, one or more of the top vias are positioned over their respective conductive ends such that three of their planes are coplanar.In other words, two opposite sidewalls and the surface corresponding to the end wall of the upper via may be coplanar with the opposite sidewalls and the end wall of the lead end.

[0052] The method may further comprise forming a lithographic mask over the conductive hardmask. The lithographic mask may be patterned to expose the first conductive end. In some embodiments of the invention, the growth inhibitor is formed on the exposed first conductive end. In some embodiments of the invention, the growth inhibitor builds up on a surface of the conductive hardmask but not on a surface of the host material, leaving a surface of the host material exposed.

[0053] In some embodiments of the invention, the via mask, the line hard mask, and the host material are replaced with an interlayer dielectric. In some embodiments of the invention, the growth inhibitor is removed before resetting portions of the line element.

[0054] Fig. 13 illustrates a flowchart 1300 illustrating a method for forming a semiconductor device according to one or more embodiments of the invention. As shown in block 1302, a conductive element is formed in a metallization layer. In some embodiments of the invention, the conductive element has two or more conductive ends. In block 1304, a region between a first conductive end and a second conductive end is filled with a host material.

[0055] In block 1306, a growth inhibitor is formed over the first conduit end. In some embodiments of the invention, the growth inhibitor comprises a self-assembled monolayer. In some embodiments of the invention, the self-assembled monolayer comprises a C6-C18 carbon chain. In some embodiments of the invention, the growth inhibitor comprises a polymer having a molecular weight of about 1 to about 10,000. In some embodiments of the invention, the polymer comprises hydroxyl or amine functional groups.

[0056] In block 1308, a via mask is selectively grown over an exposed surface of the host material. In block 1301, portions of the conductive element not covered by the via mask are recessed to define a self-aligned top via at the second conductive end.

[0057] The methods and resulting structures described herein can be used in the fabrication of IC chips. The resulting IC chips can be distributed by the manufacturer in raw wafer form (that is, as a single wafer containing multiple unpackaged chips), as a bare chip, or in a packaged form. In the latter case, the chip is mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other higher-level carrier) or in a multi-chip package (such as a ceramic carrier containing either surface interconnects or embedded interconnects, or both). In either case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing units as part of either (a) an intermediate product, such as a motherboard, or (b) a final product.The end product can be any product incorporating IC chips, ranging from toys and other low-end applications to sophisticated computer products incorporating a display, keyboard or other input device, and a central processor.

[0058] Various embodiments of the present invention are described herein with reference to the accompanying drawings. Alternative embodiments may be devised without departing from the scope of this invention. While the following description and the drawings set forth various connections and positional relationships (e.g., above, below, adjacent, etc.) between elements, one skilled in the art will recognize that many of the positional relationships described herein are independent of orientation if the described functionality is maintained even if the orientation is changed. These connections and / or positional relationships may be direct or indirect unless otherwise specified, and the present invention is not intended to be limiting in this regard.In a similar way, the term "coupled" and variations thereof describe that a connection path exists between two elements and does not imply a direct connection between the elements without intervening elements / connections between them. All such variations are considered part of the description. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or an indirect positional relationship. As an example of an indirect positional relationship, references in the present description to forming a layer "A" above a layer "B" include situations where one or more intermediate layers (e.g.a layer “C”) is / are located between layer “A” and layer “B”, as long as the relevant properties and functionalities of layer “A” and layer “B” are not significantly changed by the intervening layer(s).

[0059] The following definitions and abbreviations should be used to interpret the claims and the description. As used herein, the terms "comprises," "having," "comprises," "comprising," "has," "having," "includes," "contains," or "containing," or any other variation thereof, are intended to cover non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that has a list of elements is not necessarily limited to only those elements, but may include other elements not expressly listed or that are inherent in such composition, mixture, process, method, article, or device.

[0060] Furthermore, the term "exemplary" is used herein to mean "serving as an example, example, or illustration." Any embodiment or configuration described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or configurations. The terms "at least one" and "one or more" are to be understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "a plurality" is to be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connection" can include an indirect "connection" or a direct "connection."

[0061] References in the specification to "the one embodiment," "an embodiment," "an exemplary embodiment," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but that each embodiment may or may not include the particular feature, structure, or characteristic. Furthermore, such terms do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with one embodiment, it is conveyed that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments, whether explicitly described or not.

[0062] For descriptive purposes, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof refer to the described structures and methods as oriented in the drawing figures. The terms "overlying," "on top of," "on top," "positioned on," or "positioned on top of" mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intermediate elements, such as an interface structure, may be present between the first element and the second element.The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive layers, insulating layers, or semiconductor layers at the interface between the two elements.

[0063] Spatially relative terms, e.g., "beneath," "under," "below," "below," "above," "above," and the like, are used herein for convenience of description to describe a relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. It is understood that the spatially relative terms are intended to encompass various orientations of the unit in use or operation in addition to the orientation illustrated in the figures. For example, when the unit is turned over in the figures, elements described as being "below" other or "below" other element(s) or feature(s) are then oriented "above" the other elements or features. Thus, the term "below" can encompass both an orientation above and an orientation below. The unit can be oriented in other ways (e.g.,rotated by 90 degrees or in other orientations), and the spatially relative descriptors described herein should be interpreted accordingly.

[0064] The terms "about," "substantially," "approximately," and variations thereof are intended to convey the degree of error associated with a measurement of the particular quantity based on the equipment available at the time the application is filed. "About," for example, may encompass a range of ± 8%, 5%, or 2% of a given value.

[0065] The term “selective with respect to,” such as “a first element selective with respect to a second element,” means that the first element can be etched and the second element can act as an etch stop.

[0066] The term "conformal" (e.g., a conformal layer or a conformal deposit) means that the thickness of the layer is substantially the same on all surfaces, or that the thickness variation is less than 15% of the nominal thickness of the layer.

[0067] The terms “epitaxial growth and / or epitaxial deposition” and “epitaxially formed and / or grown” mean the growth of a semiconductor material (a crystalline material) on a deposition surface of another semiconductor material (another crystalline material), wherein the semiconductor material being grown (crystalline overlying layer) has substantially the same crystalline properties as the semiconductor material of the deposition surface (the seed material).In an epitaxial deposition process, the chemical reactants provided by the source gases can be controlled, and the system parameters can be specified so that the atoms being deposited arrive at the deposition surface of the semiconductor substrate with sufficient energy to move across the surface in such a way that the atoms being deposited align themselves with respect to the crystalline arrangement of the atoms of the deposition surface. An epitaxially grown semiconductor material can have essentially the same crystalline properties as the deposition surface on which the epitaxially grown material is formed. For example, an epitaxially grown semiconductor material deposited on a {100}-oriented crystalline surface may adopt a {100} orientation.In some embodiments of the invention, epitaxial growth and / or deposition processes may be selective with respect to forming on a semiconductor surface and may or may not deposit material on exposed surfaces, such as silicon dioxide or silicon nitride surfaces.

[0068] As noted above, for the sake of brevity, conventional techniques relating to semiconductor and integrated circuit (IC) fabrication may or may not be described in detail herein. However, as background information, a more general description of semiconductor device fabrication processes that may be employed in implementing one or more embodiments of the present invention is now provided. While specific fabrication operations used in implementing one or more embodiments of the present invention may be individually known, the described combination of operations and / or resulting structures is specific to the present invention.Thus, the specific combination of operations described in connection with the fabrication of a semiconductor device according to the present invention utilizes a variety of physical and chemical processes performed on a semiconductor substrate (e.g., a silicon substrate) that are individually known, some of which are described in the immediately following sections.

[0069] In general, the various processes used to form a microchip that is packaged into an IC fall into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process by which a material is grown on, coated with, or otherwise transferred to the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and, more recently, atomic layer deposition (ALD). Removal / etching is any process by which material is removed from the wafer. Examples include etching processes (either wet or dry), chemical mechanical planarization (CMP), and the like.Reactive ion etching (RIE), for example, is a type of dry etching process in which a chemically reactive plasma is used to remove a material, such as a masked structure of a semiconductor material, by subjecting the material to bombardment with ions that remove portions of the material from the exposed surface. The plasma is usually generated by an electromagnetic field at a low pressure (vacuum). Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and / or by ion implantation. These doping processes are followed by annealing in a furnace or rapid thermal annealing (RTA). The annealing serves to activate the implanted dopants. Layers of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g.,Semiconductor lithography (made from various forms of silicon dioxide, silicon nitride, etc.) is used to connect and disconnect transistors and their components. Selective doping of different areas of the semiconductor substrate allows the conductivity of the substrate to change when a voltage is applied. By creating patterns of these different components, millions of transistors can be manufactured and wired together to form the complex circuitry of a modern microelectronic device. Semiconductor lithography is the formation of three-dimensional relief images or structures on the semiconductor substrate for subsequent transfer of the structure to the substrate. In semiconductor lithography, the structures are formed using a light-sensitive polymer called a photoresist.To create the complex structures that comprise a transistor and the many wires that connect the millions of transistors in a circuit, lithography and etch patterning transfer steps are repeated multiple times. Each pattern printed on the wafer is aligned with respect to previously formed patterns, and the conductors, insulators, and selectively doped regions are gradually fabricated to form the final unit.

[0070] The flowchart and block diagrams in the figures illustrate possible implementations of manufacturing and / or operating methods according to various embodiments of the present invention. Various functions / acts of the method are represented by blocks in the flowchart. In some alternative implementations, the functions noted in the blocks may occur in a different order than noted in the figures. For example, two blocks shown consecutively may actually execute substantially concurrently, or the blocks may sometimes be executed in the reverse order depending on the functionality involved.

Claims

[1] A method (1200) for forming a semiconductor device, the method (1200) comprising: Forming (1202) a conductive element (102) in a metallization layer of an interconnect assembly, the conductive element (102) comprising a conductive hard mask (104); Forming (1204) a trench (106) in the conductive element (102) to expose conductive ends of the conductive element (102); Filling (1206) the trench (106) with a host material (202); Forming (1208) a growth inhibitor (402) over a first lead end of the lead element; Forming (1210) a via mask (602) over a second line end of the line element (102), wherein the via mask (602) is grown on an exposed surface of the host material (202); and Resetting (1212) portions of the conductive element (202) that are not covered with the via mask (602) to form a self-aligned upper via at the second conductive end, wherein the via mask (602) is grown using a number of growth cycles selected to target a predetermined dimension of the upper via. [2] The method (1200) of claim 1, wherein the growth inhibitor (402) prevents the via mask (602) from growing at the first line end. [3] The method (1200) of claim 1, wherein the host material (202) is selected based on the via mask (602) to ensure that the via mask (602) grows selectively on a surface of the host material (202). [4] The method (1200) of claim 3, wherein the host material (202) is further selected to comprise a wet-removable non-dielectric material. [5] The method (1200) of claim 4, wherein the host material (202) comprises titanium nitride, titanium oxide, or tantalum nitride. [6] The method (1200) of claim 1, further comprising forming a lithographic mask (302) over the line hard mask (104), wherein the lithographic mask is patterned to expose the first line end. [7] The method (1200) of claim 6, wherein the growth inhibitor (402) is formed on the exposed first lead end. [8] The method (1200) of claim 7, wherein the growth inhibitor (402) builds up on a surface of the conductive hard mask, but not on a surface of the host material (202), such that a surface of the host material (202) is left exposed. [9] The method (1200) of claim 1, comprising replacing the via mask (602), the line hard mask (104), and the host material (202) with an interlayer dielectric (1102). [10] The method (1200) of claim 1, wherein forming the trench (106) comprises removing portions of the conductive element (102) using an etching process. [11] The method (1200) of claim 1, wherein the conductive element (102) comprises a metal line. [12] The method (1200) of claim 1, further comprising removing the growth inhibitor (402) prior to resetting portions of the conductive element (102). [13] A method (1300) for forming an interconnect assembly (100), the method (1300) comprising: Forming (1302) a conductive element (102) in a metallization layer, the conductive element (102) having two or more conductive ends; Filling (1304) a region between a first conduit end and a second conduit end with a host material (202); forming (1306) a growth inhibitor (402) over the first lead end; Growing (1308) a via mask (602) over an exposed surface of the host material (202); and Resetting (1310) portions of the conductive element not covered by the via mask (602) to define a self-aligned upper via (802) at the second conductive end, wherein the via mask (602) is grown using a number of growth cycles selected to target a predetermined dimension of the upper via (802). [14] The method of claim 13, wherein the growth inhibitor (402) comprises a self-assembled monolayer. [15] The method of claim 14, wherein the self-assembled monolayer has a C6-C18 carbon chain. [16] The method of claim 13, wherein the growth inhibitor (402) comprises a polymer having a molecular weight of about 1 to about 10,000. [17] The process of claim 16, wherein the polymer has hydroxyl or amine functional groups.

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