STORAGE CELL WITH STACKED VERTICAL TRANSISTORS

Abstract

Semiconductor unit comprising: a memory cell (100; 200) with stacked vertical transistors, containing: a lower level (204) containing a plurality of lower vertical transistors with a united upper epitaxial area (Epi) (120-1, 120-2; 224-1), comprising first non-floating and floating vertical transistors (104-1, 104-3) and second non-floating and floating vertical transistors (104-4, 104-2), wherein floating vertical transistors have at least one terminal that is electrically separated from other vertical transistors of the stacked vertical transistor memory cell; an upper level (202) containing a plurality of upper vertical transistors with a united lower source / drain epi (110-1, 110-2; 222-1), including first, second, third and fourth upper vertical transistors (102-1, 102-2, 102-3, 102-4); and a cross-coupling which includes epi connections through the combined upper and lower source / drain epis (110-1, 110-2, 120-1, 120-2, 222-1, 224-1) and gate-to-epi connections through metal (130-1, 130-2, 140-1, 140-2; 218-1, 218-2) between the upper level and the lower level.

Description

BACKGROUND

[0001] The present invention relates generally to semiconductor devices, particularly to memory cells having stacked vertical transistors and methods of manufacturing the same.

[0002] Vertical transistors, such as vertical field-effect transistors (FETs), were developed as a way to reduce contact poly pitch (CPP) and increase power by vertically aligning current flow. Furthermore, because the ohmic contacts and channels are aligned vertically, the contact density per unit area of ​​a vertical transistor is higher than that of a lateral transistor.

[0003] The document US 2019 / 0 067 110 A1 relates to a 3D semiconductor device. The 3D semiconductor device comprises a first level with first single-crystal transistors; contact terminals; a first metal layer, wherein a portion of the contact terminals provide connections from the first transistors to the first metal, wherein the connections form logic circuits; a second level with second transistors; a third level with third transistors, wherein the second level overlies the first level, and wherein the third level overlies the second level; a second metal layer overlies the third level, wherein the second level contains first memory cells, wherein each of the memory cells contains at least one of the second transistors;and vertically aligned conductive terminals, wherein the second transistors are aligned with the first transistors with less than 100 nm alignment error, wherein the second transistors are junctionless transistors, wherein one end of each of the vertically aligned conductive terminals is connected to the second metal layer, wherein at least one of the vertically aligned conductive terminals is disposed directly on one of the contact terminals;

[0004] The document US 2009 / 0 114 971 A1 relates to a CMOS EPROM, EEPROM, or inverter device. The device includes an nFET device with a thin gate dielectric layer and a pFET device arranged next to the nFET device with a thick gate dielectric layer and a floating gate electrode. The thick gate dielectric layer is significantly thicker than the thin gate dielectric layer. A common drain node, to which both FET devices are connected, has no external connection in the case of a memory device and an external connection in the case of an inverter. The source regions of both FET devices and the gate electrode of the nFET device are connected to external circuitry. The pFET and nFET devices can be planar, vertical, or FinFET devices. SUMMARY

[0005] The invention relates to a semiconductor device and a method for its manufacture, the features of which are specified in the corresponding independent claims. Embodiments of the invention are specified in the dependent claims.

[0006] A semiconductor device is provided. The device includes a stacked transistor memory cell. The stacked transistor memory cell includes a lower level including a plurality of lower transistors, including at least one non-floating transistor and at least one floating transistor. The at least one floating transistor has at least one terminal that is electrically isolated from other transistors of the stacked transistor memory cell. The stacked transistor memory cell further includes an upper level including at least one upper transistor and a cross-coupling including epitaxial region (EPI) connections and gate-to-EPI connections between the upper level and the lower level.

[0007] Furthermore, a further semiconductor device is provided. The device includes a stacked vertical transistor memory cell. The stacked vertical transistor memory cell includes a lower level including a plurality of lower vertical transistors including n-type field-effect transistors (nFETs) with a combined upper epitaxial source / drain (Epi) and gate structures. The plurality of lower vertical transistors includes first and second non-floating transistors and first and second floating transistors. The first and second floating transistors have at least one terminal that is electrically isolated from other transistors of the stacked vertical transistor memory cell.The stacked vertical transistor memory cell further includes an upper level including a plurality of upper vertical transistors including p-type field-effect transistors (pFETs) with a combined lower source / drain epitaxial and gate structures. The plurality of upper vertical transistors includes first, second, third, and fourth upper vertical transistors. The stacked vertical transistor memory cell further includes cross-coupling in contact with the lower and upper level gate structures.The cross-coupling includes epi connections through the combined upper source / drain epi between the first non-floating and floating transistors and the second non-floating and floating transistors, epi connections through the combined lower source / drain epi between the first and third upper vertical transistors and the second and fourth upper vertical transistors, gate-to-epi connections through metal between the first non-floating and second floating transistors and the second non-floating and first floating transistors, and gate-to-epi connections through metal between the first and second upper vertical transistors and the third and fourth upper vertical transistors.

[0008] Furthermore, a method of manufacturing a semiconductor device is provided. The method includes forming a stacked transistor memory cell including a lower level with a plurality of lower transistors, including at least one non-floating transistor and at least one floating transistor, and an upper level with at least one upper transistor. The at least one floating transistor has at least one terminal that is electrically isolated from other transistors of the stacked vertical transistor memory cell. Forming the stacked transistor memory cell includes forming a cross-coupling including epitaxial region (EPI) connections and gate-to-EPI connections between the upper level and the lower level.

[0009] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which should be read in conjunction with the accompanying figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The following description provides details of preferred embodiments with reference to the following figures, wherein: Fig. 1 is a schematic diagram of a memory cell according to an embodiment of the present invention; Fig. 2 is a top view of a stacked vertical transistor memory cell according to an embodiment of the present invention; Fig. 3 a sectional view of the memory cell of Fig. 2 according to an embodiment of the present invention; Fig. 4 another sectional view of the memory cell of Fig. 2 according to an embodiment of the present invention; Fig. 5 is a plan view of sacrificial layers etched during fabrication of a semiconductor device according to an embodiment of the present invention; Fig. 6 a sectional view of the Fig. 5 according to an embodiment of the present invention; Fig. 7 another sectional view of the Fig. 5 according to an embodiment of the present invention; Fig. 8 is a sectional view of forming lower source / drain regions in the upper level of the semiconductor device during fabrication of the semiconductor device according to an embodiment of the present invention; Fig. 9 is another sectional view of forming lower source / drain regions in the upper level of the semiconductor device during fabrication of the semiconductor device according to an embodiment of the present invention; Fig. 10 is a sectional view of the formation of upper transistors and an interlayer dielectric (ILD) layer during the fabrication of the semiconductor device according to another embodiment of the present invention; Fig. 11 is another cross-sectional view of the formation of upper transistors and an interlayer dielectric (ILD) layer during the fabrication of the semiconductor device according to another embodiment of the present invention; Fig. 12 is a sectional view of etching performed to expose the sacrificial layers during fabrication of the semiconductor device according to another embodiment of the present invention; Fig. 13 is another sectional view of etching performed to expose the sacrificial layers during fabrication of the semiconductor device according to another embodiment of the present invention; Fig. 14 is a sectional view of the removal of sacrificial layers to form cross-coupling openings during the fabrication of the semiconductor device according to another embodiment of the present invention; Fig. 15 is another sectional view of the removal of the sacrificial layers to form cross-coupling openings during the manufacture of the semiconductor device according to another embodiment of the present invention; Fig. 16 is a sectional view of forming conductive material in the cross-coupling openings for forming cross-coupling during fabrication of the semiconductor device according to another embodiment of the present invention; Fig. 17 is another sectional view of the formation of conductive material in the cross-coupling openings for forming a cross-coupling during the manufacture of the semiconductor device according to an embodiment of the present invention; and Fig. 18 is a block diagram / flowchart illustrating a system / method for manufacturing a semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0011] The embodiments described herein provide a stacked transistor memory cell in a stacked three-dimensional (3D) transistor architecture. The stacked transistor memory cell may include floating and non-floating transistors. As used herein, a floating transistor of a memory cell is a transistor having at least one terminal (e.g., at least one of a source / drain, drain / source, and gate) that is electrically separated or isolated from other transistors of the memory cell, and none of the terminals represents an interface of the memory cell to the outside (e.g., word line (WL), bit line (BL), power supply (VDD), and ground (GND)). A non-floating transistor of a memory cell is a transistor that is not a floating transistor.This means that each of the terminals of a non-floating transistor is either connected to other transistors in the memory cell or represents an interface of the memory cell to the outside.

[0012] The stacked transistor memory cell described in accordance with the embodiments described herein includes an upper level and a lower level, each including corresponding transistors. For example, the upper level may include p-type transistors (e.g., pFETs), and the lower level may include n-type transistors (e.g., nFETs). For example, an upper-level transistor (e.g., pFET) may be used as a pass gate.

[0013] In one embodiment, the stacked transistor memory cell is a stacked vertical transistor memory cell. In particular, the stacked vertical transistor memory cell may include vertical transport FETs (VTFETs). A combined lower epitaxial region ("EPI") in the upper level may be used to connect the pass gate to a first inverter (e.g., pFET) drain. The transistor directly below the pass gate (e.g., nFET) may have a floating gate and a lower source / drain and may have its upper epi fused to the top epi (drain) of a second inverter (e.g., nFET). A cross-coupling contact may connect the gates of an inverter, which may be in direct contact with the lower epi of the pass gate and the upper epi of the floating transistor.

[0014] In aspects of the present invention, the integration of the stacked transistor memory cell within the monolithic 3D scheme offers various advantages, such as logic. For example, one or more of the following advantages can be achieved: (1) tighter packaging of circuits, thus reducing the back-end-of-the-line (BEOL) line length with energy and performance benefits; and (2) higher drive power for a given footprint.

[0015] Example applications / uses in which the present invention may be applied include, but are not limited to, the fabrication of memory devices. For example, embodiments of the present invention may be applied to the fabrication of a static random-access memory (SRAM) device formed from SRAM cells. As is known in the art, an SRAM cell is made up of transistors, which may include metal-oxide-semiconductor FETs (MOSFETs). For example, in an SRAM cell with six transistors (i.e., a 6T SRAM cell), each bit is stored on four transistors that form cross-coupled inverters, while the other two transistors are access transistors that control access to a memory cell during read and write operations.In the 6T SRAM cell embodiment described herein, the upper level may include four p-type transistors, and the lower level may include two n-type transistors. For example, the upper level could include two pass gates. However, such embodiments are not limiting. For example, in an alternative embodiment, the upper level may include n-type transistors, while the lower level may include n-type transistors.

[0016] It should be noted that aspects of the present invention are described for a given illustrative architecture; however, architectures, structures, substrate materials, and process elements and steps may be varied within the scope of aspects of the present invention.

[0017] It should also be noted that when an element such as a layer, region, or substrate is referred to as being "on" or "over" another element, it may be disposed directly on top of the other element, but there may also be intervening elements. On the other hand, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements. Furthermore, it should be noted that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. On the other hand, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0018] The present embodiments may include a blueprint for a chip with an integrated circuit, which may be generated in a graphical computer programming language and stored in a computer storage medium (such as a disk, a tape, a physical hard disk, or a virtual hard disk, such as in a storage access network). If the designer does not manufacture chips or the photolithographic masks used for chip fabrication, the designer may transmit the received blueprint directly or indirectly to appropriate companies by physical means (e.g., by providing a copy of the storage medium storing the blueprint) or electronically (e.g., through the Internet). The stored blueprint is then converted into the appropriate format (e.g.,GDSII) for the production of photolithographic masks, which may contain multiple copies of the corresponding chip blueprint to be formed on a wafer. The photolithographic masks are used to define areas of the wafer (and / or the layers thereon) that are to be etched or otherwise processed.

[0019] Methods as described herein can be used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of a raw wafer (i.e., a single wafer comprising multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other higher-level carrier) or in a multi-chip package (such as a ceramic carrier having one or both of surface interconnects or buried interconnects). In either case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing units as part of (a) an intermediate product, such as a motherboard, or (b) a final product.The final product can be any product containing integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with a display, keyboard or other input device, and a central processor.

[0020] Furthermore, it should be noted that material compounds are described in terms of listed elements, e.g. SiGe. These compounds cover different proportions of the elements in the compound, e.g. SiGe covers Si x Ge 1-x where x is less than or equal to 1, and so on. Additionally, the compound may also contain other elements and still conform to the present principles. Compounds with additional elements are referred to herein as alloys.

[0021] Throughout the specification, reference to "one embodiment" or "an embodiment," and other variations thereof, means that a particular element, structure, feature, and so forth described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in an embodiment" or "according to an embodiment," and any other variations, in various places throughout the specification do not necessarily all refer to the same embodiment.

[0022] Please note that the use of any of the following “ / ”, “and / or” and “at least one of”, for example, in the cases of “A / B”, “A and / or B” and “at least one of A and B”, is intended to include selecting only the first listed option (A), or selecting only the second listed option (B), or selecting both options (A and B). As another example, in the cases of “A, B and / or C” and “at least one of A, B and C”, this designation is intended to include selecting only the first listed option (A), or selecting only the second listed option (B), or selecting only the third listed option (C), or selecting only the first and second listed options (A and B), or selecting only the first and third listed options (A and C), or selecting only the second and third listed options (B and C), or selecting all three listed options (A, B, and C).As will be clear to the skilled person, this can be extended to as many elements as are listed.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting to particular embodiments. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. Further, it is to be understood that the terms "comprises," "having," "includes," and / or "containing," when used herein, refer to the presence of specified features, integers, steps, acts, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, acts, elements, components, and / or groups thereof.

[0024] Spatial relative terms such as "beneath", "under", "lower", "above", "upper", and the like may be used herein for convenience of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the FIGS. It should be noted that the spatial relative terms are intended to include various orientations of the unit in operation, in addition to the orientations illustrated in the FIGS. For example, when the unit is turned over in the FIGS., elements described as being "below" or "below" other element(s) or feature(s) will then be located "above" the other elements or features. Thus, the term "below" can include an orientation of both above and below.The unit may also be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Furthermore, it should be noted that a layer described as being "between" two layers may be the only layer between the two layers, or one or more intervening layers may be present.

[0025] It should be noted that although the terms first, second, etc., may be used herein to describe various elements, these elements are not intended to be limited by these terms. These terms are used only to distinguish one element from another. Thus, an element referred to below as a first element could be referred to as a second element without departing from the scope of the present concept.

[0026] Reference is now made to the drawings in which like numbers indicate like or similar elements, first Fig. 1 shows a schematic representation of a memory cell 100.

[0027] Memory cell 100 includes a stacked transistor memory cell having a plurality of transistors. In one illustrative embodiment, memory cell 100 includes a stacked vertical transistor memory cell having a plurality of vertical transistors.

[0028] The memory cell 100 may include floating and non-floating transistors. The floating transistors may have at least one terminal (e.g., at least one of a source / drain, drain / source, and gate) that is electrically isolated from other transistors. For example, as shown, the memory cell 100 includes eight transistors, including a set of transistors 102-1 through 102-4 and a set of transistors 104-1 through 104-4. In this illustrative embodiment, the plurality of transistors may include field-effect transistors (FETs). In one embodiment, the set of transistors 102-1 through 102-4 includes p-type FETs (pFETs), and the set of transistors 104-1 through 104-4 includes n-type FETs (nFETs). However, this embodiment should not be considered limiting. Transistors 140-2 and 140-3, indicated by dashed lines, correspond to floating transistors (e.g., floating nFETs).

[0029] Furthermore, a plurality of connections between corresponding ones of the plurality of transistors are shown. In particular, cross-coupling is implemented between epitaxial region ("Epi") connections and gate-to-Epi connections.

[0030] In particular, the dashed-dotted line 110-1 corresponds to a combined lower epi connection between a source / drain of the transistor 102-2 and a source / drain of the transistor 102-4, and the dashed-dotted line 110-2 corresponds to a combined lower epi connection between a source / drain of the transistor 102-1 and a source / drain of the transistor 102-3 (e.g., combined lower pFET epi connections).

[0031] The pure dotted line 120-1 corresponds to a combined upper epi connection between a drain / source of the transistor 104-2 and a drain / source of the transistor 104-4, and the pure dotted line 120-2 corresponds to a combined upper epi connection between a drain / source of the transistor 104-1 and a drain / source of the transistor 104-3 (e.g., combined upper nFET epi connections).

[0032] The solid line 130-1 corresponds to a gate-to-epi connection through metal between the source / drain of transistor 102-2 to the gates of transistors 102-1 and 104-1, the solid line 130-2 corresponds to a gate-to-epi connection through metal between the drain / source of transistor 104-2 and the gate of transistors 102-1 and 104-1, the solid line 140-1 corresponds to a gate-to-epi connection through metal between the source / drain of transistor 102-3 and the gate of transistors 102-4 and 104-4, and the solid line 140-2 corresponds to a gate-to-epi connection through metal between the drain / source of transistor 104-3.

[0033] As further shown, memory cell 100 includes a plurality of lines. Specifically, a ground line (GND) 150-1 is coupled to a source / drain of transistor 104-1, and a GND line 150-2 is coupled to a source / drain of transistor 104-4. A power supply (VDD) line 160-1 is coupled to a drain / source of transistor 102-1, and a VDD line 160-2 is coupled to a drain / source of transistor 102-4. A word line (WL) 170-1 is coupled to the gate of transistor 102-2, and a WL line 170-2 is coupled to the gate of transistor 102-3. A bit line (BL) 180-1 is coupled to a drain / source of transistor 102-3 and a complementary bit line ( ~ BL) 180-2 is coupled to a drain / source of transistor 102-2.

[0034] Fig. 2 shows a top view of a stacked transistor memory cell 200 having an upper level 202 and a lower level 204. In this illustrative example, the memory cell 200 is a stacked vertical transistor memory cell containing eight transistors (e.g., FETs), whereby the number of transistors is not to be considered limiting. The memory cell 200 may be the memory cell 100 of Fig. 1. For simplicity, some components of the memory cell 200 (e.g., gate material, upper and lower epitaxial regions (“Epis”) and sacrificial layers for forming contact) are shown in Fig. 2 not shown.

[0035] Memory cell 200 may include floating and non-floating transistors. The floating transistors may have at least one terminal (e.g., at least one of a source / drain, drain / source, and gate) that is electrically isolated from other transistors.

[0036] For example, as shown, memory cell 200 may include a plurality of fins corresponding to the plurality of transistors, including fins 206-2 through 206-8. The plurality of fins may include any suitable material according to the embodiments described herein.

[0037] As further shown, the memory cell 200 may include a plurality of contacts, including GND contacts 210-1 and 210-2, VDD contacts 212-1 and 212-2, WL contacts 214-1 and 214-2, BL contacts 216-1 and ~ BL contacts 216-2. As further shown, the memory cell 200 may include cross-coupling connections 218-1 and 218-2. As described above for Fig. 1, the cross-coupling connections may form epi-connections and gate-to-epi-connections through metal between the plurality of transistors. Sectional views of the memory cell 200 through line AA' and line BB' are shown below with reference to Fig. 3 and 4 respectively.

[0038] Fig. 3 and Fig. 4 show sectional views of the memory cell 200 of Fig. 2 and Fig. 3. In particular, Fig. 3 a sectional view through the line AA' of Fig. 2 and shows Fig. 4 a sectional view through the line BB' of Fig. 2.

[0039] As shown, memory cell 200 includes a substrate 220 with multiple layers formed thereon. Substrate 220 may include any suitable substrate structure, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, and so forth. In one example, substrate 220 may include a silicon-containing material. Illustrative examples of Si-containing materials suitable for substrate 220 may include, but are not limited to, Si, SiGe, SiGeC, SiC, and multilayers thereof. Silicon is the predominant semiconductor material used in wafer fabrication, but alternative semiconductor materials may be employed as additional layers, such as, but not limited to, germanium, gallium arsenide, gallium nitride, silicon germanium, cadmium telluride, zinc selenide, and so forth.

[0040] As above for Fig. 2, the memory cell 200 further includes fins 206-1 through 206-3 and 206-5 through 206-7, the VDD line 212-1, and the BL line 216-1. The fins 206-5 through 206-7 correspond to lower FETs, and the fins 206-1 through 206-3 correspond to upper FETs. Each of the FETs may further include a gate dielectric 208 and a gate conductor 209. The gate dielectrics 208 and the gate conductors 209 may include any suitable material according to the embodiments described herein.

[0041] For example, the gate dielectrics 208 may include a high-k dielectric material. As used herein, "high-k" refers to a dielectric material having a dielectric constant (k) greater than the dielectric constant of SiO2 at room temperature (20°C to 25°C) and atmospheric pressure (1 atm). In one embodiment, the gate dielectrics 208 may include a high-k oxide, such as HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, Y2O3, and mixtures thereof. Other examples of high-k dielectric materials for the gate dielectrics 208 include hafnium silicate, hafnium silicon oxynitride, and combinations thereof.

[0042] Examples of suitable conductive materials for the gate conductors 209 include, but are not limited to, metals, metal alloys, metal nitrides, and metal silicides, as well as laminates thereof and composites thereof. In one embodiment, the gate conductors 209 may include any conductive metal, including, but not limited to, W, Ni, Ti, Mo, Ta, Cu, Pt, Ag, Au, Ru, Ir, Rh, and Re, as well as alloys containing at least one of the aforementioned conductive elemental metals. Furthermore, the gate conductors 209 may include doped polysilicon and / or polysilicon-germanium alloy materials (i.e., with a dopant concentration of 1×10 18 Dopant atoms per cubic centimeter up to 1×10 22 Dopant atoms per cubic centimeter) and polycide materials (doped polysilicon / metal silicide stacking materials). For example, the gate conductors 209 may contain a work function metal (WFM).

[0043] In one embodiment, the gate dielectrics 208 and / or the gate conductors 209 may be deposited by chemical vapor deposition (CVD). Variations of the CVD process suitable for depositing the at least one gate dielectric layer include, but are not limited to, APCVD, LPCVD, PECVD, MOCVD, ALD, and combinations thereof.

[0044] Memory cell 200 further includes lower epitaxial ("Epi") regions 222-1 through 222-5 corresponding to lower source / drain regions. Specifically, memory cell 200 includes a combined FET lower epi region 222-1 corresponding to fins 206-1 and 206-2, and FET lower epi regions 222-2 through 222-5 corresponding to fins 206-5, 206-6, 206-3, and 206-7, respectively.

[0045] Memory cell 200 further includes upper epi-regions 224-1 through 224-6 corresponding to upper source / drain regions. Specifically, memory cell 200 includes a combined upper FET epi-region 224-1 corresponding to fins 206-5 and 206-6, and upper FET epi-regions 224-2 through 224-6 corresponding to fins 206-1, 206-2, 206-5, 206-3, and 206-7, respectively.

[0046] The epi-region 222-1 to 222-5 and 224-1 to 224-6 may contain any suitable material according to the embodiments described herein.

[0047] The terms "epitaxial growth and / or deposition" and "epitaxially formed and / or grown" mean the growth of one semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), wherein the semiconductor material being grown (crystalline overlying layer) has substantially the same crystalline characteristics as the semiconductor material of the deposition surface (seed material). In an epitaxial deposition process, the chemical reactants provided by the gas sources are controlled and the system parameters are adjusted so that the deposition atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around the surface, causing the deposition atoms to orient themselves relative to the crystalline arrangement of the atoms of the deposition surface.Thus, an epitaxially grown semiconductor material has substantially the same crystalline characteristics as the deposition surface on which the epitaxially grown material is formed. For example, a semiconductor material epitaxially grown on a {100}-oriented crystal surface will adopt a {100} orientation. In some embodiments, epitaxial growth and / or deposition processes are selective for forming on a semiconductor surface and generally do not deposit material on exposed surfaces, such as silicon dioxide or silicon nitride surfaces.

[0048] Source / drain epitaxy can be performed by ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), metal-organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), limited-reaction-processing (LRPCVD), and molecular beam epitaxy (MBE). Epitaxial materials can be grown from gaseous or liquid precursors. Epitaxial materials can be grown using vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), or another suitable method. Epitaxial silicon, silicon-germanium (SiGe) and / or carbon-doped silicon (Si:C) silicon can be doped during deposition by adding dopants, n-type dopants (e.g. phosphorus or arsenic) or p-type dopants (e.g. boron or gallium), depending on the type of transistor (in-situ doping).The dopant concentration in the source / drain can be in the range of about 1×10. 19 cm -3 up to about 2×10 21 cm -3 or preferably between 2×10 20 cm -3 and 1×10 21 cm -3 When Si:C is grown epitaxially, the Si:C layer may contain carbon in the range of 0.2 to 3.0%. When SiGe is grown epitaxially, the SiGe may have a germanium content in the range of 5% to 80%, or preferably between 20% and 60%.

[0049] Memory cell 200 further includes dielectric layers 226 that isolate the pairs of upper and lower FETs. Dielectric layers 226 may include any suitable material according to the embodiments described herein (e.g., SiO2).

[0050] The memory cell 200 further includes a plurality of spacer layers 228. The plurality of spacer layers 228 may include any suitable spacer material according to the embodiments described herein.

[0051] The memory cell 200 further includes shallow trench isolation (STI) regions 230 and interlayer dielectric (ILD) layers 240. The STI regions 230 and ILD layers 240 may include any suitable dielectric material in accordance with the embodiments described herein.

[0052] The memory cell 200 further includes an insulator layer 234 that provides NP isolation. The insulator layer 234 may include any suitable material according to the embodiments described herein. For example, the insulator layer 234 may include a nitride material.

[0053] The memory cell 200 further includes a GND contact 210-2, VDD contact 212-1, WL contact 214-2, BL contact 216-1 2 and cross-coupling connections 218-2.

[0054] The FET corresponding to fin 206-1 may correspond to a pass-gate FET, the FETs corresponding to fins 206-2 and 206-6 may correspond to an inverter, and the FET corresponding to fin 206-5 may correspond to an unconnected floating FET. Thus, the combined lower epi-region 222-1 may be used to connect the pass-gate FET to the inverter FET, the combined upper epi-region 224-1 may support cross-coupling, and the isolated lower epi-region 222-3 may correspond to an inverter ground.

[0055] Fig. 5 to 17 describe a part of a process flow for manufacturing a semiconductor device 300 having a three-dimensionally stacked vertical FET architecture, such as the one described above with reference to Fig. 2 to 4. In one embodiment, the lower FETs include nFETs and the upper FETs include pFETs.

[0056] In Fig. 5 to 7 shows Fig. 5 a plan view of the unit 300, shows Fig. 6 a sectional view of the Fig. 6 shown unit 300 through the line CC' and shows Fig. 7 a sectional view of the Fig. 6 shown unit 300 by the line D-D'.

[0057] As shown, device 300 includes a substrate 302. Substrate 302 may include any suitable substrate structure, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, and so on. In one example, substrate 302 may include a silicon-containing material. Illustrative examples of Si-containing materials may include, but are not limited to, Si, SiGe, SiGeC, SiC, and multilayers thereof. Silicon is the predominant semiconductor material used in wafer fabrication, but alternative semiconductor materials may be employed as additional layers, such as, but not limited to, germanium, gallium arsenide, gallium nitride, silicon germanium, cadmium telluride, zinc selenide, and so on.

[0058] The assembly 300 includes a plurality of upper-level fin structures, including upper-level fins 310, cover layers 312, and liners 314 formed on the sidewalls of the upper-level fins 310 and the cover layers 312. The liners 314 may include any suitable material for protecting the upper fins 310 during subsequent processing. The assembly 300 further includes a plurality of lower-level fins 316 separated from the upper-level fins 310 by insulator layers 318. The fins 310 and 316 and the insulator layers 318 may be formed from the substrate 302 by any suitable method in accordance with the embodiments described herein.For example, fins 310 and 316 and insulator layers 318 may be formed by etching through an SOI substrate, with upper-level fins 310 formed from a semiconductor layer, lower-level fins 316 formed from a base substrate layer, and insulator layers 318 formed from insulator layers disposed between the base substrate layer and the semiconductor layer. In one embodiment, lower-level fins 316 may correspond to nFETs, and upper-level fins 310 may correspond to pFETs. However, such an embodiment should not be construed as limiting.

[0059] As further shown, the lower-level fins 316 are formed on the lower-level source / drain epi regions 320, and an STI region 322 is disposed on the substrate 302 between the lower-level source / drain epi regions 320. The lower-level source / drain epi layers 320 and the STI region 322 may be formed from the substrate 302 using any suitable method in accordance with the embodiments described herein.

[0060] The device 300 further includes lower level gate stacks 324 formed around corresponding ones of the lower fins 316, a lower level spacer layer 326-1, and an ILD layer 308 corresponding to the layer 326-1 described above for Fig. 2 through 4. In one embodiment, the lower level gate stacks 324 correspond to nFET gates. The lower level gate stacks 324 may be formed using any suitable method in accordance with the embodiments described herein. For example, the lower level gate stacks 324 may be formed by depositing gate stack material including gate dielectrics and gate conductors (e.g., high-k dielectric material and a WFM), forming the ILD layer 322, and etching the exposed gate stack material. An upper lower level spacer layer 326-2 may then be formed after forming the lower level gate stacks 324.

[0061] The device 300 further includes upper lower-level source / drain epi-regions 328 formed around corresponding ones of the lower fins 316. A drive-in heat treatment process may be used to form interconnects.

[0062] Device 300 further includes sacrificial layers 330-1 and 330-2 for source / drain contacts. Sacrificial layers 330-1 and 330-2 may be formed by forming a sacrificial fill, forming corresponding mask layers, and etching the exposed portions of sacrificial layers 330-1 and 330-2. Sacrificial layers 330-1 and 330-2 may include any suitable material according to the embodiments described herein. For example, sacrificial layers 330-1 and 330-2 may include, for example, an oxide material.

[0063] As in Fig. 8 and Fig. 9, an insulator layer 332 providing NP isolation is formed. The insulator layer 332 may include any suitable material according to the embodiments described herein (e.g., a nitride material). As further shown, the liners 314 are removed, second liners 334 are formed, and lower upper-level source / drain epi regions 336 are formed around corresponding ones of the upper fins 310. The lower upper-level source / drain epi regions 336 may be formed using any suitable method according to the embodiments described herein. For example, the lower upper-level source / drain epi regions 336 may be formed by removing the liners 314 (in Fig. 6 and Fig. 7), forming a sacrificial dielectric layer (not shown) on the insulator layer 332, forming the second liners 334 on the dielectric layer, removing the sacrificial dielectric layer, and forming the lower upper-level source / drain epi regions 336 on the insulator layer 332 beneath the second liners 334 adjacent to the upper fins 310. Liner 338 may then be formed.

[0064] As in Fig. 10 and Fig. 11, portions of the liner 338 are removed and a lower upper level spacer 340-1, an ILD layer 342, upper level gate stack 344, an upper upper level spacer 340-2, upper upper level source / drain regions 346, and an ILD layer 348 are formed.

[0065] As in Fig. 12 and Fig. As shown in Figure 13, openings 350-1 and 350-2 are formed to the claddings 330-1 and 330-2, respectively. Any suitable etching technique (e.g., reactive ion etching (RIE)) may be used to form the openings 350-1 and 350-2 according to the embodiments described herein.

[0066] As in Fig. 14 and Fig. As shown in Figure 15, the panels 330-1, 330-2, and 338 are removed to form cavities 352-1 and 352-2. Any suitable method may be used to remove the panels 330-1, 330-2, and 338 according to the embodiments described herein.

[0067] As in Fig. 16 and Fig. 17, the cavities 352-1 and 352-2 are filled with a conductive material to form contacts 354-1 and 354-2, respectively. Examples of suitable conductive materials that can be used to form contacts 354-1 and 354-2 include, but are not limited to, Cu, W, Ru, Co, Al, and so on. Contacts 354-1 and 354-2 correspond to cross-couplings. In an alternative embodiment, the lower contacts of the

[0068] Fig. 18 shows a block diagram / flowchart illustrating a system / method 400 for manufacturing a semiconductor device including a stacked vertical transistor memory cell according to another embodiment of the present invention.

[0069] At block 410, a lower level of a stacked vertical transistor memory cell is provided. The lower level may include a plurality of lower vertical transistors with a combined upper source / drain. The plurality of lower vertical transistors may include first and second non-floating and first and second floating transistors. The floating transistors may have at least one terminal that is electrically isolated from other transistors of the stacked vertical transistor memory cell.

[0070] At block 420, a cross-coupling is formed between the lower level and an upper level of the stacked vertical transistor memory cell. The upper level may include a plurality of upper vertical transistors with a combined lower epitaxial source / drain region ("Epi"). The plurality of upper vertical transistors may include first, second, third, and fourth upper vertical transistors.

[0071] The plurality of lower vertical transistors further includes corresponding lower source / drain epitaxial regions, and the plurality of upper vertical transistors further includes corresponding upper source / drain epitaxial regions. The lower source / drain epitaxial regions and the upper source / drain epitaxial regions may be separated by a dielectric layer. The lower level and the upper level may be separated by insulator layers.

[0072] The plurality of lower vertical transistors may include n-type field effect transistors (nFETs) and the plurality of upper vertical transistors may include p-type field effect transistors (pFETs).

[0073] Forming the cross-coupling between the lower level and the upper level may include forming epi connections through the combined upper source / drain epi between the first non-floating and floating transistors and the second non-floating and floating transistors, forming epi connections through the combined lower source / drain epi between the first and third upper vertical transistors and the second and fourth upper vertical transistors, forming gate-to-epi connections through metal between the first non-floating and second floating transistors and the second non-floating and first floating transistors, and forming gate-to-epi connections through metal between the first and second upper vertical transistors and the third and fourth upper vertical transistors.

[0074] The lower and upper levels may further include corresponding gate structures. Forming the cross-coupling may further include bringing the gate structures of the lower and upper levels into contact.

[0075] Further details on blocks 410 and 420 are given above with reference to Fig. 1 to 17 described.

[0076] Thus, having described aspects of the invention with the detail and care required by patent law, the protection claimed and desired by the patent certificate is set forth in the appended claims.

[0077] In a preferred embodiment of the present invention described herein, a semiconductor device is provided comprising: a stacked vertical transistor memory cell including: a lower level including a plurality of lower vertical transistors including n-type field effect transistors (nFETs) with a combined upper epitaxial source / drain (Epi) region and gate structures, wherein the plurality of lower vertical transistors include first and second non-floating transistors and first and second floating transistors, wherein the first and second floating transistors have at least one terminal that is electrically isolated from other transistors of the stacked vertical transistor memory cell;an upper level including a plurality of upper vertical transistors including p-type field-effect transistors (pFETs) with a combined lower epitaxial source / drain epi and gate structures, the plurality of upper vertical transistors including first, second, third, and fourth upper vertical transistors; and a cross-coupler in contact with the gate structures of the lower and upper levels; including: epi connections through the combined upper source / drain epi between the first non-floating and floating transistors and the second non-floating and floating transistors; epi connections through the combined lower source / drain epi between the first and third upper vertical transistors and the second and fourth upper vertical transistors;Gate-to-EPI connections through metal between the first non-floating and second floating transistors and the second non-floating and first floating transistors; and gate-to-EPI connections through metal between the first and second upper vertical transistors and the third and fourth upper vertical transistors. The plurality of lower vertical transistors may further include corresponding lower source / drain Epis, and the plurality of upper vertical transistors may further include corresponding upper source / drain Epis. The device may further include dielectric layers separating the lower source / drain Epis from the upper source / drain Epis and insulator layers separating the lower level and the upper level. The device may further include wordline, bitline, power supply, and ground contacts.;

Claims

[1] Semiconductor device, comprising: a memory cell (100; 200) with stacked vertical transistors, comprising: a lower level (204) including a plurality of lower vertical transistors with a combined upper epitaxial region (Epi) (120-1, 120-2; 224-1), including first non-floating and floating vertical transistors (104-1, 104-3) and second non-floating and floating vertical transistors (104-4, 104-2), wherein floating vertical transistors have at least one terminal that is electrically isolated from other vertical transistors of the stacked vertical transistor memory cell; an upper level (202) including a plurality of upper vertical transistors with a combined lower source / drain epi (110-1, 110-2; 222-1) including first, second, third, and fourth upper vertical transistors (102-1, 102-2, 102-3, 102-4); and a cross-coupling including epi connections through the combined upper and lower source / drain epis (110-1, 110-2, 120-1, 120-2, 222-1, 224-1) and gate-to-epi connections through metal (130-1, 130-2, 140-1, 140-2; 218-1, 218-2) between the upper level and the lower level. [2] The device of claim 1, wherein the epi connections through the combined upper and lower source / drain epis include: Epi connections through the combined upper source / drain epi (120-2) between the first non-floating and floating vertical transistors (104-1, 104-3) and the combined upper source / drain epi (120-1) between the second non-floating and floating vertical transistors (104-4, 104-2) and Epi connections through the combined lower source / drain epi (110-2) between the first and third upper vertical transistors (102-1, 102-3) and the combined lower source / drain epi (110-1) between the second and fourth upper vertical transistors (102-2, 102-4); where the gate-to-epi connections through metal contain: Gate-to-epi connections through metal (130-2, 140-2) between the first non-floating vertical transistor (140-1) and the second floating vertical transistor (140-2), and the second non-floating vertical transistor (104-4) and the first floating vertical transistor (104-3); and Gate-to-epi connections through metal (130-1, 140-1) between the first and second upper vertical transistors (102-1, 102-2) and the third and fourth upper vertical transistors (102-3, 102-4). [3] The device of any preceding claim 1, wherein the plurality of lower vertical transistors comprise n-type field effect transistors (nFETs) and the plurality of upper vertical transistors comprise p-type field effect transistors (pFETs). [4] The device of any preceding claim 1, wherein the plurality of lower vertical transistors further includes corresponding lower source / drain epis (222-2, 222-3, 222-5) and the plurality of upper vertical transistors further includes corresponding upper source / drain epis (224-2, 224-3, 224-6). [5] The device of any preceding claim 4, further comprising dielectric layers (230, 240) separating the lower source / drain epis and the upper source / drain epis, and insulator layers (226, 234) separating the lower level and the upper level. [6] The device of any preceding claim, further comprising word line, bit line, power supply and ground contacts (150-1, 150-2, 160-1, 160-2, 170-1, 170-2, 180-1, 180-2; 210-1, 210-2, 212-1, 212-2, 214-1, 214-2, 216-1, 216-2). [7] A device according to any preceding claim, wherein the cross-coupling further contacts lower and upper level gate structures (208, 209). [8] A method (400) for producing a semiconductor device, comprising: Forming (410) a stacked vertical transistor memory cell (100; 200) comprising a lower level (204) comprising a plurality of lower vertical transistors with a combined upper epitaxial region (Epi) (120-1, 120-2; 224-1) including first non-floating and floating vertical transistors (104-1, 104-3) and second non-floating and floating vertical transistors (104-4, 104-2), and an upper level (202) comprising a plurality of upper vertical transistors with a combined lower source / drain Epi (110-1, 110-2; 222-1) including first, second, third, and fourth upper vertical transistors (102-1, 102-2, 102-3, 102-4), wherein floating vertical transistors have at least one terminal that is electrically isolated from other vertical transistors of the stacked vertical transistor memory cell, wherein forming the stacked vertical transistor memory cell includes: Forming (420) a cross-coupling including epi connections through the combined upper and lower source / drain epis (110-1, 110-2, 120-1, 120-2, 222-1, 224-1) and gate-to-epi connections through metal (130-1, 130-2, 140-1, 140-2; 218-1, 218-2) between the upper level and the lower level. [9] The method of claim 8, wherein forming the cross coupling further includes: Forming epi connections through the combined upper source / drain epi (120-2) between the first non-floating and floating vertical transistors (104-1, 104-3) and the combined upper source / drain epi (120-1) between the second non-floating and floating vertical transistors (104-4, 104-2); Forming epi connections through the combined lower source / drain epi (110-2) between the first and third upper vertical transistors (102-1, 102-3) and the combined lower source / drain epi (110-1) between the second and fourth upper vertical transistors (102-2, 102-4); Forming gate-to-epi connections through metal (130-2, 140-2) between the first non-floating and second floating vertical transistors (140-1, 140-2) and the second non-floating and first floating vertical transistors (104-4, 104-3); and Forming gate-to-epi connections through metal (130-1, 140-1) between the first and second upper vertical transistors (102-1, 102-2) and the third and fourth upper vertical transistors (102-3, 102-4). [10] The method of claim 8 or 9, wherein the plurality of lower vertical transistors include n-type field effect transistors (nFETs) and the plurality of upper vertical transistors include p-type field effect transistors (pFETs). [11] The method of any one of claims 8 to 10, wherein the plurality of lower vertical transistors further includes corresponding lower source / drain epis (222-2, 222-3, 222-5) and the plurality of upper vertical transistors further includes corresponding upper source / drain epis (224-2, 224-3, 224-6). [12] The method of claim 11, wherein the lower source / drain epis and the upper source / drain epis are separated by dielectric layers (230, 240) and wherein the lower level and the upper level are separated by insulator layers (226, 234). [13] The method of any one of claims 8 to 12, wherein the stacked vertical transistor unit further includes word line, bit line, power supply and ground contacts (150-1, 150-2, 160-1, 160-2, 170-1, 170-2, 180-1, 180-2; 210-1, 210-2, 212-1, 212-2, 214-1, 214-2, 216-1, 216-2). [14] The method of any one of claims 8 to 13, wherein forming the cross-coupling further includes contacting lower and upper level gate structures (208, 209).

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