Data processing units containing magnetic Josephson transitions with an embedded element for controlling a magnetic field

Abstract

Data processing unit that features: a conductive plate (12; 52) embedded in a surface of a semiconductor substrate (10; 50); at least one Josephson junction structure, JJ structure, located above the conductive plate; and first wiring structures (18P, 18V; 58) located laterally adjacent to the at least one JJ structure, wherein one of the conductive plate or the first wiring structures is configured such that a magnetic field is induced in the at least one JJ structure when an electric current is applied to it, wherein: which at least one JJ structure comprises a first region (22P) of a superconductor, a region (25P) of crystalline silicon containing Mn nanoparticles, and a second region (26P) of a superconducting material; and / or which at least one JJ structure has a cylindrical shape; and / or the first wiring structures (18p, 18V) are in direct contact with a surface of the conductive plate (12), wherein the at least one JJ structure is spaced away from the conductive plate and the conductive plate induces the magnetic field in the at least one JJ structure.

Description

BACKGROUND

[0001] The present invention relates to a data processing unit (i.e., a neuromorphic or artificial intelligence (AI)) and, more specifically, to a data processing unit comprising a structure for controlling a magnetic field within a chip, which is located near a Josephson junction structure (a JJ structure, Josephson Junction structure), and to methods for forming the same.

[0002] Magnetic JJ-containing units have been identified that can be used for advanced, low-power / high-power neuromorphic applications. A JJ has two layers of a superconducting material separated by a non-superconducting barrier layer so thin that electrons can pass through it. A JJ generally manifests itself through the Josephson effect of a supercurrent, where a current can flow infinitely across a JJ without an applied voltage.

[0003] In units containing magnetic JJs, their operation sometimes requires an external magnetic field perpendicular to the unit. A switching magnetoresistive random access memory (MRAM) has used double wires in a 90° orientation to set the function of an MRAM unit. However, there is no known implementation of this in units containing magnetic JJs. Thus, there is a need to provide a structure for controlling a magnetic field within a chip that can be integrated into units containing JJs.

[0004] Document CN 106 953 000 A relates to a superconducting magnetic field coil integrated with a Josephson junction and a method for its fabrication. The superconducting magnetic field coil comprises a plurality of lower magnetic field coil layers, a plurality of upper magnetic field coil layers, and a second insulating layer. The plurality of lower magnetic field coil layers and the plurality of upper magnetic field coil layers are separated by the second insulating layer. Holes are arranged in the second insulating layer. The holes are filled with third superconducting material layers. The upper magnetic field coil layers are connected to two adjacent lower magnetic field coil layers by the third superconducting material layers in the holes, thus forming a complete superconducting magnetic field coil. A magnetic field can be generated at the Josephson junction using the superconducting magnetic field coil according to the invention. SUMMARY

[0005] The invention relates to a data processing unit and a method for its creation, the features of which are specified in the corresponding independent claims. Embodiments are specified in the dependent claims.

[0006] A magnetic field control unit within a chip is formed near a Josephson junction structure (a JJ structure) (within 5 nm to 500 nm of it). The magnetic field control unit has wiring structures located laterally adjacent to the JJ structure. In some embodiments, the magnetic field control unit also includes a conductive plate, connected to the wiring structures and located beneath the JJ structure. The application of an electric current through the wiring structures induces a magnetic field in the JJ structure, either directly or indirectly. The strength of the field can be modulated by the amount of current flowing through the wiring structures.The magnetic field can be switched off if required by stopping the flow of current through the wiring structures.

[0007] A data processing unit is provided that includes a structure for controlling a magnetic field within a chip, located near a JJ structure. In one embodiment of the present invention, the data processing unit has a conductive plate embedded in the surface of a semiconductor substrate. At least one JJ structure is located above the conductive plate. First wiring structures are located laterally adjacent to the at least one JJ structure. In one embodiment of the present invention, a connection between the conductive plate or the first wiring structures is configured such that when an electric current is applied to it, a magnetic field is induced in the at least one JJ structure.

[0008] A method for forming such a data processing unit is provided. In one embodiment of the present invention, the method comprises forming a conductive plate in a semiconductor substrate. Next, a first layer of a dielectric material is formed on physically exposed surfaces of the semiconductor substrate and the conductive plate, the first layer of dielectric material containing through-holes that physically expose a surface of the conductive plate. Then, a metal-containing layer is formed in each of the through-holes and on a top surface of the first layer of dielectric material.Next, the metal-containing layer is structured to provide first and second metal-containing wiring structures, with the first metal-containing wiring structures in contact with the conductive plate and the second metal-containing wiring structures spaced away from the conductive plate. A JJ structure is then formed on every second metal-containing wiring structure. A second layer of dielectric material is then formed laterally adjacent to and above each JJ structure. This second dielectric layer features wiring contact structures and JJ contact structures embedded within it. The wiring contact structures are in contact with the first metal-containing wiring structures, and the JJ contact structures are in contact with the JJ structures.

[0009] In a further embodiment, the method involves forming a conductive plate in a semiconductor substrate. Next, at least one JJ structure is formed on the conductive plate. Then, a first layer of a dielectric material is formed laterally adjacent to the at least one JJ structure, the first layer of dielectric material having embedded wiring structures in contact with the semiconductor substrate. Next, a second layer of dielectric material is formed over the first layer of dielectric material and over the at least one JJ structure. The second layer of dielectric material has embedded wiring contact structures and JJ contact structures.The wiring contact structures are in contact with the wiring structures, and the JJ contact structures are in contact with the JJ structures. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a cross-sectional view of an exemplary structure that can be used according to an embodiment of the present invention, wherein the exemplary structure comprises a conductive plate embedded in a semiconductor substrate. Fig. Figure 2 is a cross-sectional view of the exemplary structure of Fig. 1 after the formation of a first layer of a dielectric material on physically exposed surfaces of the semiconductor substrate and the conductive plate. Fig. Figure 3 is a cross-sectional view of the exemplary structure of Fig. 2 after forming through-holes through the first layer of a dielectric material, each through-hole physically exposing a surface of the conductive plate. Fig. Figure 4 is a cross-sectional view of the exemplary structure of Fig. 3 after forming a metal-containing layer in each of the through-holes and on a top surface of the first layer of a dielectric material. Fig. Figure 5 is a cross-sectional view of the exemplary structure of Fig. 4, after the metal-containing layer has been structured to provide metal-containing wiring structures on the first layer of a dielectric material. Fig. Figure 6 is a cross-sectional view of the exemplary structure of Fig. 5 after forming a space-filling dielectric material in a space located between the metal-containing wiring structures. Fig. Figure 7 is a cross-sectional view of the exemplary structure of Fig. 6 after forming a precursor material stack for JJs on this. Fig. Figure 8 is a cross-sectional view of the exemplary structure of Fig. 7 after converting the precursor material stack for JJs into a JJ material stack. Fig. Figure 9 is a cross-sectional view of the exemplary structure of Fig. 8, after the JJ material stack has been structured to form a plurality of JJ structures, each JJ structure of the plurality of JJ structures being located on a surface of a metal-containing wiring structure that is not in direct contact with the conductive plate. Fig. Figure 10 is a cross-sectional view of the exemplary structure of Fig. 9 after forming a dielectric spacer that encapsulates each JJ structure. Fig. Figure 11 is a cross-sectional view of the exemplary structure of Fig. 10 after forming a second layer of a dielectric material laterally adjacent to and over each JJ structure encapsulated by the dielectric spacer. Fig. Figure 12 is a cross-sectional view of the exemplary structure of Fig. 11 after the formation of a plurality of contact openings in the second layer made of a dielectric material. Fig. Figure 13 is a cross-sectional view of the exemplary structure of Fig. 12 after forming a metal-containing contact structure in each of the contact openings. Fig. Figure 14 is a cross-sectional view of another exemplary structure that can be used according to an embodiment of the present invention, wherein the further exemplary structure comprises a conductive plate embedded in a semiconductor substrate. Fig. Figure 15 is a cross-sectional view of the exemplary structure of Fig. 14 after forming a stack of JJ material on the semiconductor substrate and the conductive plate. Fig. Figure 16 is a cross-sectional view of the exemplary structure of Fig. 15, after the JJ material stack was structured to provide a JJ structure on the conductive plate. Fig. Figure 17 is a cross-sectional view of the exemplary structure of Fig. 16 after forming a dielectric spacer that encapsulates the JJ structure. Fig. Figure 18 is a cross-sectional view of the exemplary structure of Fig. 17 after the formation of a first layer of a dielectric material laterally adjacent to the JJ structure encapsulated by the dielectric spacer. Fig. Figure 19 is a cross-sectional view of the exemplary structure of Fig. 18 after forming openings in the first layer of a dielectric material, each opening physically exposing a surface of the semiconductor substrate. Fig. Figure 20 is a cross-sectional view of the exemplary structure of Fig. 19 after forming metal-containing wiring structures in each of the openings. Fig. Figure 21 is a cross-sectional view of the exemplary structure of Fig. 20 according to forming a second layer of a dielectric material on the first layer of a dielectric material, wherein the second layer of a dielectric material has a plurality of contact structures embedded in it. DETAILED DESCRIPTION

[0010] Embodiments of the present invention will now be described in more detail with reference to the following discussion and the accompanying drawings. It should be noted that the drawings are provided for illustrative purposes only and are therefore not drawn to scale. It should also be noted that identical and corresponding elements are designated with the same reference numerals.

[0011] The following description presents numerous specific details, such as special structures, components, materials, dimensions, process steps, and techniques, to facilitate understanding of the various embodiments of the present invention. However, a person skilled in the art is aware that the various embodiments of the present invention can be carried out without these specific details. In other cases, generally known structures or process steps have not been described in detail to avoid obscuring the present invention.

[0012] It is understood that when an element, such as a layer, area, or substrate, is referred to as being "on" or "above" another element, it may be located directly on top of the other element, or there may be elements in between. Conversely, when an element is referred to as being "directly on" or "directly above" another element, there are no elements in between. It is also understood that when an element is referred to as being "below" or "under" another element, it may be located directly below or directly beneath the other element, or there may be elements in between. Conversely, when an element is referred to as being "directly below" or "directly under" another element, there are no elements in between.

[0013] First, attention will be drawn to the Fig. Reference is made to Figures 1 to 13, which describe a first method of the present invention that can be used in providing a data processing unit containing a magnetic control unit within a chip located near a JJ structure. In this embodiment of the present invention, a conductive plate is embedded in a semiconductor substrate. Wiring structures are then formed over the conductive plate. In this embodiment, some of the wiring structures are in direct contact with the conductive plate, while other wiring structures are not in contact with the conductive plate. A JJ structure is then formed over each wiring structure that is not in contact with the conductive plate. Next, contact structures are formed.Some of the contact structures are in contact with the wiring structures that are directly in contact with the conductive plate, while other contact structures are in contact with the JJ structures. Together, in this embodiment, the conductive plate and the wiring structures connected to the conductive plate serve as a unit for magnetic control, each located near a JJ structure.

[0014] In this embodiment, the conductive plate can generate a magnetic field by passing a current through the wiring structures; a magnetic field can also be generated by the wiring structures themselves, but such a magnetic field is negligible compared to the magnetic field generated by the conductive plate. The strength of the magnetic field can be modulated by the amount of current flowing through the wiring structures. Furthermore, the magnetic field can be switched off when required by stopping the current from flowing through the wiring structures.

[0015] Firstly, referring to Fig. Figure 1 shows an exemplary structure that can be used according to one embodiment of the present invention. The exemplary structure of Fig. 1 has a conductive plate 12 embedded in a semiconductor substrate 10. In particular, the conductive plate 12 is located in a groove formed in the semiconductor substrate 10 such that the semiconductor substrate 10 is laterally adjacent to and below the conductive plate 12.

[0016] The semiconductor substrate 10, which can be used in embodiments of the present invention, comprises at least one semiconductor material with semiconducting properties. Examples of semiconductor materials that can provide the semiconductor substrate 10 include, for example, silicon (Si), germanium (Ge), silicon-germanium alloys (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), III-V compound semiconductors, or II-VI compound semiconductors. III-V compound semiconductors are materials that contain at least one element from Group III of the periodic table and at least one element from Group V of the periodic table. II-VI compound semiconductors are materials that contain at least one element from Group II of the periodic table and at least one element from Group VI of the periodic table.

[0017] The semiconductor substrate 10 can be a single-crystal semiconductor material. The semiconductor substrate 10 can have any of the generally known crystal orientations. For example, the crystal orientation of the semiconductor substrate 10 can be {100}, {110}, or {111}. In embodiments of the present invention, crystallographic orientations other than those specifically mentioned can also be used.

[0018] In some embodiments, the semiconductor substrate 10 is a bulk semiconductor substrate, i.e., a substrate consisting entirely of at least one semiconductor material. In other embodiments, the semiconductor substrate 10 is a semiconductor-on-insulator (SOI) comprising a handling substrate, a buried insulator layer, and an upper layer of a semiconductor material. In such an embodiment, the conductive plate 12 may be formed only within the upper layer of a semiconductor, or within the upper layer of a semiconductor and the buried insulator layer, or within the upper layer of a semiconductor material, the buried insulator layer, and the handling substrate.

[0019] As mentioned above, the conductive plate 12 is located in a trench formed in the semiconductor substrate 10. The trench can be formed by a structuring process. In one embodiment, the structuring process comprises lithography and etching. The lithography comprises: forming a photoresist material on a material or stack of materials that needs to be structured (e.g., on the semiconductor substrate 10), exposing the photoresist material with a desired irradiation pattern, and developing the exposed photoresist using a conventional resist developer. The etching process, which is used to transfer the structure from the developed photoresist material to the semiconductor substrate 10, can be isotropic or anisotropic. In one embodiment, reactive ion etching (RIE) is used in the structuring process.The developed resist is usually removed from the structure after the etching process for structure transfer using a conventional resist removal process, such as ashing.

[0020] The trench can have numerous shapes. In one example, the trench can have a cylindrical shape. In some embodiments, the trench can have a depth of 100 nm to 500 nm, measured from the uppermost surface of the semiconductor substrate 10 to the bottom wall of the trench; although other trench depths are possible and can be used in embodiments of the present invention.

[0021] Although a single trench is described and illustrated herein, a plurality of spaced-apart trenches can be formed in the semiconductor substrate 10, and subsequently a conductive plate 12 can be formed in each of the trenches of the plurality of trenches.

[0022] Then, a conductive plate 12 is formed in each trench. The conductive plate 12 can be formed by a deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering, or plating. The deposition of a material for the conductive plate can be followed by a planarization process, such as chemical-mechanical polishing (CMP).

[0023] In some embodiments, the conductive plate 12 may be made of an electrically conductive, metal-containing material. Examples of electrically conductive, metal-containing materials that may be used for the conductive plate 12 include, but are not limited to, copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), or a copper-aluminum alloy. In some embodiments, the conductive plate 12 may be made of a superconductor. A superconductor is an element or metallic alloy in which, upon cooling below a certain threshold temperature, the material abruptly loses all electrical resistance. A superconductor allows an electric current to flow without any significant energy loss.Examples of superconductors that can be used for the conductive plate 12 include, but are not limited to, molybdenum (Mo), niobium (N), osmium (Os), rhenium (Re), rhodium (Rh), ruthenium (Ru), an Nb-Ti alloy or zirconium nitride (ZrN).

[0024] The conductive plate 12 has the same shape as the trench. In one example, the conductive plate 12 has a cylindrical shape. In some embodiments, the conductive plate 12 may have a top surface that is coplanar with the top surface of the semiconductor substrate 10. In other embodiments, the conductive plate 12 has a top surface that is located either above or below the top surface of the semiconductor substrate 10.

[0025] Now referring to Fig. 2 is the exemplary structure of Fig. Figure 1 shows the formation of a first layer 14 of a dielectric material on physically exposed surfaces of the semiconductor substrate 10 and the conductive plate 12. The first layer 14 of dielectric material is a continuous layer which comprises the entirety of the Fig. The exemplary structure shown in Figure 1 is covered. The first layer 14 of a dielectric material can consist of any dielectric material, such as silicon dioxide, silicon nitride, or silicon oxynitride. In some embodiments, the first layer 14 of a dielectric material consists entirely of a single dielectric material. In other embodiments, the first layer 14 of a dielectric material consists of a stack of two or more dielectric materials. The first layer 14 of a dielectric material can be formed using a deposition process, such as CVD or PECVD. The first layer 14 of a dielectric material can have a thickness of 10 nm to 100 nm; although other thicknesses are possible, and the thickness of the first layer 14 can be determined by comparing different thicknesses.

[0026] Layer 14 can be made of a dielectric material.

[0027] Now referring to Fig. 3 is the exemplary structure of Fig. Figure 2 shows a process by forming through-holes 16 through the first layer 14 of a dielectric material, each through-hole 16 physically exposing a surface of the conductive plate 12. In the illustrated embodiment, a pair of through-holes 16 is shown as an example. Each through-hole 16 can be formed by lithography and etching, as defined above. The resist used for structuring the first layer 14 of a dielectric material is detached from the exemplary structure after the etching process for structure transfer.

[0028] Now referring to Fig. 4 is the exemplary structure of Fig. Figure 3 shows the formation of a metal-containing layer 18 in each of the through-holes 16 and on a top surface of the first layer 14 made of a dielectric material. The metal-containing layer 18 can consist of one of the electrically conductive, metal-containing materials or of one of the superconductors mentioned above for the conductive plate 12. In one embodiment, the metal-containing layer 18 consists of a material with the same composition as the conductive plate 12. For example, the metal-containing layer 18 and the conductive plate 12 can both consist of copper. In another embodiment, the metal-containing layer 18 consists of a material that differs in composition from that of the conductive plate 12. For example, the metal-containing layer 18 can consist of nitrocellulose (Nb), and the conductive plate 12 can consist of copper.

[0029] The metal-containing layer 18 can be formed by a deposition process, including, for example, CVD, PECVD, sputtering, or plating. The metal-containing layer 18 has a thickness sufficient to fill each through-hole 16 and to extend above a top surface of the first layer 14 made of a dielectric material.

[0030] Now referring to Fig. 5 is the exemplary structure of Fig. Figure 4 shows the metal-containing layer 18 being structured to provide metal-containing wiring structures 18P on the first layer 14 of a dielectric material. As shown, some of the metal-containing wiring structures 18P include a lower through-contact area 18V that is in direct contact with a surface of the underlying conductive plate 12, while other metal-containing structures 18P do not include the lower through-contact area 18V. The metal-containing wiring structures 18P that include a lower through-contact area 18V can be referred to as a first wiring structure or a combined lead-through-contact wiring structure, while the metal-containing wiring structures 18P that do not include the lower through-contact area 18V can be referred to as a second wiring structure or a lead-through-contact wiring structure.

[0031] Structuring the metal-containing layer 18 includes lithography and etching, as defined above. As in Fig. As shown in Figure 5, there is a space 19 between each of the metal-containing wiring structures 18P. As also shown in Figure 5, there is a gap 19 between each of the metal-containing wiring structures 18P. Fig. As shown in Figure 5, each of the first wiring structures (18P / 18V) is located laterally adjacent to an area containing the second wiring structures 18P.

[0032] Now referring to Fig. 6 is the exemplary structure of Fig. Figure 5 shows the formation of a space-filling dielectric material 20 in the space 19 located between the metal-containing wiring structures 18P. The space-filling dielectric material 20 can comprise any dielectric material, including one of the dielectric materials mentioned above for the first layer 14 made of a dielectric material. In one embodiment, the space-filling dielectric material 20 comprises a dielectric material that is the same in composition as the dielectric material provided by the first layer 14 made of a dielectric material.In another embodiment, the space-filling dielectric material 20 consists of a dielectric material that differs in composition from the dielectric material provided by the first layer 14 made of a dielectric material.

[0033] The space-filling dielectric material 20 can be formed by depositing a dielectric material into each space 19 and optionally on top of each metal-containing wiring structure 18P. The dielectric material providing the space-filling dielectric material 20 can be deposited by CVD, PECVD, or PVD. In some embodiments, the deposition of the dielectric material providing the space-filling dielectric material 20 can be followed by a planarization process, such as CMP.

[0034] The gap-filling dielectric material 20 completely fills each gap 19, and the gap-filling dielectric material 20 typically has a top surface that is coplanar with a top surface of each metal-containing wiring structure 18P.

[0035] Now referring to Fig. 7 is the exemplary structure of Fig. 6 after forming a precursor material stack MS1 for JJs shown on this. In some embodiments and as in Fig. As shown in Figure 7, a metal-containing cover layer 28 can be formed on a top surface of the precursor material stack MS1 for JJs. At this point, the precursor material stack for JJs is not an active JJ structure. The precursor material stack MS1 for JJs comprises, from bottom to top, a first layer 22 of a superconducting material, a layer 24 containing amorphous silicon-manganese (aSi-Mn), and a second layer 26 of a superconducting material. Although aSi-Mn is specifically described and illustrated as layer 24, the present invention considers embodiments in which layer 24 is an aX-M layer, where X is a semiconductor material, such as Si, Ge, or SiGe, and M is a magnetic material, such as Co, Ni, Fe, Mn, or any combination thereof.

[0036] The first layer 22 of a superconducting material can be any of the superconducting materials mentioned above for the conductive plate 12. The first layer 22 of a superconducting material can be composed of a superconducting material that is the same in composition as the superconducting material that can be used for the conductive plate 12 and / or the metal-containing wiring structures 18P, or that differs in composition from it. The first layer 22 of a superconducting material can be formed by a deposition process, including, for example, CVD, PECVD, sputtering, plating, or ALD. The first layer 22 of a superconducting material can have a thickness of 5 nm to 50 nm, although other thicknesses are being considered and may be used for the first layer 22 of a superconducting material.

[0037] The aSi-Mn layer 24 consists of amorphous silicon with manganese (Mn) incorporated into it. The Mn content within the aSi-Mn layer 24 can range from 15 atomic percent to 60 atomic percent. The aSi-Mn layer 24 can be formed by first depositing a layer of amorphous silicon and then incorporating Mn into the amorphous silicon layer using techniques such as plasma doping or diffusion into the amorphous silicon layer. Alternatively, the aSi-Mn layer 24 can be formed using an in-situ deposition process. The aSi-Mn layer 24 is a thin layer with a thickness of 1 nm to 50 nm. This thickness allows for the transfer of electrons between the first and second superconducting materials. If sufficient Mn is present in the aSi-Mn layer 24 to create a normal conductor, then the thickness of the aSi-Mn layer 24 can be greater than the area mentioned above.

[0038] The second layer 26 of a superconducting material can be one of the superconducting materials mentioned above for the conductive plate 12. The second layer 26 of a superconducting material can consist of a superconducting material that is the same in composition as the superconducting material that can be used for the first layer 22 of a superconducting material and / or for the conductive plate 12 and / or for the metal-containing wiring structures 18P, or that differs in composition from it. The second layer 26 of a superconducting material can be formed by a deposition process, including, for example, CVD, PECVD, sputtering, plating, or ALD.The second layer 26 made of a superconducting material can have a thickness of 5 nm to 50 nm, although other thicknesses for the second layer 26 made of a superconducting material are being considered and can be used for the second layer 26 made of a superconducting material.

[0039] The metal-containing top layer 28 can optionally be formed on the precursor material stack MS1 for JJs. The metal-containing top layer 28 can consist of Ti, Ta, TiN, TaN, W, WN, or any other high-melting-point metals or conductive metal nitrides. The metal-containing top layer 28 can consist of a single material or a multilayer material stack. The metal-containing top layer 28 can be formed by a deposition process, including, for example, CVD, PECVD, sputtering, plating, or ALD. The metal-containing top layer 28 can have a thickness of 5 nm to 50 nm, although other thicknesses are being considered and may be used for the metal-containing top layer 28.

[0040] Now referring to Fig. 8 is the exemplary structure of Fig. Figure 7 shows the conversion of the predecessor material stack MS1 for JJs into a JJ material stack MS2. The JJ material stack MS2 is active after the conversion step. In the conversion step, the aSi-Mn layer 24 is converted into a crystalline silicon layer 25 containing Mn nanoparticles (i.e., into a layer of crystalline silicon containing Mn nanoparticles dispersed within it; generally, in the conversion step, an aX-M material, where X is a semiconductor material such as Si, Ge, or SiGe, and M is a magnetic material such as Co, Ni, Fe, Mn, or any combination thereof, is converted into a crystalline X layer containing M nanoparticles, where M and X are defined as above. The first and second layers 22, 26 of a superconducting material remain unchanged during the conversion. The conversion involves a low-oxygen annealing process (i.e., 10 -7 up to 10-19 The tempering process can be carried out at a temperature of 300 °C to 500 °C. The pressure during the tempering process can range from 2 Torr to 150 Torr. The tempering process is usually carried out in hydrogen (H₂). In some embodiments, an inert environment such as helium (He), argon (Ar), or nitrogen (N₂) can be used. In still other embodiments, tempering can be performed under vacuum. The tempering process can involve furnace tempering, laser tempering, or microwave tempering. The duration of the tempering process varies depending on the type of tempering process used. Generally, furnace tempering is carried out for a longer period than laser or microwave tempering.

[0041] In some embodiments, and if not previously formed, the metal-containing top layer 28, as defined above, can be formed on the JJ material stack MS2. Alternatively, the formation of the metal-containing top layer 28 can be omitted entirely from the process.

[0042] Now referring to Fig. 9 is the exemplary structure of Fig. Figure 8 shows the JJ material stack MS2 after it has been structured to form a plurality of JJ structures, which are designated as JJ in the drawings, wherein each JJ structure of the plurality of JJ structures is located on a surface of a metal-containing wiring structure 18P (e.g., on the second wiring structure) that is not in direct contact with the conductive plate 12. During the structuring of the JJ material stack MS2, the metal-containing cover layer 28 is also structured, if present. Although a plurality of JJ structures are described and shown, the present invention also works when a single JJ structure is formed on a single second metal-containing wiring structure 18P.

[0043] The structuring process includes lithography and etching. The etching is typically anisotropic, such as RIE, ion beam etching, or plasma etching. Each JJ structure has a remaining (i.e., unetched) region of the first layer 22 of a superconducting material (referred to below as a first region 22P of a superconducting material), a remaining (i.e., unetched) region of layer 25 of crystalline silicon containing Mn nanoparticles (referred to below as a region 25P of crystalline silicon containing Mn nanoparticles), and a remaining (unetched) region of the second layer 26 of a superconducting material (referred to below as a second region 26P of a superconducting material).If the metal-containing cover layer 28 is present, there is a remaining (unetched) area of ​​the metal-containing cover layer 28 on top of each JJ structure (referred to below as a metal-containing cover 28P).

[0044] Each JJ structure and, if present, each metal-containing cover 28P can have a cylindrical shape (although other shapes are possible) and has a critical dimension (CD) that is usually, but not necessarily always, smaller than the underlying CD of the surface of a metal-containing wiring structure 18P that is not in direct contact with the conductive plate 12. As shown, the various elements (22P, 25P, 26P) of the JJ structure each have an outermost sidewall oriented perpendicular to each other. If present, the metal-containing cover 28P has an outermost sidewall oriented perpendicular to the outermost sidewall of the underlying JJ structure. As shown, the first wiring structures (18P / 18V) are laterally adjacent to the area containing the JJ structures.

[0045] Now referring to Fig. 10 is the exemplary structure of Fig. Figure 9 shows the formation of a dielectric spacer 30 that encapsulates each JJ structure. The dielectric spacer 30 consists of a dielectric material that differs in composition from the space-filling dielectric material 20. In some embodiments, the dielectric material providing the dielectric spacer 30 can provide passivation for the JJ structure.

[0046] In one embodiment, the dielectric spacer 30 is made of silicon nitride. In another embodiment, the dielectric spacer 30 can be made of a dielectric material containing atoms of silicon, carbon, and hydrogen. In some embodiments, and in addition to the atoms of carbon and hydrogen, the dielectric material providing the dielectric spacer 30 can contain atoms of at least one of nitrogen and oxygen. In other embodiments, and in addition to the atoms of silicon, nitrogen, carbon, and hydrogen, the dielectric material providing the dielectric spacer 30 can contain atoms of boron. In one example, the dielectric spacer 30 can be made of a dielectric nBLOK material containing atoms of silicon, carbon, hydrogen, nitrogen, and oxygen.In an alternative example, the dielectric spacer 30 can consist of a dielectric SiBCN material containing atoms of silicon, boron, carbon, hydrogen and nitrogen.

[0047] The dielectric spacer 30 can be formed by first depositing a continuous layer of the dielectric material that provides the dielectric spacer 30. The deposition of the dielectric material providing the dielectric spacer 30 is followed by etching of the spacer, for example by RIE. The dielectric spacer 30 can have a thickness of 10 nm to 200 nm. Other thicknesses are possible and can be used for the thickness of the dielectric spacer. The dielectric spacer 30 typically has a top surface that is coplanar with a top surface of the metal-containing cover 28P, or, if the metal-containing cover 28P is not present, with a top surface of the JJ structure.Although the dielectric spacer 30 is shown to have the shape of an I, the dielectric spacer 20 may have the shape of an L and may extend onto exposed surfaces of the metal-containing wiring structure 18P and / or the space-filling dielectric material 20.

[0048] Now referring to Fig. 11 is the exemplary structure of Fig. Figure 10 shows the formation of a second layer 32 of a dielectric material laterally adjacent to and above each JJ structure encapsulated by the dielectric spacer 30. The second layer 32 of a dielectric material can consist of one of the dielectric materials mentioned above for the first layer 14 of a dielectric material; the dielectric material providing the second layer 32 of a dielectric material usually differs in composition from the dielectric material providing the dielectric spacer 30.The second layer 32 made of a dielectric material can also consist of a dielectric interlayer material, such as undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a low k-dielectric spin-on layer, a low k-dielectric layer produced by chemical vapor deposition (CVD), or any combination thereof. The term "low k," as used herein, refers to a dielectric material having a dielectric constant of less than 4.0 (all dielectric constants are measured in a vacuum unless otherwise specified herein). In another embodiment, the dielectric material for the second layer 32 made of a dielectric material can be a self-planarizing material, such as a spin-on glass (SOG) or a low k-dielectric spin-on material.The second layer 32, made of a dielectric material, can be formed using a deposition process, such as CVD, PECVD or a spin-on coating.

[0049] Now referring to Fig. 12 is the exemplary structure of Fig. Figure 11 shows the formation of a plurality of contact openings (34Z, 34Y) in the second layer 32 made of a dielectric material. The plurality of contact openings can be formed by lithography and etching. Each contact opening 34Z physically exposes a surface of one of the metal-containing wiring structures 18P, which contain the lower through-contact region 18V, while each contact opening 34Y physically exposes either a top surface of one of the metal-containing covers 28P or the top surface of one of the second regions 26P made of a superconducting material. Contact openings 34Z can be referred to as wiring contact openings, while contact openings 34Y can be referred to as JJ-structure contact openings.

[0050] Now referring to Fig. 13 is the exemplary structure of Fig. Figure 12 shows the formation of a metal-containing contact structure (36Y, 36Z) in each of the contact openings (34Y, 34Z). Each metal-containing contact structure (36Y, 36Z) can consist of a contact metal or a contact metal alloy. Examples of contact metals include, but are not limited to, tungsten (W), aluminum (Al), or copper (Cu). An example of a contact metal alloy is a Cu-Al alloy. In some embodiments, a superconductor can be used in providing each metal-containing contact structure (36Y, 36Z), as described above. Superconductors may be a preferred material for the contact structures (36Y, 36Z) because they reduce power consumption and heating of the chip.As shown, each metal-containing contact structure (36Y, 36Z) has a top surface that is coplanar with a top surface of the second layer 32 made of a dielectric material.

[0051] Each metal-containing contact structure (36Y, 36Z) can be formed by filling the contact openings with a conductive material that provides the metal-containing contact structures (36Y, 36Z). In some embodiments, the filling of the contact openings with the conductive material that provides the metal-containing contact structures (36Y, 36Z) can be followed by a planarization process.

[0052] In some embodiments of the present invention, each metal-containing contact structure 36Z is in contact with a surface of one of the metal-containing wiring structures 18P, which includes the lower through-contact region 18V; each metal-containing contact structure 36Y is in contact with a top surface of one of the metal-containing covers 28P or the top surface of one of the second regions 26P made of a superconducting material. The metal-containing contact structure 36Z can be referred to as a wiring contact structure, while each metal-containing contact structure 36Y can be referred to as a JJ contact structure.

[0053] First, attention will be drawn to the Fig. Reference is made to references 14 to 21, which describe a second method of the present invention that can be used in providing a data processing unit containing a magnetic control unit within a chip located near a JJ structure. In this embodiment of the present invention, a conductive plate is embedded in a semiconductor substrate, and at least one JJ structure is formed on a surface of the conductive plate. Wiring structures are then formed laterally adjacent to the at least one JJ structure and are in contact with a surface of the semiconductor substrate. Next, contact structures are formed. Some of the contact structures are in contact with the wiring structures that are directly in contact with the semiconductor substrate, while other contact structures are in contact with the JJ structures.In this embodiment, the wiring structures, not the conductive plate, serve as a unit for magnetic control located near the JJ structure. In this embodiment, the conductive plate acts as a wiring structure for the JJ structure.

[0054] In this embodiment, the magnetic field is generated by the wiring structures, not by the conductive plate, by passing a current through the wiring structures. The strength of the magnetic field can be modulated by the amount of current flowing through the wiring structures. Furthermore, the magnetic field can be switched off when required by stopping the current from flowing through the wiring structures.

[0055] Firstly, referring to Fig. Figure 14 shows another exemplary structure that can be used according to one embodiment of the present invention. This exemplary structure of Fig. 14 comprises a conductive plate 52 embedded in a semiconductor substrate 50. The semiconductor substrate 50 and the conductive plate 52 for this embodiment of the present invention are the same as the semiconductor substrate 10 and the conductive plate 12, respectively, for the embodiment described above. Fig. 1. The embodiment shown. As stated above, the conductive plate 52 of this embodiment is not used to generate a magnetic field, but is instead used as a wiring structure for the JJ structure.

[0056] Now referring to Fig. 15 is the exemplary structure of Fig. Figure 14 shows the formation of a JJ material stack MS2 on the semiconductor substrate 50 and the conductive plate 52. The JJ material stack MS2 of this embodiment comprises a first layer 22 of a superconducting material as defined above, a layer 25 of crystalline silicon containing Mn nanoparticles as defined above, and a second layer 26 of a superconducting material as defined above. It should be noted that instead of the crystalline silicon containing Mn nanoparticles, other crystalline semiconductor materials containing M nanoparticles as defined above may be used. The JJ material stack MS2 of this embodiment can be formed using the process steps mentioned above for the formation of the JJ material stack (see, for example, the preceding description regarding the Fig. 7 to 8). In some embodiments, a metal-containing top layer 28, as defined above, is present on the JJ material stack MS2. In other embodiments, the metal-containing top layer 28 is not present on the JJ material stack MS2.

[0057] Now referring to Fig. 16 is the exemplary structure of Fig. Figure 15 shows the JJ material stack MS2 after it has been structured to provide a JJ structure on the conductive plate 52. The structuring of the JJ material stack MS2 in this embodiment is the same as the structuring of the JJ material stack MS2 in the previous embodiment of the present invention (see Figure 15). Fig. 9 and the preceding discussion regarding Fig. 9) Each JJ structure has a remaining (i.e., unetched) region of the first layer 22 of a superconducting material (hereinafter referred to as a first region 22P of a superconducting material), a remaining (i.e., unetched) region of layer 25 of crystalline silicon containing Mn nanoparticles (hereinafter referred to as a region 25P of crystalline silicon containing Mn nanoparticles), and a remaining (unetched) region of the second layer 26 of a superconducting material (hereinafter referred to as a second region 26P of a superconducting material). If the metal-containing cover layer 28 is present, a remaining (unetched) region of the metal-containing cover layer 28 is present on top of each JJ structure (hereinafter referred to as a metal-containing cover layer 28P).

[0058] Each JJ structure and, if present, each metal-containing cover 28P can have a cylindrical shape (although other shapes are possible) and has a CD that is usually, but not necessarily always, smaller than the underlying CD of the surface of a conductive plate 52. As shown, the various elements (22P, 25P, 26P) of the JJ structure each have an outermost sidewall oriented perpendicular to each other. If present, the metal-containing cover 28P has an outermost sidewall oriented perpendicular to the outermost sidewall of the underlying JJ structure.

[0059] Now referring to Fig. 17 is the exemplary structure of Fig. Figure 16 shows a dielectric spacer 30 forming a structure that encapsulates the JJ structure. The dielectric spacer 30 of this embodiment is the same as the dielectric spacer 30 mentioned above. See, for example, the preceding discussion regarding Fig. 10.

[0060] Now referring to Fig. 18 is the exemplary structure of Fig. Figure 17 shows the formation of a first layer 54 of a dielectric material laterally adjacent to the JJ structure encapsulated by the dielectric spacer. The first layer 54 of a dielectric material in this embodiment of the present invention can consist of one of the dielectric materials mentioned above for the first layer 14 of a dielectric material. Alternatively, the first layer 54 of a dielectric material in this embodiment can also consist of a dielectric interlayer material, such as undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a low k-dielectric spin-on layer, a low k-dielectric layer produced by chemical vapor deposition (CVD), or any combination thereof.The term “low k”, as used herein, denotes a dielectric material having a dielectric constant of less than 4.0 (all dielectric constants are measured in a vacuum unless otherwise stated herein). In another embodiment, a self-planarizing material, such as a spin-on glass (SOG) or a dielectric spin-on material with a low k, may be used as the dielectric material for the first layer 54 of a dielectric material.

[0061] The first layer 54 of a dielectric material can be formed using a deposition process, such as CVD, PECVD, or a spin-on coating. The deposition of the dielectric material providing the first layer 54 can be followed by a planarization process, such as CMP, or a back-etching process. The first layer 54 of a dielectric material has a top surface that is coplanar with either the top surface of the first layer 54 of a dielectric material or, if the first layer 54 is a dielectric material, with the top surface of the second region 26P of a superconducting material.

[0062] Now referring to Fig. 19 is the exemplary structure of Fig. Figure 18 shows the formation of openings 56 in the first layer 54 of a dielectric material, wherein each opening 56 physically exposes a surface of the semiconductor substrate 50. The openings 56 can be formed by lithography and etching, as defined above.

[0063] Now referring to Fig. 20 is the exemplary structure of Fig. Figure 19 shows a metal-containing wiring structure 58 formed in each of the openings 56. Each metal-containing wiring structure 58 can comprise one of the electrically conductive metals, electrically conductive metal alloys, or superconducting materials mentioned above for the conductive plate 12. Each metal-containing wiring structure 58 can be made of a material that is the same in composition as the material that provides the conductive plate 52 or that differs in composition from it. A pair of metal-containing wiring structures 58 is shown as an example.

[0064] Each metal-containing wiring structure 58 can be formed by depositing an electrically conductive metal, an electrically conductive metal alloy, or a superconducting material using one of the deposition processes mentioned above for forming the conductive plate 12. The deposition of the material providing the metal-containing wiring structure 58 may be followed by a planarization process, such as CMP. Each metal-containing wiring structure 58 has a top surface that is usually, but not necessarily always, coplanar with a top surface of the first layer 54 made of a dielectric material. As shown, the metal-containing wiring structures 58 are located laterally adjacent to the region containing the JJ structure.

[0065] Now referring to Fig. 21 is the exemplary structure of Fig.20 shown after forming a second layer 60 of a dielectric material on the first layer 54 of a dielectric material, wherein the second layer 60 of a dielectric material has a plurality of contact structures (62Y, 62Z) embedded in it.

[0066] The second layer 60 of a dielectric material in this embodiment of the present invention can comprise one of the dielectric materials mentioned above for the first layer 54 of a dielectric material. The second layer 60 of a dielectric material can consist of a dielectric material that is the same in composition as the dielectric material provided by the first layer 54 of a dielectric material, or that differs from it in composition. The second layer 60 of a dielectric material can be formed using one of the deposition processes mentioned above for forming the first layer 54 of a dielectric material.

[0067] The majority of contact structures (62Y, 62Z) embedded in the second layer 60 of a dielectric material can be formed by first providing contact openings in the second layer 60 of a dielectric material, with some of the contact openings physically exposing the metal-containing wiring structures 58 and other contact openings physically exposing either a top surface of the metal-containing cover 28P or, if the metal-containing cover 38P is not present, a top surface of the second region 28P of a superconducting material of the JJ structure. The contact openings can be formed by lithography and etching.

[0068] Each metal-containing contact structure (62Y, 62Z) can consist of a contact metal or a contact metal alloy. Examples of contact metals include, but are not limited to, tungsten (W), aluminum (Al), or copper (Cu). An example of a contact metal alloy is a Cu-Al alloy. In some embodiments, a superconductor, as defined above, can be used in providing each metal-containing contact structure. Superconductors are a preferred material for the contact structures (62Y, 62Z) because they reduce power consumption and chip heating. As shown, each metal-containing contact structure (62Y, 62Z) has a top surface that is coplanar with a top surface of the second layer 60 made of a dielectric material.

[0069] Each metal-containing contact structure (62Y, 62Z) can be formed by filling the contact openings with a conductive material that provides the metal-containing contact structures (62Y, 62Z). In some embodiments, the filling of the contact openings with the conductive material that provides the metal-containing contact structures (62Y, 62Z) can be followed by a planarization process.

[0070] In embodiments of the present invention, each metal-containing contact structure 62Z is ​​in contact with a surface of one of the metal-containing structures 58, and each metal-containing contact structure 62Y is in contact with a top surface of one of the metal-containing covers 28P or the top surface of one of the second areas 26P made of a superconducting material. The metal-containing contact structure 62Z can be referred to as a wiring contact structure, while each metal-containing contact structure 62Y can be referred to as a JJ contact structure.

[0071] Although the present invention has been shown and described specifically with regard to preferred embodiments thereof, it is understood by those skilled in the art that the foregoing and further modifications with regard to shapes and details can be made without departing from the scope of the present invention. Therefore, the present invention is not intended to be limited to the exact shapes and details that have been described and illustrated, but is intended to fall within the scope of the appended claims.

[0072] In a preferred embodiment of the present invention, a method for forming a data processing unit is provided, wherein the method comprises: forming a conductive plate in a semiconductor substrate; forming at least one Josephson junction structure (a JJ structure) on the conductive plate; forming a first layer of a dielectric material laterally adjacent to the at least one JJ structure, wherein the first layer of a dielectric material has embedded wiring structures that are in contact with the semiconductor substrate;and forming a second layer of a dielectric material over the first layer of a dielectric material and over the at least one JJ structure, wherein the second layer of a dielectric material comprises wiring contact structures and JJ contact structures embedded therein, and wherein the wiring contact structures are in contact with the wiring structures and the JJ contact structures are in contact with the JJ structures. The formation of the JJ structure preferably comprises: forming a precursor material stack for JJs, comprising a first layer of a superconducting material, a layer of manganese-containing amorphous silicon, and a second layer of a superconducting material;Converting the precursor material stack for JJs into a JJ material stack, wherein the conversion includes annealing by which the layer of manganese-containing amorphous silicon is transformed into a layer of Mn nanoparticle-containing crystalline silicon; and structuring the JJ material stack. Prior to forming the second layer of a dielectric material, the process preferably further includes forming a dielectric spacer that encapsulates the JJ structure.

Claims

[1] Data processing unit comprising: a conductive plate (12; 52) embedded in a surface of a semiconductor substrate (10; 50); at least one Josephson junction structure, JJ structure, located above the conductive plate; and first wiring structures (18P, 18V; 58) laterally adjacent to the at least one JJ structure, wherein one of the conductive plate or the first wiring structures is configured to induce a magnetic field in the at least one JJ structure when an electric current is applied thereto, wherein: the at least one JJ structure comprises a first region (22P) made of a superconductor, a region (25P) made of crystalline silicon containing Mn nanoparticles, and a second region (26P) made of a superconductor material; and / or the at least one JJ structure has a cylindrical shape; and / or the first wiring structures (18p, 18V) are in direct contact with a surface of the conductive plate (12), wherein the at least one JJ structure is spaced from the conductive plate and the conductive plate induces the magnetic field in the at least one JJ structure. [2] The data processing unit of claim 1, wherein the at least one JJ pattern is located on a surface of a second wiring pattern that is laterally spaced from the first wiring patterns and vertically spaced from the conductive plate. [3] The data processing unit of claim 2, wherein the at least one JJ structure has a critical dimension that is less than a critical dimension of the second wiring structure. [4] The data processing unit according to claim 2, further comprising a wiring contact structure in contact with each first wiring structure and a JJ contact structure in contact with the at least one JJ structure. [5] The data processing unit according to claim 1, wherein the first wiring patterns are directly in contact with a surface of the semiconductor substrate, wherein the at least one JJ pattern is located on a surface of the conductive plate, and wherein the first wiring patterns induce the magnetic field. [6] The data processing unit according to claim 5, further comprising a wiring contact structure in contact with each first wiring structure and a JJ contact structure in contact with the at least one JJ structure. [7] The data processing unit according to claim 1, wherein the conductive plate is made of an electrically conductive metal, an electrically conductive metal alloy, or a superconductor material. [8] The data processing unit according to claim 1, wherein the first wiring structures are made of an electrically conductive metal, an electrically conductive metal alloy, or a superconductor material. [9] The data processing device of claim 1, further comprising a dielectric spacer encapsulating the at least one JJ structure. [10] The data processing unit of claim 1, further comprising a metal-containing cover (28P) located on the second region of a superconducting material of the at least one JJ structure. [11] A method for forming a data processing unit, the method comprising: Forming a conductive plate (12; 52) in a semiconductor substrate (10; 50); Forming a first layer (14) of a dielectric material on physically exposed surfaces of the semiconductor substrate and the conductive plate, the first layer of a dielectric material having through holes (16) that physically expose a surface of the conductive plate; Forming a metal-containing layer (18V) in each of the through holes and on a top surface of the first layer of dielectric material; Patterning the metal-containing layer to provide first and second metal-containing wiring structures (18P), wherein the first metal-containing wiring structures are in contact with the conductive plate and the second metal-containing wiring structures are spaced from the conductive plate; Forming a Josephson junction structure (a JJ structure) on every second metal-containing wiring structure; and Forming a second layer (32) of dielectric material laterally spaced from and over each JJ structure, the second layer of dielectric material having wiring contact structures (36Z) and JJ contact structures (36Y) embedded therein, the wiring contact structures being in contact with the first metal-containing wiring structures and the JJ contact structures being in contact with the JJ structures. [12] The method of claim 11, wherein forming the JJ structure comprises: Forming a precursor material stack for JJs comprising a first layer (22) of a superconductor material, a layer (24) of manganese-containing amorphous silicon, and a second layer (26) of a superconductor material; Converting the precursor material stack for JJs into a JJ material stack, wherein the converting comprises annealing to convert the layer of manganese-containing amorphous silicon into a layer of crystalline silicon containing Mn nanoparticles (25); and Structuring the JJ material stack. [13] The method of claim 11, further comprising, prior to forming the second layer of dielectric material, forming a dielectric spacer (30) encapsulating the JJ structure. [14] The method of claim 11, further comprising forming a gap-filling dielectric material (20) in spaces located between each first and second wiring structure.

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