Multifunctional data transfer interface to support shared workspace use between data processing systems

Abstract

Method for data transmission in a data processing environment (3800), wherein the method comprises: Configuring a data transfer interface of a second host data processing system (100b), wherein the data transfer interface comprises a first operating mode that supports connecting an attached functional unit (222) to the second host data processing system (100b), and a second operating mode that supports connecting a first host data processing system (100a) to the second host data processing system (100b) for shared host-to-host memory use, and wherein configuring the data transfer interface includes configuring the data transfer interface in the second operating mode to support shared host-to-host memory use; Receiving, from the first host data processing system (100a) at the data transmission interface of the second host data processing system (100b) a host instruction in a first instruction set, wherein the host instruction specifies a memory access to a memory (402b1) connected to the second host data processing system (100b), wherein both the first and the second host data processing system (100b) have a first and second coherent memory area respectively, and wherein the first and second coherent memory areas are not coherent with each other; Translating the host command into a second command in a different second command set, such that the first host data processing system (100a) emulates an attached functional unit (222) connected to the data transmission interface of the second host data processing system (100b); Transmission of the second command to a host bus protocol interface of the second host data processing system (100b), wherein the second host data processing system (100b) comprises a system structure to which a plurality of data transmission participants are connected; and Based on the receipt of the second Initiate command, through the host bus protocol interface on the system structure of the second host data processing system (100b), a host bus protocol memory access request is issued, specifying the memory access.

Description

BACKGROUND OF THE INVENTION

[0001] The present invention relates generally to data processing and in particular to an improved data transmission interface and a data transmission protocol for data transmission between data processing system components and data processing systems.

[0002] A conventional multiprocessor (MP) data processing system has multiple processing units (each of which may include one or more processor cores and their various cache memory), input / output (I / O) units, and data storage, which may include both system memory (volatile and / or non-volatile) and non-volatile mass storage. With increasingly sophisticated processor technology and the growing size of code and working data sets, system memory is becoming an increasingly significant overall cost driver for enterprise-class systems.As a result, data processing systems that support dynamic sharing of system memory by different data processing systems or sharing of large centralized "memory tanks" between data processing systems are increasingly favored because the cost per system for system memory can be reduced.

[0003] Some data processing systems support the sharing of system memory through dedicated hardware, which tends to be expensive (thus reducing or negating the benefit of shared memory) and poorly scalable as organizations grow. This application recognizes that it would be useful and desirable to extend existing data transfer interfaces of data processing systems to support system-to-system and / or system-to-centralized memory tank data transfer with minimal additional cost and complexity.

[0004] DE 10 2018 123 817 A1 discloses a method and a device for driverless access of a host to a non-volatile storage device via a PCIe connection, wherein a memory section of the storage device is mapped into the host memory and load / store instructions are executed under negotiation of a minimum transaction packet size.

[0005] DE 196 81 711 T5 discloses a method and a device for connecting a device compatible with a first bus protocol to an external bus.

[0006] US 2012 / 0023293A1 discloses a wireless communications device which, when connected to a host via USB, instructs the host to recognize the device as a USB mass storage device and simultaneously wirelessly transmits a device identifier to a communications network, whereupon the network restricts the communications service to a specific data storage system.

[0007] US 2020 / 0 226 070 A1 discloses a memory controller that receives original map data segments, stores them at source addresses, and converts them to destination addresses using a predefined offset in order to sequentially store the segments in destination memory areas.

[0008] US 2010 / 0268868A1 discloses a flash memory device comprising a controller and a working memory that stores linking tables that associate logical addresses with physical addresses, enabling the controller to translate logical addresses from the host into physical addresses and access the flash memory accordingly. SUMMARY

[0009] In at least one embodiment, a data transmission interface of a second host data processing system receives a host instruction in a first instruction set from a first host data processing system. The host instruction specifies a memory access to memory connected to the second host data processing system. The data transmission interface translates the host instruction into an instruction in a different second instruction set, which emulates connecting an attached functional unit to the data transmission interface. The data transmission interface displays the second instruction for a host bus protocol interface of the second host data processing system.Upon receiving the second command, the host bus protocol interface on a system structure of the second host data processing system initiates a host bus protocol memory access request specifying the memory access. As a result of this process, a host data processing system can utilize an existing data transmission interface suitable for supporting the connection of an attached functional unit to shared host-to-host memory access.

[0010] In at least one embodiment, a page table entry for an address specified in the second instruction is fixed in a page frame table of the second host data processing system. The page table entry fixed in the page frame table allows for an asymmetry between the first and second instruction sets.

[0011] In at least one embodiment, the data transmission interface is a first data transmission interface, the second host data transmission system comprises a second data transmission interface, and the host command is a first host command. In such an embodiment, the second data transmission interface, upon receiving the host bus protocol memory access request on the system structure, issues a second host command specifying the memory access. In this way, the memory access request is transported via the system structure of the second host data processing system to an attached memory or third host data processing system connected to the second data transmission interface.

[0012] In at least one embodiment, the data transmission interface comprises a first operating mode that supports connecting an attached functional unit to the second host data processing system, and a second operating mode that supports connecting the first host data processing system to the second host data processing system for shared host-to-host memory access. In such an embodiment, the data transmission interface is configured in the second operating mode to support shared host-to-host memory access.

[0013] In at least one embodiment, a data transmission controller for a host data processing system with a system structure comprises a controller circuit. The controller circuit is configured to receive a host command in a first instruction set from another data processing system, wherein the host command specifies a memory access to memory connected to the host data processing system. The host command is translated by the controller circuit into a command in a different second instruction set, which emulates connecting an attached functional unit to the data transmission controller.The controller circuit represents the second command to a host bus protocol interface, which, based on the reception of the second command on the system structure of the host data processing system, initiates a host bus protocol memory access request specifying the memory access.

[0014] In at least one embodiment, the design structure is concretely embodied in a machine-readable storage unit for the design, manufacture, or testing of an integrated circuit. The design structure includes a data transfer controller for a host data processing system with a system structure. The data transfer controller comprises a controller circuit configured to receive a host instruction in a first instruction set from another data processing system. The host instruction specifies a memory access to memory connected to the host data processing system. The controller circuit translates the host instruction into an instruction in a different second instruction set, which emulates connecting an attached functional unit to the data transfer controller.The controller circuit represents the second command to a host bus protocol interface, which, based on the reception of the second command on the system structure of the host data processing system, initiates a host bus protocol memory access request specifying the memory access.

[0015] According to one aspect, a method for data transmission in a data processing environment is provided, wherein the method comprises: configuring a data transmission interface of a second host data processing system, wherein the data transmission interface comprises a first operating mode that supports connecting an attached functional unit to the second host data processing system, and a second operating mode that supports connecting a first host data processing system to the second host data processing system for shared host-to-host memory use, and wherein configuring the data transmission interface comprises configuring the data transmission interface in the second operating mode to support shared host-to-host memory use;Receiving, from the first host data processing system at the data transmission interface of the second host data processing system, a host instruction in a first instruction set, wherein the host instruction specifies a memory access to memory connected to the second host data processing system, wherein both the first and the second host data processing system have a first and second coherent memory area respectively, and wherein the first and second coherent memory areas are not coherent with each other; translating the host instruction into a second instruction in a different second instruction set such that the first host data processing system emulates an attached functional unit connected to the data transmission interface of the second host data processing system;Transmission of the second command to a host bus protocol interface of the second host data processing system, wherein the second host data processing system comprises a system structure to which a plurality of data transmission participants are connected; and, based on the receipt of the second command, initiating, through the host bus protocol interface on the system structure of the second host data processing system, a host bus protocol memory access request specifying the memory access.

[0016] According to another aspect, a data transmission controller is provided for a second host data processing system with a system structure to which a plurality of data transmission participants are connected, wherein the data transmission controller has: controller circuitry configured to perform: receiving, from a first host data processing system, a host command in a first command set, wherein the host command specifies a memory access to memory connected to the host data processing system, wherein both the first and the second host data processing system have a first and second coherent memory area respectively, and wherein the first and second coherent memory areas are not coherent with each other;Translating the host command into a second command in a different second command set, such that the first host data processing system emulates connecting an attached functional unit to the data transfer controller, wherein: the data transfer controller has a first operating mode that supports connecting an attached functional unit to the second host data processing system, and a second operating mode that supports connecting the second host data processing system to the first data processing system for host-to-host memory sharing; the controller circuitry is configured to perform the translation only based on a configuration of the data transfer controller in the second operating mode to support host-to-host memory sharing; transmitting the second command to a host bus protocol interface;and based on the receipt of the second Initiate command, through the host bus protocol interface on the system structure of the host data processing system, a host bus protocol memory access request specifying the memory access.

[0017] In one embodiment, the data transmission controller of the preceding paragraph is provided, wherein: the host bus protocol memory access command is a read command; the controller circuit is further configured to perform: receiving data from a system memory of the host data processing system, as specified by the host bus protocol memory access request; outputting, to the further data processing system, a read response comprising the data.

[0018] According to another aspect, a design structure, concretely embodied in a machine-readable storage unit, is provided for the design, manufacture, or testing of an integrated circuit, wherein the design structure comprises: a data transmission controller for a second host data processing system with a system structure to which a plurality of data transmission participants are connected, wherein the data transmission controller comprises: controller circuitry configured to perform: receiving, from a first data processing system, a host command in a first command set, wherein the host command specifies a memory access to a memory connected to the host data processing system.wherein both the first and second host data processing systems have a first and second coherent memory area, respectively, and wherein the first and second coherent memory areas are not coherent with each other; translating the host instruction into a second instruction in a different second instruction set such that the first host data processing system emulates an attached functional unit connected to the data transfer controller, wherein: the data transfer controller has a first operating mode that supports connecting an attached functional unit to the second host data processing system, and a second operating mode that supports connecting the second host data processing system to the first data processing system for host-to-host memory sharing; the controller circuit is configured,to perform the translation only based on a configuration of the data transmission controller in the second operating mode to support shared host-to-host memory usage; transmission of the second command to a host bus protocol interface; and, based on receiving the second command, initiating a host bus protocol memory access request through the host bus protocol interface on the system structure of the host data processing system, specifying the memory access.

[0019] According to a further embodiment, a system is provided comprising: the data transmission controller according to paragraph 16, wherein the data transmission controller is a first data transmission controller; a second data transmission controller of the second host data processing system, which is connected to the first data transmission controller of the second host data processing system, wherein the second data transmission controller comprises a controller circuit configured to perform: receiving the read response and translating the read response into a different second response set, which emulates an attached working memory connected to the second data transmission controller.

[0020] According to a further embodiment, a system is provided comprising: the data transmission controller according to paragraph 15; the host data processing system connected to the data transmission controller, wherein the host data processing system includes a system memory which stores a page frame table; wherein: the second command specifies an address; the host data processing system is configured to fix a page table entry for the address in the page frame table of the system memory.

[0021] According to a further embodiment, a system is provided comprising: the host command, which is a first host command; the data transmission controller according to paragraph 15, wherein the data transmission controller is a first data transmission controller; the second host data processing system connected to the data transmission controller, wherein the second host data processing system comprises a second data transmission controller, wherein the second data transmission controller, based on receiving the host bus protocol memory access request on the system structure, issues a second host command specifying the memory access. Brief description of the different views of the drawings

[0022] Preferred embodiments of the present invention are described below for illustrative purposes only and with reference to the following drawings: Fig. Figure 1 is an overview block diagram of an exemplary host data processing system according to one embodiment; Fig. Figure 2 is a more detailed block diagram of an exemplary processing unit of a host data processing system according to an embodiment; Fig. Figure 3 illustrates an exemplary protocol stack for a data transmission interface between a host data processing system and an attached functional unit or working memory (AFUM) according to one embodiment; Fig. Figure 4 presents an exemplary protocol stack for a data transmission interface configured to support the connection of a working memory unit to a host data processing system according to one embodiment; Fig. Figure 5 illustrates an exemplary protocol stack for a data transmission interface configured to support connection of an attached functional unit (AFU) to a host data processing system according to one embodiment; Fig. 6 is a time-space diagram of a read command of an AFU according to an embodiment; Fig. Figures 7 to 10 are time-space diagrams of different responses from a host data processing system to the read command of an AFU according to one embodiment; Fig. 11 is a time-space diagram of a write command of an AFU according to an embodiment; Fig. Figures 12 to 15 are time-space diagrams of different responses from a host data processing system to the write command of an AFU according to an embodiment; Fig. 16 is a logical overview flowchart of an exemplary procedure by which a host transaction layer of a host data processing system responds to a command from an AFU according to an embodiment; Fig. 17 is a logical overview flowchart of an exemplary procedure by which an AFU issues an AFUM command to a host data processing system and processes a host response according to an embodiment; Fig. Figure 18 is a time-space diagram of a read instruction issued by a host data processing system to an attached working memory according to one embodiment; Fig. Figures 19 to 20 are time-space diagrams of different responses from an attached working memory to the read command of a host data processing system according to one embodiment; Fig. Figure 21 is a time-space diagram of a write command issued by a host data processing system to an attached working memory according to one embodiment; Fig. Figures 22 to 23 are time-space diagrams of different responses from an attached working memory to the write command of a host data processing system according to one embodiment; Fig. 24 is a logical overview flowchart of an exemplary procedure by which a transaction layer serving an AFUM responds to a command from a host data processing system according to an embodiment; Fig. 25 is a logical overview flowchart of an exemplary procedure by which a host transaction layer of a host data processing system issues a command to an AFUM and processes an AFUM response according to an embodiment; Fig. 26 presents an exemplary protocol stack for a data transmission interface configured to support connecting one host data processing system to another host data processing system to enable shared memory use according to one embodiment; Fig. 27 is a more detailed block diagram of a Command, Control and Power and Response Translation (CCR XLATE) layer in the protocol stack of Fig. 26; Fig. 28 is a time-space diagram of a read command issued from a host data processing system to an attached host data processing system according to an embodiment; Fig. Figures 29 to 30 are time-space diagrams of different responses from an attached host processing system to the read command of another host data processing system according to one embodiment; Fig. Figure 31 is a time-space diagram of a write command issued from a host data processing system to an attached host data processing system according to one embodiment; Fig. Figures 32 to 33 are time-space diagrams of different responses from an attached host processing system to the write command of another host data processing system according to one embodiment; Fig. Figure 34 is a logical overview flowchart of an exemplary process for initializing data processing systems for shared memory use according to one embodiment; Fig. Figure 35 is a time-space diagram of a write command issued by an AFU to a host data processing system and an associated response from the host data processing system according to an embodiment implementing a fast write response mode; Fig. 36 is a logical overview flowchart of an exemplary procedure by which a host transaction layer of a host data processing system responds to an AFUM write command according to an embodiment; Fig. 37 is a time-space diagram of a write command issued from a host data processing system to another host data processing system and an associated write response according to an embodiment that implements a fast write response mode; Fig. Figure 38 is an overview block diagram of an exemplary topology of a data processing environment in which a plurality of host data processing systems are connected to allow sharing of the main memory of the host data processing systems and / or a main memory in a main memory facility according to an embodiment; Fig. 39 is a time-space diagram of a multi-hop read instruction issued by an initiating host data processing system to a receiving host data processing system via an intermediate host data processing system and an associated response according to an embodiment; Fig. 40 is a time-space diagram of a multi-hop write instruction issued by an initiating host data processing system to a receiving host data processing system via an intermediate host data processing system and an associated response according to an embodiment; Fig. 41 is a time-space diagram of a multi-hop read instruction issued by an initiating host data processing system to a receiving host data processing system via an intermediate host data processing system and an associated response according to a further embodiment; Fig. Figure 42 is a data flow diagram illustrating a design process according to one embodiment. DETAILED DESCRIPTION

[0023] With the following reference to the figures, in which the same reference numerals consistently refer to similar or corresponding parts, and in particular with reference to Fig. Reference 1 illustrates a block diagram depicting an exemplary data processing system 100 according to one embodiment. In various use cases and topologies, a data processing system such as the data processing system 100, which includes hardware components and may additionally include software and / or firmware components, can be referred to in the prior art as a "host" or "host data processing system".

[0024] In the illustrated embodiment, the data processing system 100 is a cache-coherent multiprocessor (MP) data processing system comprising several processing nodes 102 for processing data and instructions. The processing nodes 102 are connected via a system interface 110 for transmitting address, data, and control information. The system interface 110 can be implemented, for example, as an interconnection with buses, a switched interface, or a hybrid interface.

[0025] In the illustrated embodiment, each processing node 102 is implemented as a multi-chip module (MCM) containing one or more (e.g., four) processing units 104a to 104d, each preferably implemented as an integrated circuit. The processing units 104 in each processing node 102 are connected to each other and to the system interface 110 for data transmission via a local interface 114, which can be implemented like the system interface 110, for example, with one or more buses and / or switches. The system interface 110 and the local interfaces 114 together form a system architecture.In at least some preferred embodiments, data transmission on the system structure corresponds to a so-called host bus protocol, which defines, among other things, predetermined sets of legal requests, responses, and control information that are transmitted between participants in data transmissions (e.g., cache memories, memory controllers, etc.) across the system structure.

[0026] As explained in more detail below with reference to Fig. As described in Section 2, in some embodiments one or more of the processing units 104 (and possibly all processing units 104) each comprise a memory controller 106, which is connected to the local interface 114 to provide an interface to a respective system memory 108. Data and instructions located in the system memory 108 can generally be accessed, cached, and modified by a processor core in each processing unit 104 of each processing node 102 in the data processing system 100. In alternative embodiments, one or more memory controllers 106 (and the system memory 108) can be connected directly or indirectly (e.g., via a switch) to the system interface 110 instead of via a local interface 114.

[0027] The expert will understand that the data processing system is 100% of Fig. 1. Many additional components not illustrated may be included, such as connecting bridges, non-volatile memory, network connections, or connected units, etc. Since such additional components are not necessary for understanding the described embodiments, they are omitted in Fig. 1 is neither illustrated nor discussed further herein. However, it should also be clear that the improvements described herein are applicable to data processing systems of various architectures and are by no means limited to the generalized data processing system architecture described in Fig. 1 is illustrated.

[0028] With the following reference to Fig. Figure 2 shows a more detailed block diagram of an exemplary processing unit 104 according to one embodiment. In the illustrated embodiment, each processing unit 104 is an integrated circuit with one or more processor cores 200 for processing instructions and data. In the illustrated example, a processor core 200 comprises one or more execution units 202 that execute instructions from multiple concurrent hardware execution threads.

[0029] The processor core 200 additionally includes a memory management unit (MMU) 204, which is responsible for translating effective addresses, determined by the execution of memory-related instructions in one or more execution units 202, into real addresses in a real address range referenced by all processing units 104 in the data processing system 100. The MMU 204 performs the translation from effective to real address by referencing one or more translation structures 206, such as an address translation buffer (TLB), an effective-to-real address translation cache (ERAT), a segment translation buffer (SLB), etc. The number and / or type of address translation structures can vary between implementations and architectures. The address translation structure(s) 206 reduces or...reduce the latency associated with address translation by caching local copies of selected address translations that can be retrieved from the system memory 108, as further explained below.

[0030] The operation of each processor core 200 is supported by a multi-level memory hierarchy, the lowest level of which comprises the composite system memory provided by the various system memories 108 and made accessible via the memory controllers 106. The range(s) of real addresses for which a single memory controller 106 is responsible can be defined, for example, by hypervisor and / or operating system software through the appropriate configuration of one or more base address registers (BARs) 216 in the memory controller 106. As illustrated, one or more system memories 108 store one or more system data structures (SDSs) 224, which provide an account for shared host-to-host memory usage, as described herein.For example, the SDSs 224 can define the different address ranges assigned to the various memory locations and data connections of the data processing system 100, as described below. Furthermore, one or more system memory locations 108 store a page frame table 210 containing a plurality of page table entries (PTEs) 212, each PTE 212 specifying a translation from effective to real address for a corresponding memory page located in one of the system memory locations 108. The PTEs 212 also specify access restrictions (e.g., read-only, read / write (R / W), etc.) for the various memory pages. The PTEs 212, which are accessed by the page frame table 210 via an MMU 204, can be cached by the MMU 204 for subsequent access, for example in the address translation structure or address translation structures 206.The SDSs 224 and the page frame table 210, for example, can be created, managed and updated by operating system and / or hypervisor software running in the data processing system 100.

[0031] The multi-level memory hierarchy of each processor core 200 additionally comprises one or more levels of cache memory, which in the illustrative embodiment include storage in a Level One (L1) cache memory 208, which is private for each processor core 200, and storage in a Level Two (L2) cache memory 230, which is also private for each processor core 200. Although the illustrated cache memory hierarchy comprises only two cache memory levels, it will be clear to those skilled in the art that alternative embodiments may include additional levels (L3, L4, etc.) of chip-integrated or chip-external, private or shared, in-line or lookaside cache memory, which may be fully inclusive, partially inclusive, or non-inclusive with respect to the contents of the upper levels of the cache memory.

[0032] In the illustrated embodiment, each processing unit 104 further comprises an integrated and distributed structure controller 214, which is responsible for controlling the execution of operations on the system structure according to the host bus protocol and for implementing the coherence data transmission required to implement the desired cache memory coherence protocol. The processing unit 104 may also include an integrated I / O (input / output) controller 218, which supports the connection of one or more I / O units and / or I / O channels (not illustrated).

[0033] In the example shown, the processing unit 104 also includes an attached functional unit or memory (AFUM) controller 220, which, in at least one operating mode, supports the connection to the host data processing system 100 of an attached unit, referred to herein as an attached functional unit or memory (AFUM) 222. Thus, the AFUM 222 can be a unit such as memory that responds only to host commands received from the host data processing system 100, or alternatively, it can be a unit that can issue AFUM commands (including AFUM read and AFUM write commands) to the host data processing system 100. The range(s) of real addresses for which an AFUM controller 220 is responsible when serving attached memory can be defined as follows:For example, they can be defined by hypervisor and / or operating system software through the appropriate configuration of one or more base address registers (BARs) 224 in the AFUM controller 220. In at least some embodiments, the AFUM controller 220 can include an address translation cache (ATC) 226, which provides low-latency storage for address translations between the real address space referenced by data transmissions on the system structure and the effective address space used by the connected AFUM 222 (which is preferably the same as the effective address space referenced by the processor cores 200).

[0034] As indicated, the AFUM 222 is connected to the AFUM controller 220 via an AFUM interface 225. In some cases, the AFUM interface 225 can be integrated with or packaged within the AFUM 222. In other cases, the AFUM interface 225 can be implemented in a separate unit or package separate from the AFUM 222. It should also be clear that several different types of AFUMs 222 can be implemented simultaneously in a host data processing system 100. For example, one or more AFUMs 222 can be connected functional units (FMUs) (e.g., accelerator chips), while one or more other AFUMs 222 can be connected memory units.

[0035] In the embodiment of Fig. 2 The processing unit 104 additionally includes a nested memory management unit (NMMU) 228, which provides address translations for other data transmission participants on request, such as the AFUM controller 220. It should be clear that in other embodiments the NMMU 228 can be connected in the data exchange to provide address translations for data transmission participants, including the AFUM controller 220, alternatively or additionally, for example, by connecting to the system intermediate connection 110 instead of the local intermediate connection 114.

[0036] With the following reference to Fig. Figure 3 illustrates an exemplary protocol stack 300 for transmitting information between a host data processing system (e.g., the data processing system 100) and an AFUM 222 according to one embodiment. The data transmission protocol implemented by the protocol stack 300 defines the rules, syntax, semantics, and timing of data transmission between the host data processing system 100 and the AFUM 222. Typically, the protocol stack 300 comprises several individual layers, each of which executes a specific subset of the data transmission protocol and transmits the results of the processing to the adjacent layer(s). Each layer of the protocol stack 300 can be implemented by hardware, software, or a combination of hardware and software.

[0037] In the example shown, the protocol stack 300 on the host side comprises a host bus protocol layer 302, a host bus protocol interface layer 304, a host transaction layer 306, a host transaction frame / analysis layer 308, a host data layer 310, and a host physical layer 312, all of which can be implemented, for example, in the AFUM controller 200. The host bus protocol layer 302 is configured to receive and output commands (requests), responses, and control information on the system structure of a host data processing system 100 by using the host bus protocol implemented by that host data processing system 100. The host bus protocol interface layer 304 provides an interface that converts information received by the host bus protocol layer 302 into individual transactions, which are received and processed by the host transaction layer 306.The Host Bus Protocol interface layer 304 similarly translates transactions received from the Host Transaction Layer 306 into commands, responses, and control information in the Host Bus Protocol, which is implemented by the Host Bus Protocol layer 302. The Host Transaction Frames / Analysis Layer 308 packs and unpacks sequences of one or more transactions into and out of frames, which are processed by the Host Data Layer 310. The Host Data Layer 310 monitors the provisioning of frames to and the receipt of frames from the AFUM interface 225 via the physical Host Layer 312. For example, the Host Data Layer 310 can perform functions such as checking frame integrity, providing error correction, and retaking frames containing errors on the physical Host Layer 312.

[0038] The Protocol Interface 300 layer, implemented in the AFUM Interface 225, with each corresponding to a similar protocol layer on the host side, comprises an AFUM Protocol Layer 324, an AFUM Protocol Interface Layer 322, an AFUM Transaction Layer 320, an AFUM Transaction Framework / Analysis Layer 318, an AFUM Data Layer 316, and a Physical AFUM Layer 314. The AFUM Protocol Layer 324 is configured to transmit commands (requests), responses, and control information to the AFUM 222 using a protocol implemented by the AFUM 222. The AFUM Protocol Interface Layer 322 provides an interface that performs a conversion between the information transmitted by the AFUM Protocol Layer 324 and individual transactions processed by the AFUM Transaction Layer 320.The host transaction frame / analysis layer 318 packs and unpacks sequences of one or more transactions into and out of frames that are processed by the AFUM data layer 316. The AFUM data layer 316 monitors the provisioning of frames to the host and the receipt of frames from the host via a physical AFUM layer 314, for example by checking frame integrity, providing error correction, and re-repeating frames that contain errors.

[0039] In at least some embodiments, the layers of the protocol stack 300, collectively referred to as 330, can be implemented in a conventional manner. To avoid unnecessary obscurity regarding the innovative concepts disclosed herein, the protocol layers 330 are omitted in the following discussion and illustrations, and their presence is simply assumed.

[0040] With the following reference to Fig. Figure 4 presents an exemplary protocol stack 400 for a data transmission interface configured to support the connection of an attached memory unit 402 to a host data processing system 100 according to one embodiment. As indicated by the same reference numerals, the protocol stack 400 comprises a host bus protocol layer 302, a host bus protocol interface layer 304, and a host transaction layer 306, which, as previously described, can be implemented in the AFUM controller 220 of a host data processing system 100. The AFUM interface 225 likewise comprises an AFUM protocol layer 324, an AFUM protocol interface layer 322, and an AFUM transaction layer 320, as previously described. The AFUM protocol layer 324 of the AFUM interface 225 is connected in data exchange with an AFUM, which is implemented as an attached memory unit 402.

[0041] In this arrangement, the host bus protocol interface layer 304 receives host bus protocol requests, such as host bus protocol read and write requests on the system structure of the host data processing system 100. Each host bus protocol read or write request specifies at least the request type and a real address to be accessed, and host bus protocol write requests additionally specify data to be written to the specified real address. For each such host bus protocol request, the host bus protocol interface layer 304 determines, by reference to BAR(s) 224, whether the real address of the request falls within a real address range belonging to the connected memory 402. If not, the host bus protocol request is simply ignored.If the real address of the host bus protocol request falls within a real address range belonging to the connected memory 402, the host bus protocol interface layer 304 forwards the host bus protocol request to the host transaction layer 306. The host transaction layer 306 then converts the host bus protocol request into a suitable corresponding host instruction. For a host instruction directed to connected memory 402, this instruction is either a host read instruction specifying a real address (e.g., Host_Rd(Addr)) or a host write instruction specifying a real address and data to be written to connected memory 402 (e.g., Host_Wr(Addr,Data)).

[0042] In response to a host read command, the AFUM interface 225 processes the host command through protocol layers 320 to 324 and responds with one of two responses - an AFUM read response indicating success and providing the requested data (e.g., AFUM_Rd_Resp(Data)) or an AFUM read response indicating failure of the read request (e.g., AFUM_Rd_Failed). The AFUM interface 225 responds similarly to a host write command by processing the host write command and providing one of two responses - an AFUM write response indicating success of the host write command in updating connected memory 402 (e.g., AFUM_Wr_Resp), or an AFUM write response indicating failure of the write command to update connected memory 402 (e.g., AFUM_Wr_Failed).The AFUM controller 220 processes the AFUM response received from the AFUM interface 225 at host transaction layer 306 and host bus protocol interface layer 304. If required or permitted by the host bus protocol, it outputs a host bus protocol response generated based on the AFUM response on the system structure of the host data processing system 100. However, it should be noted that some host bus protocols do not require or support a host bus protocol response for an AFUM write response.

[0043] With the following reference to Fig. Figure 5 presents an exemplary protocol stack 500 for a data transmission interface configured to support the connection of an attached functional unit (FMU) 502 to a host data processing system 100 according to one embodiment. As indicated by the same reference numerals, the protocol stack 500 comprises a host bus protocol layer 302, a host bus protocol interface layer 304, and a host transaction layer 306, which, as previously described, can be implemented in the AFUM controller 220 of a host data processing system 100. The AFUM interface 225 likewise comprises an AFUM protocol layer 324, an AFUM protocol interface layer 322, and an AFUM transaction layer 320, as previously described. The AFUM protocol layer 324 of the AFUM interface 225 is connected in data exchange with an AFUM, for example an accelerator that is implemented as an AFU 502.

[0044] The AFU 502 can initiate and issue AFUM commands directed to the host data processing system 100. These AFUM commands, received by the AFUM protocol layer 304, each specify at least the command type and an effective address to be accessed, and may additionally specify data to be written to the specified effective address. Each such AFUM command is processed (and possibly translated) by the AFUM protocol interface layer 322 and the AFUM transaction layer 320 to issue one of a set of AFUM commands, which includes at least one AFUM read command (e.g., AFUM_Rd(Addr)) and one AFUM write command (e.g., AFUM_Wr(Addr,Data)).

[0045] In response to an AFUM command, the host transaction layer 306 of the AFUM controller 220 determines whether the ATC 226 contains an address translation entry that can translate the effective address specified by the AFUM command into a real address within the real address range of the host data processing system 100. Based on the success of this translation from effective to real address, and if the host data processing system 100 successfully responds to a host bus protocol request generated from the AFUM command by protocol layers 302 to 306, protocol layers 302 to 306 provide a corresponding host response, which is transmitted back to the AFU 502 via protocol layers 320 to 324 of the AFUM interface 225.

[0046] For AFUM read commands, the Host Data Processing System 100 can provide any of three host responses: (1) a host read response indicating successful completion of the read operation without errors and providing the requested data (e.g., Host_Rd_Resp(Data,NErr)), (2) a host read response indicating completion of the read operation and providing data containing one or more errors (e.g., Host_Rd_Resp(Data,Err)), or (3) a host read response indicating an initial error in finding an effective-to-real address translation for the effective address specified by the read / write command (e.g., Host_Rd_Failed_XLATE). Similarly, the Host Data Processing System 100 responds to an AFUM write command by providing one of three host responses: (1) a host write response indicating successful completion of the write operation without errors (e.g.,(1) a host write response indicating (2) a write operation terminated with one or more errors (e.g., Host_Wr_Resp(NErr)), or (3) a host write response indicating an initial failure to find an effective-to-real address translation for the effective address specified by the AFUM write command (e.g., Host_Wr_Failed_XLATE). In addition to these six host responses, Host Data Processing System 100 is configured to provide two further responses, each indicating a final success or failure to find a translation of an effective address specified in an AFUM command (e.g., Host_XLATE_Complete and Host_XLATE_Err).

[0047] It should be clear that the protocol stacks 300, 400, 500 can support additional commands and responses that differ from the read and write commands and responses, which are particularly relevant in Fig. Sections 4 to 5 have been explained in detail. For example, protocol stacks 300 to 500 can support data transmission that enables other memory access instructions (e.g., atomic memory operations (AMOs)), requests interrupts, and supports flow control through the implementation of power and / or virtual channel management.

[0048] With the following reference to Fig. Figures 6 to 10 show time-space diagrams of an AFU read command from an AFU 502 and various possible host responses to the AFU read command according to one embodiment.

[0049] As in Fig. As shown in Figure 6, the AFU 502 issues an AFUM read command 600 (e.g., AFUM_Rd(Addr)) to a host data processing system 100 via the protocol stack 500, as described above with reference to Fig. 5 explained. In the Fig. In the success scenario shown in Figure 7, the AFUM controller 220 of the host data processing system 100 successfully receives an address translation for the effective address specified in the AFUM read instruction 600, translates the effective address into a real address by referencing the address translation entry, and initiates a host bus protocol read request on the system structure of the host data processing system 100 by specifying the real address obtained from the address translation. In response to the host bus protocol read request, the data requested by the host bus protocol read request can be returned to the AFUM controller 220, for example, by a cache memory (e.g., one of the L2 cache memories 230) or a memory controller 106.In response to receiving the requested data, the AFUM controller 220 provides a Host Read Response 700 to the AFU 502, which provides the requested data and indicates "No error" (e.g. Host_Rd_Resp(Data,NErr)).

[0050] Fig. Figure 8 describes the case where a read error occurs. In this case, the AFUM controller 220 of the host data processing system 100 successfully receives an address translation for the effective address specified in the AFUM read command 600, translates the effective address into a real address by referencing the address translation entry, and initiates a host bus protocol read request on the system structure of the host data processing system 100 by specifying the real address obtained from the address translation. However, in this case, the host bus protocol read request in the host data processing system 100 is unsuccessful, for example, due to a parity or ECC (error correction code) error. In response to a read error notification, the AFUM controller 220 issues a host read response 800 indicating an error (e.g., Host_Rd_Resp(Data,Err)).In some implementations, the error message can be provided in the data field of the host read response.

[0051] Fig. Figure 9 illustrates the case where the AFUM read command 600 fails because the AFUM controller 220 is unable to obtain an address translation entry for the effective address specified by the AFUM read command 600, but the required address translation entry is subsequently provided by the operating system software. In this case, the AFUM controller 220 of the host data processing system 100 receives the AFUM read command 600 and attempts unsuccessfully to obtain an address translation entry for the effective address specified in the AFUM read command 600. In response to the failure to obtain an address translation entry for the effective address, the AFUM controller 220 issues a Host Read Error Response 900 to the AFU 502, indicating that the failure was due to a failure to obtain an address translation entry for the effective address (e.g., Host_Rd_Failed_XLATE).Furthermore, the AFUM controller 220 initiates an operating system interrupt requesting the necessary address translation. In response to the operating system indicating that the address translation is available in page frame table 210, the AFUM controller 220 sends a "Translation Complete" host response 902 (e.g., Host_XLATE_Complete) to the AFUM 222, indicating that the address translation entry for the effective address of the AFUM read request 600 is now available. Upon receiving the "Translation Complete" host response 902, the AFUM 222 can optionally reissue the AFUM read command as an AFUM read command 904 (e.g., AFUM_Rd(Addr)), which may then be successful, as shown in [reference to relevant document]. Fig. 7 shown (assuming the address translation entry is still valid in page frame table 210 when AFUM read command 904 is issued).

[0052] Fig. Figure 10 represents the case in which the AFUM read command 600 fails because the AFUM controller 220 is unable to obtain an address translation entry for the effective address specified by the AFUM read command 600, and the required address translation entry is subsequently not provided by the operating system software. In this case, the AFUM controller 220 of the host data processing system 100 receives the AFUM read command 600 and attempts unsuccessfully to obtain an address translation entry for the effective address specified in the AFUM read command 600. In response to the failure to obtain an address translation entry for the effective address, the AFUM controller 220 issues a Host Read Error Response 1000 to the AFU 502, indicating that the failure was due to a failure to obtain an address translation entry for the effective address (e.g., Host_Rd_Failed_XLATE).Furthermore, the AFUM controller 220 initiates an interrupt from the operating system, which requests the required address translation. In response to the operating system indicating that the address translation is unavailable, the AFUM controller 220 sends a host translation error response 1002 (e.g., Host_XLATE_Err) to the AFUM 222, indicating that no address translation entry was found for the effective address of the AFUM read request 600.

[0053] With the following reference to Fig. Figures 11 to 15 show time-space diagrams of a write command from an AFU 502 and various responses from a host data processing system to the write command from the AFU 502 according to one embodiment.

[0054] As in Fig. As shown in Figure 11, the AFU 502 issues an AFUM write command 1100 (e.g., AFUM_Wr(Addr,Data)) to a host data processing system 100 via the protocol stack 500, as described above with reference to Fig. 5 explained. In the Fig. In the successful scenario shown in Figure 12, the AFUM controller 220 of the host data processing system 100 successfully receives an address translation and write authorization for the effective address specified in the AFUM write command 1100. Once the required address translation and write authorization are obtained, the AFUM controller 220 translates the effective address into a real address by referencing the address translation entry and initiates a host bus protocol write request on the system structure of the host data processing system 100. The host bus protocol write request specifies the real address obtained from the address translation and includes or is accompanied by the payload of the AFUM write command 1100.In response to a successful host bus protocol write request to update system memory 108 (or any other memory-associated resource, such as attached memory 402), the AFUM controller 220 provides a host write response 1200 to AFU 502 indicating "No error" (e.g., Host_Wr_Resp(NErr)).

[0055] Fig. Figure 13 describes the case where a write error occurs. In this case, the AFUM controller 220 of the host data processing system 100 responds to the AFUM write command 1100 by receiving an address translation entry and write permission for the effective address specified in the AFUM write command 1100. Once the necessary address translation and write permission are obtained, the AFUM controller 220 translates the effective address into a real address by referencing the address translation entry and initiates a host bus protocol write request on the system structure of the host data processing system 100. Again, the host bus protocol write request specifies the real address obtained from the address translation and includes or is accompanied by the payload of the AFUM write command 1100.In this case, however, the host bus protocol write request in the host data processing system 100 fails, for example, due to a parity or ECC error. In response to a message on the system structure indicating a failed host bus protocol write request, the AFUM controller 220 issues a host write response 1300 indicating a write error (e.g., Host_Wr_Resp(Err)).

[0056] Fig. Figure 14 illustrates the case where the AFUM read command 1100 fails because the AFUM controller 220 is unable to obtain an address translation entry and write permission for the effective address specified by the AFUM write command 1100, but the required address translation entry and write permission are subsequently provided by the operating system. In this case, the AFUM controller 220 of the host data processing system 100 receives the AFUM write command 1100 and attempts unsuccessfully to obtain an address translation entry and write permission for the effective address specified in the AFUM write command 1100.In response to the failure to obtain an address translation entry and write permission for the effective address, AFUM controller 220 issues a host write error response 1400 to AFU 502, indicating that the failure was due to a failure to obtain the address translation entry and write permission for the effective address (e.g., Host_Wr_Failed_XLATE). AFUM controller 220 also initiates an operating system interrupt requesting the required address translation and write permission. Upon receiving confirmation from the operating system that the address translation and write permission are available in page frame table 210, AFUM controller 220 issues a "Translation Complete" host response 1402 to AFUM 222 (e.g., Host_XLATE_Complete), indicating that the address translation entry for the effective address of AFUM write instruction 1100 is now available.In response to receiving the host response "Translation complete" 1402, the AFUM 222 can optionally issue the AFUM write command again as an AFUM write command 1404 (e.g. AFUM_Wr(Addr)), which may then be successful, as in . Fig. 12 shown (assuming the address translation entry and write permission are still valid in page frame table 210 when the AFUM write command 1404 is issued).

[0057] Fig. Figure 15 describes the case in which the AFUM write command 1100 fails because the AFUM controller 220 is unable to obtain an address translation entry for the effective address specified by the AFUM write command 1100, and the address translation entry and write permission are subsequently not provided by the operating system. In this case, the AFUM controller 220 of the host data processing system 100 receives the AFUM write command 1100 and attempts unsuccessfully to obtain an address translation entry and write permission for the effective address specified in the AFUM write command 1100.In response to the failure to obtain an address translation entry and write permission for the effective address, the AFUM controller 220 issues a Host Write Error Response 1400 to the AFU 502, indicating that the failure was due to a failure to obtain the address translation entry and write permission for the effective address (e.g., Host_Wr_Failed_XLATE). Additionally, the AFUM controller 220 initiates an operating system interrupt requesting the required address translation and write permission. In response to the operating system indicating that the requested address translation entry and / or write permission are unavailable, the AFUM controller 220 issues a Host Translation Error Response 1502 to the AFUM 222 (e.g., Host_XLATE_Err), indicating that no address translation entry and / or write permission for the effective address of the AFUM write command 1100 was found.

[0058] With the following reference to Fig. Figure 16 presents a logical overview flowchart of an exemplary procedure by which a host transaction layer 306 of a host data processing system 100 responds to a command from an AFU 502 according to an embodiment. The process of Fig. 16 begins at block 1600 and then continues with block 1602, which illustrates the host transaction layer 306, which is either an AFUM read command 600 (see e.g.) from the AFU 502 (see e.g. Fig. 6) or an AFUM write command 1100 (see e.g. Fig. 11) receives. In response to receiving the AFUM instruction, host transaction layer 306 determines at block 1604 whether to skip the translation of the effective address specified in the AFUM instruction. Host transaction layer 306 can determine to skip the effective address translation, for example, based on the effective address of AFUM instruction 600 or 1100 falling within a predetermined address range, a specification provided in AFUM instruction 600 or 1100 and / or a configuration of the AFUM controller 220. If determined at block 1604 to skip the translation of the effective address specified in the AFUM instruction, the process proceeds to block 1636, which is described below. Otherwise, the process proceeds to block 1606.

[0059] Block 1606 illustrates the host transaction layer 306, which determines whether ATC 226 contains an address translation entry to translate the effective address specified in AFUM instruction 600 or 1100 into a real address. In response to a determination by host transaction layer 306 that ATC 226 contains the relevant address translation entry, the process proceeds to block 1630 and subsequent blocks. Conversely, if host transaction layer 306 determines that ATC 226 does not contain the relevant address translation entry, the process proceeds from block 1606 to block 1610 and subsequent blocks.

[0060] With reference to block 1610, host transaction layer 306 initiates, via host bus protocol interface layer 304 and host bus protocol layer 302, a transmission of an NMMU translation request for the effective address of the AFUM instruction (block 1610) to NMMU 228. Host transaction layer 306 then waits to receive a host bus protocol response to the NMMU translation request (at block 1612). Upon receiving a host bus protocol response to the NMMU translation request indicating success and providing the requested address translation entry, host transaction layer 306 installs the address translation entry in ATC 226 (at block 1614). The process then proceeds to block 1630, which is described below.

[0061] In response to the host bus protocol response to the NMMU translation request indicating failure (i.e., the address translation entry is not returned by NMMU 228), the process proceeds from block 1612 to block 1616, which illustrates host transaction layer 306, which outputs a host read error response 900, 1000 (e.g., Host_Rd_Failed_XLATE) or a host write error response 1400, 1500 (e.g., Host_Wr_Failed_XLATE) to AFU 502. Furthermore, the host transaction layer 306 initiates, via the host bus protocol interface layer 304 and the host bus protocol layer 302, the transmission of an interrupt request to an operating system or hypervisor running on a processor core 200, to a processing unit 102. The interrupt request requests the address translation for the effective address specified by the AFUM instruction and all necessary access permissions (at a block 1618).

[0062] Block 1620 represents the host transaction layer 306 monitoring to determine whether a successful response to the interrupt request has been received from the operating system or hypervisor (often provided by a memory-mapped input / output (MMIO) operation). In response to a success response, host transaction layer 306 issues a "Translation Complete" host response (e.g., Host_XLATE_Complete) to AFU 502 (at block 1622). However, in response to a failure response, host transaction layer 306 issues a "Translation Error" host response (e.g., Host_XLATE_Err) to AFU 502 (at block 1624). The process terminates either after block 1622 or block 1624. Fig. 16 on one block 1640.

[0063] With reference to block 1630, host transaction layer 306 determines whether the AFUM instruction received at block 1602 is an AFUM write instruction. If not, the process proceeds to block 1636, which is described below. However, if host transaction layer 306 determines that the AFUM instruction received at block 1602 is an AFUM write instruction, host transaction layer 306 determines at block 1632 whether the address translation entry accessed by ATC 226 at block 1606, or received by NMMU 226 at blocks 1612 to 1614, includes write permissions for the real address referenced by the AFUM write instruction. If so, the process proceeds to block 1636, which is described below.However, if host transaction layer 306 determines at block 1632 that the address translation entry does not provide write permission for the real address referenced by the AFUM write instruction, host transaction layer 306 removes the address translation entry from ATC 226 (at block 1634). The process then proceeds to block 1616, which has been written.

[0064] Referring to block 1636, host transaction layer 306 initiates processing of the read or write operation specified by the AFUM command in host data processing system 100 by causing the corresponding host bus protocol request to be issued on the system structure via host bus protocol interface layer 304 and host bus protocol layer 302. It should be clear that if block 1604 specifies that address translation of the effective address of an AFUM command should be skipped, other, unillustrated techniques, including appropriate configuration of page frame table 210, are used to ensure that the effective address is within a permitted address range and has any necessary write permissions.Depending on the success or failure of the Host Bus Protocol request initiated at block 1636, Host transaction layer 306 issues a corresponding host response to AFU 502 (at block 1638). Specifically, in response to an AFUM read request, Host transaction layer 306 issues either a Host Read Response 700, which provides the requested data and indicates "No Error" (e.g., Host_Rd_Resp(Data,NErr)), or a Host Read Response 800, which indicates a read error (e.g., Host_Rd_Resp(Data,Err)). In response to an AFUM write command, host transaction layer 306 either issues a host write response 1200 indicating "No error" (e.g., Host_Wr_Resp(NErr)) or a host write response 1300 indicating a write error (e.g., Host_Wr_Resp(Err)). After block 1638, the process terminates at block 1640.

[0065] With the following reference to Fig. Figure 17 illustrates a logical overview flowchart of an exemplary procedure by which an AFU 502 issues a command to a host data processing system 100 and processes the host response according to one embodiment. The process of Fig. Section 17 begins at block 1700 and then continues with block 1702, which illustrates the AFUM transaction layer 320, which issues an AFUM command, such as an AFUM read command 600 (e.g., AFUM_Rd(Addr)) or an AFUM write command 1100 (e.g., AFUM_Wr(Addr,Data)), to the host transaction layer 306. The AFUM transaction layer 320 then listens for a response to the AFUM command, as shown in blocks 1704 to 1706. In response to a determination at block 1704 that the host response is a Host Read Response 700 providing the data requested by an AFUM Read Instruction 600 and indicating "No Error" (e.g., Host_Rd_Resp(Data,NErr)) or a Host Write Response 1200 indicating "No Error" (e.g., Host_Wr_Resp(NErr)), the process moves to block 1710.If, as indicated at block 1710, the AFUM command issued at block 1702 was an AFUM write command 1100 and not an AFUM read command 600, processing by AFUM transaction layer 320 simply terminates at block 1726. However, if the AFUM command issued at block 1702 was an AFUM read command 600 and not an AFUM write command 1100, AFUM transaction layer 320 returns the requested data to AFU 502 (at block 1712). The process then terminates. Fig. 17 on one block in 1726.

[0066] If, referring back to block 1704, the received host response is neither a Host Read Response 700 nor a Host Write Response 1200, the AFUM transaction layer 320 determines at block 1706 whether the host response indicates an initial translation error (e.g., Host_Rd_Failed_XLATE 900, 1000 or Host_Wr_Failed_XLATE 1400, 1500). If not, the process returns to block 1704. However, if the AFUM transaction layer 320 determines that the host response indicates an initial translation error, it repeats the monitoring process at block 1720 for an additional host translation response indicating whether the address translation for the effective address of the AFUM command has been successfully loaded into page frame table 210.In response to receiving a Host_XLATE_Complete 902, 1402 response indicating that the address translation for the effective address of the AFUM command has been successfully loaded into page frame table 210, the process proceeds from . Fig. The process moves from block 1720 to block 1722 and then returns from block 1722 to block 1702. The process following this path means that AFU 502 can reissue the AFUM command, as shown at references 904 and 1404. However, if AFUM transaction layer 320 instead receives a response Host_XLATE_Err 1002 or 1502 indicating that the translation for the effective address of the AFUM command has not been loaded into page frame table 210, the process continues from block 1722 with block 1724, which illustrates AFUM transaction layer 320 initiating error handling for the failed AFUM command. After block 1724, the process terminates. Fig. 17 on one block in 1726.

[0067] With the following reference to Fig. Figures 18 to 20 show time-space diagrams of a host read command issued by a host data processing system 100 to an attached memory 402 and various responses from the attached memory 402 to the host read command of the host data processing system 100 according to an embodiment.

[0068] As in Fig. As shown in Figure 18, the AFUM controller 220 of the host data processing system 100 issues a host read command 1800 (e.g., Host_Rd(Addr)) to an AFUM 222, which is configured or translated as an attached memory 402 via the protocol stack 400, as described above with reference to Fig. 4 discussed. In the Fig. In the successful scenario shown in Figure 19, the AFUM transaction layer 320 transmits a read instruction, corresponding to the host read instruction 1800, to the connected memory 402 via the AFUM protocol interface layer 322 and the AFUM protocol layer 324, where all protocol layers 320 to 324 can be implemented in the AFUM interface 225. In response to the read instruction, the connected memory 402 returns the data specified by the actual address of the host read instruction 1800. The AFUM protocol interface layer 322 forwards the requested data to the host transaction layer 306 in an AFUM read response 1900 (e.g., AFUM_Rd_Resp(Data)).

[0069] Fig. Item 20 represents the case in which a read error occurs. In this case, the connected memory 402 responds to the read command received from the AFUM interface 225 with a message indicating a failure of the read command. Accordingly, the AFUM interface 225 outputs an AFUM read response 2000 indicating a read error (e.g., AFUM_Rd_Failed). In an alternative implementation, the read error information can be provided in a data field of the AFUM read response 1900.

[0070] With the following reference to Fig. Figures 21 to 23 illustrate time-space diagrams of a write command issued by a host data processing system 100 to an AFUM 222 configured as an attached memory 402, and various responses from the attached memory 402 to the write command according to one embodiment.

[0071] As in Fig. As shown in Figure 21, the AFUM controller 220 of the host data processing system 100 issues a host write command 2100 (e.g., Host_Wr(Addr,Data)) to an AFUM 222, which is configured or translated as an attached memory 402 via the protocol stack 400, as described above with reference to Fig. 4 discussed. In the Fig. In the success scenario shown in Figure 22, the AFUM transaction layer 320 transmits a write command, corresponding to the host write command 1800 (including the real address and the write data), to the connected memory 402 via the AFUM protocol interface layer 322 and the AFUM protocol layer 324, where all protocol layers 320 to 324 can be implemented in the AFUM interface 225. In response to the write command, the connected memory 402 returns an indication of the success of the write command to the AFUM protocol interface layer 322. In response, the AFUM protocol interface layer 322 issues an AFUM write response 2200 to the host transaction layer 306, indicating the success of the host write command 2100 (e.g., AFUM_Wr_Resp).

[0072] Fig. Figure 23 represents the case in which a write error occurs. In this case, the connected memory 402 responds to the write command received from the AFUM interface 225 with a message indicating a write command failure. Accordingly, the AFUM interface 225 outputs an AFUM write response 2300 indicating a write error (e.g., AFUM_Wr_Failed).

[0073] With the following reference to Fig. Figure 24 presents a logical overview flowchart of an exemplary procedure by which an AFUM transaction layer 320, serving an AFUM 222, responds to a command from a host data processing system 100 according to an embodiment. The process of Fig. 24 begins at block 2400 and then continues with block 2402, which illustrates the AFUM transaction layer 320, which is issued by the AFUM controller 220 either a host read command 1800 (see e.g. Fig. 18) or a host write command 2100 (see e.g. Fig. 21) receives. In response to receiving the host command, the AFUM transaction layer 320 initiates processing of the read or write operation specified by the host command in the attached memory 402 (at block 2402). Depending on the success or failure of the read or write operation initiated at block 2404, the host transaction layer 320 issues a corresponding AFUM response to the AFUM controller 220 (at block 2406). Specifically, in response to a success of the host command, the AFUM transaction layer 320 either issues an AFUM read response 1900, which provides the requested data (e.g., AFUM_Rd_Resp(Data)), or an AFUM write response 2200, which indicates the success of the write (e.g., AFUM_Wr_Resp), as shown at block 2410. In particular, in response to a host command failure, the AFUM transaction layer 320 either returns an AFUM read response 2000 indicating a read error (e.g.,AFUM_Rd_Failed) or an AFUM write response 2300 indicating a write error (e.g., AFUM_Wr_Failed), as shown at block 2408. The process terminates either after block 2408 or block 2410. Fig. 24 on a block 2412.

[0074] With the following reference to Fig. 25 presents a logical overview flowchart of an exemplary procedure by which a host transaction layer 306 processes a command issued to an AFUM 222, configured as an attached memory 402, according to one embodiment. The process of Fig. Section 25 begins at block 2500 and continues with block 2502, which illustrates host transaction layer 306, issuing an AFUM command, such as a host read command 1800 (e.g., Host_Rd(Addr)) or a host write command 2100 (e.g., Host_Wr(Addr,Data)), to AFUM transaction layer 320. Host transaction layer 306 then listens for an AFUM response to the host command, as shown in blocks 2504 to 2506. In response to a determination at block 2504 that the AFUM response is an AFUM read response 1900 providing the data requested by the host read command 900 (e.g., AFUM_Rd_Resp(Data)), or an AFUM write response 2200 indicating a success of a host write command (e.g., Host_Wr_Resp), the process moves to block 2510.If, as indicated at block 2510, the host command issued at block 2502 was a host write command 2100 and not a host read command 1800, processing by host transaction layer 306 simply ends at block 2516. However, if the host command issued at block 2502 was a host read command 1800 and not a host write command 2100, host transaction layer 306 returns the requested data to host data processing system 100 (at block 2512). The process then terminates. Fig. 25 at block 2516.

[0075] If, referring back to block 2504, the received AFUM response is neither an AFUM read response 1900 nor an AFUM write response 2200, the host transaction layer 306 determines at block 2506 whether the AFUM response indicates a read or write error (e.g., AFUM_Rd_Failed 2000 or AFUM_Wr_Failed 2300). If not, the process returns to block 2504. However, if the host transaction layer 306 determines that the AFUM response indicates a read or write error, it initiates error handling for the failed host command (at block 2514). After block 2514, the process terminates. Fig. 25 on a block 2516.

[0076] The preceding explanation described in detail a multi-function data transmission interface that can be used to support data transmission between a Host Data Processing System 100 and an AFUM 222, which can be configured as an attached memory 402 or an AFU 502. It should be clear that the data transmission interface supports simultaneous data transmission of both Host commands initiated by the Host Data Processing System 100 and AFUM commands initiated by the AFUM 222.The data transmission interface thus provides a practical means of enabling data transmission between the host processing system 100 and a connected unit, thereby relieving the connected unit of the requirements of supporting the host bus protocol and / or the coherence protocol of the host processing system 100, while still allowing shared data use between the connected unit and the host processing system 100. According to one aspect of the invention disclosed herein, the described data transmission interface can be extended to allow the connection of two or more host processing systems for data transmission, for example, to enable shared memory use between the host processing systems.In the context of this application, each such “host” is understood to mean at least the set of processing and memory resources that form a coherent memory area in which the processing resources have read and write access to the memory resources without using the data transfer interface disclosed herein. Since the sharing of memory resources by hosts via the data transfer interface is, by definition, not coherent, higher-level software (e.g., operating system or hypervisor software) can optionally specify whether access to overlapping memory areas by different hosts should be restricted, for example, by protecting memory pages.

[0077] With the following reference to Fig. Figure 26 presents an exemplary protocol stack 2600 for a data transmission interface configured to support a connection to a host data processing system to support memory sharing according to one embodiment. In the illustrated embodiment, a first host data processing system 100 (designated as "Host A") is connected in data exchange with a different second host data processing system 100 (designated as "Host B"). As further described below with reference to Fig. As discussed in section 38, the data exchange connection between Host A and Host B can be implemented by directly connecting an AFUM Controller 220 in Host A to an AFUM Controller 220 in Host B via a data transmission connection. Alternatively or additionally, an AFUM Controller 220 in Host A and an AFUM Controller 220 in Host B can be connected via one or more intermediary units in the data exchange, such as one or more host data processing systems, switches, data transmission links, etc.

[0078] As indicated by the same reference symbols, the section of the 2600 protocol stack implemented on both Host A and Host B includes a Host Bus Protocol Layer 302a or 302b, a Host Bus Protocol Interface Layer 304a or 304b, and a Host Transaction Layer 306a or 306b, as previously described. These protocol layers (just like the non-illustrated Host Transaction Frame / Analysis Layer 308a to 308b, a Host Data Layer 310a to 310b, and a Host Physical Layer 312a to 312b) can be implemented in an AFUM Controller 220. Additionally, both Host A and Host B include a Command, Control, Power, and Response Transaction (CCR XLATE) Layer 2602a or 2602b. From the perspective of Host A, the CCR XLATE layer 2602b translates incoming host commands initiated by Host A into AFUM commands, thereby emulating or providing a visual representation for the receiving host (i.e.,Host B) is made to appear as if the initiating host (i.e., Host B) is an AFU 502. Similarly, CCR XLATE layer 2602a translates incoming host responses from the receiving host (i.e., Host B), issued in response to AFUM responses issued by CCR XLATE layer 2602b, into AFUM responses, thus emulating, or making it appear to the initiating host (i.e., Host A), that the receiving host (i.e., Host B) is an attached memory 402. For host commands initiated by Host B, the functions performed by CCR XLATE layers 2602a and 2602b are reversed. Thus, the CCR XLATE layer 2602a translates host commands from host B into AFUM commands (which emulate the connection of an AFU 502 to host A), and the CCR XLATE layer 2602b translates host responses from host A into AFUM responses (which emulate the connection of an attached memory to host B).As a result, host-to-host data transfer can be handled seamlessly by reusing the existing AFUM data transfer protocol despite asymmetries between the AFUM and host command and response sets.

[0079] As indicated above, command and response sets are asymmetric, implemented by hosts and the AFUMs 222. For example, by comparing Fig. 9 to 10 and 14 to 15 with Fig. As observed in Figures 19 to 20 and 22 to 23, the set of host responses is more comprehensive than the set of AFUM responses, in particular because the host response set includes the host read and write error responses 900, 1400, a "translation complete" host response 902, 1402, and a host translation error response 1002, 1502. The AFUM response set does not include these or corresponding response messages at all. As a result, the AFUM response set, which is reused in the host-to-host data transmission, cannot transmit occurrences of translation errors or page protection errors. Consequently, in a preferred embodiment, the possibility of address translation errors or page protection errors is eliminated by fixing in the page frame table 210 of the destination host the page table entries referenced by host commands of the initiating host.

[0080] With the following reference to Fig. 27 will show a more detailed block diagram of the CCR XLATE layer 2602 in the protocol stack 2600 of Fig. 26. In this embodiment, the CCR XLATE layer 2602, which can be implemented in hardware, software, or a combination of hardware and software, comprises layer inputs 2700 that receive host commands, host responses, and host control / power messages originating from another host data processing system 100. As described above, host commands are used, among other things, to initiate read and write access to shared memory, and host responses provide answers to AFUM commands. Host control / power messages are used, for example, to coordinate the flow of commands and responses between hosts, allocate and release power used for the allocation of data transmission links on a power-based basis, and translate virtual channels.The layer inputs 2700 are connected via a bypass path 2702 to a first set of inputs 2704 of a selection logic, which is located in . Fig. 27 is represented by a mode multiplexer 2706. The layer inputs 2700 are additionally connected to a translation logic 2710.

[0081] In the illustrated embodiment, the translation logic 2710 comprises a command translation (Command XLATE) logic 2720, which translates host commands of an initiating host connected to the AFUM controller 220 into AFUM commands, as detailed below with reference to Fig. Sections 28 to 33 discuss this. In a preferred embodiment, the translation logic 2710 is implemented using only combinational logic capable of operating at wire speed. The instruction translation logic 2710 is associated with an optional address translation (Addr XLATE) logic 2722, which is capable of translating real addresses specified by host instructions. In a particularly preferred embodiment, the address translation performed by the address translation logic 2722, if present, is carried out without reference to an address translation structure (e.g., an address translation cache or address translation buffer) but is instead implemented directly using combinational logic that can, for example, add or subtract an address offset.The translation logic 2710 additionally includes a response translation logic 2724, which translates host responses from a receiving host connected to the AFUM controller 220 into AFUM responses, as detailed below with reference to . Fig. 28 to 33 are discussed. Furthermore, the translation logic 2710 includes a control and power translation logic 2726, which translates host control and power messages into AFUM control and power messages. The outputs of the command translation logic 2720, the response translation logic 2724, and the control and power logic 2726 are checked at a second set of inputs 2708 of the mode multiplexer 2706.

[0082] The mode-division multiplexer 2706 selects between the messages specified at its first set of inputs 2704 and the second set of inputs 2708, based on the setting of a configuration register 2712. This register can be initialized, for example, via a memory-associated input / output (MMIO) operation of a host data processing system 100 to configure the CCR XLATE layer 2602. For instance, if an AFUM controller 220 is used to connect a host data processing system 100 to an AFUM 222 for data exchange, the setting of the configuration register 2712 controls the mode-division multiplexer to select the messages represented at the first set of inputs 2704 for forwarding via a layer output 2714 to the associated host transaction layer 306.However, if an AFUM 220 is to be used to connect the host data processing system 100 for shared memory use, the setting of the configuration register 2712 controls the mode multiplexer to select messages to be represented at the second set of inputs 2708 for forwarding via the layer output 2714.

[0083] With the following reference to Fig. Figures 28 to 30 show a time-space diagram of a read command issued by a first host data processing system (e.g., Host A) to an attached host data processing system (e.g., Host B) via the data transmission interface provided by connected AFUM controllers 220, and various responses of the attached host data processing system to the read command according to an embodiment.

[0084] As in Fig. As shown in Figure 28, an AFUM controller 220 of host A (i.e., the "initiating host") issues a host read command 2800 (e.g., Host_Rd(Addr)) specifying a real address from which data is to be read for an AFUM controller 220 of host B (i.e., the "receiving host" or "destination host"), where the AFUM controllers 220 of both hosts are configured for host-to-host data transmission via the protocol stack 2600 by setting configuration register 2712. In response to receiving a host read command 2800, the CCR XLATE layer 2602b of host B translates the host read command 2800 and, optionally, the real address specified by the host read command 2800.For example, an instruction translation logic 2720 translates the host read instruction 2800 into an AFUM read instruction 2802 (AFUM_Rd(TAddr)), which is emulated for the receiving host B, or makes it appear as if the AFUM read instruction 2802 was initiated by an AFU 502 directly connected to the AFUM controller 220 of host B. Optionally, the address translation logic 2722 of host B can translate the real address specified by the host read instruction 2800 to obtain a translated address (TAddr). The CCR XLATE layer 2602b then passes this AFUM read instruction 2802 to the host transaction layer 306b of host B, which processes the AFUM read instruction 2802 as described above. Fig. 16 described and processed.

[0085] In the Fig. In the success case described in section 29, host B, in response to the host bus protocol read request initiated by host transaction layer 306b at block 1636, returns the data requested by the AFUM read instruction 2802 to the AFUM controller 220. Host B's host bus protocol interface layer 304b forwards the requested data to host transaction layer 306b, which issues a host read response 2900 providing the requested data and indicating "No error" (e.g., Host_Rd_Resp(Data,NErr)).

[0086] Host read response 2900 is received and processed by CCR XLATE layer 2602a of Host A. In response to receiving the host read response 2900, the response translation logic 2724 of CCR XLATE layer 2602a translates the host read response 2900 into an AFUM read response 2902 (e.g., AFUM_Rd_Resp(Data)), thereby emulating, or from Host A's perspective, the appearance that Host A is connected to attached memory 402. It should be noted that the "No Error" (NErr) indicator provided in the host read response 2900 causes response translation logic 2724 to provide AFUM_Rd_Resp(Data) instead of AFUM_Rd_Failed. The CCR XLATE layer 2602a forwards the AFUM read response 2902 to the host bus protocol interface 304a, which receives the AFUM read response 2902 as above with reference to Fig. 25 describes how this is handled. For example, the host bus protocol interface 304a can transmit the requested data to the requesting master (e.g., an L2 cache 230) in host A by using the host bus protocol of host A. The requesting master can then cache the requested data or process it in some other way.

[0087] Fig. Item 30 represents the case where a read error occurs in Host B. In this case, in response to the Host Bus Protocol read request initiated by Host Transaction Layer 306b at block 1636, Host B responds to Host Bus Protocol Interface Layer 304b with a message indicating a failure of the Host Bus Protocol read request. Host Bus Protocol Interface Layer 304b of Host B accordingly issues a Host Read Response 3000 indicating a read error (e.g., Host_Rd_Resp(Data,Err)). In some implementations, the read error information can be provided in a data field of a Host Read Response 3000.

[0088] Host read response 3000 is received and processed by CCR XLATE layer 2602a of host A. In response to receiving host read response 3000, the response translation logic 2724 of CCR XLATE layer 2602a translates host read response 3000 into an AFUM read response 3002 indicating a failure (e.g., AFUM_Rd_Failed). It should be noted that the `Err` value provided in host read response 3000 causes response translation logic 2724 to provide AFUM_Rd_Failed instead of AFUM_Rd_Resp(Data). The CCR XLATE layer 2602a forwards the AFUM read response 3002 to the host bus protocol interface 304a, which performs error handling as described above with reference to block 2514 of Fig. 25 described initiated.

[0089] With the following reference to Fig. Figures 31 to 33 illustrate time-space diagrams of a write command issued by a first host data processing system (e.g., Host A) to a connected host data processing system (e.g., Host B) via the data transmission interface provided by connected AFUM controllers 220, and various responses of the connected host data processing system to the write command according to one embodiment. As explained above, the AFUM controllers 220 of both hosts are configured for host-to-host memory sharing via protocol stack 2600 by setting configuration register 2712.

[0090] As in Fig. As shown in Figure 31, an AFUM controller 220 of the initiating host A issues a host write command 3100 (e.g., Host_Wr(Addr,Data)), which specifies a real address and data to be written to that real address. The host write command 3100 is issued to an AFUM controller 220 of the receiving host B. Upon receiving the host write command 3100, the CCR XLATE layer 2602b of host B translates the host write command 3100 and, optionally, the real address specified by the host write command 3100. For example, the command translation logic 2720 translates the host write command 3100 into an AFUM write command 3102 (AFUM_Wr(TAddr,Data)) which is emulated for the receiving host B or gives the appearance that the AFUM write command 3102 was initiated by an AFU 502 that is directly connected to the AFUM controller 220 of host B.Optionally, the address translation logic 2722 of host B can translate the real address specified by the host write command 3100 to obtain a translated address (TAddr). The CCR XLATE layer 2602b then passes this AFUM write command 3102 to the host transaction layer 306b of host B, which executes the AFUM write command 3102 as above, with reference to... Fig. 16 described and processed.

[0091] In the Fig. In the success case shown in Figure 32, host B responds to the host bus protocol write request initiated by host transaction layer 306b, such as with reference to block 1636 of Fig. 16 discusses the requested write operation and optionally returns a success indicator for the write request to the AFUM controller 220. (Some host bus protocols provide information about the success of write requests, while others do not. For those that do not, the AFUM controller 220 assumes success and provides the appropriate host response.) In response to the completion of the write request, host transaction layer 306b of host B issues a host write response 3200 indicating "No error" (e.g., Host_Wr_Resp(NErr)).

[0092] Host write response 3200 is received and processed by CCR XLATE layer 2602a of Host A. In response to receiving Host write response 3200, the response translation logic 2724 of CCR XLATE layer 2602a translates the Host write response 3200 into an AFUM write response 3202 (e.g., AFUM_Wr_Resp), thereby emulating, or from Host A's perspective, the appearance that an attached memory 402 has completed the requested write operation. It should be noted that the "No Error" (NErr) indicator provided in Host write response 3200 causes response translation logic 2724 to provide AFUM_Wr_Resp instead of AFUM_Wr_Failed. The CCR XLATE layer 2602a forwards the AFUM write response 3202 to the host bus protocol interface 304a, which receives the AFUM write response 3202 as above, with reference to Fig. 25 describes how this can be modified. For example, the host bus protocol interface 304a can report a success for the requested write operation to the requesting master (e.g., an L2 cache 230) in host A by using the host bus protocol from host A. Alternatively, the host bus protocol interface 304a can allow or require that the write request be terminated without issuing a host bus protocol message on the system structure of host A, in which case the AFUM write response 3202 can be discarded by the host transaction layer 306a.

[0093] Fig. Figure 33 represents the case where a write error occurs in Host B. In this case, Host B responds to the Host Bus Protocol write request made by Host transaction layer 306b at block 1636 of Fig. 16, initiated, sends a message to host B's host bus protocol interface layer 304b indicating a failed host bus protocol write request. Host B's host bus protocol interface layer 304b accordingly issues a host write response 3300 indicating a write error (e.g., Host_Wr_Resp(Err)).

[0094] Host write response 3300 is received and processed by CCR XLATE layer 2602a of host A. In response to receiving host write response 3300, the response translation logic 2724 of CCR XLATE layer 2602a translates the host write response 3300 into an AFUM write response 3302 indicating a failure (e.g., AFUM_Rd_Failed). It should be noted that the (Err) specification provided in host write response 3300 causes response translation logic 2724 to provide AFUM_Wr_Failed instead of AFUM_Wr_Resp. CCR XLATE layer 2602a forwards the AFUM write response 3302 to the host bus protocol interface 304a, which performs error handling as described above with reference to block 2514 of [document name missing in original text]. Fig. 25 described initiated.

[0095] With the following reference to Fig. Figure 34 presents a logical overview flowchart of an exemplary process for initializing data processing systems for shared memory use according to one embodiment. The process of Fig. Section 34 begins at block 3400 and continues with block 3402, which illustrates the host data processing systems 100 (e.g., Host A and Host B) connected for shared memory use, coordinating their respective allocations of memory areas in the real address space. For example, this coordination can be implemented by hypervisor and / or operating system software running on one or both of the host data processing systems 100. Additionally, each of the host data processing systems 100 initializes the page table entries 212 in the page frame table 210 to provide a translation from effective to real address on each of the hosts (at block 3404).

[0096] As further specified at block 3406, the host data transmission systems 100 exchange data with each other (e.g., via hypervisor software) to store in the system memory 108 of each host data processing system 100 acting as a receiving (or destination) host all page table entries used to translate real addresses that can be specified by host commands from an initiating host (block 3406). Each host data processing system 100 additionally initializes its respective AFUM controllers 220 and corresponding BAR registers 216 and 224 (at block 3408). As noted above, the initialization of the AFUM controllers 220 includes setting the configuration registers 2712 to specify host-to-host data exchange via the AFUM controllers 220. The initialization of BAR registers 216 and 224 initiates host bus protocol memory access requests (e.g., reads, writes, etc.).) on the system structures of the hosts, which are to be forwarded accordingly, either via a memory controller 106 to a local system memory 108 in the host or via an AFUM controller 220 to a receiving host. After block 3408, the process of . Fig. 34 on block 3410.

[0097] With the following reference to Fig. Figure 35 illustrates a time-space diagram of a write command issued by an AFU 502 to a host data processing system 100 and an associated response from the host data processing system 100 according to an embodiment that implements a fast-response write mode. As shown in Fig. As shown in Figure 11, the AFU 502 issues an AFUM write command 1100 (e.g., AFUM_Wr(Addr,Data)) to a host data processing system 100 via the protocol stack 500 of Fig. 5 out. In the previous embodiment described above, with reference to Fig. In steps 12 to 13, a host bus protocol write request corresponding to the AFUM write command 1100 is processed in the receiving host data processing system 100 before the host transaction layer 306 provides a host write response 1200 or 1300 for the AFU 502. In contrast, an AFUM controller 220 configured to operate in the fast-response write mode, as described in Fig. Figure 35 shows that instead an AFUM write command 3500 with a host write response 3502 indicating "No Error" (e.g., Host_Wr_Resp(NErr)) is issued, possibly before and without consideration of processing the host bus protocol write request in the receiving host data processing system 100. Issuing the host write response 3502 without considering the success or failure of the host bus protocol write attempts, which are determined by the translation / authorization error cases in Fig. Errors 14 to 15 must not occur. To prevent these errors, the relevant PTEs 212 are fixed in the receiving host.

[0098] With the following reference to Fig. Figure 36 presents a logical overview flowchart of an exemplary procedure by which a host transaction layer 306 of an AFUM controller 220 responds to a write command according to the one described in Fig. 35 illustrated quick-response writing mode answers. The process of Fig. Process 36 begins at block 3600 and then continues with block 3602, which illustrates a host transaction layer 306 of an AFUM controller 220 configured to operate in fast-response write mode, receiving an AFUM write command 3500 (e.g., AFUM_Wr(Addr,Data)). After block 3602, the process branches from Fig. Block 36 and continues in parallel with blocks 3604 and 3606. Block 3604 represents the host transaction layer 306 of an AFUM controller 220, which issues a host response 3502 indicating "No Error" (e.g., Host_Wr_Resp(NErr)) before processing a host bus protocol write request corresponding to the AFUM write command 3500 in the receiving host data processing system 100, without considering the processing of the host bus protocol write request itself. The process continues from block 3604 to join point 3619.

[0099] Referring to block 3606, host transaction layer 306 determines whether to skip the effective address translation specified in the AFUM write instruction 3500 and the write enforcement. Host transaction layer 306 may decide to skip the effective address translation and write enforcement, for example, based on the effective address of the AFUM instruction falling within a predetermined address range, a specification provided in the AFUM instruction and / or a configuration of the AFUM controller 220. In response to an affirmative determination at block 3606, the process proceeds to block 3618, which is described below. Otherwise, the process proceeds to block 3608.It should be clear that if a provision is made at block 3606 to skip address translation and write permission enforcement, other, unillustrated techniques, including appropriate configuration of page frame table 210, will be used to ensure that the effective address is within an allowed address range and has the necessary write permission.

[0100] Block 3608 illustrates the host transaction layer 306, which determines whether the ATC 226 contains an address translation entry to translate the effective address specified in the AFUM write instruction 3500 into a real address. In response to the host transaction layer 306 determining that the ATC 226 contains the relevant address translation entry, the process proceeds to block 3614, which is described below. Conversely, if the host transaction layer 306 determines that its ATC 226 does not contain the relevant address translation entry, the host transaction layer 306 initiates a transfer to the NMMU 228, via the host bus protocol interface layer 304 and the host bus protocol layer 302, of an NMMU translation request for the effective address specified by the AFUM write instruction 3500 (at block 3610).If the relevant page table entry 212 is fixed in the system memory 108, as above with reference to block 3406 of . Fig. As described in 34, the NMMU 228 succeeds in obtaining the required translation entry and supporting the requested address translation entry in the AFUM controller 220 for an installation in the ATC 226 (at a block 3612).

[0101] At block 3614, host transaction layer 306 protects against write protection errors by determining whether the address translation entry for the effective address specified by host write instruction 3500 indicates write permission for the effective address specified by AFUM write instruction 3500. If so, host transaction layer 306 initiates processing of the write operation specified by AFUM write instruction 3500 in host data processing system 100 by causing the host bus protocol interface layer 304 and host bus protocol layer 302 (at block 3616) to issue the corresponding host bus protocol write request on the system structure.However, if the host transaction layer 306 determines at block 3614 that the address translation entry does not provide write permission for the effective address specified by the AFUM write instruction 3500, the host transaction layer 306 initiates error handling, as shown at block 3618. After block 3616 or block 3618, the process exits. Fig. 36 to the junction point 3619. Once both sections of the process from Fig. The process ends when block 3619 converges again at block 3619. Fig. 36 on a block 3620.

[0102] After testing the quick-response writing mode, which, compared to the one in Fig. The alternative writing mode shown in sections 11 to 13 is described in more detail in Fig. As explained in sections 35 to 36, it should be clear that a design compromise can be reached between the allocation of data transmission resources (e.g., command queues, data transmission capacity, virtual channels, etc.) to the write command and the availability of information concerning the successful or unsuccessful completion of a host bus protocol write request at the receiving host data processing system 100. In particular, an early output of the host write response 3502, without regard to the success or failure of a write operation at the receiving host data processing system 100, allows the initiating participant (e.g., an AFU 502) to release its resources allocated to the write command more quickly, thus freeing these resources for earlier allocation to other commands.In the case of an AFU 502 directly connected to an AFUM controller 220, this time difference between the various write modes may not be significant enough to guarantee any loss of information regarding the success or failure of the write operation in the receiving host data processing system 100. However, in implementations where AFUM controllers 220 are connected for shared memory from host to host (especially across multiple hops), the use of the fast-response write mode can advantageously free up data transfer resources of the initiating data processing system 100 (and any data processing system 100 located between the initiating and receiving data processing systems 100), thereby reducing errors and / or performance problems resulting from the complete exhaustion of such data transfer resources and simplifying the design complexity.

[0103] Fig. Figure 37 is a time-space diagram of a write command issued from one host data processing system to another host data processing system, and an associated write response according to an embodiment that incorporates the fast write response mode and the protocol stack 2600 of Fig. 26 uses, as described above.

[0104] As in Fig. As shown in Figure 37, an AFUM controller 220 of the initiating host A issues a host write command 3700 (e.g., Host_Wr(Addr,Data)), which specifies a real address and data to be written to that real address. The host write command 3700 is issued to an AFUM controller 220 of the receiving host B. Upon receiving the host write command 3700, the CCR XLATE layer 2602b of host B translates the host write command 3700 and, optionally, the real address specified by the host write command 3700. For example, the command translation logic 2720 translates the host write command 3700 into an AFUM write command 3702 (AFUM_Wr(TAddr,Data)), which emulates, or gives the appearance to, the receiving host B that the AFUM write command 3702 was initiated by an AFU 502 directly connected to the AFUM controller 220 of host B.Optionally, the address translation logic 2722 of host B can translate the real address specified by the host write command 3700 to obtain a translated address (TAddr). The CCR XLATE layer 2602 then passes this AFUM write command 3702 to the host transaction layer 306b of host B, which executes the AFUM write command 3702 as above, with reference to... Fig. The processing described in section 16 involves initiating a host bus protocol write request on the system structure of host B to write the data, for example, to system memory 108.

[0105] Instead of waiting for the conclusion of the host bus protocol write request to provide a host response, host transaction layer 306b responds to the AFUM write command 3500 with a host write response 3704 indicating "No Error" (e.g., Host_Wr_Resp(NErr)), possibly before and without considering any processing of the host bus protocol write request in the receiving host data processing system 100. The host write response 3704 is received and processed by the CCR XLATE layer 2602a of host A. In response to receiving the host write response 3704, the response translation logic 2724 of the CCR XLATE layer 2602a translates the host write response 3704 into an AFUM write response 3706 (e.g., AFUM_Wr_Resp), thereby emulating, or from the perspective of host A, the appearance that an attached memory 402 has completed the requested write operation.The CCR XLATE layer 2602a forwards the AFUM write response 3706 to the host bus protocol interface 304a, which receives the AFUM write response 2702 as above with reference to . Fig. 25 describes how this can be modified. For example, the host bus protocol interface 304a can report a success for the requested write operation to the requesting master (e.g., an L2 cache 230) in host A by using the host bus protocol of host A. Alternatively, if permitted or required by the host bus protocol of host A, the host bus protocol interface 304a can allow the write request to be terminated without issuing a host bus protocol message on the system structure of host A, in which case the AFUM write response 3706 can be discarded by the host transaction layer 306a.

[0106] As indicated above, host-to-host memory sharing is not limited to connecting two hosts, but can instead be extended to any desired number of participating host processing systems and can utilize a large number of different connection topologies. For example, Fig. Figure 38 presents an overview block diagram of an exemplary topology of a data processing environment in which a plurality of host data processing systems 100 are interconnected in data exchange to support shared memory usage. As explained below, the memory shared by the interconnected data processing systems 100 can comprise a variety of different types of memory, for example, memory provided by system memory 108 of host data processing systems 100, by attached memory 402, and / or by a memory facility. It should be clear that Fig. 38 omits the illustration of many components of the illustrated host data processing system 100 in order to avoid unnecessary incomprehensibility of inventive details.

[0107] In the illustrated example, a data processing environment 3800 comprises four host data processing systems 100a, 100b, 100c and 100d, each comprising several processing nodes 102, as previously described with reference to Fig. As described in sections 1 to 2. In this example, each host data processing system 100 comprises at least two processing nodes. Thus, host data processing system 100a comprises at least processing nodes 102a1 to 102a2, host data processing system 100b comprises at least processing nodes 102b1 to 102b2, host data processing system 100c comprises at least processing nodes 102c1 to 102c2, and host data processing system 100d comprises at least processing nodes 102d1 to 102d2. In this example, one or more processing nodes 102 of each host processing system 100 comprise one or more AFUM controllers 220.For example, processing node 102a1 of host data processing system 100a includes AFUM controllers 220a1 and 220a2, processing node 102b1 of host data processing system 100b includes AFUM controllers 220b1 to 220b4, processing node 102c1 of host data processing system 100c includes AFUM controllers 220c1 and 220c2, and processing node 102d1 of host data processing system 100d includes AFUM controllers 220d1 and 220d2. To support host-to-host memory sharing, the AFUM controller 220a2 of host processing node 100a is connected to the AFUM controller 220d1 of host processing node 100d, the AFUM controller 220a1 of host processing node 100a is connected to the AFUM controller 220b1 of host processing node 100b, and the AFUM controller 220b2 of host processing node 100b is connected to the AFUM controller 220c2 of host processing node 100c.Thus, each host data processing system 100 is connected to each other host data processing systems 100a to 100d via one or more hops for data exchange. Although in at least some embodiments it would be preferable to avoid the cost and complexity of other mechanisms for connecting the host data processing systems 100 for data exchange, it should be clear that the host data processing systems 100 can optionally be connected by other additional means, such as a switch 3804, which in the illustrated embodiment is connected to the AFUM controller 220d2 of host data processing system 100d and the AFUM controller 220b3 of host data processing system 100b.

[0108] The data processing environment 3800 additionally includes a memory facility 3802, which provides a high-capacity memory tank available for shared use by all host data processing systems 100 in the data processing environment 3800. In this example, the memory facility 3802 includes a host bus 3810, which supports the connection of multiple memory controllers 106, each supporting a respective facility memory 3812. The memory facility 3802 additionally includes an AFUM controller 220e1, which is connected for data exchange between the switch 3804 and the host bus 3810, and an AFUM controller 220e2, which is connected for data exchange between the host bus 3810 and the attached memory 402e1. The 3802 memory unit also includes an AFUM interface 225, to which an attached 402e2 memory unit is connected.

[0109] To reduce costs and complexity, the memory facility 3802 preferably omits the processing nodes 102 for general-purpose processing (but may, for example, include a service processor). The memory facility 3802 preferably includes a fixed page frame table 210 (not illustrated) stored in one or more facility memories 3812, into which PTEs 212 can be written by host data processing systems 100, for example, by using AFUM write instructions. The memory facility 3802 preferably includes or is connected to an NMMU 228 (not illustrated) to obtain all address translation entries needed to translate addresses specified in incoming instructions.

[0110] As noted above, the depicted 3800 data processing system environment supports shared read and write access to all of the various memory types within the 3800 data processing system environment by requesters in all host data processing systems 100 via the described data transfer interface. For example, each host data processing system 100, if the host data processing systems 100a through 100d, the memory facility 3802, and the data transfer links connecting them, as shown in Fig. 34, as described, configured, and enabled, each host computer 100 can access its own system memory 108 or the system memory 108 of any of the other host computer systems 100, as represented by the system memory 108c of host computer system 100c. Likewise, each host computer 100 can access its own attached memory 402 or the attached memory 402 of any of the other host computer systems 100 or the memory facility 3802, as represented by the attached memory 402b1 of host computer system 100b and the attached memory 402e1 through 402e2 in memory facility 3802. Furthermore, each host computer 100 can access the facility memory 3812 of memory facility 3802.

[0111] When host-to-host access to shared memory in the 3800 data processing system environment occurs via one or more intermediary hosts, the flow of multi-hop commands and responses is the same as previously described, except that the transmission of commands and responses across the intermediary hosts (hops) is facilitated by using the host bus protocol of the intermediary hosts. In certain cases, the native host bus protocol of a host data processing system 100 may not provide a set of commands and responses sufficient to transmit all commands and responses used in the described host-to-host memory sharing. In such cases, the host bus protocol is preferably extended as needed to support the described transmission of host bus protocol commands and responses.Of course, alternative embodiments can implement a host bus protocol that is more directly compatible with the described commands and responses. Support for multi-hop memory access as described may also require the implementation of virtual channels by the host bus protocol of the host data processing systems' system architecture and on the data transmission links between the AFUM 220 controllers to avoid deadlocks. The implementation of such virtual channels is known to those skilled in the art.

[0112] To illustrate the flow of multi-hop commands and responses, a multi-hop host read command and response are shown, which Fig. 28 to 29 correspond to, in Fig. 29 specified, a multi-hop host write command and a response that Fig. 31 to 32 correspond to, will be in Fig. 40 was specified, and a multi-hop host write command and response that Fig. 37 correspond to, will be in Fig. 41. Data flows that illustrate error cases (e.g., corresponding to the one-hop error cases described in Fig. 30 and Fig. 33 are shown), are omitted for the sake of brevity, but the implementation of these data flows will be easily clear to the expert from the following discussion.

[0113] With the following reference to Fig. Figure 39 illustrates a time-space diagram of a multi-hop read instruction issued by an initiating host data processing system to a receiving host data processing system via an intermediate host data processing system, and an associated response according to one embodiment.

[0114] In the example of Fig. 39 initiates an L2 cache 230 to send a host bus protocol read request (not shown) to the system structure of the host data processing system 100a. The host bus protocol read request specifies a real address that identifies data to be requested by the associated processor core 200. In this example, the requested data resides in a system memory 108 of the host data processing system 100c. Upon receiving the host bus protocol read request, the AFUM controller 220a1 of the host data processing system 100a, by reference to its BAR 224, determines that it is responsible for the real address of the host bus protocol read request and accordingly issues a host read instruction 3900 (e.g., Host_Rd(Addr)) to the AFUM controller 220b1 of the host data processing system 100b.In response to receiving a host read command 3900, the CCR XLATE layer 2602 of the AFUM controller 220b1 translates the host read command 3900 and, optionally, the real address specified by the host read command 3900 to obtain an AFUM read command 3902 (AFUM_Rd(TAddr1)). The CCR XLATE layer 2602 of the AFUM controller 220b1 then passes the AFUM read command 3902 to the host transaction layer 306 of the AFUM controller 220b1, which initiates a host bus protocol read request 3904 (e.g., HBP_Rd(TAddr1)) on the system structure of the host data processing system 100b.

[0115] In response to receiving the host bus protocol read request 3904 on the system structure of the host data processing system 100b, the AFUM controller 220b2 of the host data processing system 100b determines, by reference to its BAR 224, that it is responsible for the real address of the host bus protocol 3904 and accordingly issues a host read command 3906 (e.g. Host_Rd(TAddr1)) to the AFUM controller 220c2 of the host data processing system 100c. In response to receiving a host read command 3906, the CCR XLATE layer 2602 of the AFUM controller 220c2 translates the host read command 3906 and optionally the translated real address specified by the host read command 3906 to obtain an AFUM read command 3908 (AFUM_Rd(TAddr2)).The CCR XLATE layer 2602 of the AFUM controller 220c2 then passes this AFUM read instruction 3908 to the host transaction layer 306 of the AFUM controller 220c2, which in turn initiates a host bus protocol read request on the system structure of the host data processing system 100c. For example, the host bus protocol read request might request data stored in the system memory 108c. In this case, a match between the real address specified by the host bus protocol read request and an address range specified by a BAR 216 of the memory controller 106 causes the memory controller 106 to access the requested data in the system memory 108c and return the requested data to the AFUM controller 220c2.

[0116] In response to receiving the requested data, the host transaction layer 306 of the AFUM controller 220c2 issues a host read response 3910, which provides the requested data and indicates "No error" (e.g., Host_Rd_Resp(Data,NErr)). The host read response 3910 is received and processed by the CCR XLATE layer 2602 of the AFUM controller 220b2 of the host data processing system 100b. In response to receiving the host read response 3910, the CCR XLATE layer 2602 of the AFUM controller 220b2 translates the host read response 3910 into an AFUM read response 3912 (e.g., AFUM_Rd_Resp(Data)) and forwards the AFUM read response 3912 to the host bus protocol interface layer 304 of the AFUM controller 220b2. In response, the host bus protocol interface layer 304 initiates a host bus protocol read response 3914 (e.g., HBP_Rd_Resp(Data, NErr)) on the system structure of the host data processing system 100b.In response to receiving the Host Bus Protocol Read Response 3914, the Host Transaction Layer 306 of an AFUM Controller 220b1 issues a Host Read Response 3916, which provides the requested data and indicates "No Error" (e.g., Host_Rd_Resp(Data,NErr)). The Host Read Response 3916 is received and processed by the CCR XLATE Layer 2602 of the AFUM Controller 220a1 of the Host Data Processing System 100a. In response to receiving the host read response 3916, the CCR XLATE layer 2602 translates the host read response 3916 into an AFUM read response 3918 (e.g., AFUM_Rd_Resp(Data)) and forwards the AFUM read response 3918 to the host bus protocol interface layer 304 of the host data processing system 100a. In response, the host bus protocol interface layer 304 initiates its own non-illustrated host bus protocol read response (e.g.,HBP_Rd_Resp(Data, NErr)) on the system structure of the host data processing system 100a, which delivers the requested data to the original requester (e.g. L2 cache 230).

[0117] With the following reference to Fig. Figure 40 presents a time-space diagram of a multi-hop write instruction issued by an initiating host data processing system to a receiving host data processing system via an intermediate host data processing system, and an associated response according to one embodiment.

[0118] In the example of Fig. 40 initiates an L2 cache 230, which does not illustrate a host bus protocol write request, on the system structure of the host data processing system 100a. The host bus protocol write request specifies a real address and data to be written to that real address. Upon receiving the host bus protocol write request, the AFUM controller 220a1, by referencing its BAR 224, determines that it is responsible for the real address of the host bus protocol write request and accordingly issues a host write command 4000 (e.g., Host_Wr(Addr,Data)) to the AFUM controller 220b1 of the host data processing system 100b. In response to receiving the host write command 4000, the CCR XLATE layer 2602 of the AFUM controller 220b1 translates the host write command 4000 and optionally the real address specified by the host write command 4000 to receive an AFUM write command 4002 (AFUM_Wr(TAddr1,Data)).The CCR XLATE layer 2602 of the AFUM controller 220b1 then passes the AFUM write command 4002 to the host transaction layer 306 of the AFUM controller 220b1, which initiates a host bus protocol write request 4004 (e.g. HBP_Wr(TAddr1,Data)) on the system structure of the host data processing system 100b.

[0119] In response to receiving the host bus protocol write request 4004 on the system structure of the host data processing system 100b, the AFUM controller 220b2, by reference to its BAR 224, determines that it is responsible for the real address of the host bus protocol 4004 and accordingly issues a host write command 4006 (e.g., Host_Wr(TAddr1,Data)) to the AFUM controller 220c2 of the host data processing system 100c. Upon receiving the host write command 4006, the CCR XLATE layer 2602 of the AFUM controller 220c2 translates the host write command 4006 and, optionally, the translated real address specified by the host write command 4006 to obtain an AFUM write command 4008 (e.g., AFUM_Wr(TAddr2,Data)).The CCR XLATE layer 2602 of the AFUM controller 220c2 then passes this AFUM write instruction 4008 to the host transaction layer 306 of the AFUM controller 220c2, which in turn initiates a host bus protocol write request on the system structure of the host data processing system 100c. For example, the host bus protocol write request might request the payload to be stored in the system memory 108c. In this case, a match between the real address specified by the host bus protocol write request and an address range specified by a BAR 216 of the memory controller 106 causes the memory controller 106 to store the payload of the host bus protocol write request in the system memory 108c.

[0120] In response to the successful completion of the host bus protocol write request in host data processing system 100c (which can be confirmed by a response on the system structure of host data processing system 100c), the host transaction layer 306 of AFUM controller 220c2 in host data processing system 100c issues a host write response 4010 indicating "No error" (e.g., Host_Wr_Resp(NErr)). The host write response 4010 is received and processed by the CCR XLATE layer 2602 of AFUM controller 220b2 in host data processing system 100b. In response to receiving the host write response 4010, the CCR XLATE layer 2602 of the AFUM controller 220b2 translates the host write response 4010 into an AFUM write response 4012 (e.g. AFUM_Wr_Resp) and forwards the AFUM write response 4012 to the host bus protocol interface layer 304 of the AFUM controller 220b2.In response, the host bus protocol interface layer 304 initiates a host bus protocol write response 4014 (e.g., HBP_Wr_Resp(NErr)) on the system structure of the host data processing system 100b. As noted earlier, some host bus protocols do not natively include a host bus protocol write response indicating "No Error". In embodiments that use end-to-end data transmission of write responses, as in . Fig. As shown in Figure 40, the message sets of such host bus protocols can be extended to allow data transmission on the system structure of a write response indicating "No error" (e.g., the host bus protocol write response 4014). Of course, an alternative host bus protocol that is more directly compatible with the described message protocol can be implemented.

[0121] In response to receiving the Host Bus Protocol write response 4014, the Host Transaction Layer 306 of the AFUM Controller 220b1 issues a Host Write Response 4016 indicating "No Error" (e.g., Host_Wr_Resp(NErr)). The Host Write Response 4016 is received and processed by the CCR XLATE Layer 2602 of the AFUM Controller 220a1 of the Host Data Processing System 100a. In response to receiving the host write response 4016, the CCR XLATE layer 2602 of the AFUM controller 220a1 translates the host write response 4016 into an AFUM write response 4018 (e.g. AFUM_Rd_Resp) and forwards the AFUM write response 4018 to the host bus protocol interface layer 304 of the AFUM controller 220a1.In response, the host bus protocol interface layer 304 can initiate a host bus protocol write response on the system structure of the host data processing system 100a, if required or permitted by the host bus protocol of the host data processing system 100a.

[0122] With the following reference to Fig. 41 illustrates a time-space diagram of a multi-hop write instruction issued by an initiating host data processing system to a receiving host data processing system via an intermediate host data processing system, and an associated response according to a further embodiment implementing a fast write response mode.

[0123] In the example of Fig. 41 initiates an L2 cache 230, which does not illustrate a host bus protocol write request, on the system structure of the host data processing system 100a. The host bus protocol write request specifies a real address and data to be written to that real address. Upon receiving the host bus protocol write request, the AFUM controller 220a1, by reference to its BAR 224, determines that it is responsible for the real address of the host bus protocol write request and accordingly issues a host write command 4100 (e.g., Host_Wr(Addr,Data))) to the AFUM controller 220b1 of the host data processing system 100b. In response to receiving the host write command 4100, the CCR XLATE layer 2602 of the AFUM controller 220b1 translates the host write command 4100 and optionally the real address specified by the host write command 4100 to receive an AFUM write command 4102 (AFUM_Wr(TAddr1,Data)).The CCR XLATE layer 2602 of the AFUM controller 220b1 then passes the AFUM write command 4102 to the host transaction layer 306 of the AFUM controller 220b1.

[0124] Instead of waiting for the write operation to complete, the host transaction layer 306 of the AFUM controller 220b1 responds to the AFUM write command 4102 with a host write response 4116, which indicates "No error" regardless of whether the write operation was processed (e.g., Host_Wr_Resp(NErr)). The host write response 4116 is received and processed by the CCR XLATE layer 2602 of the AFUM controller 220a1, which translates the host write response 4116 into an AFUM write response 4118 (e.g., AFUM_Wr_Resp). The CCR XLATE layer 2602 of the AFUM controller 220a1 forwards the AFUM write response 4118 to the associated host bus protocol interface layer 304, which in turn can initiate a host bus protocol write response on the system structure of the host data processing system 100a, if required or permitted by the host bus protocol of the host data processing system 100a.

[0125] In addition to issuing the host write response 4116 to the AFUM write command 4102, host transaction layer 306 also responds by issuing a host bus protocol write request 4104 (e.g., HBP_Wr(TAddr1,Data)) on the system structure of the host data processing system 100b. Upon receiving the host bus protocol write request 4104 on the system structure of the host data processing system 100b, the AFUM controller 220b2 determines, by reference to its BAR 224, that it is responsible for the real address of the host bus protocol 4104 and accordingly issues a host write command 4106 (e.g., Host_Wr(TAddr1,Data)) to the AFUM controller 220c2 of the host data processing system 100c.In response to receiving the host write command 4106, the CCR XLATE layer 2602 of the AFUM controller 220c2 translates the host write command 4106 and optionally the translated real address specified by the host write command 4106 to receive an AFUM write command 4108 (e.g. AFUM_Wr(TAddr2,Data)). The CCR XLATE layer 2602 of the AFUM controller 220c2 then passes this AFUM write command 4108 to the host transaction layer 306 of the AFUM controller 220c2, which in turn initiates a host bus protocol write request on the system structure of the host data processing system 100c and simultaneously issues a host write response 4110, which indicates "No error" (e.g. Host_Wr_Resp(NErr)) regardless of the processing of the host bus protocol write command.

[0126] Host write response 4110 is received and processed by the CCR XLATE layer 2602 of the AFUM controller 220b2 of the host data processing system 100b. In response to receiving the host write response 4110, the CCR XLATE layer 2602 translates the host write response 4110 into an AFUM write response 4112 (e.g., AFUM_Wr_Resp) and forwards the AFUM write response 4112 to the host bus protocol interface layer 304 of the AFUM controller 220b2. As indicated, the host bus protocol interface layer 304 of the AFUM controller 220b2 does not forward the AFUM write response 4112 and thus omits forwarding the AFUM write response 4112 to the host data processing system 100a.

[0127] With regard to the preceding description of shared memory usage through multi-hop data transfer, the 3800 data processing environment can be configured to implement any of several different alternative modes for handling shared multi-hop memory usage. In one mode, multi-hop read and write operations can be handled using synchronous end-to-end data transfer, as described in Fig. Figures 39 to 40 are shown. In a second mode, multi-hop read operations can be processed by using synchronous end-to-end data transmission, as shown in Fig. 39 shown, and multi-hop write operations can be handled by using the asynchronous data transfer of the fast write response mode, as shown in Fig. 41 shown. In a third mode, multi-hop writes can be performed by using the in Fig. The asynchronous data transfer shown in Figure 41 is not permitted, and multi-hop reads via the data transfer interface provided by the AFUM controller 220 are not allowed. Instead, in this third mode, reads from remotely located memory can be implemented using conventional Remote Direct Memory Access (RDMA) write operations. For example, an initiating host that wants to read from remotely located memory in a receiving host can write a read destination address from which data should be read into a specified memory location in the receiving host. In response to the receiving host detecting the write operation to the specified memory location, the receiving host accesses the requested data using the read destination address and writes the data into the memory of the initiating host.

[0128] With the following reference to Fig. Figure 42 presents a block diagram of an exemplary design flow 4200, which is used, for example, for the design of semiconductor IC logic, simulation, testing, layout, and fabrication. The design flow 4200 comprises processes, machines, and / or mechanisms for processing design structures or units to generate logically or otherwise functionally equivalent representations of the design structures and / or units described herein. The design structures processed and / or generated by the design flow 4200 may be encoded on machine-readable transmission or storage media to include data and / or instructions that, when executed or otherwise processed on a data processing system, generate a logically, structurally, mechanically, or otherwise functionally equivalent representation of hardware components, circuits, units, or systems.The machines include, but are not limited to, all machines used in an IC design process, such as those used to design, manufacture, or simulate a circuit, component, unit, or system. For example, the machines may include: lithography machines, machines and / or equipment for generating masks (e.g., electron beam writers), computers or equipment for simulating design structures, any device used in the manufacturing or testing process, or any machine for programming functionally equivalent representations of the design structures into any medium (e.g., a machine for programming a programmable gate array).

[0129] The Design Flow 4200 can vary depending on the type of representation being developed. For example, a Design Flow 4200 for creating an application-specific integrated circuit (ASIC) may differ from a Design Flow 4200 for developing a standard component or from a Design Flow 4200 for instantiating the design in a programmable array, such as a programmable gate array (PGA) or a field-programmable gate array (FPGA) developed by Altera. ® Inc. or Xilinx ® Inc. is offered.

[0130] Fig.Figure 42 illustrates several such design structures, including an input design structure 4220, which is preferably processed by a design process 4200. The design structure 4220 can be a logical simulation design structure that is generated and processed by the design process 4200 to produce a logically equivalent functional representation of a hardware unit. The design structure 4220 can also, or alternatively, include data and / or program instructions that, when processed by the design process 4200, generate a functional representation of the physical structure of a hardware unit. Regardless of whether the design structure 4200 represents functional and / or structural design features, it can be generated using electronic computer-aided design (ECAD) as implemented by a core developer / designer.When the design structure 4220 is encoded on a machine-readable data transmission, gate array, or storage medium, it can be accessed and processed by one or more hardware and / or software modules in the design process 4200 to represent an electronic component, circuit, electronic or logic module, device, unit, or system, as shown herein, for example. The design structure 4220 may therefore include files or other data structures, including human- and / or machine-readable source code, compiled structures, and computer-executable code structures, which, when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design.Such data structures may include Hardware Description Language (HDL) design entities or other data structures that are conformal to and / or compatible with lower-level HDL design languages, such as Verilog and VHDL, and / or higher-level design languages ​​such as C or C++.

[0131] The Design Process 4200 preferably uses and integrates hardware and / or software modules to synthesize, translate, or otherwise process a design / simulation that is functionally equivalent to the components, circuits, units, or logic structures shown herein, in order to generate a netlist 4280 that may contain design structures such as the Design Structure 4200. The netlist 4280 may, for example, contain compiled or otherwise processed structures that represent a list of wires, discrete components, logic gates, control circuits, I / O units, models, etc., that describe the connections to other elements and circuits in the design of an integrated circuit.The netlist can be synthesized using an iterative process in which the netlist is resynthesized once or several times, depending on the design specifications and parameters for the unit. Just as with other design structure types described herein, the netlist 4280 can be recorded on a machine-readable storage medium or programmed into a programmable gate array. The medium can be non-volatile storage, such as a magnetic or optical disk drive, a programmable gate array, compact flash memory, or other flash memory. Alternatively, or in addition, the medium can be system or cache memory, or buffer memory.

[0132] The design process 4200 can include hardware and software modules for processing a variety of input data structure types, including the netlist 4280. Such data structure types may, for example, be found in library elements 4230 and comprise a set of commonly used elements, circuits, and units, including models, layouts, and symbolic representations for a particular manufacturing technology (e.g., various technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications 4240, characterization data 4250, verification data 4260, design rules 4270, and test data files 4285, which may include input test patterns, output test results, and other test information.Design process 4200 may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, and process simulation for operations such as casting, molding, and compression molding. A person skilled in the art of mechanical design can recognize the extent of possible mechanical design tools and applications used in design process 4200 without deviating from the scope of protection and inventive concept of the invention. Design process 4200 may also include modules for performing standard circuit design processes, such as timing analysis, verification, design rule checking, and the placement and routing of operations.

[0133] The design process 4200 uses and integrates logical and physical design tools, such as HDL compilers and simulation model build tools, to process the design structure 4220, along with some or all of the supporting data structures shown, and any additional mechanical design or data (where applicable), to generate a second design structure 4290. The design structure 4290 resides on a storage medium or programmable gate array in a data format suitable for exchanging data between mechanical units and structures (e.g., information stored in IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or reproducing such mechanical design structures).Similar to design structure 4220, design structure 4290 preferably comprises one or more files, data structures, or other computer-encoded data or instructions located on transmission or data storage media, which, when executed by an ECAD system, generate a logically or otherwise functionally equivalent form of one or more embodiments of the invention. In one embodiment, design structure 4290 may include a compiled executable HDL simulation model that functionally simulates the units shown herein.

[0134] The Design Structure 4290 can also use a data format used for exchanging layout data for integrated circuits and / or a symbolic data format (e.g., information stored in a GDSII (GDS2), HL1, OASIS, map files, or any other suitable format for storing such design data structures). The Design Structure 4290 can contain information such as symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, metal planes, vias, shapes, data for routing through the manufacturing line, and any other data requested by a manufacturer or another designer / developer to create a unit or structure as described above and shown herein.The design structure 4290 can then proceed to a stage 4295, at which the design structure 4290 continues, for example, with a tape-out, is released for manufacturing, is released for a mask house, is sent to another design house, is sent back to the customer, etc.

[0135] As described, in at least one embodiment, a data transmission interface of a second host data processing system receives a host command in a first command set from a first host data processing system. The host command specifies a memory access to memory connected to the second host data processing system. The data transmission interface translates the host command into a command in a different second command set, which emulates connecting an attached functional unit to the data transmission interface. The data transmission interface displays the second command for a host bus protocol interface of the second host data processing system.Based on the receipt of the second command, the host bus protocol interface on a system structure of the second host data processing system initiates a host bus protocol memory access request, which specifies the memory access.

[0136] Although various embodiments have been shown and described in detail, it will be clear to a person skilled in the art that various changes in form and detail can be made to them without deviating from the inventive concept and the scope of protection of the claims in the Annex, and that these alternative implementations as a whole fall within the scope of protection of the claims in the Annex.

[0137] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, processes, and computer program products according to various embodiments of the present invention. In this context, each block in the flowcharts or block diagrams can represent a module, segment, or part of instructions that includes one or more executable instructions for implementing the specific logical function(s). In some alternative implementations, the functions specified in the block may occur in a different order than shown in the figures. For example, two blocks shown consecutively may actually be executed essentially in parallel, or the blocks may sometimes be executed in reverse order, depending on the functionality involved.It should also be noted that each block of the block diagrams and / or flowcharts, as well as combinations of blocks in the block diagrams and / or flowcharts, can be implemented by special hardware-based systems that perform the specified functions or actions, or execute combinations of special hardware and computer instructions.

[0138] Although aspects relating to a computer system that executes program code controlling the functions of the present invention have been described, it should be clear that the present invention can alternatively be implemented as a program product with a computer-readable storage unit that stores program code which can be processed by a processor of a data processing system to cause the data processing system to perform the described functions. The computer-readable storage unit may comprise volatile or non-volatile memory, an optical or magnetic disk, or the like, but does not exclude fixed content such as signal propagation per se, transmission media per se, and energy forms per se.

[0139] For example, the program product may include data and / or instructions that, when executed or otherwise processed on a data processing system, generate a logically, structurally, or otherwise functionally equivalent representation (including a simulation model) of hardware components, circuits, units, or systems disclosed herein. Such data and / or instructions may include hardware description language (HDL) design entities or other data structures that are conformal to and / or compatible with lower-level HDL design languages, such as Verilog and VHDL, and / or higher-level design languages, such as C or C++. Furthermore, the data and / or instructions may also use a data format suitable for exchanging layout data of integrated circuits and / or a symbolic data format (e.g.,Information stored in a GDSII (GDS2), HL1, OASIS, map files or any other suitable format for storing such design data structures) is used.

Claims

[1] Method for data transmission in a data processing environment (3800), wherein the method comprises: Configuring a data transfer interface of a second host data processing system (100b), wherein the data transfer interface comprises a first operating mode that supports connecting an attached functional unit (222) to the second host data processing system (100b), and a second operating mode that supports connecting a first host data processing system (100a) to the second host data processing system (100b) for shared host-to-host memory use, and wherein configuring the data transfer interface includes configuring the data transfer interface in the second operating mode to support shared host-to-host memory use; Receiving, from the first host data processing system (100a) at the data transmission interface of the second host data processing system (100b) a host instruction in a first instruction set, wherein the host instruction specifies a memory access to a memory (402b1) connected to the second host data processing system (100b), wherein both the first and the second host data processing system (100b) have a first and second coherent memory area respectively, and wherein the first and second coherent memory areas are not coherent with each other; Translating the host command into a second command in a different second command set, such that the first host data processing system (100a) emulates an attached functional unit (222) connected to the data transmission interface of the second host data processing system (100b); Transmission of the second command to a host bus protocol interface of the second host data processing system (100b), wherein the second host data processing system (100b) comprises a system structure to which a plurality of data transmission participants are connected; and Based on the receipt of the second Initiate command, through the host bus protocol interface on the system structure of the second host data processing system (100b), a host bus protocol memory access request is issued, specifying the memory access. [2] Method according to claim 1, wherein: the second command specifies an address; The method further includes fixing a page table entry (212) for the address in a page frame table (210) of the second host data processing system (100b). [3] Method according to claim 1, wherein: the data transmission interface is a first data transmission interface; the second host data processing system (100b) includes a second data transmission interface which is one of the majority of data transmission participants connected to the system structure; The host command is a first host command; and The method further includes the second data transmission interface based on receiving the host bus protocol memory access request on the system structure, which issues a second host command specifying the memory access. [4] Method according to claim 3, wherein an output of the second host command comprises an output of the second host command based on an address specified in the host bus protocol memory access request which belongs to a predetermined address range. [5] Method according to claim 3, wherein output of the second host instruction comprises output of the second host instruction to a third host data processing system (100c) comprising at least one processor core and a main memory, wherein the third host data processing system (100c) has a third coherent main memory area which is not coherent with the first and second coherent main memory areas. [6] Method according to claim 1, wherein: The translation process involves translating a first address, specified in the host command, into a second address and placing the second address in the second command. [7] Method according to claim 1, wherein: The host bus protocol memory access command is a read command; the procedure further features: the second host data processing system (100b) that accesses data specified by the host bus protocol memory access request in a system memory of the second host data processing system (100b) and returns the data to the data transmission interface; the data transmission interface of the second host data processing system (100b) which outputs a read response to the first host data processing system (100a), wherein the read response includes the data. [8] The method of claim 7, further comprising: a data transmission interface of the first host data processing system (100a) that receives the read response and translates the read response into a different second response set that emulates an attached working memory connected to the data transmission interface. [9] Method for data transmission in a data processing environment (3800), wherein the method comprises: Receiving, from a first host data processing system (100a) at a data transmission interface of a second host data processing system (100b) a host instruction in a first instruction set, wherein the host instruction specifies a memory access to a memory connected to the second host data processing system (100b), wherein both the first and the second host data processing system (100b) have a first and second coherent memory area respectively, and wherein the first and second coherent memory areas are not coherent with each other; Translating the host command into a second command in a different second command set, such that the first host data processing system (100a) emulates an attached functional unit connected to the data transmission interface of the second host data processing system (100b); Transmission of the second command to a host bus protocol interface (108) of the second host data processing system (100b), wherein the second host data processing system (100b) comprises a system structure to which a plurality of data transmission participants are connected; based on the receipt of the second Initiate command, through the host bus protocol interface on the system structure of the second host data processing system (100b), a host bus protocol memory access request specifying the memory access, wherein the host bus protocol memory access command is a write command; the second host data processing system (100b) that writes data specified by the host bus protocol memory access request to a system memory of the second host data processing system (100b); and the data transmission interface of the second host data processing system (100b), before the write operation is completed and without regard to the success or failure of the write operation, which issues a write response to the first host data processing system indicating a success of the write command. [10] Data transmission controller (220) for a second host data processing system (100b) with a system structure to which a plurality of data transmission participants are connected, wherein the data transmission controller (220) comprises: Controller circuit configured to perform: Receiving, from a first host data processing system (100a), a host instruction in a first instruction set, wherein the host instruction specifies a memory access to a memory connected to the second host data processing system (100b), wherein both the first and the second host data processing system (100b) have a first and second coherent memory area respectively, and wherein the first and second coherent memory areas are not coherent with each other; Translating the host command into a second command in a different second command set, such that the first host data processing system (100a) emulates connecting an attached functional unit to the data transmission controller (220), wherein: the data transmission controller (220) has a first operating mode that supports connecting an attached functional unit to the second host data processing system (100b) and a second operating mode that supports connecting the second host data processing system (100b) to the first data processing system (100a) for shared host-to-host memory use; the controller circuit is configured to perform translation only based on a configuration of the data transfer controller in the second operating mode to support shared host-to-host memory usage; Transmission of the second command to a host bus protocol interface (108); and Based on the receipt of the second Initiate command, through the host bus protocol interface (108) on the system structure of the second host data processing system (100b), a host bus protocol memory access request specifying the memory access. [11] Data transmission controller (220) according to claim 10, wherein: The translation process involves translating a first address, specified in the host command, into a second address and placing the second address in the second command. [12] Data transmission controller (220) according to claim 10, wherein: The host bus protocol memory access command is a read command; The controller circuit is further configured to perform: Receiving data from a system memory of the second host data processing system (100b) specified by the host bus protocol memory access request; Output to the first data processing system, a read response that includes the data. [13] System that features: the data transmission controller (220) according to claim 12, wherein the data transmission controller is a first data transmission controller; a second data transmission controller (220) of the second host data processing system (100b) connected to the first data transmission controller of the second host data processing system (100b), the second data transmission controller comprising a controller circuit configured to: Receiving the read response and translating the read response into a different second response set that emulates an attached working memory connected to the second data transmission controller (220). [14] System that features: the data transmission controller (220) according to claim 10; the host data processing system (100) connected to the data transmission controller (220), wherein the host data processing system (200) includes a system memory that stores a page frame table (210); where: the second command specifies an address; the host data processing system (100) is configured to fix a page table entry (212) for the address in the page frame table (210) of the system memory. [15] System that features: the host command, which is a first host command; the data transmission controller (220) according to claim 10, wherein the data transmission controller (220) is a first data transmission controller (220a), and wherein the host command is a first host command; the second host data processing system (100b) is connected to the data transmission controller (220), wherein the second host data processing system (100b) includes a second data transmission controller (220b), wherein the second data transmission controller (220b) issues a second host command specifying the memory access based on receiving the host bus protocol memory access request on the system structure. [16] System according to claim 15, wherein the second data transmission controller (220b) issues the second host command based on an address specified in the host bus protocol memory access request which belongs to a predetermined address range. [17] System according to claim 15, wherein: the second data transmission controller (220b) issues the second host command to a third host data processing system (100c) that is connected to the second host data processing system. [18] Data transmission controller (220) for a second host data processing system (100b) with a system structure to which a plurality of data transmission participants are connected, wherein the data transmission controller (220) has: Controller circuit configured to perform: Receiving, from a first host data processing system (100a), a host instruction in a first instruction set, wherein the host instruction specifies a memory access to a memory (402b) connected to the second host data processing system (100b), wherein both the first and the second host data processing system (100b) have a first and second coherent memory area respectively, and wherein the first and second coherent memory areas are not coherent with each other; Translating the host command into a second command in a different second command set, so that the first host data processing system (100a) emulates connecting an attached functional unit to the data transmission controller (220); Transmission of the second command to a host bus protocol interface (108); based on a reception of the second Initiate command, through the host bus protocol interface (108) on the system structure of the second host data processing system (100b), a host bus protocol memory access request specifying the memory access, wherein the host bus protocol memory access command is a write command; Outputting a write response to the first data processing system (100a) indicating a success of the write command, without regard to whether the write command was successful or failed. [19] Design structure, which is concretely embodied in a machine-readable storage unit for the design, manufacture or testing of an integrated circuit, wherein the design structure comprises: a data transmission controller (220) for a second host data processing system (100b) with a system structure to which a plurality of data transmission participants are connected, wherein the data transmission controller has: Controller circuit configured to perform: Receiving, from a first data processing system (100a), a host instruction in a first instruction set, wherein the host instruction specifies a memory access in a memory (402b) connected to the second host data processing system (100b), wherein both the first and the second host data processing system (100b) have a first and second coherent memory area respectively, and wherein the first and second coherent memory areas are not coherent with each other; Translating the host command into a second command in a different second command set, such that the first host data processing system (100a) emulates an attached functional unit connected to the data transmission controller (220), wherein: the data transmission controller (220) has a first operating mode that supports connecting an attached functional unit to the second host data processing system (100b), and a second operating mode that supports connecting the second host data processing system (100b) to the first data processing system for shared host-to-host memory use; the controller (220) circuit is configured to perform translation only based on a configuration of the data transfer controller in the second operating mode to support shared host-to-host memory usage; Transmission of the second command to a host bus protocol interface (108); and Based on the receipt of the second Initiate command, through the host bus protocol interface on the system structure of the second host data processing system (100b), a host bus protocol memory access request specifying the memory access. [20] Design structure according to claim 19, wherein: The translation process involves translating a first address, specified in the host command, into a second address and placing the second address in the second command. [21] Design structure according to claim 19, wherein: The host bus protocol memory access command is a read command; The controller circuit is further configured to perform: Receiving data from a system memory of the second host data processing system (100b), specified by the host bus protocol memory access request; and Output to the first data processing system, a read response that includes the data. [22] Design structure, which is concretely embodied in a machine-readable storage unit for the design, manufacture or testing of an integrated circuit, wherein the design structure comprises: a data transmission controller (220) for a second host data processing system (100b) with a system structure to which a plurality of data transmission participants are connected, wherein the data transmission controller has: Controller circuit configured to perform: Receiving, from a first data processing system (100a), a host instruction in a first instruction set, wherein the host instruction specifies a memory access in a memory (402b) connected to the second host data processing system (100b), wherein both the first and the second host data processing system (100b) have a first and second coherent memory area respectively, and wherein the first and second coherent memory areas are not coherent with each other; Translating the host command into a second command in a different second command set, such that the first host data processing system (100a) emulates an attached functional unit connected to the data transmission controller (220); Transmission of the second command to a host bus protocol interface (108); based on a reception of the second Initiate command, through the host bus protocol interface on the system structure of the second host data processing system (100b), a host bus protocol memory access request specifying the memory access, wherein the host bus protocol memory access command is a write command; and Outputting a write response to the first data processing system (100a) indicating a success of the write command, without regard to whether the write command was successful or failed.

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