DATA STORAGE DEVICE AND METHOD FOR OPERATING A DATA STORAGE DEVICE

Abstract

Data storage device comprising an integrated circuit further comprising a control unit (100) and a storage array (400) of charge-based memory cells, wherein: the storage array (400) comprises a first subsection (410) that can be operated as a storage unit and a second subsection (420) that can be operated as a dosimeter; the control unit (100) is capable of providing a reference current (Iref) and To perform memory access operations in order to access memory with reference to the reference stream (Iref); and the control unit (100) is further capable of analyzing a statistical distribution of read streams (Iread) using memory access operations in the second subsection (420), the analysis comprising the following: counting logical reading errors of the Memory access operations and calibration of the reference current (Iref) depending on a number of counted logical read errors, which is also an indicator of total ionization dose (TID).

Description

Realm of Revelation

[0001] This disclosure relates to a data storage device, an electronic device and a method for operating a data storage device.

[0002] This patent application claims priority over German patent application 102020126995.1, the disclosure content of which is hereby incorporated by reference. background

[0003] Document US 2011 / 0275356A1 describes methods and circuits for detecting and reporting high-energy particles using cell phones and other portable computing devices. Document US 6388259B1 describes a method and apparatus for radiation detection.

[0004] For many decades, memory technologies have been successfully miniaturized to achieve higher speeds and higher chip densities at lower bit costs. The problem of circuit reliability in electronics has always accompanied integration. In fact, the miniaturization of technology is limited precisely by the reliability problem itself. In radioactive environments, a reliability-oriented design can be even more critical and requires special attention. Memory is no exception, as it is a core component of almost every electronic system. Therefore, it must also be tolerant of such environments. Historically, many solutions have been employed to harden non-volatile memory, depending on the application, ranging from the use of innovative materials and intelligent layout techniques to more sophisticated solutions such as error-correcting coding and circuit redundancy.Furthermore, storage structures have also been used as dosimeters in the past, especially charge-based ones that utilize the intrinsic sensitivity of the charge to the total ionizing dose (TID).

[0005] Two problems are intertwined: a radiation-tolerant design and knowledge of the system's wear level. State-of-the-art solutions either involve relatively complex structures for controlling memory wear or combine separate, independent blocks that then interact via a higher abstraction layer. Furthermore, such solutions are either not accurate enough to determine the actual memory wear—for example, if the dosimeter uses a different technology or material than the storage device—or they require a complete scan of the memory to determine the degree of damage.

[0006] Fig. Figure 9 shows an embodiment of a prior art data storage device. The device can be used for CMOS-based non-volatile memory architectures. Such a memory comprises a control logic block 100, a column control and data buffer block 200, a row control block 300, and a memory array block 400. The control block 100 includes a reference current source that provides a reference current IREF, for example, for READ memory access operations in direct comparison with single-ended bit cell structures, as well as the logic for controlling the memory architecture. Block 200 includes data buffers, output drivers, and generally the column control of the memory array. The row control block 300 contains word line drivers and generally the row controls of the memory array. The memory array block 400 comprises an array of memory bit cells for storing information.

[0007] Memory access operations can be implemented as single-ended or differential architectures. In single-ended architectures, for example, READ operations are performed on a data buffer block of block 200, typically by stream comparators. The READ operation is successful if the comparator returns the correct last write operation on the bit cell, either erased or programmed in the case of the single-ended version, or the correct programmed page in a differential architecture.

[0008] Fig. Figure 10 shows an ideal distribution of the read current of charge-based bit cells. As the figure shows, there is a distinct open window between the distributions of programmed cells and erased cells, and the optimal position for the reference current IREF in the comparator lies in the middle of this window. Adaptive reference methods for reading non-volatile memory bit cells have been explored, for example, based on monitoring the cumulative distribution function (CDF) of the voltage threshold of all bit cells in the array.

[0009] One problem with this type of robustness approach is that the entire memory array is searched to determine the optimal position for the reference current IREF. This means the algorithm complexity is directly related to the dimensions of the memory array. Therefore, if N is the number of bit cells in the memory array, and B is the number of bits available to set the reference current IREF, the complexity of the algorithm to determine the optimal threshold is: O(N,B)=2B+N.

[0010] Considering that for a specific case with B < 10 and N > 1000, both additions are important for calculating the overall complexity, it immediately becomes clear that such an analysis becomes computationally expensive for large storage arrays. Furthermore, considering that the storage itself lacks dosimeter functionality, the system requires a separate component for estimating the radiation wear rate.

[0011] The purpose of the present disclosure is to specify a data storage device, an electronic device and a method for operating a data storage device with improved radiation tolerance and improved knowledge of the radiation wear level.

[0012] These problems are solved by the subject matter of the independent claims. Further developments and embodiments are described in the dependent claims.

[0013] It is understood that each feature described in relation to any embodiment may be used alone or in combination with other features described herein, and may be used in combination with one or more features of any other embodiment or any combination of any other embodiment, unless described as an alternative. Furthermore, equivalents and modifications not described below may also be used without departing from the scope of protection of the display, the display device, and the method for operating a display as defined in the appended claims. Brief description

[0014] The following describes an improved concept in the field of memory technology. This improved concept enables both wear control and dosimetry estimation in a single integrated data storage device. The device comprises a hybrid memory circuit with charge-based memory cells, such as sidewall spacer memory bit cells. One section of an array of charge-based memory cells operates as memory, while another section is designated for dosimeter operation. By continuously calibrating the reference current, it is possible to obtain a system that is both adaptive and state-aware, capable of monitoring the radiation absorption of the entire circuit.

[0015] In at least one embodiment, a data storage device comprises an integrated circuit, which further includes a control unit and a storage array of charge-based memory cells. The storage array comprises a first subsection and a second subsection.

[0016] During operation of the data storage device, the first section of the storage array functions as storage. The second section of the storage array, on the other hand, functions as a dosimeter.

[0017] The control unit provides a reference current and performs memory access operations to access the memory with reference to this current. Furthermore, the control unit analyzes a statistical distribution of read streams using memory access operations in the second subsection. This analysis includes counting logical read errors from the memory access operations and calibrating the reference current based on the number of counted logical read errors. The number of counted logical read errors also serves as an indicator of the total ionization dose (TID).

[0018] The proposed data storage device improves radiation tolerance and radiation wear degree knowledge in a single device. Indeed, the two aspects of radiation-tolerant design and wear degree detection in an electronic system are interconnected. The improved concept addresses both aspects in a unique way. In a sense, the data storage device represents a hybrid memory circuit that enables both wear control and dosimetry estimation based on charge-based memory cells, such as sidewall spacer memory bit cells.Thanks to the array of charge-based memory cells in the second subsection dedicated to dosimetry and thanks to a calibration of the data storage device, it is possible to obtain a system that is both adaptive and state-aware, capable of monitoring the radiation absorption of the entire device and of any electronic device in which the data storage device is contained.

[0019] In many applications, it can be technically advantageous to monitor the wear and tear of the data retention of the storage array. This is true, for example, for most applications in medicine, high-energy physics, and aerospace, where radiation hardness is an important parameter for design architecture. The proposed data storage device combines the use of a dosimeter and a memory in a single device. This combination of memory and dosimeter is implemented on the scale of the storage array itself, using charge-based memory cells, with only a relatively small addition of circuitry and logic. In particular, for a given number N of charge-based memory cells in the storage array, the architecture of the proposed concept can have a number of charge-based memory cells corresponding to the following equation: N'=N(1+a).

[0020] N' is the total number of charge-based memory cells in the memory array, and the parameter a denotes the proportion of charge-based memory cells that is intended for the second subsection, i.e., for dosimetry operation, where: 0 < a < 1.

[0021] Due to the nature of the dosimeter and the memory blocks, it can be assumed that both sections behave identically and that the damage caused by the total ionization dose (TID) is of the same type. In fact, ionizing radiation has a very specific effect on charge-based bit cells, such as sidewall spacer memory bit cells. Given that the stored information depends on the amount of electrical charge deposited in certain layers, and that ionizing radiation affects the movement of electronic charge, the information stored in the memory cells can be degraded. This degradation has been shown to be monotonic and tends to eliminate the charge pumped into the memory cells, for example, in a nitride spacer or an insulated conductive layer.In other words, it is possible to correlate the TID with the charge stored in the cells. This result is encoded in the number of logical read errors. If the data storage device continues to be exposed to ionizing radiation, the movement of the electronic charge leads to an increase in logical read errors during memory access operations. Counting the logical read errors not only allows for the calibration of the reference current but is also itself an indicator of the total ionization dose (TID).

[0022] In summary, the improved concept offers several advantages, including compliance with standard CMOS processes, the use of the same circuitry for reading and writing the memory and the dosimeter, and a compact and integrated design thanks to the layout of the charge-based memory cells and the memory itself. Furthermore, the overall system provides flexibility in data evaluation from the dosimeter to define the current reference, utilizing both maximum non-overlapping current configurations and specific percentiles of the estimated cumulative distribution function (CDF).

[0023] In the following, charge-based memory refers to any type of semiconductor memory that encodes data as a quantity of charge. Examples include sidewall spacer memory bit cells, but also charge-capture bit cells like those used in Sonos and the widely used floating-gate bit cells. The term "memory" refers to a device in which data is stored in a semiconductor, for example, a metal-oxide semiconductor (MOS), by memory cells on an integrated memory chip. Memory can be accessed through memory access operations. Bits containing binary data are stored in the memory cells. Memory access operations include the basic operations of "reading," in which the data content of a memory word is read non-destructively, and "writing," in which data is stored in a memory word, replacing all previously stored data there.Memory cells are accessed with reference to the reference stream. In addition, a specific memory cell can be accessed via its characteristic read and / or write stream.

[0024] Charge-based memory cells are typically read by comparing the read currents (or memory values) stored in the cells with one or more thresholds, such as one or more reference currents. If the memory is not damaged by environmental factors, the number of memory cells resembles a statistical distribution of read currents. This distribution is referred to as the "statistical distribution of read currents." The distribution may exhibit two separate curves, which can be assigned to the "programmed" and "erased" memory cells. These two curves may be separated by a specific open current window, or "delta." The reference current may be set to a current value within an interval defined by delta. For example, the reference current may be set to delta / 2.

[0025] In at least one embodiment, the memory cells of the second subsection are pre-charged to exhibit a low read current and are programmed before the use of the memory macroblock, i.e., the first subsection. This allows the memory cells of the second subsection to be prepared for use as a dosimeter. A read current is considered "low" if it falls within the smallest 10% or 1% of the statistical read current distribution. A truly "low" read current can be determined by the specific application. For a particular CMOS technology, such as 65 nm for sidewall spacers, a low read current might be between 0 and 10 to 15 µA. A high read current might be between 25 and 40 µA. However, this can change depending on technological advancements. For example, different read currents result when using 180 nm.A first characterization of the technology can therefore determine what is defined as "low" and what as "high", and whether the memory will work, that is, whether the read window is large enough to be reliable.

[0026] In at least one embodiment, the data storage device comprises a column control block. The column control block includes comparators that can be operated to compare read streams with the reference stream. During operation of the data storage device, the column control block can control memory access operations. During these operations, the comparators compare the read streams with the reference stream.

[0027] For example, the data content of a memory word is read from a specific memory cell. This means that the memory cells are addressed with their characteristic read current relative to the reference current. This is done under the control of the column control block. The read current of the respective memory cell is then compared with the reference current to detect any logical read errors that may occur due to radiation exposure. The column control block and the comparators are electronic components that can be used for both the first and second sections, i.e., for memory and dosimeters. Therefore, it is not necessary to implement separate electronics for each function. This further improves space requirements and cost-efficiency.

[0028] In at least one embodiment, the comparators include current-reading amplifiers. The current-reading amplifiers are configured in a single-ended or differential structure. The current-reading amplifiers compare the read currents with the reference current.

[0029] In at least one embodiment, the column control block also includes a data buffer and a bit-line driver. A row control block includes a word-line driver. The data buffer, bit-line driver, and word-line driver enable the control of the memory to read or write to a specific memory cell. The data buffer, bit-line driver, and word-line driver are electronic components that can be used for both the first and second subsections, i.e., for the memory and the dosimeter. This further improves space requirements and cost-efficiency.

[0030] In at least one embodiment, the control block includes a counter. The counter is configured to analyze the statistical distribution of read currents in the second subsection as a function of a number of memory cells. The analysis consists of successively comparing read currents from the statistical distribution of read currents with the reference current using comparators, for example, current read amplifiers. A logical TRUE or FALSE signal is generated for each comparison, depending on whether the comparison fulfills a comparison criterion or not.

[0031] The comparison criterion is met, for example, if a read current is smaller or larger than the reference current, or not. Typically, a logical FALSE signal is generated when a read current is larger than the reference current, thus indicating a logical read error. Depending on the actual memory architecture, this criterion can also be reversed. Finally, the number of logical FALSE signals is counted as the number of recorded logical read errors.

[0032] Charge-based memory cells are affected by the radiation to which they are exposed. As explained above, the radiation can alter the charges or the charge distribution within the cells. Since the memory cells store data, radiation exposure can affect the charge state, leading to information loss. This information loss can, in turn, be determined by the number of counted logical read errors. Therefore, the number of counted logical read errors can serve a dual purpose.

[0033] First, this figure can be used to calibrate the reference current. Radiation-induced changes in charge and charge distribution within the cells can affect the statistical distribution of read currents. The curves of "programmed" and "erased" memory cells can shift in the current, and the "delta" can change as a result. The number of counted logical read errors represents this shift and, in turn, allows the determination of the "delta," or in other words, the reference current. Calibration to the reference current can improve the accuracy and reliability of the memory despite the harmful radiation to which it is exposed.

[0034] Secondly, the number of counted logical read errors is also a measure of the TID. For example, the number of counted logical read errors can be correlated with the programming of the memory cells, such as the programming pulse times, in the second subsection to determine the TID. The number of counted logical read errors not only improves accuracy and reliability but also provides a convenient way to determine the total ionization dose (TID) of a single hybrid device.

[0035] In at least one embodiment, the control block can be operated to analyze the statistical distribution of the read streams by performing the following steps. First, under the control of the control block, data is stored in the memory array by writing initial memory values ​​to the charge-based memory cells of the second subsection. Second memory values ​​are then read from the charge-based memory cells of the second subsection. The number of charge-based memory cells of the second subsection that return logical FALSE signals, thus indicating a read stream higher than the reference stream and a logical read error, is counted.

[0036] The processes for writing and reading memory values ​​are identical for the first and second subsections of the memory array. Therefore, the number of counted logical read errors and the measurement of the reference current and TID can be determined using a single electronic component for both subsections. There is no need to provide separate electronics for the memory and dosimeter functions. This saves space and reduces costs.

[0037] In at least one embodiment, the control block can calibrate the reference current depending on the number of counted logical read errors. The calibrated reference current is then set as the reference current for performing memory access operations on the memory cells.

[0038] In at least one embodiment, the number of charge-based memory cells of the first subsection is greater than the number of charge-based memory cells of the second subsection.

[0039] To achieve the desired accuracy of the dosimeter, the second subsection can be equipped with a specific number of memory cells for the dosimeter function. The distribution of read streams during a read access to the memory tends to be the same as the dimensions of the two subsections of the memory array increase, provided the same programming and erasing operations are used. Therefore, a dimension of the dosimetry array can be determined with a view to achieving a desired statistical pool. This also contributes to achieving convergence of the distributions of the two subsections.

[0040] In at least one embodiment, the second subsection comprises at least one block of memory cells with the same programming. This identical programming corresponds to the programming of the memory cells of the first subsection.

[0041] In at least one embodiment, the second subsection can be further subdivided into blocks of memory cells, wherein the cells of a block have the same programming. For example, the block with the longest programming pulse time of the blocks can be the last to fail.

[0042] At least one block with the same programming as the memory cells in the first subsection allows for a direct comparison between the memory cells of the first subsection (memory) and the second subsection (dosimeter). Thus, it can generally be assumed that the cells of the second subsection are affected in the same way as those of the first subsection. Since the radiation acts equally on both arrays, the shift in the distribution is also the same in both arrays. Furthermore, due to the nature of the first and second subsections as memory and dosimeter, respectively, it can be assumed that both arrays behave identically and that the damage caused by the total ionization dose is of the same type.

[0043] In at least one embodiment, the charge-based memory cells used in the first and second subsections are of the same type. The separation into a first and a second subsection can therefore only be a matter of different control and programming. The functionality of the memory and the dosimeter can thus be achieved by a common array of charge-based memory cells, which are, for example, integrated into a single, shared chip.

[0044] In at least one embodiment, the control block can be operated to determine, at least for the block with the same programming, a number of logical read errors from the read streams, which is a measure of the total ionization dose (TID).

[0045] For example, ionizing radiation has a very specific effect on charge-based memory cells, such as sidewall spacer memory bit cells. Given that the stored information depends on the amount of electrical charge deposited in certain layers, and that the effect of ionizing radiation on these devices is related to the movement of electronic charge within the layer stack, the stored information can be affected depending on the time-ingress interference (TID). This degradation can be monotonic and tends to eliminate the charge pumped into the cells, for example, in the nitride spacers. Therefore, it is possible to correlate the TID with the charge stored in the cells at a given time.

[0046] In at least one embodiment, the second subsection is divided into blocks of memory cells with different pre-charge states. Each block has a different pulse time for programming. The different pre-charge states, or pulse times for programming, make it possible to adjust or extend the detection range of the dosimeter. The number of counted logical errors in the different blocks correlates with the total ionization dose.

[0047] For example, for a first preload state, a specific number of counted logical errors corresponds to a first TID value. For a second preload state, however, a specific number of counted logical errors can correspond to a second, but different, TID value. The set of preload states or pulse times for programming defines how the number of counted logical errors can be translated into TID values. Furthermore, the set of preload states or pulse times for programming defines a measurement range of the dosimeter. The number of memory cell blocks with different preload states can be any number starting with 1 and can only be limited by the desired measurement range.

[0048] In at least one embodiment, the following equation applies: N⋅aM≥200.

[0049] Here, N denotes the total number of charge-based memory cells of the first subsection, the parameter a a fraction of the total number of charge-based memory cells contained in the second subsection, and M a number of blocks in the second subsection.

[0050] The second section, dedicated to dosimetry, encompasses a specific area. This area, or rather the number of cells in the second section, affects the measurement accuracy. The size of the dosimeter can also be adapted to the type of environment in which it is used. A minimum block size can be maintained to achieve a desired accuracy, for example, to preserve statistical coherence. The system is adaptable with respect to the number of these blocks required to achieve the desired accuracy. It has been shown that the limit proposed by the equation above supports statistical coherence for many environments.

[0051] In at least one embodiment, the memory cells contained in the second subsection are never reprogrammed or updated after the initial conditioning of this subsection, in particular they are not programmed with a specific pulse time.

[0052] As previously mentioned, radiation alters the charge and charge distribution throughout the memory. Consequently, the reference current for memory access operations may need to be calibrated to maintain the reliability of the data storage device despite harmful radiation. This process can be supplemented by reprogramming, for example, the pulse timings. However, the memory cells included in the second subsection must not be reprogrammed and therefore remain in their original programmed state. If the memory cells belonging to the dosimetry array are never updated, they represent the worst-case scenario for data retention. In this way, the reported number of counted logical errors and the TID values ​​are recorded relative to the initial state of the data storage. In other words, the reported TID is actually a measure of the device's overall lifetime.

[0053] In at least one embodiment, an electronic device comprises a data storage device according to one or more of the aspects discussed herein. The electronic device also comprises a host system. Any host system intended to operate under harsh radiation conditions can benefit from the data storage device. For example, the host system may include at least one of the following: - a medical device, - a device for aviation, - a detector for high-energy physics, - an integrated wear-controlled spacecraft device, - a portable mobile device for personal use, - a portable detector for food radioactivity or - a portable detector to check for radioactive activity in the surrounding area.

[0054] In at least one embodiment, a method for operating a data storage device is applied to a device comprising an integrated circuit with a control unit and a storage array of charge-based memory cells. The storage array comprises a first subsection that can be operated as memory and a second subsection of charge-based memory cells that can be operated as a dosimeter. The method includes the steps of providing a reference current using the control unit. Memory access operations are performed to access the memory with reference to the reference current in order to analyze a statistical distribution of read streams. A number of logical read errors of the memory access operations in the second subsection are counted.Finally, the reference current is calibrated depending on the number of counted logical read errors, which is also an indicator of total ionization dose (TID).

[0055] In at least one embodiment, the memory is programmed with different pulse times and / or pre-charge states by writing initial memory values ​​to the charge-based memory cells of the second subsection. Second memory values ​​are read from the memory cells with reference to the reference current. Logical read errors are counted in the second subsection and serve as an indicator of a first reference state, i.e., relative to the reference current. Second memory values ​​are then also read from the memory cells with reference to at least one intermediate reference current, which differs from the reference current of the first reference state. Logical read errors are counted in the second subsection with reference to the intermediate reference current and serve as an indicator of a second reference state. The number of logical read errors for the first and at least the second reference state are then compared.The reference current is calibrated so that the reference current with the lower number of logical errors is set as the "new" reference current.

[0056] Further embodiments of the method for operating a data storage device according to the improved concept will be apparent to a person skilled in the art from the embodiments of the data storage device and the electronic device described herein.

[0057] The proposed concept described here offers several advantages over a solution using dedicated memory and dosimetry blocks, and the same applies to the use of separate blocks. Compared to a system using two blocks for memory and dosimeter functions, there is a significant improvement in area efficiency, as most operations are performed using the same circuitry. Furthermore, using the same structures for both blocks aids in system downtime detection, which is further enhanced by their proximity in the layout.

[0058] A potential problem compared to using a dedicated dosimeter could be the accuracy and nonlinearity of the system itself. Since the proposed concept can indeed rely on the failure of certain dosimeter blocks and even incorporates statistical techniques to improve the granularity of the detected dose, the quantization error and accuracy may not be comparable to those of a dedicated block. As already indicated in the description above, the more relevant comparison, to put the presented invention into proper perspective, can only be made in relation to the memory block, which does not contain a dosimeter section.Indeed, with a significant increase in surface area (simply by using a larger storage array), it is possible to ensure a meaningful statistical pool for tracking the wear level of the entire storage system, with the additional information about the TID level, which is also relevant for any electronic device used with the data storage device. This additional functionality can prove particularly valuable in challenging environments, such as in medicine, high-energy physics, and aerospace applications, to obtain a reliable understanding of the system's health and error margin.

[0059] Regarding the computational effort, this analysis is required for two different processes: determining the TID level and calibrating the reference. Specifically, determining the TID level may require a read operation across the entire dosimetry range Na and is therefore proportional to the size of the dosimetry array. Calculating the dose deposited on the electronic device requires counting the number of logical errors during this process and determining the statistical distribution of the results. Clearly, the complexity depends primarily on the size of the storage array (i.e., the value of a), which must be large enough to form a significant statistical pool but small enough to avoid overly complicating the calculation.The decision as to where to place this compromise point depends heavily on the application, i.e., on the desired accuracy and the availability of the area of ​​the entire system.

[0060] The same line of reasoning applies to the calibration of the reference, for example, the reference current for a single-ended memory cell structure or a memory cell bias for a differential structure, with the addition that the dosimetry array is divided into M blocks with different programming depths (pulse duration in the programming process). In particular, the charge injected into the memory layer of the memory cells in the different blocks can vary depending on the granularity of the analysis at the TID level. As mentioned earlier, one of these blocks can have the same programming depth as the first subsection of the memory array to achieve an optimal injected charge with a reasonable compromise between endurance and data retention. This can be the block to be analyzed to achieve the optimum for the reference itself.Thus, the complexity can be proportional to the size of the dosimetry array block, multiplied by the binary accuracy of the digital calibration. O(NaM,B)=BNaM

[0061] Applications operating in harsh environments could greatly benefit from monitoring system damage and would gain significant computational and area advantages by using the proposed concept. In particular, all integrated systems incorporating a data storage device as proposed would solve two important problems with a single component.

[0062] The following description of figures representing exemplary embodiments can further illustrate and explain aspects of the improved concept. Components and parts with the same structure or function are marked with corresponding reference numerals. Where components and parts in different figures have the same function, their description is not necessarily repeated for each subsequent figure. Brief description of the drawings

[0063] They show: Fig. 1 an embodiment of a data storage device, Fig. 2 an embodiment of a dosimeter subsection, Fig. 3 an exemplary embodiment of the architecture of a reading amplifier, Fig. 4. An example of the distribution of reading flows and the exemplary effects of TID on this distribution. Fig. 5. An example of the distribution of read streams for charge-based memory cells after a programming operation. Fig. 6. An example of a time-to-failure diagram for different programming pulse times, Fig. 7. An example diagram of the detected logical errors for different programming pulse times. Fig. 8 An exemplary flowchart for a procedure for operating a data storage device, Fig. 9 an embodiment of a data storage device according to the prior art and Fig. 10 an ideal distribution of the read streams of charge-based bit cells. Detailed description

[0064] Fig. Figure 1 shows an embodiment of a data storage device. The data storage device comprises an integrated circuit, which further includes a control unit 100, a column control and data buffer block 200, a row control block 300, and a memory array 400 consisting of charge-based memory cells. The control unit 100 includes logic or a processor for controlling the operation and control of the data storage device, for example, for controlling memory access operations. Furthermore, the control unit 100 includes a reference current source that provides a reference current Iref for the aforementioned memory access operations, such as read memory access operations. The control unit 100 also includes logic, such as digital and analog functional units, for calibrating the reference current Iref, for example, a counter for analyzing a statistical distribution of memory access operations, such as successful read operations.The column control and data buffer block 200 includes data buffer 210 and a bit line driver 220. The row control block 300 includes row controls of the memory array, such as word line drivers.

[0065] The memory array 400 comprises a first subsection 410 and a second subsection 420. Both subsections contain charge-based memory cells of the same type. The charge-based memory cells include, for example, sidewall spacer memory bit cells. The subsections have different functions. The first subsection 410 functions as memory (also called the memory subsection), and the second subsection 420 functions as a dosimeter (also called the dosimeter subsection).

[0066] The operation of the storage and dosimeter section, i.e., the first subsection 410 and the second subsection 420, is controlled by the control unit 100. For example, memory access operations are performed to access the memory using the reference current provided by the control unit. The control unit analyzes a statistical distribution of the read currents based on memory access operations in the second subsection 420. This analysis includes counting the logical read errors of the memory access operations. The number of logical read errors is derived from this count. As explained in more detail below, the number of logical read errors enables the calibration of the reference current and is an indicator of the total ionization dose (TID).

[0067] Fig. Figure 2 shows an embodiment of a dosimeter subsection. The dosimeter subsection, i.e., the second subsection 420, is further subdivided into blocks of memory cells. Five blocks 421, 422, 423, 424, and 425 are shown as examples. The number of blocks can vary depending on the actual implementation. The memory cells in a block have the same preload state, for example, program times or pulse times for programming. However, memory cells from different blocks each have different preload states. Furthermore, block 421 of memory cells initially has the same preload state as the memory cells of the first subsection 410.

[0068] Fig. Figure 3 shows an embodiment of the architecture of a read amplifier. The column control block can control memory access operations based on the reference current Iref provided by the control unit 100. For this purpose, the column control block includes 200 comparators. In this embodiment, the comparators are implemented as current read amplifiers SA. There are at least two fundamental concepts from which the read amplifier architecture of the column control block is derived: a single-ended structure (see left side of the drawing) or a differential structure (see right side of the drawing). The current read amplifiers compare the read currents Iread with the reference current Iref.

[0069] The following section presents basic functional and design considerations for the various embodiments of the Fig. 1 to 3 explained in more detail.

[0070] Fig. Figure 4 shows an example of the distribution of read streams and the exemplary effects of the TID on this distribution. The graph shows the number of memory cells in memory array 400 as a function of the read stream Iread. Memory access operations include the basic operations of "reading," in which the data content of a memory word is read non-destructively, and "writing," in which data is stored in a memory word, replacing the data previously stored there. Access to the memory cells is performed with reference to the reference stream Iref. A specific memory cell can also be accessed by comparing the read or write streams (or memory values) stored in the cells with one or more thresholds, for example, the reference stream Iref. The diagram shows two distributions of "programmed" cells and "erased" cells. There is an open window Δ between the two distributions.An optimal position for the reference current Iref, which is used as a reference in the comparator, can be in the middle of this window Δ.

[0071] In its initial state, the data storage device, including the memory array 400 (i.e., both the first and second subsections 410 and 420), has not yet been exposed to any harmful radiation. This state can be characterized by an "initial" reference current Iref, which results from the open window Δ described above. The initial state changes when the data storage device is exposed to harmful radiation. In fact, ionizing radiation has a very specific effect on charge-based bit cells. The stored information depends on the amount of electrical charge that accumulates in the memory cells through memory accesses. Ionizing radiation affects the movement of electronic charge in the cells, and the information stored therein as charge can be affected. As a result, the distribution of read currents shifts away from the initial state.

[0072] For example, two distributions of programmed and erased cells are separated by a different, shifted open window Δ'. Typically, the open window is reduced by radiation exposure. This shift can be seen as an indication of environmental damage and provides a way to estimate the TID. This will be examined in more detail below. Due to radiation damage, the initial reference current may no longer be in its optimal position. To ensure the operation of the data storage device, i.e., the storage subsection 410, despite the radiation exposure, the reference current Iref must therefore be calibrated. In a calibrated state, a calibrated reference current Iref' is used to determine the reference current Iref based on the shifted open window Δ'.

[0073] Since the radiation acts equally on both the first and second subsections 410, 420 of the memory, the shift in the distribution of both memory arrays will also be the same. Furthermore, due to the nature of the dosimeter and memory subsections, it can be assumed that both arrays behave identically and that the damage caused by the total ionization dose (TID) is of the same type. To determine the TID deposited on the data storage device, the dosimetry subsection 420 can be programmed to determine a worst-case scenario, for example, during the manufacturing phase of the data storage device. The initial programming involves various pulse durations or pre-charge states, for example, by writing initial memory values ​​to the charge-based memory cells of the second subsection 420.

[0074] This initial programming of the dosimetry subsection 420 is never updated during the entire lifetime of the data storage device. This is because, in this case, the data stored in the charge-based memory cells of the dosimetry subsection is always in the worst possible state, meaning it is never updated and is therefore tied to the lifetime of the device itself. Furthermore, not only are the charge-based memory cells in the dosimeter subsection not updated, but the amount of charge pumped into the storage element is also not optimal for maximizing the device's lifetime; instead, it is calibrated to fail at a specific TID level.

[0075] The TID level can be determined in different ways or a combination thereof. One possibility is to control the failure of memory cells in the second subsection, for example, in each programming block. For instance, a block can fail (or be considered failing) when a predetermined number of logical errors is reached. Another possibility is to control the increment of logical errors in the memory array and correlate the number of logical errors with a TID level.

[0076] Fig. Figure 5 shows an example of the read current distribution for charge-based memory cells after a programming operation. The graph shows the read current as a function of the programming pulse time (mean and standard deviation of the current distribution). In charge-based memory cells, the injected charge is controlled, for example, by the pulse time during the programming operation, i.e., by determining a change in the device current, as in Fig. Figure 5 illustrates this. The memory element consists, for example, of a silicon nitride spacer. In this way, it is possible to determine the magnitude of the TID absorbed by the second subsection 420 using a number M blocks with different charge amounts by analyzing the sector failure rate, in the simplest case like a thermometer, in the more complex case with a more sophisticated statistical analysis. This is possible due to the monotonic behavior of the read streams of charge-based memory cells, such as sidewall spacer bit cells, with respect to the TID.

[0077] Fig. Figure 6 shows an example of a time-to-failure diagram for different programming pulse times. The diagram is based on a differential read amplifier architecture. The read current differences are plotted as a function of the TID (on a logarithmic scale). Each line in the diagram represents the current difference between a programmed and an unprogrammed memory cell. Three different lines are shown, corresponding to the different pulse times of the initial programming. The read window, or open window Δ, in the distribution of read currents decreases monotonically with the TID. One benefit is that by analyzing only the result of the memory read operations, the data storage device becomes less dependent on analog references.Nevertheless, it is also possible to determine an optimum for a digitally adjustable current reference by using the dosimetry subsection as a benchmark for the entire memory array, taking into account the worst-case scenario condition for this subsection.

[0078] As already mentioned above in relation to Fig. As explained in section 3, the dosimeter subsection 420 comprises a number of M blocks of memory cells, each with identical programming. One of these M blocks of the dosimeter initially has the same programming states as the memory cells of the first subsection 410. This block forms the basis for extrapolating an optimal state for reading the memory array, for example, by sampling the block and adjusting the reference current. In other words, the calibration of the reference current for memory access operations can be limited to one block of the second subsection and not to all blocks. This block 421 can be prepared in its initial state with the same programming as the memory cells of the first subsection 410.Since the programming of block 421 is never updated during the entire operation of the data storage device, a failure of block 421 with the same programming represents an upper limit for the tolerance to TID of the entire storage array 400 and can thus guarantee a basic performance.

[0079] In summary, the time to failure of the read current distribution depends on the initial charge deposited in the memory cells of a given block, which is related to the pulse duration in the programming operation associated with that memory cell. Thus, the pulse duration determines the data retention and the block's tolerance to the time-in-time (TID). This means that the design of the memory subsection 410 and the dosimetry subsection 420 can be tailored to the operating environment of an electronic device containing the data storage device. In the medical field, for example, every bit of information is critical, and the amount of TID deposited in the chips is small compared to high-energy physics experiments and aerospace applications.Therefore, in a medical application, some dosimetry sectors in memory can be programmed to drop out slightly depending on the amount of TID received. From the data in . Fig. Figure 6 shows that the block programmed at 200 µs is much more sensitive to a low TID level than the blocks programmed at 800 µs (the nominal pulse time of the programming process for the current memory subsection).

[0080] Fig. Figure 7 shows an example diagram of detected logical errors for different programming pulse times. The TID can also be determined by counting the number of logical errors, for example, using the read amplifier architecture. The diagram shown in the drawing depicts the number of logical errors as a function of the TID. The number of detected logical errors also depends on the different programming pulse times used to program the memory cells in the various blocks.

[0081] Radiation leads to a monotonic degradation of charges in charge-based memory cells and tends to eliminate charge that has been pumped into the memory cells, for example, into the nitride spacer. Thus, it is possible to correlate the TID with the charge stored in the cells. This finding is reflected in the number of logical read errors that can be counted using the read amplifier (see Fig. 7) If the data storage device continues to be exposed to ionizing radiation, the movement of electronic charge leads to an increase in logical read errors during memory access operations. The number of logical read errors is also an indicator of the total ionization dose (TID).

[0082] There is usually a trade-off between the area cost and the number of blocks M in the second subsection 420. The relationship between these two factors can determine the accuracy of the dosimetry. However, accuracy can be increased by increasing the granularity, i.e., by analyzing the number of logical errors occurring in the blocks and correlating them with a specific TID level. Since the shrinking of the read window is monotonic, it is possible to correlate the degree of degradation with a TID level in a given block by analyzing the degradation of the open window Δ. However, due to the nonlinear behavior of the read window degradation in conjunction with pulse timing adjustment, multiple blocks are more accurate. Timing adjustment also selects the desired amount of charge in the spacer, thus better defining potential block failure points. Fig. Figure 7 shows an example of the applied concept. In the example shown in the drawing, with 30 logical errors in block 1, 10 logical errors in block 2, and perhaps one initial failure in block 3, a dose of 2 krad was deposited on the data storage device.

[0083] More generally, the memory and dosimeter subsections occupy specific areas of Memory 400. The area dedicated to the dosimetry subsection 420 can be adapted to the system in which it is used; for example, the data storage device can be integrated into an electronic device intended to operate in a specific radiation environment. Other parameters to consider include the size of the memory. It has been shown that a minimum block size must be maintained to ensure the desired statistical coherence. However, the memory is highly adaptable with regard to the number of memory cells. For example, the second subsection 420 can comprise a specific number of blocks. The actual number can only be limited by the number required to achieve the desired accuracy.

[0084] It has been found that a minimum block size can be achieved based on the following equation: NaM≥200

[0085] Here, N denotes the total number of charge-based memory cells of the first subsection, the parameter a a fraction of the total number of charge-based memory cells contained in the second subsection, and M a number of blocks in the second subsection.

[0086] Considering the basic block size, another parameter to be taken into account is the trade-off between the area budget for the proposed data storage device in an electronic device and the desired accuracy with respect to the dosimetry steps. This means that Na, which represents the overall size of the dosimetry subsection within the block and thus the area cost for the additional dosimetry function, and M, the number of blocks with different programming depths (and thus different tolerance levels with respect to TID), must be considered in relation to the ratio for statistical coherence explained above.

[0087] In addition to the size of the dosimetry subsection and the blocks, the amount of charge injected into each block can also be considered as a further parameter, as this determines the radiation tolerance of each block and the failure threshold of the respective block. The memory cell array belonging to dosimetry subsection 420 must never be updated, which represents the worst-case scenario for data retention. To achieve reliable operation of the data storage device, the size of the dosimetry array Na, the number of sectors M, and the amount of charge injected into each memory cell of each block—i.e., the pulse time t used in the programming process—can be adjusted. i (e.g. t1, t2, t3, t4 or t5 in Fig. 3) be calibrated.

[0088] Fig. Figure 8 shows an exemplary flowchart for a procedure for operating a data storage device. The flowchart illustrates a possible routine for calibrating the reference current Iref. This procedure can be applied to both the differential bit cell structure and the single-ended structure. The procedure can be applied to the entire dosimeter subsection 420. The failure of block 421 (with the same programming state as the memory subsection) is defined by the first failure and determines the guaranteed lifetime of the device.

[0089] As a general guideline, calibration can include programming the memory with different pulse times or pre-charge states and reading secondary memory values ​​from the memory cells. Logical read errors are counted in the second part of the process. The number of logical read errors is counted for a specific reference current and compared to the number of logical errors associated with other, different reference currents. The resulting number of logical errors for different currents is then processed to determine the reference that ensures the longest lifetime of the overall circuit.

[0090] In the case of a differential structure of the memory cells, the calibration of the reference current for the read operation can consist of selecting a correct bias voltage for the read amplifier SA, for example a gate voltage for both components that make up the memory cell (see Fig. 2) to find an optimum with respect to the number of correct operations in the block. The bias Vref represents the reference used throughout the array of both the memory and dosimetry memory cells 410 and 420, and this reference value is determined by reading the block in dosimetry subsection 420 with the same programming states as in memory subsection 410. This would mean that the calibration process would have to be repeated throughout the lifetime of the memory to improve read performance. This applies to both the differential and single-ended structures.

[0091] The flowchart in Fig. Figure 8 assumes that the control unit 100 includes a digital-to-analog converter (DAC) for generating the reference current. As already mentioned, shows Fig. Figure 8 shows a possible sequence of steps to be performed to calibrate the reference current. The actual procedures are also made clear by the pseudo-program code shown in the drawing and explained below.

[0092] The search for an optimal reference current begins in step S1. The procedure actually starts in the middle of the digital-to-analog converter. In step S2, a series of variables are defined. The reference current is referred to as the reference. Both `top_range` and `bottom_range` are defined by the current reference current as the starting point. In the next step, S3, the memory cells in the second subsection are read to determine the number of logical read errors, `Count(reference)`. Specifically, the number of logical read errors in the block is determined for each bit. This process is repeated for all generated values ​​of the DAC (following a kind of binary search starting from the center). In the flowchart, `top_range` and `bottom_range` represent the upper and lower maximum and minimum values, respectively, that the reference-generating DAC allows.

[0093] Step S4 specifies that the following algorithm is repeated until the index reaches the number of bits B. This number defines the granularity of the algorithm.

[0094] In step S5, the algorithm begins with the DAC mean value between the upper (top) and the reference value defined in step S2. Two further reference values, ref1 and ref2, are generated (by updating the upper and lower (bottom) limits of the interval considered for selecting the reference current). For example, two further reference values ​​are calculated as follows: top1=top; bottom1=reference; ref1=(top1−bottom1) / 2; top2=reference;bottom2=bottom; ref2=(top2−bottom3) / 2; ind=ind+1; top0=ref1;bottom0=ref2; ref0=reference;

[0095] In step S6, the control unit 100 recalculates the number of logical read errors in the block for each reference; that is, based on these definitions and intermediate calculations of the references ref0, ref1 and ref2, the corresponding counts of logical read errors Count(reference1) for ref1 and Count(reference2) for ref2 are counted, for example, assuming that this would lead to the desired block if the aforementioned references were the point of the analyzed DAC.

[0096] In step S7, these three numbers are then compared: Count(ref0) = Count(reference) Count(ref1) = Count(reference1) Count(ref2)=Count(reference1), That is, the two values ​​generated by the new step and the old selected point. If the numbers are different, in step S8 the algorithm selects the new midpoint reference that generates the fewest logical read errors, denoted as reference,indmax, by updating the search interval by returning to step S4. This is achieved through the following calculations: reference,indmax=min{Count(ref0),Count(ref1);Count(ref2)}; top=top,indmax,bottom=bottom,indmax

[0097] If the numbers show the same number of logical read errors, the middle reference is selected in step S9.

[0098] In the case of a single-ended structure, the problem presents itself differently. It is much more difficult to define the best current reference for the single-ended memory cell—that is, a current that can be compared to the current "stored" in the actual memory cell to determine whether the memory cell has been previously programmed or not—because reference memory cells are absent, as they are instead present in the differential structure.

[0099] To perform correct calibration, a two-pronged approach is possible: Firstly, a section within the dosimetry subsection can be isolated that should not be affected by the programming process, thus designating one of the blocks as unprogrammed. This approach requires an additional section to achieve the desired calibration. However, this ensures an accurate comparison of the reference currents for both a programmed and an unprogrammed section of the second subsection. For example, a binary search, as described above, could be performed on the reference currents generated by the DACs in the same manner as described in the flowchart, but only within the unprogrammed section. A comparison with a programmed section can then be used to update the reference current.

[0100] Another approach could be to calibrate the data storage device only after a final failure of one of the blocks in the second subsection is detected. For example, the blocks could be programmed with different pulse times. Let us consider the five blocks 421 to 425 in Fig. 3 with pulse times t1 to t5. Let us further assume that t1 > t2 > t3 > t4 > t5. Prepared in this way, the earliest block 421, with the longest pulse time t1, can fail last, along with the memory subsection. In other words, the longer the pulse time, the closer the memory subsection is to its programmed state. When the block with the shortest pulse time begins to fail, indicated by the number of logical read errors, the other blocks can be used as triggers for subsequent calibrations. Then, block 425, which is "closer" to a "fresh" memory cell block, can act as an unprogrammed block, providing a sufficiently reliable comparison for programmed blocks and allowing a renewed binary search for the reference value for the current.Being "closer" to a "fresh" memory cell can be considered closer to a cell where the programming process was easier, defined, for example, as the one with the shorter pulse duration. This method may be less reliable for generating a reference value, but it would be useful in some applications, particularly those that make extensive use of error-correcting code and software techniques to reduce errors in large memories. Equally sized memories instead of smaller memories with OTP, for example.

[0101] The improved concept described above works with various types of charge-based memory cells, since all charge-based bit cells respond similarly to the TID. In the specific embodiments shown above, the improved concept is illustrated using sidewall spacer memory bit cells, but the same hypothesis applies equally to other charge-based memory cells or bit cells. Depending on the timing of the pulse in the programming process, the current in the memory cell also varies during the read operation, as shown in Fig.Figure 4 illustrates alternative implementations of the basic memory cell, such as single-ended or differential structures, do not differ significantly. The read operation is similar, as it is recommended that the current reference be generated using the same cell type as the sidewall spacer storage device. Thus, while in the differential structure the comparison between the two components takes place as part of the cell itself, in the single-ended implementation the comparison is made between a memory cell and a current generated by a similar component (which is therefore affected by radiation in the same way). Simultaneously, the analysis of the dosimetry subsection can be performed digitally by counting the number of read errors, thereby ensuring independence between the dosimetry operation and the structure of the memory cell (i.e., differential or single-ended).Instead, the calibration of the current source for optimizing the read operation depends on the aforementioned structure. However, the optimum is the same in both cases, meaning the best statistical result at the output. This means that for single-ended cells, the optimum is the current level that best separates programmed and erased cells, while for the differential implementation, a sensible best bias of the memory cells is the one that yields the highest number of correct responses during read operations.

[0102] In conclusion, the improved concept enhances the state of the art by coupling the operation of a memory with that of the dosimeter. Prior art solutions either involve highly complex structures for controlling memory wear or combine separate, independent blocks that then interact via a higher level of abstraction. Furthermore, previous attempts either lack accuracy in determining the effective memory wear (if the dosimeter uses a different technology or material than the memory device) or require a complete scan of the memory to determine the degree of damage.Thanks to charge-based memory cells, such as sidewall spacer memory bit cells, and their inherently higher tolerance compared to other charge-based devices based on standard CMOS, the proposed concept does not require special shielding or packaging for most applications.

[0103] The proposed data storage device allows for layout customization similar to that of a memory block. One aspect is that the ratio between the charge-based memory cells in the first subsection (memory) and the second subsection (dosimeter) varies depending on the desired reliability and overall memory size, along with the mechanism for adjusting the memory's reference current. It is evident that the absolute dosimetry data are closely related to the size of the second subsection, which is dedicated solely to dosimetry, and to the sensitivity of the current source provided by the control block. Therefore, it can be advantageous to have a non-precise, compact, integrated absolute measurement of the total ionization dose (TID) within the electronic system, which serves as an accurate and fast adaptive reference current tuning mechanism to improve the memory's radiation tolerance.

[0104] Some of the improvements can be summarized as follows: • Smaller footprint compared to a separate dosimeter and storage • High reuse of common blocks (e.g., readout) and high compatibility with existing technologies such as CMOS, • Increased integration at the circuit and system level, • Higher memory reliability compared to systems using other technologies, • The simplicity of the proposed invention promotes the reusability of the concept and • Independence of the method from analogous sources.

[0105] Although this description contains many details, these should not be understood as limitations on the scope of the invention or the claims, but rather as descriptions of features specific to certain embodiments of the invention. Certain features described in this description in connection with individual embodiments can also be realized in combination in a single embodiment. Conversely, various features described in connection with a single embodiment can also be implemented separately in several embodiments or in any suitable subcombination.Furthermore, although features described above are said to act in certain combinations and are even originally claimed as such, in some cases one or more features from a claimed combination may be removed from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

[0106] Even if the processes in the drawings are depicted in a specific sequence, this should not be interpreted as meaning that these processes must be carried out in the shown order or in a sequential order, or that all depicted processes must be performed to achieve the desired results. Under certain circumstances, multitasking and parallel processing can be advantageous.

[0107] Several embodiments have been described. Nevertheless, various modifications can be made without affecting the spirit and scope of the invention. Accordingly, other embodiments also fall within the scope of the claims. Reference sign 100 control units 200 column control and data buffer block 210 data buffers 220 bit line drivers 300 line control block 400 storage array 410 first subsection 420 second subsection 421 block of memory cells 422 block of memory cells 423 block of memory cells 424 block of memory cells 425 block of memory cells Iref Reference current Iref' calibrated reference current iRead reading stream Vref Preload Δ open window Δ' shifted open window

Claims

[1] Data storage device comprising an integrated circuit further comprising a control unit (100) and a storage array (400) of charge-based memory cells, wherein: the storage array (400) comprises a first subsection (410) that can be operated as a storage unit and a second subsection (420) that can be operated as a dosimeter; the control unit (100) can be operated to provide a reference current (Iref) and To perform memory access operations in order to access memory with reference to the reference stream (Iref); and the control unit (100) is further capable of analyzing a statistical distribution of read streams (Iread) using memory access operations in the second subsection (420), the analysis comprising the following: counting logical reading errors of the Memory access operations and calibration of the reference current (Iref) depending on a number of counted logical read errors, which is also an indicator of total ionization dose (TID). [2] Device according to claim 1, further comprising a column control block (200) that is operable for memory access operations and includes comparators, wherein the comparators are operable during the memory access operations to compare read streams (Iread) with the reference stream (Iref). [3] Device according to claim 2, wherein: the comparators include current-reading amplifiers (SA) configured in a single-ended or differential structure, and the current read amplifiers (SA) are capable of comparing read currents (Iread) with the reference current (Iref), and / or the column control block (200) further comprises a data buffer (210) and a bit line driver (220), a line control block (300) includes a word line driver (310). [4] Device according to claim 2 or 3, wherein the control unit (100) comprises: a counter for analyzing the statistical distribution of read streams (Iread) in the second subsection (420) as a function of a number of memory cells, wherein the analysis includes the following: successive comparison of read streams (Iread) from the statistical distribution of read streams with the reference stream (Iref) using the stream read amplifiers (SA), Generating a logical TRUE or FALSE signal for each comparison, depending on whether the comparison meets or fails to meet a comparison criterion, and Counting the number of logical FALSE signals as the number of counted logical read errors. [5] Device according to any one of claims 1 to 4, wherein the control unit (100) is operable to analyze the statistical distribution of read streams (Iread) by performing the following steps: Storing data in the memory array (400) by writing first memory values ​​into the charge-based memory cells of the second subsection (420), Reading second memory values ​​from the charge-based memory cells of the second subsection (420) and Counting the number of charge-based memory cells of the second subsection (420) that return logical FALSE signals, indicating a read current (Iread) that is higher than the reference current (Iref) and indicating a logical read error. [6] Device according to claim 5, wherein the control unit (100) is operable to calibrate the reference current (Iref) depending on the number of counted logical read errors and to perform a memory access operation on the memory cells using the calibrated reference current (Iref') as the reference current (Iref). [7] Device according to any one of claims 1 to 6, wherein a number of charge-based memory cells of the first subsection (410) is greater than a number of charge-based memory cells of the second subsection (420). [8] Device according to any one of claims 1 to 7, wherein the second subsection (420) comprises at least one block (421) of memory cells with the same programming, wherein the same programming corresponds to the programming of the memory cells of the first subsection (410). [9] Device according to claim 8, wherein the control unit (100) is operable to determine, at least for the block (421) with the same programming, a number of errors from the read streams (Iread) as a measure of the total ionization dose (TID). [10] Device according to any one of claims 1 to 9, wherein the second subsection (420) is divided into blocks (421, 422, 423, 424, 425) of memory cells with different precharge states and each block (421, 422, 423, 424, 425) has a different pulse time for programming (t1, t2, t3, t4, t5). [11] Device according to claim 10, wherein N denotes the total number of charge-based memory cells of the first subsection (410), the parameter a denotes a fraction of the total number of charge-based memory cells contained in the second subsection (420), and M denotes a number of blocks in the second subsection (420), and wherein: N⋅aM≥200. [12] Device according to any one of claims 1 to 11, wherein the memory cells contained in the second subsection (420) are never reprogrammed after the initial preparation of this subsection, in particular not programmed with a specific pulse time. [13] Electronic device comprising a data storage device according to any one of claims 1 to 12 and a host system comprising at least one of the following elements: a medical device a device for aviation, a detector for high-energy physics, an integrated wear-controlled Spacecraft device, a portable mobile device for personal use, a portable detector for food radioactivity or a portable detector for checking the radioactive activity in the environment. [14] Method for operating a data storage device, wherein the device comprises an integrated circuit with a control unit (100) and a storage array (400) of charge-based memory cells, wherein the storage array (400) comprises a first subsection (410) that can be operated as a memory and a second subsection (420) of charge-based memory cells that can be operated as a dosimeter; wherein the method comprises the following steps: Providing a reference current (Iref) using the control unit (100), Performing memory access operations to access memory with reference to the reference stream (Iref), to analyze a statistical distribution of reading streams (Iread), Counting logical read errors of the memory access operations in the second subsection (420), Calibrating the reference current (Iref) depending on a number of counted logical read errors, which is also an indicator of total ionization dose (TID). [15] The method of claim 14, comprising the following further steps: Programming the memory array (400) with different pulse time or preload states by writing initial memory values ​​into the charge-based memory cells of the second subsection (420) and / or erasing data in the memory array (400), Reading second memory values ​​from the memory cells of the second subsection (420) with reference to the reference stream (Iref) and counting the logical errors, which are an indicator of a first reference state, Reading second memory values ​​from the memory cells of the second subsection (420) with reference to at least one intermediate reference stream and counting the logical errors that are an indicator of a second reference state, Comparing the number of logical errors for the first and at least the second reference state and Calibrating the reference current (Iref) so that the reference current (Iref) with the lower number of logical errors is set as the reference current.

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