Neuromorphic unit with multiple connections

Abstract

A neuromorphic memory element comprises a memristor, a plurality of neuromorphic memory elements, and a method for operating them. The memristor has an input signal terminal, an output signal terminal, a control signal terminal, and a memristive active channel containing a phase-change material. The memristive active channel extends longitudinally between the input signal terminal and the output signal terminal. A control signal voltage at the control signal terminal is configured to represent volatile biological neuronal processes of the neuromorphic memory element, and a bias voltage between the input signal terminal and the output signal terminal is configured to represent non-volatile biological neuronal processes of the neuromorphic memory element.

Description

BACKGROUND

[0001] This disclosure relates to a neuromorphic storage element comprising a memristor, and more specifically to a neuromorphic storage element emulating synaptic brain behavior. This disclosure is directed in particular to a plurality of neuromorphic storage elements and to a method for operating a neuromorphic storage element comprising a memristor.

[0002] Due to the increasing availability of information in both science and business, data analysis remains in high demand. To analyze the growing proportion of unstructured or semi-structured data, artificial intelligence techniques are employed – very often in the form of machine learning systems. These machine learning systems are frequently implemented as artificial neural networks based on classic von Neumann architectures. This architecture typically executes the cycle of retrieving instructions / data, executing them, and optionally writing the results back. The CPU (central processing unit) is connected to system memory via a bus system.

[0003] In contrast to this conventional von Neumann architecture, the human brain has a large number of neurons with synapses, each of which serves both for data processing and storage, thus functioning as a biological, in-memory data processing system. Because of this unique structure, the brain is extremely energy-efficient in dealing with emotions, learning, and thinking. For example, simulating five seconds of brain activity using 20 W of power requires approximately several hundred seconds and kilowatts, or even up to one megawatt, of power using state-of-the-art supercomputers. In the circuitry of such a natural neural network, a neuron integrates inputs from other neurons, while the synapse relays the signals.Synapses outnumber neurons by several orders of magnitude, and the processes of learning and memory in the network are related to the synapses (synaptic efficiency or weighting). SUMMARY

[0004] According to one aspect of the present invention, a neuromorphic storage element is provided which includes a memristor. The memristor can have an input signal terminal, an output signal terminal, and a control signal terminal. The neuromorphic storage element can also have a memristive active channel comprising a phase-change material, wherein the memristive active channel extends longitudinally between the input signal terminal and the output signal terminal.

[0005] The control signal voltage of the control signal terminal can be configured to represent volatile biological neuronal processes of the neuromorphic memory element, and a bias voltage between the input signal terminal and the output signal terminal can be configured to represent non-volatile biological neuronal processes of the neuromorphic memory element.

[0006] According to another aspect, a method for operating a neuromorphic storage element comprising a memristor is provided. The memristor can have an input signal terminal, an output signal terminal, a control signal terminal, and a memristive active channel comprising a phase-changing material. The memristive active channel can extend longitudinally between the input signal terminal and the output signal terminal.

[0007] The method can also include applying a control signal voltage, representing volatile biological neuronal processes of the neuromorphic memory element, to the control signal terminal and applying a bias voltage between the input signal terminal and the output signal terminal, representing non-volatile biological neuronal processes of the neuromorphic memory element.

[0008] US 2019 / 0065929 A1 discloses a neuromorphic synaptic device with a programmable synaptic device having non-volatile and volatile properties and a control signal generator that applies control signals in read and write modes to implement predefined synaptic dynamics.

[0009] US 2019 / 0305220 A1 discloses systems and methods for manufacturing and using a non-volatile, multi-pole RRAM device in which a voltage bias is applied via a gate to change the resistance state of a metal oxide storage element.

[0010] CHEN, Huawei [et al.]: Time tailoring van der Waals heterostructures for human-memory system programming. In: Advanced Science, Vol. 6, 2019, No. 20, p. 1901072. https: / / doi.org / 10.1002 / advs.201901072 [accessed on May 17, 2024] discloses a neuromorphic storage device based on a van der Waals heterostructure with stacked volatile and non-volatile functional layers, which flexibly implements and transitions between sensory, short-term, and long-term memory, as well as enabling decision functions and in-situ outcome storage.

[0011] BAO, Lin [et al.]: Dual-gated MoS2 neuristor for neuromorphic computing. In: ACS applied materials & interfaces, Vol. 11, 2019, No. 44, pp. 41482-41489. https: / / doi.org / 10.1021 / acsami.9b10072 [accessed on 17.05.2024] discloses a MoS2 neuristor with a dual-gate transistor structure in which an ionic top gate and an electronic back gate control the ion and charge carrier movement, so that the device can be programmed as a neuron, synapse or n-type MOSFET for reconfigurable neuromorphic circuits. Brief description of the multiple views in the drawings

[0012] Embodiments of the invention are described with reference to different patent specifications. In particular, some embodiments are described with reference to claims relating to the type of method, while other embodiments are described with reference to claims relating to the type of apparatus. However, a person skilled in the art can understand from the foregoing and the following description that, unless otherwise stated, in addition to any combination of features belonging to one type of patent specification, any combination of features belonging to other patent specifications, in particular between features of claims relating to the type of method and features of claims relating to the type of apparatus, are to be considered as disclosed in the present document.

[0013] The aspects defined above and further aspects of the present disclosure will become clear from the examples to be described below and explained with reference to the examples of embodiments to which the invention is not limited.

[0014] Various embodiments of the invention are described only by way of example and with reference to the following drawings: Fig. Figure 1 is a schematic block representation of an embodiment of the neuromorphic storage element according to the invention, which includes a memristor according to some embodiments. Fig. Figure 2 is a schematic block representation showing an alternative embodiment of the neuromorphic memory element. Fig. Figure 3 is a block diagram showing an embodiment that includes a second upper gate and optionally a third upper gate. Fig. Figure 4A is a block diagram illustrating the effect of homeoplasticity using a global gate according to some embodiments. Fig. Figure 4B is a timing diagram showing presynaptic signals and postsynaptic signals according to some embodiments that depend on a voltage applied to a global gate. Fig. Figure 5A is a block representation of a timing diagram showing an embodiment of a first approach for STP using a global gate according to some embodiments. Fig. Figure 5B is a time-lapse diagram showing a typical evolution of time-related STP fatigue signals at the level of the emulation unit according to some embodiments. Fig. Figure 6 is a block representation of a timing diagram showing an embodiment of a second approach for STP using a global gate according to some embodiments. Fig. Figure 7 is a schematic representation showing an exemplary embedding of a plurality of the neuromorphic storage elements in a crossbar array according to some embodiments. Fig. Figure 8 is a schematic block diagram showing components for operating the cross-rail arrangement of the majority of neuromorphic storage elements according to some embodiments. DETAILED DESCRIPTION

[0015] One area for advancing neuromorphic platforms, both to improve existing applications and to enable new ones, is to design neurons and synapses to be increasingly inspired by the brain. This may require a radical rethinking of the concepts for human-made units that emulate synaptic dynamics. Several independent processes are known to govern synaptic efficiency, which can be broadly divided into two categories: long-term plasticity (LTP) and short-term plasticity (STP). Based on this, synaptic efficiency (G) can be expressed as a function of: G(t)=α(t)*W / t)*F(t) where: W(t) represents the long-term plasticity (W). F(t) represents the short-term plasticity (F) and α(t) may be related to changes in the media of the networks (homeostasis) and could represent multiplicative mathematical operations (e.g. addition, subtraction).

[0016] "Homeostasis" refers to global modulations underlying synapses (homeoplasticity or homeostatic plasticity). This is primarily controlled by ion concentrations, the concentration of various hormones, and temperature, to name just a few parameters that provide global regulation of synaptic strength and neuronal firing.

[0017] W(t) is related to long-term memory and F(t) is related to short-term memory and sometimes also refers to an effect called "synaptic fatigue / facilitation". Furthermore, neurons can exhibit a variety of temporal dynamics such as adaptive thresholding and membrane leakage. Thus: T'(t)=α(t)*T(t)*K(t) where: T'(t) represents the dynamic threshold for firing a neuron. T(t) represents the resting threshold for firing a neuron and α(t) in relation to changes in the medium of the network (homeostasis)

[0018] Furthermore, regarding the synaptic property, it is known that: K'(t)=α(t)*K(t) where K'(t) represents the course of the transient voltage in a postsynaptic signal K(t) represents a presynaptic signal or a postsynaptic attenuation tail and α(t) may be related to changes in the medium of the network (homeostasis).

[0019] Currently available neuromorphic hardware, synaptic and neuronal dynamics are typically implemented using conventional CMOS circuits and memristor circuits. Implementation options include two-transistor / one-memristor solutions as well as one-transistor / one-memristor solutions (e.g., for simulating a synapse). One of the challenges of working with memristors to achieve full tunability is that they may require a non-memristive circuit, which complicates unit fabrication and is often unrelated to unit physics.

[0020] In an attempt to simulate a synapse with a projected phase-change memory unit, featuring a phase-change memory core, a middle layer surrounded by an active channel, which is itself surrounded by a gate oxide, has proven problematic. To be fully tunable, the unit requires additional material (the active channel), which complicates the fabrication process and reduces the memristor's operational efficiency.

[0021] A third approach could involve a phase-change memory (PCM) unit, which implements an integrate-and-fire neuron by integrating inputs in the PCM conductance state and resetting them once the conductance reaches a firing threshold. In this case, the memristive conductance represents the neuron's membrane potential. However, this solution also has drawbacks: there is no "membrane leak," which may be necessary for some spatiotemporal data computations, and there is no threshold dynamics, which is required for adaptive learning.

[0022] Therefore, due to the limited options for modeling neuronal dynamics, currently available technical models of a synapse or neuron have only limited potential for simulating a fully functional synaptic / neuron network. Consequently, there may be a need for a neuromorphic unit that enables better simulation of synaptic activity.

[0023] In the context of this description, the following conventions, terms and / or expressions may be used.

[0024] The term "neuromorphic memory element" can refer here to a multi-terminal unit, i.e., at least one memristive unit with three terminals, without requiring separate PCM and active layers. Instead, the PCM layer or core and the active channel can be identical, thus eliminating a material layer. The neuromorphic memory element can be used to emulate synaptic effects known from mammalian brains.

[0025] The term "memristor" (a portmanteau of memory and resistor) refers to the familiar nonlinear electrical component with two terminals, associated with electric charge and magnetic flux. In the concept discussed here, the nonlinear properties of the memristor can be influenced by additional gates. The resistance value can be adjusted between several values ​​during a write operation. The programmed resistance value retains its value even when no voltage is applied to the memristor. However, due to the non-ideal behavior of such units, the resistance value can change over time. The programmed resistance value can be read back, allowing the memristor to be used as a memory or storage base element.

[0026] The term "memristive active channel" can refer here to a channel of a PCM that is connected between an input terminal and an output terminal.

[0027] The term "phase-change material" (PCM) can – in the context of memristors – refer to a transition between states of the material, e.g., between non-classical (as opposed to the classical states of "liquid" and "solid") states of matter, such as the uniformity of crystals, where the material transitions from conforming to one crystalline structure to conforming to another, which may be a higher or lower energy state, i.e., from a crystalline state to an amorphous state, which exhibit different electrical conductivities.

[0028] The term "volatile biological neuronal processes" can refer to short-term effects, for example in the context of short-term memory, such as those resulting from the leakage behavior of a neuron's membrane. This effect—in the context of synapses—can also be described as "synaptic fatigue."

[0029] The term "non-volatile biological neuronal processes" can refer to long-term effects related to the long-term memory of mammalian brains. It can also be called "long-term plasticity" (LTP).

[0030] The term "long-term plasticity" (LTP) can be related to synaptic plasticity in brain models—that is, in neuroscience—and can refer—particularly in the form of synaptic plasticity—to the ability of synapses to become stronger or weaker over time, which is important for the neurochemical basis of learning and memory. LTP should not be confused with long-term potentiation, which is the opposite of long-term depression (LTD). Both of these can be influenced in mammalian brains by the availability of neurotransmitters and hormones, which both form the basis for (synaptic) long-term plasticity. LTP effects typically last from minutes to hours.

[0031] The term "short-term plasticity" (STP)—specifically synaptic short-term plasticity as opposed to synaptic long-term plasticity—refers to the effects of synaptic activity over a shorter period than LTP. Synaptic short-term plasticity can operate on a timescale ranging from tenths of milliseconds to a few minutes. Therefore, STP and LTP effects can be clearly distinguished. Furthermore, short-term plasticity can either strengthen or weaken a synapse.

[0032] The proposed neuromorphic memory element, which incorporates a memristor, the majority of neuromorphic memory elements, and the method for operating them can offer several advantages, contributions, and technical effects.

[0033] The proposed solution can overcome problems found in projected, PCM-based synaptic elements, where a phase-change memory is surrounded by an active channel, a gate oxide, and an outer gate. Such configurations are comparatively difficult to fabricate and require relatively large production volumes. Furthermore, such configurations may require an active channel material, which can be omitted in the proposed solution. In contrast, in the proposed unit, the active channel and the phase-change material can be identical, thus improving the memristor's operational efficiency and emulating neuronal dynamics.

[0034] By utilizing the field-effect property inherent in memristors, the proposed approach eliminates the need for a projection layer. This reduces material costs, time, and labor, and eliminates the complexity involved in chip design and manufacturing.

[0035] By employing a backgate configuration, various embodiments can enable gate-level modulation of a neural network implemented using a plurality of the proposed neuromorphic units. In particular, for hybrid units, the backgate can enable global modulation, while selective gates can allow local modulation specific to a single neuromorphic unit.

[0036] Furthermore, eliminating the core projection layer in phase-change storage units can improve heat retention within the unit and reduce power consumption. Overall, this can lead to a significant improvement in the energy required to operate the proposed units.

[0037] The field effect introduced by the gate (in any form) can be used to represent the firing threshold of a neuron and to realize a long-term threshold value in the unit's non-volatile state, as well as a dynamic or adaptive threshold by tuning the unit's gate. To explain the biological background, a neuron integrates presynaptic impulses, and when the accumulation exceeds a firing threshold, it also fires a postsynaptic impulse. However, the firing threshold is not constant, and in the adaptive learning scheme, its magnitude changes.

[0038] The field effect introduced by the unit's gate can also be used to enable properties of a leaky neuronal membrane by adding transient nonlinearity to the simulated neuron. To explain the biological background, the delay in the build-up and decay of the postsynaptic signal is due to the leaky behavior of the neuron's membrane. The voltage waveform of a leaky integrate-and-fire model is crucial for understanding how most sensory information is processed. While a presynaptic signal has vertical edges, postsynaptic signals in leaky membranes have rounded edges.

[0039] In short, the entire set of properties of a biological synapse can be emulated, which can enable much more natural behavior in artificial neural networks. Both volatile and non-volatile neural processes can be realized using the memristive active channel.

[0040] The following describes additional embodiments that are applicable to the associated method.

[0041] According to some advantageous embodiments of the neuromorphic memory element, the neuromorphic memory element can be configured to emulate long-term plasticity dynamics (LTP dynamics) via non-volatile modulation of a memristor's conductance during a write operation, i.e., during a programming operation. The neuromorphic memory element can also be configured to emulate short-term plasticity dynamics (STP dynamics) via volatile modulation of the memristor's conductance during a read operation. In this case, the neuromorphic memory element can be configured to emulate neuronal dynamics via volatile modulation of the memristor's conductance during both read and write operations. Therefore, the novel neuromorphic unit can enable the simulation or emulation of the entire complex behavior of a natural, biological synapse, including short-term, long-term, local, and global effects.This makes the unit ideally suited for building even better artificial neural networks.

[0042] According to some embodiments of the neuromorphic storage element, the memristive unit can have an upper surface and a rear surface, a first dielectric material layer on top of the upper surface of the support material, a source resolution, and a sink terminal connected by the memristive active channel on top of the dielectric material. Furthermore, the memristive unit can have a rear gate below the first dielectric material layer. A support material can be positioned between the first dielectric metal layer and the rear gate. This support material can be silicon-based. Additionally, the rear gate can also be a conductive material.

[0043] According to some embodiments of the neuromorphic storage element, the memristive unit may have a carrier material containing: a source terminal and a sink terminal connected by the memristive active channel at the top of the carrier material, a dielectric material layer at the top of the memristive active channel, and a control gate at the top of the dielectric material layer.

[0044] These embodiments can be considered a direct alternative to the embodiments described above. However, in this case, the backgate can be replaced by the control gate above the active channel and used in the same way as the backgate can be used as described below, e.g., as a global gate for a plurality of neuromorphic memory elements that have a common upper control gate.

[0045] According to some alternative embodiments of the neuromorphic memory element, the substrate material can be conductive and can directly serve as the backgate. Therefore, the substrate material and the backgate can be identical. This can reduce manufacturing effort and also lower the cost of the neuromorphic memory element. However, in selected situations, the version of the neuromorphic memory element that includes a dedicated substrate material may be a more practical approach, for example, when other active elements—such as those used in CMOS technology—can be integrated along with one or more of the neuromorphic memory elements.

[0046] According to further alternative embodiments of the neuromorphic memory element, the substrate material can be a metal or a highly doped semiconductor, e.g., highly doped silicon. The conductive silicon (or other semiconductor) can be connected to a terminal that is to be wired to a gate voltage source.

[0047] According to further alternative embodiments of the neuromorphic storage element, the support material can be a silicon substrate, and the rear gate can be a conductive layer on top of the rear surface of the silicon substrate. The conductive layer on top of the rear surface of the silicon substrate (or another semiconductor as the support material) can typically be a metal gate.

[0048] According to an alternative embodiment, the neuromorphic storage element can have a second dielectric material layer on top of the memristive active channel and a first upper gate on top of the second dielectric material layer. However, a further material layer can be positioned between the active channel and the second dielectric material layer. The first upper gate can influence the properties alternatively and / or additionally to the back control gate. In particular, a voltage applied to the back gate and / or to the alternative upper gate can, in both cases, represent the transient effects of the artificial synapse—i.e., of the neuromorphic storage element—i.e., the short-term plasticity dynamics.

[0049] According to a further embodiment, and thus according to several other alternative configurations of the neuromorphic storage element, the memristive unit can also have a second upper gate adjacent to a first side of the memristive active channel. The second upper gate can also be positioned on the same dielectric layer as the active channel. Thus, when viewed from the substrate, the second upper gate is not located above the active channel, but rather next to it. It can also be referred to as a side gate, since it can be positioned on one side of the active channel in the same horizontal plane.

[0050] Furthermore, and according to an additional embodiment of the neuromorphic memory, the memristive unit can also have a third upper gate adjacent to a second side of the memristive active channel, on the opposite side of the memristive active channel from the second upper gate. The second and third upper gates can form another upper gate shape. Thus, the active channel can be positioned between the second and third upper gates. Therefore, the second upper gate, the active channel, and the third upper gate can all be positioned on top of the dielectric layer, i.e., in the same horizontal plane.

[0051] Some further developed embodiments of the concept according to the invention can also have a plurality of neuromorphic memory elements, wherein the control signal connection can be common to a plurality of the neuromorphic memory elements. Here, the control signal connection can be designed to emulate more global effects of the volatile biological neuronal processes. Therefore, it may not be necessary to select individual memristors of the different neuromorphic memory elements sequentially, but rather a single global control connection (i.e., a global gate signal) may suffice to address a large number of neuromorphic memory elements.

[0052] The conductivity of the memristor can be either decreased or increased depending on the polarity of the gate voltage. If the global gate and the upper gate have different polarities, the field effect on the memristor may be canceled out.

[0053] The following is a detailed description of the figures. Instructions in the figures are schematic. First, a block diagram of an embodiment of the neuromorphic memory element according to the invention is given. Subsequently, further embodiments, as well as embodiments of the plurality of memristors and the plurality of neuromorphic memories, and the method for operating a neuromorphic memory element comprising a memristor are described.

[0054] Fig. Figure 1 shows an embodiment of the neuromorphic storage element 100. It comprises a memristor having an input signal terminal 104, an output signal terminal 106, and a control signal terminal 110. Between the input signal terminal 104 and the output signal terminal 106, a memristive active channel 108—i.e., a channel element—has a phase-changing material, which is the active channel. The memristive active channel extends longitudinally between the input signal terminal and the output signal terminal; that is, its extension vertically to a first direction defined by a line between the input signal terminal 104 and the output signal terminal 106 is smaller than in the first direction.

[0055] This means that a control signal voltage Vgs at the control signal terminal is configured to represent volatile biological neuronal processes of the neuromorphic memory element, and a bias voltage between the input signal terminal and the output signal terminal is configured to represent non-volatile biological neuronal processes of the neuromorphic memory element.

[0056] To provide physical stability, the neuromorphic storage element 100 can have a support material 102, e.g., a semiconductor such as silicon, and a dielectric layer 112 between the support material 102 on one side and the input terminal 104, the active channel 108, and the output terminal 106 on the other. Therefore, the input terminal 104, the active channel 108 (as PCM), and the output terminal 106 lie in the same plane, i.e., above the dielectric layer 112. Both a second terminal of the control signal voltage Vgs and the input source terminal 104 can be connected to ground.

[0057] Fig. Figure 2 shows an alternative embodiment 200 of the neuromorphic storage element. In addition to those already mentioned in the context of Fig. In the element discussed, a second dielectric layer 202, comprising the memristive material, is positioned on top of the active channel 108. The second dielectric layer 202 insulates the upper gate 204 from the active channel 108. In this configuration, the neuromorphic storage element can be emulated with dynamic short-term plasticity through the upper gate. Since the second dielectric material 202 can be much thinner than the substrate 102, the upper gate can be much smaller compared to the rear gate 110 on the other side of the support material 102 and require a smaller amount of electrical charge to influence the active channel 108.

[0058] However, a single rear gate 110 can actively influence a plurality of neuromorphic memory elements 100, representing a global modulation of an array of neuromorphic memory elements 100 on a chip or wafer level. Alternatively, the upper gate can also be used for the same purpose. Purely local modulation can also be achieved by the embodiment shown in the next figure.

[0059] Fig. Figure 3 shows an embodiment 300 which includes a second upper gate 302 and optionally also a third upper gate 304. Fig. 3 is in contrast to the Fig. 1 and Fig. Figure 2 (side view of the cross-section) shows a top view of the neuromorphic storage element 100. The active channel 108 is positioned between the second upper gate 302 and the third upper gate 304. Both upper gates 302 and 304 can also be positioned on the dielectric layer 110. The second upper gate 302 and the third upper gate 304 can advantageously be used for local modulation of the active channel 108, i.e., operating at an individual unit level. In this configuration, the first upper gate can additionally be positioned on top of the upper channel, as shown in Figure 2. Fig. Figure 2 is shown. Furthermore, in other configurations, the rear gate 110 may also be present.

[0060] Therefore, the neuromorphic memory element 100 is in any case a unit with at least three terminals. The input signal terminal 104 can also be referred to as the sink, while the output signal terminal 106 can also be referred to as the source. The third terminal—that is, the gate terminal or control terminal—can be limited to a single memristor of a single neuromorphic memory element or be shared by multiple memristors in different, separate units of neuromorphic elements (NMEs). Each NME can thus emulate the LTP dynamics via non-volatile modulation of the memristive conductance during the write (programming) operation; each NME can emulate the STP dynamics via volatile modulation of the memristive conductance during the read operation.Furthermore, each NME can emulate neuronal dynamics via transient modulation of memristive conductance during both reading and writing processes.

[0061] Fig. Figure 4A illustrates the effect of homeoplasticity using a global gate. Fig. Figure 4A shows an arrangement 400 of presynaptic elements 404 and postsynaptic elements 406, while an element 408, in combination with the connections shown in rectangle 402, represents artificial synapses and their respective synaptic effects. In mammals, global brain mechanisms modulate neuronal processing, i.e., homeoplasticity. Ion concentrations, concentrations of various hormones, and temperatures are some of the parameters that provide global regulation of synaptic strength and neuronal firing. Homeoplasticity can be reproduced with a neuromorphic chip using the global timing scheme. These so-called global clock concepts can be used for adaptive learning, where neuronal firing can be intensified or attenuated. This is similar to the elevation and suppression responses of mammalian synapses to psychotropic drugs.

[0062] Fig. Figure 4B shows presynaptic signals 410 and postsynaptic signals 414 that depend on a voltage 410 applied to a global gate. Without a voltage applied to the global gate, the amplitude of the presynaptic signals 410 and postsynaptic signals 414 can be considered to be at a level of 100%. However, when a positive voltage 410 is applied to the global gate during period 416, the postsynaptic signals 414 are shown to be clearly below the level of 100%.

[0063] Conversely, if a negative voltage 410 is applied to the global gate during period 418, the postsynaptic signals 414 are shown to be clearly above the 100% level. After period 418 and without a gate voltage signal 412, the presynaptic signals 410 and the postsynaptic signals 414 are again at their respective 100% levels. Thus, the postsynaptic signals 414 can be increased or decreased, depending on the gate configuration, either for a single neuromorphic storage element or globally for a plurality of neuromorphic storage elements.

[0064] Fig. Figure 5A shows an embodiment 500 of a first approach for STP using a global gate, where asynchronous inputs X are used to address R neuromorphic units. A line 502 symbolizes a series of input signal pulses X(t). i), e.g., at times t3, t2, t1, i.e., X(t3), X(t2), X(t1) for input during read and write operations for the weights to be read from or written to (i.e., programmed into) the respective memristor. Two units, a modulation signal detector 504 and a two-terminal input forwarding module 506, control which signals reach a specific memristor 508, 510, 512 (symbolized by the switch 514). The two terminals mentioned above are the source and sink of the unit described above.

[0065] The inputs at the two terminals and at the global gate are asynchronous with each other. For an input pulse at two terminals (X(t) i ), R j ) at time t i The input must be placed in the third terminal (i.e., the gate) of unit R. j at time t i equal f j (t i) be (i.e., R(t) are inputs encoding f). At other times, it can be any other signal. Thus, it can be F0 = 0, or it can be f k , k ≠ j. Therefore, a single global signal can be used to the gate of all memristive units if it switches the signal that is present at any given time t. i This is crucial. This is the task of the modulation signal selection unit 504. Symbols 516 show crucial function values ​​f over time.

[0066] Fig. 5B shows typical signal developments of time-related STP fatigue at the level of the emulation unit, which can be understood as a transient decrease in synaptic effectiveness resulting from the applied transient effects triggered when the presynaptic inputs arrive. Signal 518 shows the input signal pulses, signal 520 shows an output signal without an applied gate voltage, and signal 522 shows an output signal with an applied gate voltage (as selected by the modulation signal selection unit 502).

[0067] Fig. Figure 6 shows an embodiment 600 of a second approach for STP using a global gate, where asynchronous inputs X are used to address R neuromorphic units. Apart from only minor differences compared to Fig. 5A uses the same reference numbers and does not explain them again.

[0068] Furthermore, jitter is introduced. Due to the jitter of the inputs at two terminals, causing them to be mismatched yet still using the global signaling scheme, the jitter must either: (i) be small relative to the temporal dynamics of the gate modulation signal, or (ii) also be applied to the gate terminal. Furthermore, the jitter must be small relative to the temporal dynamics of the input at two terminals.

[0069] Therefore, synapses that must remain immune to actions of the global gate can be used in parallel with the global gate input and modulated by the upper gate (as described above), but with a gate polarity that opposes the field effect from the lower gate. The main differences between Fig. 5A and Fig. 6 consist of the input signals X(t) to the memristors R(t) at 602 and the way in which the modulation signal detector 504 works.

[0070] Fig. Figure 7 shows an exemplary embedding of a plurality of neuromorphic memory elements 706 in a crossbar assembly 700. The crossbar assembly 700 has horizontal word lines 702 (only one of which has a reference digit) and vertical bit lines 704 (only one of which has a reference digit) for addressing the plurality of neuromorphic memory elements 706 at their respective intersection points. The word lines 702 and the bit lines 704 serve to address the respective neuromorphic memory elements 706 (or, for example, 708). The word lines 702 can be activated by the connections 714, 716, and 718. Connections for the bit lines 704 are not explicitly shown. The crossbar assembly represents an "mxn" matrix with rows of neuromorphic memory elements 706 of G. 11 up to G m1 up to G n1 up to G nm dar.

[0071] Furthermore, the gate contacts 712 (e.g., for the lower right corner of the crossbar array) are shown for each neuromorphic memory element 706. These gate contacts are connected diagonally compared to the word lines 702 and the bit lines 704. The diagonal gate lines (no explicit reference numeral) connect a plurality of the neuromorphic memory elements 706 across diagonally positioned intersection points of the word line 702 and the bit line 704. The gate voltage can be applied to the gate terminals 720, ..., 730. The respective gate voltage is effective only at addressed neuromorphic memory elements 706. The gates can be any gate selected from the back gate and any type of upper gate. In addition, parallel gate lines can be present to distinguish between the back gate and any of the upper gates.

[0072] Fig. Figure 8 shows components 800 for operating the crossbar assembly of the majority of the neuromorphic memory elements in the crossbar assembly 700. The word lines (of which only three are shown) are connected to digital-to-analog converters 802, which convert read or write commands into pulses 804. The bit lines are connected to amplifiers 806, which in turn are connected to analog-to-digital converters 808. In this way, the crossbar assembly 700 can be digitally addressed, and the output of the crossbar assembly can also be digitally processed.

[0073] Furthermore, the connections to the gate lines are shown symbolically, while the digital-to-analog converter 810 connected to the global gate is in contact with the neuromorphic memory elements 706 of the crossbar 700. Additional digital-to-analog converters 812 for addressing the local gates are also shown (in Fig. 7 and Fig.(not explicitly shown in Figure 8), which are normally implemented as upper gates. These gates are controlled by the volatile signals 814, which are symbolically shown as signals decreasing over time.

[0074] The descriptions of the various embodiments are intended for illustrative purposes only and are not meant to be exhaustive or limited to the invention as disclosed. Many modifications and variations are conceivable for those skilled in the art without these constituting a deviation from the scope of protection of the described embodiments. The terminology used herein has been chosen to explain the fundamental concepts of the embodiments, their practical application, and the technical improvements compared to technologies already available on the market in the best possible way, and to enable others with the relevant expertise to understand the embodiments disclosed herein. Any advantages of certain embodiments do not necessarily apply to all embodiments, and a particular embodiment need not utilize all of the advantages discussed herein.

[0075] The present disclosure may apply to a system and a method and / or may be implemented together with a computer program product. The computer program product may include a computer-readable storage medium (or media) on which computer-readable program instructions are stored to cause a processor to execute aspects of the present invention.

[0076] The medium can be an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system used for data transmission. Examples of computer-readable media include semiconductor or solid-state memory, magnetic tape, removable floppy disks, random access memory (RAM), read-only memory (ROM), magnetic hard disks, and optical discs. Current examples of optical discs include read-only storage media such as compact discs (CD-ROMs), rewritable compact discs (CR-R / W), DVDs, and Blu-ray discs.

[0077] The computer-readable storage medium can be a physical unit on which instructions for use by a unit for executing instructions can be stored and retained. The computer-readable storage medium can be, for example, but is not limited to, an electronic storage unit, a magnetic storage unit, an optical storage unit, an electromagnetic storage unit, a semiconductor storage unit, or any suitable combination thereof.A non-exhaustive list of more precise examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable read-only memory in the form of a compact disc (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanically coded unit such as punched cards or raised structures in a groove with instructions recorded on them, or any suitable combination of the foregoing.A computer-readable storage medium, as used herein, is not to be interpreted as consisting of volatile signals per se, such as radio waves or freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through an optical fiber cable), or electrical signals transmitted via a cable.

[0078] The computer-readable program instructions described herein can be downloaded over a network, such as the internet, a local area network, a wide area network, and / or a wireless network, from a computer-readable storage medium to the relevant data processing units or to an external computer or storage device. The network may include copper transmission cables, fiber optic transmission lines, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in the data processing unit receives computer-readable program instructions from the network and forwards them for storage on a computer-readable storage medium within the respective data processing unit.

[0079] Computer-readable program instructions for performing operations of the present invention may be assembly instructions, ISA instructions (ISA = Instruction Set Architecture), machine instructions, machine-dependent instructions, microcode, firmware instructions, data for setting states, or either source code or object code written in any combination of one or more programming languages, including an object-oriented programming language such as Smalltalk, C++ or similar, and conventional procedural programming languages ​​such as the programming language "C" or similar programming languages.The computer-readable program instructions can be executed entirely on the user's computer, partially on the user's computer as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, via the internet using an internet service provider).In some embodiments, electronic circuits, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), which execute computer-readable program instructions, can be used to personalize the electronic circuit by utilizing state information from the computer-readable program instructions, thus implementing aspects of the present invention.

[0080] Aspects of the present invention are described herein with reference to flowchart representations and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the invention. It will be clear that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented using computer-readable program instructions.

[0081] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a specialized computer, or other programmable data processing devices to create a machine such that the instructions executed by the processor of the computer or other programmable data processing devices provide the means to perform the functions / actions specified in a block or blocks of the flowchart(s) and / or block diagram(s).These computer-readable program instructions may also be stored in a computer-readable medium that can instruct a computer, other programmable data processing devices, or other units to function in a certain manner, such that the computer-readable medium with instructions stored on it constitutes a product containing instructions that implement the function / action specified in a block or blocks of the flowcharts and / or block diagrams.

[0082] The computer-readable program instructions can also be loaded into a computer, other programmable data processing devices, or other units to cause a series of operations to be performed on the computer, other programmable devices, or other units in order to create a computer-implemented process, such that the instructions executed on the computer, other programmable devices, or other unit realize the functions / actions specified in a block or blocks of the flowcharts and / or block diagrams.

[0083] The flowcharts and / or block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this context, each block in the flowcharts or block diagrams can represent a module, segment, or section of instructions that includes one or more executable instructions for implementing the specified logic function(s). In some alternative implementations, the functions specified in the block can be executed in a different order than that shown in the figures.For example, two consecutively listed blocks can indeed be executed essentially simultaneously, or the blocks can sometimes be executed in reverse order, depending on the functionality associated with them. Furthermore, it should be noted that each block in the block diagrams and / or flowchart representations, as well as combinations of blocks in the block diagrams and / or flowchart representations, can be implemented using dedicated hardware-based systems to perform the specified functions or actions, or using combinations of dedicated hardware and dedicated computer instructions.

[0084] The terminology used herein serves solely to describe certain embodiments and is not intended to limit the invention. In the sense used herein, the singular forms "a" and "the" also include the plural forms, unless expressly stated otherwise in the context. Furthermore, it is understood that the terms "has" or "have" when used in this description denote the presence of specified features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0085] The corresponding structures, materials, actions, and equivalents of all means or step-plus-function elements in the following claims are intended to include all structures, materials, or actions for performing the function in conjunction with other expressly claimed elements. The description of the present invention is intended for illustration and description purposes but is not meant to be exhaustive or limited to the invention as disclosed. Many modifications and variations are conceivable for those skilled in the art without these constituting a deviation from the scope of protection of the invention. The embodiments have been selected and described to explain the basic concepts and practical application of the invention in the best possible way and to enable other skilled in the art to understand different embodiments with various modifications for the respective use under consideration.

Claims

[1] Neuromorphic memory element (100; 200; 408; 706) that has a memristive unit, wherein the memristive unit has: a carrier material (102) having a top surface and a back surface; a first dielectric material layer (112) at the top surface of the support material; a memristive active channel (108) which has a phase-change material and is adjacent to an upper surface of the first dielectric material layer; a source port (104) and a sink port (106) connected by the memristive active channel (108); and a rear gate (110) below the first dielectric material layer; where: the memristive active channel extends longitudinally between the source port and the sink port; a control signal (412) at the rear gate (110) is configured to represent volatile biological neuronal processes of the neuromorphic storage element; and a bias between the source terminal and the sink terminal is configured to represent non-volatile biological neuronal processes of the neuromorphic storage element. [2] Neuromorphic memory element (100; 200; 408; 706) that has a memristive unit, wherein the memristive unit has: a carrier material (102); a memristive active channel (108) which incorporates a phase-change material; a source port (104) and a sink port (106) which are connected at the top of the carrier material by the memristive active channel (108); a second dielectric material layer (202) adjacent to the upper surface of the memristive active channel; and a control gate (204) at the top of the second dielectric material layer; where: the memristive active channel extends longitudinally between the source port and the sink port; a control signal (412) at the control gate is configured to represent volatile biological neuronal processes of the neuromorphic storage element; and a bias between the source terminal and the sink terminal is configured to represent non-volatile biological neuronal processes of the neuromorphic storage element. [3] Neuromorphic memory element according to claim 1 or 2, wherein the neuromorphic memory element is configured to emulate: long-term plasticity dynamics via non-volatile modulation of a memristor conductance during a writing process; from short-term plasticity dynamics via transient modulation of memristor conductance during a read operation; and from neuronal dynamics to transient modulation of memristor conductance during read and write operations. [4] Neuromorphic storage element according to claim 2, wherein the memristive unit comprises: a first dielectric material layer (112) between the support material and the memristive active channel; and a rear gate (110) below the first dielectric material layer. [5] Neuromorphic storage element according to claim 1 or 4, wherein the carrier material is conductive and wherein the carrier material is the rear gate. [6] Neuromorphic storage element according to claim 5, wherein the substrate material is a metal or a highly doped semiconductor. [7] Neuromorphic storage element according to claim 1 or 4, wherein the support material is a silicon substrate and wherein the rear gate is a conductive layer on top of the rear surface of the silicon substrate. [8] Neuromorphic storage element according to claim 1, wherein the memristive unit further comprises: a second dielectric material layer (202) at the top of the memristive active channel; and a first upper gate (204) at the top of the second dielectric material layer. [9] Neuromorphic storage element according to one of the preceding claims, wherein the memristive unit further comprises a second upper gate (302) adjacent to a first side of the memristive active channel. [10] Neuromorphic storage element according to claim 9, wherein the memristive unit further comprises a third upper gate (304) adjacent to a second side of the memristive active channel and opposite the memristive active channel to the second upper gate. [11] A plurality of neuromorphic memory elements, each of which is a neuromorphic memory element according to any of the preceding claims, wherein a control signal connection of a plurality of the neuromorphic memory elements is common to one or more of the following gates: a lower gate, a control gate, a first upper gate, a second upper gate, a third upper gate. [12] Method for operating a neuromorphic storage element (100; 200; 408; 706) comprising a memristive unit, wherein the memristive unit comprises: a source connection (104); a sink connection (106); a carrier material (102) having a top surface and a back surface; a first dielectric material layer (112) at the top surface of the support material; a memristive active channel (108) comprising a phase-change material and adjacent to an upper surface of the dielectric material, the memristive active channel extending longitudinally between and connecting the source terminal and the sink terminal; and a rear gate (110) below the first dielectric material layer; the procedure exhibits: Applying a control signal (412) to the rear gate, which represents volatile biological neuronal processes of the neuromorphic storage element; and Applying a bias voltage between the source terminal and the sink terminal, representing non-volatile biological neuronal processes of the neuromorphic storage element. [13] Method for operating a neuromorphic storage element (100; 200; 408; 706) comprising a memristive unit, wherein the memristive unit comprises: a carrier material (102); a source connection (104); a sink connection (106); a memristive active channel (108) at the top of the support material which has a phase-changing material, wherein the memristive active channel extends longitudinally between and connects the input signal terminal and the output signal terminal; a second dielectric material layer (202) adjacent to the upper surface of the memristive active channel; and a first upper gate (204) at the top of the second dielectric material layer; the procedure exhibits: Applying a control signal (412) to the upper first gate, which represents volatile biological neuronal processes of the neuromorphic storage element; and Applying a bias voltage between the source terminal and the sink terminal, representing non-volatile biological neuronal processes of the neuromorphic storage element. [14] Method according to claim 12 or 13, further comprising emulation by the neuromorphic storage element: long-term plasticity dynamics via non-volatile modulation of a memristor conductance during a writing process; from short-term plasticity dynamics via transient modulation of memristor conductance during a read operation; and from neuronal dynamics to transient modulation of memristor conductance during read and write operations. [15] Method according to claim 13, wherein the memristive unit comprises: a first dielectric material layer (112) between the support material and the memristive active channel; and a rear gate (110) below the first dielectric material layer. [16] Method according to claim 12 or 15, wherein: the carrier material is conductive; and The carrier material is the rear gate. [17] Method according to claim 16, wherein the support material is a metal or a highly doped semiconductor. [18] Method according to claim 12 or 15, wherein: the substrate material is a silicon substrate; and The rear gate is a conductive layer located on the top of the rear surface of the silicon substrate. [19] The method of claim 12, wherein the memristive unit further comprises: a second dielectric material layer (202) at the top of the memristive active channel; and a first upper gate (204) at the top of the second dielectric material layer. [20] Method according to any one of the preceding claims 12 to 19, wherein the memristive unit further comprises a second upper gate (302) adjacent to a first side of the memristive active channel.

Images